LXR linux/drivers/gpu/drm/amd/display/dc/dcn21/dcn21

   1/*
   2* Copyright 2018 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25#ifndef DAL_DC_DCN21_DCN21_HUBBUB_H_
  26#define DAL_DC_DCN21_DCN21_HUBBUB_H_
  27
  28#include "dcn20/dcn20_hubbub.h"
  29
  30#define HUBBUB_HVM_REG_LIST() \
  31        SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
  32        SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
  33        SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
  34        SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
  35        SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
  36        SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
  37        SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
  38        SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
  39        SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
  40        SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
  41        SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\
  42        SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\
  43        SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
  44        SR(DCHVM_CTRL0), \
  45        SR(DCHVM_MEM_CTRL), \
  46        SR(DCHVM_CLK_CTRL), \
  47        SR(DCHVM_RIOMMU_CTRL0), \
  48        SR(DCHVM_RIOMMU_STAT0)
  49
  50#define HUBBUB_REG_LIST_DCN21()\
  51        HUBBUB_REG_LIST_DCN20_COMMON(), \
  52        HUBBUB_SR_WATERMARK_REG_LIST(), \
  53        HUBBUB_HVM_REG_LIST()
  54
  55#define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \
  56        HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh), \
  57        HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \
  58        HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \
  59        HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \
  60        HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \
  61        HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \
  62        HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \
  63        HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \
  64        HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \
  65        HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, mask_sh), \
  66        HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, mask_sh), \
  67        HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, mask_sh), \
  68        HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, mask_sh), \
  69        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \
  70        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \
  71        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \
  72        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \
  73        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \
  74        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \
  75        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \
  76        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D, mask_sh), \
  77        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \
  78        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \
  79        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \
  80        HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh), \
  81        HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh), \
  82        HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \
  83        HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh), \
  84        HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh), \
  85        HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh), \
  86        HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh), \
  87        HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh), \
  88        HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh), \
  89        HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh), \
  90        HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh), \
  91        HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh), \
  92        HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh), \
  93        HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh), \
  94        HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh), \
  95        HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh), \
  96        HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \
  97        HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \
  98        HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \
  99        HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh)
 100
 101#define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\
 102        HUBBUB_MASK_SH_LIST_HVM(mask_sh), \
 103        HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
 104        HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
 105        HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 106        HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \
 107        HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
 108        HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
 109        HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
 110        HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
 111        HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh)
 112
 113void dcn21_dchvm_init(struct hubbub *hubbub);
 114int hubbub21_init_dchub(struct hubbub *hubbub,
 115                struct dcn_hubbub_phys_addr_config *pa_config);
 116bool hubbub21_program_watermarks(
 117                struct hubbub *hubbub,
 118                struct dcn_watermark_set *watermarks,
 119                unsigned int refclk_mhz,
 120                bool safe_to_lower);
 121bool hubbub21_program_urgent_watermarks(
 122                struct hubbub *hubbub,
 123                struct dcn_watermark_set *watermarks,
 124                unsigned int refclk_mhz,
 125                bool safe_to_lower);
 126bool hubbub21_program_stutter_watermarks(
 127                struct hubbub *hubbub,
 128                struct dcn_watermark_set *watermarks,
 129                unsigned int refclk_mhz,
 130                bool safe_to_lower);
 131bool hubbub21_program_pstate_watermarks(
 132                struct hubbub *hubbub,
 133                struct dcn_watermark_set *watermarks,
 134                unsigned int refclk_mhz,
 135                bool safe_to_lower);
 136
 137void hubbub21_wm_read_state(struct hubbub *hubbub,
 138                struct dcn_hubbub_wm *wm);
 139
 140void hubbub21_construct(struct dcn20_hubbub *hubbub,
 141        struct dc_context *ctx,
 142        const struct dcn_hubbub_registers *hubbub_regs,
 143        const struct dcn_hubbub_shift *hubbub_shift,
 144        const struct dcn_hubbub_mask *hubbub_mask);
 145
 146#endif /* DAL_DC_DCN21_DCN21_HUBBUB_H_ */
 147