LXR linux/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "reg_helper.h"
  27
  28#include <linux/delay.h>
  29#include "core_types.h"
  30#include "link_encoder.h"
  31#include "dcn21_link_encoder.h"
  32#include "stream_encoder.h"
  33
  34#include "i2caux_interface.h"
  35#include "dc_bios_types.h"
  36
  37#include "gpio_service_interface.h"
  38
  39#define CTX \
  40        enc10->base.ctx
  41#define DC_LOGGER \
  42        enc10->base.ctx->logger
  43
  44#define REG(reg)\
  45        (enc10->link_regs->reg)
  46
  47#undef FN
  48#define FN(reg_name, field_name) \
  49        enc10->link_shift->field_name, enc10->link_mask->field_name
  50
  51#define IND_REG(index) \
  52        (enc10->link_regs->index)
  53
  54static struct mpll_cfg dcn21_mpll_cfg_ref[] = {
  55        // RBR
  56        {
  57                .hdmimode_enable = 0,
  58                .ref_range = 1,
  59                .ref_clk_mpllb_div = 1,
  60                .mpllb_ssc_en = 1,
  61                .mpllb_div5_clk_en = 1,
  62                .mpllb_multiplier = 238,
  63                .mpllb_fracn_en = 0,
  64                .mpllb_fracn_quot = 0,
  65                .mpllb_fracn_rem = 0,
  66                .mpllb_fracn_den = 1,
  67                .mpllb_ssc_up_spread = 0,
  68                .mpllb_ssc_peak = 44237,
  69                .mpllb_ssc_stepsize = 59454,
  70                .mpllb_div_clk_en = 0,
  71                .mpllb_div_multiplier = 0,
  72                .mpllb_hdmi_div = 0,
  73                .mpllb_tx_clk_div = 2,
  74                .tx_vboost_lvl = 5,
  75                .mpllb_pmix_en = 1,
  76                .mpllb_word_div2_en = 0,
  77                .mpllb_ana_v2i = 2,
  78                .mpllb_ana_freq_vco = 2,
  79                .mpllb_ana_cp_int = 9,
  80                .mpllb_ana_cp_prop = 15,
  81                .hdmi_pixel_clk_div = 0,
  82        },
  83        // HBR
  84        {
  85                .hdmimode_enable = 0,
  86                .ref_range = 1,
  87                .ref_clk_mpllb_div = 1,
  88                .mpllb_ssc_en = 1,
  89                .mpllb_div5_clk_en = 1,
  90                .mpllb_multiplier = 192,
  91                .mpllb_fracn_en = 1,
  92                .mpllb_fracn_quot = 32768,
  93                .mpllb_fracn_rem = 0,
  94                .mpllb_fracn_den = 1,
  95                .mpllb_ssc_up_spread = 0,
  96                .mpllb_ssc_peak = 36864,
  97                .mpllb_ssc_stepsize = 49545,
  98                .mpllb_div_clk_en = 0,
  99                .mpllb_div_multiplier = 0,
 100                .mpllb_hdmi_div = 0,
 101                .mpllb_tx_clk_div = 1,
 102                .tx_vboost_lvl = 5,
 103                .mpllb_pmix_en = 1,
 104                .mpllb_word_div2_en = 0,
 105                .mpllb_ana_v2i = 2,
 106                .mpllb_ana_freq_vco = 3,
 107                .mpllb_ana_cp_int = 9,
 108                .mpllb_ana_cp_prop = 15,
 109                .hdmi_pixel_clk_div = 0,
 110        },
 111        //HBR2
 112        {
 113                .hdmimode_enable = 0,
 114                .ref_range = 1,
 115                .ref_clk_mpllb_div = 1,
 116                .mpllb_ssc_en = 1,
 117                .mpllb_div5_clk_en = 1,
 118                .mpllb_multiplier = 192,
 119                .mpllb_fracn_en = 1,
 120                .mpllb_fracn_quot = 32768,
 121                .mpllb_fracn_rem = 0,
 122                .mpllb_fracn_den = 1,
 123                .mpllb_ssc_up_spread = 0,
 124                .mpllb_ssc_peak = 36864,
 125                .mpllb_ssc_stepsize = 49545,
 126                .mpllb_div_clk_en = 0,
 127                .mpllb_div_multiplier = 0,
 128                .mpllb_hdmi_div = 0,
 129                .mpllb_tx_clk_div = 0,
 130                .tx_vboost_lvl = 5,
 131                .mpllb_pmix_en = 1,
 132                .mpllb_word_div2_en = 0,
 133                .mpllb_ana_v2i = 2,
 134                .mpllb_ana_freq_vco = 3,
 135                .mpllb_ana_cp_int = 9,
 136                .mpllb_ana_cp_prop = 15,
 137                .hdmi_pixel_clk_div = 0,
 138        },
 139        //HBR3
 140        {
 141                .hdmimode_enable = 0,
 142                .ref_range = 1,
 143                .ref_clk_mpllb_div = 1,
 144                .mpllb_ssc_en = 1,
 145                .mpllb_div5_clk_en = 1,
 146                .mpllb_multiplier = 304,
 147                .mpllb_fracn_en = 1,
 148                .mpllb_fracn_quot = 49152,
 149                .mpllb_fracn_rem = 0,
 150                .mpllb_fracn_den = 1,
 151                .mpllb_ssc_up_spread = 0,
 152                .mpllb_ssc_peak = 55296,
 153                .mpllb_ssc_stepsize = 74318,
 154                .mpllb_div_clk_en = 0,
 155                .mpllb_div_multiplier = 0,
 156                .mpllb_hdmi_div = 0,
 157                .mpllb_tx_clk_div = 0,
 158                .tx_vboost_lvl = 5,
 159                .mpllb_pmix_en = 1,
 160                .mpllb_word_div2_en = 0,
 161                .mpllb_ana_v2i = 2,
 162                .mpllb_ana_freq_vco = 1,
 163                .mpllb_ana_cp_int = 7,
 164                .mpllb_ana_cp_prop = 16,
 165                .hdmi_pixel_clk_div = 0,
 166        },
 167};
 168
 169
 170static bool update_cfg_data(
 171                struct dcn10_link_encoder *enc10,
 172                const struct dc_link_settings *link_settings,
 173                struct dpcssys_phy_seq_cfg *cfg)
 174{
 175        int i;
 176
 177        cfg->load_sram_fw = false;
 178        cfg->use_calibration_setting = true;
 179
 180        //TODO: need to implement a proper lane mapping for Renoir.
 181        for (i = 0; i < 4; i++)
 182                cfg->lane_en[i] = true;
 183
 184        switch (link_settings->link_rate) {
 185        case LINK_RATE_LOW:
 186                cfg->mpll_cfg = dcn21_mpll_cfg_ref[0];
 187                break;
 188        case LINK_RATE_HIGH:
 189                cfg->mpll_cfg = dcn21_mpll_cfg_ref[1];
 190                break;
 191        case LINK_RATE_HIGH2:
 192                cfg->mpll_cfg = dcn21_mpll_cfg_ref[2];
 193                break;
 194        case LINK_RATE_HIGH3:
 195                cfg->mpll_cfg = dcn21_mpll_cfg_ref[3];
 196                break;
 197        default:
 198                DC_LOG_ERROR("%s: No supported link rate found %X!\n",
 199                                __func__, link_settings->link_rate);
 200                return false;
 201        }
 202
 203        return true;
 204}
 205
 206bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc)
 207{
 208        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 209        int value;
 210
 211        if (enc->features.flags.bits.DP_IS_USB_C) {
 212                REG_GET(RDPCSTX_PHY_CNTL6,
 213                                RDPCS_PHY_DPALT_DISABLE, &value);
 214
 215                if (value == 1) {
 216                        ASSERT(0);
 217                        return false;
 218                }
 219                REG_UPDATE(RDPCSTX_PHY_CNTL6,
 220                                RDPCS_PHY_DPALT_DISABLE_ACK, 0);
 221
 222                udelay(40);
 223
 224                REG_GET(RDPCSTX_PHY_CNTL6,
 225                                                RDPCS_PHY_DPALT_DISABLE, &value);
 226                if (value == 1) {
 227                        ASSERT(0);
 228                        REG_UPDATE(RDPCSTX_PHY_CNTL6,
 229                                        RDPCS_PHY_DPALT_DISABLE_ACK, 1);
 230                        return false;
 231                }
 232        }
 233
 234        REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 1);
 235
 236        return true;
 237}
 238
 239
 240
 241static void dcn21_link_encoder_release_phy(struct link_encoder *enc)
 242{
 243        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 244
 245        if (enc->features.flags.bits.DP_IS_USB_C) {
 246                REG_UPDATE(RDPCSTX_PHY_CNTL6,
 247                                RDPCS_PHY_DPALT_DISABLE_ACK, 1);
 248        }
 249
 250        REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 0);
 251
 252}
 253
 254void dcn21_link_encoder_enable_dp_output(
 255        struct link_encoder *enc,
 256        const struct dc_link_settings *link_settings,
 257        enum clock_source_id clock_source)
 258{
 259        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 260        struct dcn21_link_encoder *enc21 = (struct dcn21_link_encoder *) enc10;
 261        struct dpcssys_phy_seq_cfg *cfg = &enc21->phy_seq_cfg;
 262
 263        if (!dcn21_link_encoder_acquire_phy(enc))
 264                return;
 265
 266        if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
 267                dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
 268                return;
 269        }
 270
 271        if (!update_cfg_data(enc10, link_settings, cfg))
 272                return;
 273
 274        enc1_configure_encoder(enc10, link_settings);
 275
 276        dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT);
 277
 278}
 279
 280void dcn21_link_encoder_enable_dp_mst_output(
 281        struct link_encoder *enc,
 282        const struct dc_link_settings *link_settings,
 283        enum clock_source_id clock_source)
 284{
 285        if (!dcn21_link_encoder_acquire_phy(enc))
 286                return;
 287
 288        dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
 289}
 290
 291void dcn21_link_encoder_disable_output(
 292        struct link_encoder *enc,
 293        enum signal_type signal)
 294{
 295        dcn10_link_encoder_disable_output(enc, signal);
 296
 297        if (dc_is_dp_signal(signal))
 298                dcn21_link_encoder_release_phy(enc);
 299}
 300
 301
 302static const struct link_encoder_funcs dcn21_link_enc_funcs = {
 303        .read_state = link_enc2_read_state,
 304        .validate_output_with_stream =
 305                dcn10_link_encoder_validate_output_with_stream,
 306        .hw_init = enc2_hw_init,
 307        .setup = dcn10_link_encoder_setup,
 308        .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
 309        .enable_dp_output = dcn21_link_encoder_enable_dp_output,
 310        .enable_dp_mst_output = dcn21_link_encoder_enable_dp_mst_output,
 311        .disable_output = dcn21_link_encoder_disable_output,
 312        .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
 313        .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
 314        .update_mst_stream_allocation_table =
 315                dcn10_link_encoder_update_mst_stream_allocation_table,
 316        .psr_program_dp_dphy_fast_training =
 317                        dcn10_psr_program_dp_dphy_fast_training,
 318        .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
 319        .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
 320        .enable_hpd = dcn10_link_encoder_enable_hpd,
 321        .disable_hpd = dcn10_link_encoder_disable_hpd,
 322        .is_dig_enabled = dcn10_is_dig_enabled,
 323        .destroy = dcn10_link_encoder_destroy,
 324        .fec_set_enable = enc2_fec_set_enable,
 325        .fec_set_ready = enc2_fec_set_ready,
 326        .fec_is_active = enc2_fec_is_active,
 327        .get_dig_frontend = dcn10_get_dig_frontend,
 328        .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
 329        .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
 330};
 331
 332void dcn21_link_encoder_construct(
 333        struct dcn21_link_encoder *enc21,
 334        const struct encoder_init_data *init_data,
 335        const struct encoder_feature_support *enc_features,
 336        const struct dcn10_link_enc_registers *link_regs,
 337        const struct dcn10_link_enc_aux_registers *aux_regs,
 338        const struct dcn10_link_enc_hpd_registers *hpd_regs,
 339        const struct dcn10_link_enc_shift *link_shift,
 340        const struct dcn10_link_enc_mask *link_mask)
 341{
 342        struct bp_encoder_cap_info bp_cap_info = {0};
 343        const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
 344        enum bp_result result = BP_RESULT_OK;
 345        struct dcn10_link_encoder *enc10 = &enc21->enc10;
 346
 347        enc10->base.funcs = &dcn21_link_enc_funcs;
 348        enc10->base.ctx = init_data->ctx;
 349        enc10->base.id = init_data->encoder;
 350
 351        enc10->base.hpd_source = init_data->hpd_source;
 352        enc10->base.connector = init_data->connector;
 353
 354        enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 355
 356        enc10->base.features = *enc_features;
 357
 358        enc10->base.transmitter = init_data->transmitter;
 359
 360        /* set the flag to indicate whether driver poll the I2C data pin
 361         * while doing the DP sink detect
 362         */
 363
 364/*      if (dal_adapter_service_is_feature_supported(as,
 365                FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
 366                enc10->base.features.flags.bits.
 367                        DP_SINK_DETECT_POLL_DATA_PIN = true;*/
 368
 369        enc10->base.output_signals =
 370                SIGNAL_TYPE_DVI_SINGLE_LINK |
 371                SIGNAL_TYPE_DVI_DUAL_LINK |
 372                SIGNAL_TYPE_LVDS |
 373                SIGNAL_TYPE_DISPLAY_PORT |
 374                SIGNAL_TYPE_DISPLAY_PORT_MST |
 375                SIGNAL_TYPE_EDP |
 376                SIGNAL_TYPE_HDMI_TYPE_A;
 377
 378        /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
 379         * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
 380         * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
 381         * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
 382         * Prefer DIG assignment is decided by board design.
 383         * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
 384         * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
 385         * By this, adding DIGG should not hurt DCE 8.0.
 386         * This will let DCE 8.1 share DCE 8.0 as much as possible
 387         */
 388
 389        enc10->link_regs = link_regs;
 390        enc10->aux_regs = aux_regs;
 391        enc10->hpd_regs = hpd_regs;
 392        enc10->link_shift = link_shift;
 393        enc10->link_mask = link_mask;
 394
 395        switch (enc10->base.transmitter) {
 396        case TRANSMITTER_UNIPHY_A:
 397                enc10->base.preferred_engine = ENGINE_ID_DIGA;
 398        break;
 399        case TRANSMITTER_UNIPHY_B:
 400                enc10->base.preferred_engine = ENGINE_ID_DIGB;
 401        break;
 402        case TRANSMITTER_UNIPHY_C:
 403                enc10->base.preferred_engine = ENGINE_ID_DIGC;
 404        break;
 405        case TRANSMITTER_UNIPHY_D:
 406                enc10->base.preferred_engine = ENGINE_ID_DIGD;
 407        break;
 408        case TRANSMITTER_UNIPHY_E:
 409                enc10->base.preferred_engine = ENGINE_ID_DIGE;
 410        break;
 411        case TRANSMITTER_UNIPHY_F:
 412                enc10->base.preferred_engine = ENGINE_ID_DIGF;
 413        break;
 414        case TRANSMITTER_UNIPHY_G:
 415                enc10->base.preferred_engine = ENGINE_ID_DIGG;
 416        break;
 417        default:
 418                ASSERT_CRITICAL(false);
 419                enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 420        }
 421
 422        /* default to one to mirror Windows behavior */
 423        enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
 424
 425        result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
 426                                                enc10->base.id, &bp_cap_info);
 427
 428        /* Override features with DCE-specific values */
 429        if (result == BP_RESULT_OK) {
 430                enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
 431                                bp_cap_info.DP_HBR2_EN;
 432                enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
 433                                bp_cap_info.DP_HBR3_EN;
 434                enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
 435                enc10->base.features.flags.bits.DP_IS_USB_C =
 436                                bp_cap_info.DP_IS_USB_C;
 437        } else {
 438                DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
 439                                __func__,
 440                                result);
 441        }
 442        if (enc10->base.ctx->dc->debug.hdmi20_disable) {
 443                enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
 444        }
 445}
 446