1/* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifndef __DAL_ASIC_ID_H__ 27#define __DAL_ASIC_ID_H__ 28 29/* 30 * ASIC internal revision ID 31 */ 32 33/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */ 34#define SI_TAHITI_P_A0 0x01 35#define SI_TAHITI_P_B0 0x05 36#define SI_TAHITI_P_B1 0x06 37#define SI_PITCAIRN_PM_A0 0x14 38#define SI_PITCAIRN_PM_A1 0x15 39#define SI_CAPEVERDE_M_A0 0x28 40#define SI_CAPEVERDE_M_A1 0x29 41#define SI_OLAND_M_A0 0x3C 42#define SI_HAINAN_V_A0 0x46 43 44#define SI_UNKNOWN 0xFF 45 46#define ASIC_REV_IS_TAHITI_P(rev) \ 47 ((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0)) 48 49#define ASIC_REV_IS_PITCAIRN_PM(rev) \ 50 ((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0)) 51 52#define ASIC_REV_IS_CAPEVERDE_M(rev) \ 53 ((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0)) 54 55#define ASIC_REV_IS_OLAND_M(rev) \ 56 ((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0)) 57 58#define ASIC_REV_IS_HAINAN_V(rev) \ 59 ((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN)) 60 61/* DCE80 (based on ci_id.h in Perforce) */ 62#define CI_BONAIRE_M_A0 0x14 63#define CI_BONAIRE_M_A1 0x15 64#define CI_HAWAII_P_A0 0x28 65 66#define CI_UNKNOWN 0xFF 67 68#define ASIC_REV_IS_BONAIRE_M(rev) \ 69 ((rev >= CI_BONAIRE_M_A0) && (rev < CI_HAWAII_P_A0)) 70 71#define ASIC_REV_IS_HAWAII_P(rev) \ 72 (rev >= CI_HAWAII_P_A0) 73 74/* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */ 75#define KV_SPECTRE_A0 0x01 76 77/* KV2 with Spooky GFX core, including downgraded from Spectre core, 78 * 3-4-1-1 (CU-Pix-Primitive-RB) */ 79#define KV_SPOOKY_A0 0x41 80 81/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ 82#define KB_KALINDI_A0 0x81 83 84/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ 85#define KB_KALINDI_A1 0x82 86 87/* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ 88#define BV_KALINDI_A2 0x85 89 90/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ 91#define ML_GODAVARI_A0 0xA1 92 93/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ 94#define ML_GODAVARI_A1 0xA2 95 96#define KV_UNKNOWN 0xFF 97 98#define ASIC_REV_IS_KALINDI(rev) \ 99 ((rev >= KB_KALINDI_A0) && (rev < KV_UNKNOWN)) 100 101#define ASIC_REV_IS_BHAVANI(rev) \ 102 ((rev >= BV_KALINDI_A2) && (rev < ML_GODAVARI_A0)) 103 104#define ASIC_REV_IS_GODAVARI(rev) \ 105 ((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN)) 106 107/* VI Family */ 108/* DCE10 */ 109#define VI_TONGA_P_A0 20 110#define VI_TONGA_P_A1 21 111#define VI_FIJI_P_A0 60 112 113/* DCE112 */ 114#define VI_POLARIS10_P_A0 80 115#define VI_POLARIS11_M_A0 90 116#define VI_POLARIS12_V_A0 100 117#define VI_VEGAM_A0 110 118 119#define VI_UNKNOWN 0xFF 120 121#define ASIC_REV_IS_TONGA_P(eChipRev) ((eChipRev >= VI_TONGA_P_A0) && \ 122 (eChipRev < 40)) 123#define ASIC_REV_IS_FIJI_P(eChipRev) ((eChipRev >= VI_FIJI_P_A0) && \ 124 (eChipRev < 80)) 125 126#define ASIC_REV_IS_POLARIS10_P(eChipRev) ((eChipRev >= VI_POLARIS10_P_A0) && \ 127 (eChipRev < VI_POLARIS11_M_A0)) 128#define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) && \ 129 (eChipRev < VI_POLARIS12_V_A0)) 130#define ASIC_REV_IS_POLARIS12_V(eChipRev) ((eChipRev >= VI_POLARIS12_V_A0) && \ 131 (eChipRev < VI_VEGAM_A0)) 132#define ASIC_REV_IS_VEGAM(eChipRev) (eChipRev >= VI_VEGAM_A0) 133 134/* DCE11 */ 135#define CZ_CARRIZO_A0 0x01 136 137#define STONEY_A0 0x61 138#define CZ_UNKNOWN 0xFF 139 140#define ASIC_REV_IS_STONEY(rev) \ 141 ((rev >= STONEY_A0) && (rev < CZ_UNKNOWN)) 142 143/* DCE12 */ 144#define AI_UNKNOWN 0xFF 145 146#define AI_GREENLAND_P_A0 1 147#define AI_GREENLAND_P_A1 2 148#define AI_UNKNOWN 0xFF 149 150#define AI_VEGA12_P_A0 20 151#define AI_VEGA20_P_A0 40 152#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_VEGA12_P_A0) 153#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_VEGA12_P_A0) 154 155#define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_VEGA20_P_A0)) 156#define ASICREV_IS_VEGA20_P(eChipRev) ((eChipRev >= AI_VEGA20_P_A0) && (eChipRev < AI_UNKNOWN)) 157 158/* DCN1_0 */ 159#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */ 160#define RAVEN_A0 0x01 161#define RAVEN_B0 0x21 162#define PICASSO_A0 0x41 163/* DCN1_01 */ 164#define RAVEN2_A0 0x81 165#define RAVEN1_F0 0xF0 166#define RAVEN_UNKNOWN 0xFF 167#define RENOIR_A0 0x91 168#ifndef ASICREV_IS_RAVEN 169#define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN) 170#endif 171#define PRID_DALI_DE 0xDE 172#define PRID_DALI_DF 0xDF 173#define PRID_DALI_E3 0xE3 174#define PRID_DALI_E4 0xE4 175 176#define PRID_POLLOCK_94 0x94 177#define PRID_POLLOCK_95 0x95 178#define PRID_POLLOCK_E9 0xE9 179#define PRID_POLLOCK_EA 0xEA 180#define PRID_POLLOCK_EB 0xEB 181 182#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0)) 183#ifndef ASICREV_IS_RAVEN2 184#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RENOIR_A0)) 185#endif 186#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN)) 187 188#define FAMILY_RV 142 /* DCN 1*/ 189 190 191#define FAMILY_NV 143 /* DCN 2*/ 192 193enum { 194 NV_NAVI10_P_A0 = 1, 195 NV_NAVI12_P_A0 = 10, 196 NV_NAVI14_M_A0 = 20, 197 NV_SIENNA_CICHLID_P_A0 = 40, 198 NV_DIMGREY_CAVEFISH_P_A0 = 60, 199 NV_BEIGE_GOBY_P_A0 = 70, 200 NV_UNKNOWN = 0xFF 201}; 202 203#define ASICREV_IS_NAVI10_P(eChipRev) (eChipRev < NV_NAVI12_P_A0) 204#define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0)) 205#define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN)) 206#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0)) 207#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0) && (eChipRev < NV_DIMGREY_CAVEFISH_P_A0)) 208#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_BEIGE_GOBY_P_A0)) 209#define ASICREV_IS_BEIGE_GOBY_P(eChipRev) ((eChipRev >= NV_BEIGE_GOBY_P_A0) && (eChipRev < NV_UNKNOWN)) 210#define GREEN_SARDINE_A0 0xA1 211#ifndef ASICREV_IS_GREEN_SARDINE 212#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF)) 213#endif 214#define FAMILY_VGH 144 215#define DEVICE_ID_VGH_163F 0x163F 216#define VANGOGH_A0 0x01 217#define VANGOGH_UNKNOWN 0xFF 218 219#ifndef ASICREV_IS_VANGOGH 220#define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN)) 221#endif 222#define GREEN_SARDINE_A0 0xA1 223#ifndef ASICREV_IS_GREEN_SARDINE 224#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF)) 225#endif 226 227#define FAMILY_YELLOW_CARP 146 228 229#define YELLOW_CARP_A0 0x01 230#define YELLOW_CARP_B0 0x02 // TODO: DCN31 - update with correct B0 ID 231#define YELLOW_CARP_UNKNOWN 0xFF 232 233#ifndef ASICREV_IS_YELLOW_CARP 234#define ASICREV_IS_YELLOW_CARP(eChipRev) ((eChipRev >= YELLOW_CARP_A0) && (eChipRev < YELLOW_CARP_UNKNOWN)) 235#endif 236 237 238/* 239 * ASIC chip ID 240 */ 241 242/* DCE60 */ 243#define DEVICE_ID_SI_TAHITI_P_6780 0x6780 244#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800 245#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808 246#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820 247#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828 248#define DEVICE_ID_SI_OLAND_M_6600 0x6600 249#define DEVICE_ID_SI_OLAND_M_6608 0x6608 250#define DEVICE_ID_SI_HAINAN_V_6660 0x6660 251 252/* DCE80 */ 253#define DEVICE_ID_KALINDI_9834 0x9834 254#define DEVICE_ID_TEMASH_9839 0x9839 255#define DEVICE_ID_TEMASH_983D 0x983D 256 257/* RENOIR */ 258#define DEVICE_ID_RENOIR_1636 0x1636 259 260/* Asic Family IDs for different asic family. */ 261#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape Verde (M), Oland (M), Hainan (V) */ 262#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */ 263#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */ 264#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */ 265#define FAMILY_CZ 135 /* Carrizo */ 266 267#define FAMILY_AI 141 268 269#define FAMILY_UNKNOWN 0xFF 270 271 272 273#endif /* __DAL_ASIC_ID_H__ */ 274