LXR linux/drivers/gpu/drm/amd/display/include/link_service

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef __DAL_LINK_SERVICE_TYPES_H__
  27#define __DAL_LINK_SERVICE_TYPES_H__
  28
  29#include "grph_object_id.h"
  30#include "dal_types.h"
  31#include "irq_types.h"
  32
  33/*struct mst_mgr_callback_object;*/
  34struct ddc;
  35struct irq_manager;
  36
  37enum {
  38        MAX_CONTROLLER_NUM = 6
  39};
  40
  41enum dp_power_state {
  42        DP_POWER_STATE_D0 = 1,
  43        DP_POWER_STATE_D3
  44};
  45
  46enum edp_revision {
  47        /* eDP version 1.1 or lower */
  48        EDP_REVISION_11 = 0x00,
  49        /* eDP version 1.2 */
  50        EDP_REVISION_12 = 0x01,
  51        /* eDP version 1.3 */
  52        EDP_REVISION_13 = 0x02
  53};
  54
  55enum {
  56        LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
  57};
  58
  59enum link_training_result {
  60        LINK_TRAINING_SUCCESS,
  61        LINK_TRAINING_CR_FAIL_LANE0,
  62        LINK_TRAINING_CR_FAIL_LANE1,
  63        LINK_TRAINING_CR_FAIL_LANE23,
  64        /* CR DONE bit is cleared during EQ step */
  65        LINK_TRAINING_EQ_FAIL_CR,
  66        /* other failure during EQ step */
  67        LINK_TRAINING_EQ_FAIL_EQ,
  68        LINK_TRAINING_LQA_FAIL,
  69        /* one of the CR,EQ or symbol lock is dropped */
  70        LINK_TRAINING_LINK_LOSS,
  71        /* Abort link training (because sink unplugged) */
  72        LINK_TRAINING_ABORT,
  73};
  74
  75enum lttpr_mode {
  76        LTTPR_MODE_NON_LTTPR,
  77        LTTPR_MODE_TRANSPARENT,
  78        LTTPR_MODE_NON_TRANSPARENT,
  79};
  80
  81struct link_training_settings {
  82        struct dc_link_settings link_settings;
  83        struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
  84
  85        enum dc_voltage_swing *voltage_swing;
  86        enum dc_pre_emphasis *pre_emphasis;
  87        enum dc_post_cursor2 *post_cursor2;
  88        bool should_set_fec_ready;
  89
  90        uint16_t cr_pattern_time;
  91        uint16_t eq_pattern_time;
  92        enum dc_dp_training_pattern pattern_for_cr;
  93        enum dc_dp_training_pattern pattern_for_eq;
  94
  95        bool enhanced_framing;
  96        bool allow_invalid_msa_timing_param;
  97        enum lttpr_mode lttpr_mode;
  98};
  99
 100/*TODO: Move this enum test harness*/
 101/* Test patterns*/
 102enum dp_test_pattern {
 103        /* Input data is pass through Scrambler
 104         * and 8b10b Encoder straight to output*/
 105        DP_TEST_PATTERN_VIDEO_MODE = 0,
 106
 107        /* phy test patterns*/
 108        DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
 109        DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
 110        DP_TEST_PATTERN_SYMBOL_ERROR,
 111        DP_TEST_PATTERN_PRBS7,
 112        DP_TEST_PATTERN_80BIT_CUSTOM,
 113        DP_TEST_PATTERN_CP2520_1,
 114        DP_TEST_PATTERN_CP2520_2,
 115        DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2,
 116        DP_TEST_PATTERN_CP2520_3,
 117
 118        /* Link Training Patterns */
 119        DP_TEST_PATTERN_TRAINING_PATTERN1,
 120        DP_TEST_PATTERN_TRAINING_PATTERN2,
 121        DP_TEST_PATTERN_TRAINING_PATTERN3,
 122        DP_TEST_PATTERN_TRAINING_PATTERN4,
 123        DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4,
 124
 125        /* link test patterns*/
 126        DP_TEST_PATTERN_COLOR_SQUARES,
 127        DP_TEST_PATTERN_COLOR_SQUARES_CEA,
 128        DP_TEST_PATTERN_VERTICAL_BARS,
 129        DP_TEST_PATTERN_HORIZONTAL_BARS,
 130        DP_TEST_PATTERN_COLOR_RAMP,
 131
 132        /* audio test patterns*/
 133        DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED,
 134        DP_TEST_PATTERN_AUDIO_SAWTOOTH,
 135
 136        DP_TEST_PATTERN_UNSUPPORTED
 137};
 138
 139enum dp_test_pattern_color_space {
 140        DP_TEST_PATTERN_COLOR_SPACE_RGB,
 141        DP_TEST_PATTERN_COLOR_SPACE_YCBCR601,
 142        DP_TEST_PATTERN_COLOR_SPACE_YCBCR709,
 143        DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED
 144};
 145
 146enum dp_panel_mode {
 147        /* not required */
 148        DP_PANEL_MODE_DEFAULT,
 149        /* standard mode for eDP */
 150        DP_PANEL_MODE_EDP,
 151        /* external chips specific settings */
 152        DP_PANEL_MODE_SPECIAL
 153};
 154
 155/* DPCD_ADDR_TRAINING_LANEx_SET registers value */
 156union dpcd_training_lane_set {
 157        struct {
 158#if defined(LITTLEENDIAN_CPU)
 159                uint8_t VOLTAGE_SWING_SET:2;
 160                uint8_t MAX_SWING_REACHED:1;
 161                uint8_t PRE_EMPHASIS_SET:2;
 162                uint8_t MAX_PRE_EMPHASIS_REACHED:1;
 163                /* following is reserved in DP 1.1 */
 164                uint8_t POST_CURSOR2_SET:2;
 165#elif defined(BIGENDIAN_CPU)
 166                uint8_t POST_CURSOR2_SET:2;
 167                uint8_t MAX_PRE_EMPHASIS_REACHED:1;
 168                uint8_t PRE_EMPHASIS_SET:2;
 169                uint8_t MAX_SWING_REACHED:1;
 170                uint8_t VOLTAGE_SWING_SET:2;
 171#else
 172        #error ARCH not defined!
 173#endif
 174        } bits;
 175
 176        uint8_t raw;
 177};
 178
 179
 180/* DP MST stream allocation (payload bandwidth number) */
 181struct dp_mst_stream_allocation {
 182        uint8_t vcp_id;
 183        /* number of slots required for the DP stream in
 184         * transport packet */
 185        uint8_t slot_count;
 186};
 187
 188/* DP MST stream allocation table */
 189struct dp_mst_stream_allocation_table {
 190        /* number of DP video streams */
 191        int stream_count;
 192        /* array of stream allocations */
 193        struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
 194};
 195
 196#endif /*__DAL_LINK_SERVICE_TYPES_H__*/
 197