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12#include <linux/module.h>
13#include <linux/spinlock.h>
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/console.h>
17#include <linux/dma-mapping.h>
18#include <linux/list.h>
19#include <linux/of_graph.h>
20#include <linux/of_reserved_mem.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23
24#include <drm/drm_atomic_helper.h>
25#include <drm/drm_crtc.h>
26#include <drm/drm_debugfs.h>
27#include <drm/drm_drv.h>
28#include <drm/drm_fb_cma_helper.h>
29#include <drm/drm_fb_helper.h>
30#include <drm/drm_gem_cma_helper.h>
31#include <drm/drm_gem_framebuffer_helper.h>
32#include <drm/drm_irq.h>
33#include <drm/drm_modeset_helper.h>
34#include <drm/drm_of.h>
35#include <drm/drm_probe_helper.h>
36#include <drm/drm_vblank.h>
37
38#include "hdlcd_drv.h"
39#include "hdlcd_regs.h"
40
41static int hdlcd_load(struct drm_device *drm, unsigned long flags)
42{
43 struct hdlcd_drm_private *hdlcd = drm->dev_private;
44 struct platform_device *pdev = to_platform_device(drm->dev);
45 struct resource *res;
46 u32 version;
47 int ret;
48
49 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
50 if (IS_ERR(hdlcd->clk))
51 return PTR_ERR(hdlcd->clk);
52
53#ifdef CONFIG_DEBUG_FS
54 atomic_set(&hdlcd->buffer_underrun_count, 0);
55 atomic_set(&hdlcd->bus_error_count, 0);
56 atomic_set(&hdlcd->vsync_count, 0);
57 atomic_set(&hdlcd->dma_end_count, 0);
58#endif
59
60 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
61 hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
62 if (IS_ERR(hdlcd->mmio)) {
63 DRM_ERROR("failed to map control registers area\n");
64 ret = PTR_ERR(hdlcd->mmio);
65 hdlcd->mmio = NULL;
66 return ret;
67 }
68
69 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
70 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
71 DRM_ERROR("unknown product id: 0x%x\n", version);
72 return -EINVAL;
73 }
74 DRM_INFO("found ARM HDLCD version r%dp%d\n",
75 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
76 version & HDLCD_VERSION_MINOR_MASK);
77
78
79 ret = of_reserved_mem_device_init(drm->dev);
80 if (ret && ret != -ENODEV)
81 return ret;
82
83 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
84 if (ret)
85 goto setup_fail;
86
87 ret = hdlcd_setup_crtc(drm);
88 if (ret < 0) {
89 DRM_ERROR("failed to create crtc\n");
90 goto setup_fail;
91 }
92
93 ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
94 if (ret < 0) {
95 DRM_ERROR("failed to install IRQ handler\n");
96 goto irq_fail;
97 }
98
99 return 0;
100
101irq_fail:
102 drm_crtc_cleanup(&hdlcd->crtc);
103setup_fail:
104 of_reserved_mem_device_release(drm->dev);
105
106 return ret;
107}
108
109static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
110 .fb_create = drm_gem_fb_create,
111 .atomic_check = drm_atomic_helper_check,
112 .atomic_commit = drm_atomic_helper_commit,
113};
114
115static void hdlcd_setup_mode_config(struct drm_device *drm)
116{
117 drm_mode_config_init(drm);
118 drm->mode_config.min_width = 0;
119 drm->mode_config.min_height = 0;
120 drm->mode_config.max_width = HDLCD_MAX_XRES;
121 drm->mode_config.max_height = HDLCD_MAX_YRES;
122 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
123}
124
125static irqreturn_t hdlcd_irq(int irq, void *arg)
126{
127 struct drm_device *drm = arg;
128 struct hdlcd_drm_private *hdlcd = drm->dev_private;
129 unsigned long irq_status;
130
131 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
132
133#ifdef CONFIG_DEBUG_FS
134 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
135 atomic_inc(&hdlcd->buffer_underrun_count);
136
137 if (irq_status & HDLCD_INTERRUPT_DMA_END)
138 atomic_inc(&hdlcd->dma_end_count);
139
140 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
141 atomic_inc(&hdlcd->bus_error_count);
142
143 if (irq_status & HDLCD_INTERRUPT_VSYNC)
144 atomic_inc(&hdlcd->vsync_count);
145
146#endif
147 if (irq_status & HDLCD_INTERRUPT_VSYNC)
148 drm_crtc_handle_vblank(&hdlcd->crtc);
149
150
151 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
152
153 return IRQ_HANDLED;
154}
155
156static void hdlcd_irq_preinstall(struct drm_device *drm)
157{
158 struct hdlcd_drm_private *hdlcd = drm->dev_private;
159
160 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
161 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
162}
163
164static int hdlcd_irq_postinstall(struct drm_device *drm)
165{
166#ifdef CONFIG_DEBUG_FS
167 struct hdlcd_drm_private *hdlcd = drm->dev_private;
168 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
169
170
171 irq_mask |= HDLCD_DEBUG_INT_MASK;
172
173 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
174#endif
175 return 0;
176}
177
178static void hdlcd_irq_uninstall(struct drm_device *drm)
179{
180 struct hdlcd_drm_private *hdlcd = drm->dev_private;
181
182 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
183
184#ifdef CONFIG_DEBUG_FS
185
186 irq_mask &= ~HDLCD_DEBUG_INT_MASK;
187#endif
188
189
190 irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
191
192 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
193}
194
195#ifdef CONFIG_DEBUG_FS
196static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
197{
198 struct drm_info_node *node = (struct drm_info_node *)m->private;
199 struct drm_device *drm = node->minor->dev;
200 struct hdlcd_drm_private *hdlcd = drm->dev_private;
201
202 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
203 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
204 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
205 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
206 return 0;
207}
208
209static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
210{
211 struct drm_info_node *node = (struct drm_info_node *)m->private;
212 struct drm_device *drm = node->minor->dev;
213 struct hdlcd_drm_private *hdlcd = drm->dev_private;
214 unsigned long clkrate = clk_get_rate(hdlcd->clk);
215 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
216
217 seq_printf(m, "hw : %lu\n", clkrate);
218 seq_printf(m, "mode: %lu\n", mode_clock);
219 return 0;
220}
221
222static struct drm_info_list hdlcd_debugfs_list[] = {
223 { "interrupt_count", hdlcd_show_underrun_count, 0 },
224 { "clocks", hdlcd_show_pxlclock, 0 },
225};
226
227static void hdlcd_debugfs_init(struct drm_minor *minor)
228{
229 drm_debugfs_create_files(hdlcd_debugfs_list,
230 ARRAY_SIZE(hdlcd_debugfs_list),
231 minor->debugfs_root, minor);
232}
233#endif
234
235DEFINE_DRM_GEM_CMA_FOPS(fops);
236
237static const struct drm_driver hdlcd_driver = {
238 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
239 .irq_handler = hdlcd_irq,
240 .irq_preinstall = hdlcd_irq_preinstall,
241 .irq_postinstall = hdlcd_irq_postinstall,
242 .irq_uninstall = hdlcd_irq_uninstall,
243 DRM_GEM_CMA_DRIVER_OPS,
244#ifdef CONFIG_DEBUG_FS
245 .debugfs_init = hdlcd_debugfs_init,
246#endif
247 .fops = &fops,
248 .name = "hdlcd",
249 .desc = "ARM HDLCD Controller DRM",
250 .date = "20151021",
251 .major = 1,
252 .minor = 0,
253};
254
255static int hdlcd_drm_bind(struct device *dev)
256{
257 struct drm_device *drm;
258 struct hdlcd_drm_private *hdlcd;
259 int ret;
260
261 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
262 if (!hdlcd)
263 return -ENOMEM;
264
265 drm = drm_dev_alloc(&hdlcd_driver, dev);
266 if (IS_ERR(drm))
267 return PTR_ERR(drm);
268
269 drm->dev_private = hdlcd;
270 dev_set_drvdata(dev, drm);
271
272 hdlcd_setup_mode_config(drm);
273 ret = hdlcd_load(drm, 0);
274 if (ret)
275 goto err_free;
276
277
278 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
279
280 ret = component_bind_all(dev, drm);
281 if (ret) {
282 DRM_ERROR("Failed to bind all components\n");
283 goto err_unload;
284 }
285
286 ret = pm_runtime_set_active(dev);
287 if (ret)
288 goto err_pm_active;
289
290 pm_runtime_enable(dev);
291
292 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
293 if (ret < 0) {
294 DRM_ERROR("failed to initialise vblank\n");
295 goto err_vblank;
296 }
297
298 drm_mode_config_reset(drm);
299 drm_kms_helper_poll_init(drm);
300
301 ret = drm_dev_register(drm, 0);
302 if (ret)
303 goto err_register;
304
305 drm_fbdev_generic_setup(drm, 32);
306
307 return 0;
308
309err_register:
310 drm_kms_helper_poll_fini(drm);
311err_vblank:
312 pm_runtime_disable(drm->dev);
313err_pm_active:
314 drm_atomic_helper_shutdown(drm);
315 component_unbind_all(dev, drm);
316err_unload:
317 of_node_put(hdlcd->crtc.port);
318 hdlcd->crtc.port = NULL;
319 drm_irq_uninstall(drm);
320 of_reserved_mem_device_release(drm->dev);
321err_free:
322 drm_mode_config_cleanup(drm);
323 dev_set_drvdata(dev, NULL);
324 drm_dev_put(drm);
325
326 return ret;
327}
328
329static void hdlcd_drm_unbind(struct device *dev)
330{
331 struct drm_device *drm = dev_get_drvdata(dev);
332 struct hdlcd_drm_private *hdlcd = drm->dev_private;
333
334 drm_dev_unregister(drm);
335 drm_kms_helper_poll_fini(drm);
336 component_unbind_all(dev, drm);
337 of_node_put(hdlcd->crtc.port);
338 hdlcd->crtc.port = NULL;
339 pm_runtime_get_sync(dev);
340 drm_atomic_helper_shutdown(drm);
341 drm_irq_uninstall(drm);
342 pm_runtime_put(dev);
343 if (pm_runtime_enabled(dev))
344 pm_runtime_disable(dev);
345 of_reserved_mem_device_release(dev);
346 drm_mode_config_cleanup(drm);
347 drm->dev_private = NULL;
348 dev_set_drvdata(dev, NULL);
349 drm_dev_put(drm);
350}
351
352static const struct component_master_ops hdlcd_master_ops = {
353 .bind = hdlcd_drm_bind,
354 .unbind = hdlcd_drm_unbind,
355};
356
357static int compare_dev(struct device *dev, void *data)
358{
359 return dev->of_node == data;
360}
361
362static int hdlcd_probe(struct platform_device *pdev)
363{
364 struct device_node *port;
365 struct component_match *match = NULL;
366
367
368 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
369 if (!port)
370 return -ENODEV;
371
372 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
373 of_node_put(port);
374
375 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
376 match);
377}
378
379static int hdlcd_remove(struct platform_device *pdev)
380{
381 component_master_del(&pdev->dev, &hdlcd_master_ops);
382 return 0;
383}
384
385static const struct of_device_id hdlcd_of_match[] = {
386 { .compatible = "arm,hdlcd" },
387 {},
388};
389MODULE_DEVICE_TABLE(of, hdlcd_of_match);
390
391static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
392{
393 struct drm_device *drm = dev_get_drvdata(dev);
394
395 return drm_mode_config_helper_suspend(drm);
396}
397
398static int __maybe_unused hdlcd_pm_resume(struct device *dev)
399{
400 struct drm_device *drm = dev_get_drvdata(dev);
401
402 drm_mode_config_helper_resume(drm);
403
404 return 0;
405}
406
407static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
408
409static struct platform_driver hdlcd_platform_driver = {
410 .probe = hdlcd_probe,
411 .remove = hdlcd_remove,
412 .driver = {
413 .name = "hdlcd",
414 .pm = &hdlcd_pm_ops,
415 .of_match_table = hdlcd_of_match,
416 },
417};
418
419module_platform_driver(hdlcd_platform_driver);
420
421MODULE_AUTHOR("Liviu Dudau");
422MODULE_DESCRIPTION("ARM HDLCD DRM driver");
423MODULE_LICENSE("GPL v2");
424
