1
2
3
4
5
6#include <linux/clk.h>
7#include <linux/component.h>
8#include <linux/delay.h>
9#include <linux/dma-fence.h>
10#include <linux/dma-mapping.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/regulator/consumer.h>
16#include <linux/thermal.h>
17
18#include "etnaviv_cmdbuf.h"
19#include "etnaviv_dump.h"
20#include "etnaviv_gpu.h"
21#include "etnaviv_gem.h"
22#include "etnaviv_mmu.h"
23#include "etnaviv_perfmon.h"
24#include "etnaviv_sched.h"
25#include "common.xml.h"
26#include "state.xml.h"
27#include "state_hi.xml.h"
28#include "cmdstream.xml.h"
29
30static const struct platform_device_id gpu_ids[] = {
31 { .name = "etnaviv-gpu,2d" },
32 { },
33};
34
35
36
37
38
39int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
40{
41 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
42
43 switch (param) {
44 case ETNAVIV_PARAM_GPU_MODEL:
45 *value = gpu->identity.model;
46 break;
47
48 case ETNAVIV_PARAM_GPU_REVISION:
49 *value = gpu->identity.revision;
50 break;
51
52 case ETNAVIV_PARAM_GPU_FEATURES_0:
53 *value = gpu->identity.features;
54 break;
55
56 case ETNAVIV_PARAM_GPU_FEATURES_1:
57 *value = gpu->identity.minor_features0;
58 break;
59
60 case ETNAVIV_PARAM_GPU_FEATURES_2:
61 *value = gpu->identity.minor_features1;
62 break;
63
64 case ETNAVIV_PARAM_GPU_FEATURES_3:
65 *value = gpu->identity.minor_features2;
66 break;
67
68 case ETNAVIV_PARAM_GPU_FEATURES_4:
69 *value = gpu->identity.minor_features3;
70 break;
71
72 case ETNAVIV_PARAM_GPU_FEATURES_5:
73 *value = gpu->identity.minor_features4;
74 break;
75
76 case ETNAVIV_PARAM_GPU_FEATURES_6:
77 *value = gpu->identity.minor_features5;
78 break;
79
80 case ETNAVIV_PARAM_GPU_FEATURES_7:
81 *value = gpu->identity.minor_features6;
82 break;
83
84 case ETNAVIV_PARAM_GPU_FEATURES_8:
85 *value = gpu->identity.minor_features7;
86 break;
87
88 case ETNAVIV_PARAM_GPU_FEATURES_9:
89 *value = gpu->identity.minor_features8;
90 break;
91
92 case ETNAVIV_PARAM_GPU_FEATURES_10:
93 *value = gpu->identity.minor_features9;
94 break;
95
96 case ETNAVIV_PARAM_GPU_FEATURES_11:
97 *value = gpu->identity.minor_features10;
98 break;
99
100 case ETNAVIV_PARAM_GPU_FEATURES_12:
101 *value = gpu->identity.minor_features11;
102 break;
103
104 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
105 *value = gpu->identity.stream_count;
106 break;
107
108 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
109 *value = gpu->identity.register_max;
110 break;
111
112 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
113 *value = gpu->identity.thread_count;
114 break;
115
116 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
117 *value = gpu->identity.vertex_cache_size;
118 break;
119
120 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
121 *value = gpu->identity.shader_core_count;
122 break;
123
124 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
125 *value = gpu->identity.pixel_pipes;
126 break;
127
128 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
129 *value = gpu->identity.vertex_output_buffer_size;
130 break;
131
132 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
133 *value = gpu->identity.buffer_size;
134 break;
135
136 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
137 *value = gpu->identity.instruction_count;
138 break;
139
140 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
141 *value = gpu->identity.num_constants;
142 break;
143
144 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
145 *value = gpu->identity.varyings_count;
146 break;
147
148 case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
149 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
150 *value = ETNAVIV_SOFTPIN_START_ADDRESS;
151 else
152 *value = ~0ULL;
153 break;
154
155 case ETNAVIV_PARAM_GPU_PRODUCT_ID:
156 *value = gpu->identity.product_id;
157 break;
158
159 case ETNAVIV_PARAM_GPU_CUSTOMER_ID:
160 *value = gpu->identity.customer_id;
161 break;
162
163 case ETNAVIV_PARAM_GPU_ECO_ID:
164 *value = gpu->identity.eco_id;
165 break;
166
167 default:
168 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
169 return -EINVAL;
170 }
171
172 return 0;
173}
174
175
176#define etnaviv_is_model_rev(gpu, mod, rev) \
177 ((gpu)->identity.model == chipModel_##mod && \
178 (gpu)->identity.revision == rev)
179#define etnaviv_field(val, field) \
180 (((val) & field##__MASK) >> field##__SHIFT)
181
182static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
183{
184 if (gpu->identity.minor_features0 &
185 chipMinorFeatures0_MORE_MINOR_FEATURES) {
186 u32 specs[4];
187 unsigned int streams;
188
189 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
190 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
191 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
192 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
193
194 gpu->identity.stream_count = etnaviv_field(specs[0],
195 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
196 gpu->identity.register_max = etnaviv_field(specs[0],
197 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
198 gpu->identity.thread_count = etnaviv_field(specs[0],
199 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
200 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
201 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
202 gpu->identity.shader_core_count = etnaviv_field(specs[0],
203 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
204 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
205 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
206 gpu->identity.vertex_output_buffer_size =
207 etnaviv_field(specs[0],
208 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
209
210 gpu->identity.buffer_size = etnaviv_field(specs[1],
211 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
212 gpu->identity.instruction_count = etnaviv_field(specs[1],
213 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
214 gpu->identity.num_constants = etnaviv_field(specs[1],
215 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
216
217 gpu->identity.varyings_count = etnaviv_field(specs[2],
218 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
219
220
221 streams = etnaviv_field(specs[3],
222 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
223 if (streams)
224 gpu->identity.stream_count = streams;
225 }
226
227
228 if (gpu->identity.stream_count == 0) {
229 if (gpu->identity.model >= 0x1000)
230 gpu->identity.stream_count = 4;
231 else
232 gpu->identity.stream_count = 1;
233 }
234
235
236 if (gpu->identity.register_max)
237 gpu->identity.register_max = 1 << gpu->identity.register_max;
238 else if (gpu->identity.model == chipModel_GC400)
239 gpu->identity.register_max = 32;
240 else
241 gpu->identity.register_max = 64;
242
243
244 if (gpu->identity.thread_count)
245 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
246 else if (gpu->identity.model == chipModel_GC400)
247 gpu->identity.thread_count = 64;
248 else if (gpu->identity.model == chipModel_GC500 ||
249 gpu->identity.model == chipModel_GC530)
250 gpu->identity.thread_count = 128;
251 else
252 gpu->identity.thread_count = 256;
253
254 if (gpu->identity.vertex_cache_size == 0)
255 gpu->identity.vertex_cache_size = 8;
256
257 if (gpu->identity.shader_core_count == 0) {
258 if (gpu->identity.model >= 0x1000)
259 gpu->identity.shader_core_count = 2;
260 else
261 gpu->identity.shader_core_count = 1;
262 }
263
264 if (gpu->identity.pixel_pipes == 0)
265 gpu->identity.pixel_pipes = 1;
266
267
268 if (gpu->identity.vertex_output_buffer_size) {
269 gpu->identity.vertex_output_buffer_size =
270 1 << gpu->identity.vertex_output_buffer_size;
271 } else if (gpu->identity.model == chipModel_GC400) {
272 if (gpu->identity.revision < 0x4000)
273 gpu->identity.vertex_output_buffer_size = 512;
274 else if (gpu->identity.revision < 0x4200)
275 gpu->identity.vertex_output_buffer_size = 256;
276 else
277 gpu->identity.vertex_output_buffer_size = 128;
278 } else {
279 gpu->identity.vertex_output_buffer_size = 512;
280 }
281
282 switch (gpu->identity.instruction_count) {
283 case 0:
284 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
285 gpu->identity.model == chipModel_GC880)
286 gpu->identity.instruction_count = 512;
287 else
288 gpu->identity.instruction_count = 256;
289 break;
290
291 case 1:
292 gpu->identity.instruction_count = 1024;
293 break;
294
295 case 2:
296 gpu->identity.instruction_count = 2048;
297 break;
298
299 default:
300 gpu->identity.instruction_count = 256;
301 break;
302 }
303
304 if (gpu->identity.num_constants == 0)
305 gpu->identity.num_constants = 168;
306
307 if (gpu->identity.varyings_count == 0) {
308 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
309 gpu->identity.varyings_count = 12;
310 else
311 gpu->identity.varyings_count = 8;
312 }
313
314
315
316
317
318 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
319 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
320 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
321 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
322 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
323 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
324 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
325 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
326 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
327 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
328 etnaviv_is_model_rev(gpu, GC880, 0x5106))
329 gpu->identity.varyings_count -= 1;
330}
331
332static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
333{
334 u32 chipIdentity;
335
336 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
337
338
339 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
340 gpu->identity.model = chipModel_GC500;
341 gpu->identity.revision = etnaviv_field(chipIdentity,
342 VIVS_HI_CHIP_IDENTITY_REVISION);
343 } else {
344 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
345
346 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
347 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
348 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
349
350
351
352
353
354 if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
355 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
356 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
357 }
358
359
360
361
362
363
364
365 if ((gpu->identity.model & 0xff00) == 0x0400 &&
366 gpu->identity.model != chipModel_GC420) {
367 gpu->identity.model = gpu->identity.model & 0x0400;
368 }
369
370
371 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
372 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
373
374 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
375
376
377
378
379 gpu->identity.revision = 0x1051;
380 }
381 }
382
383
384
385
386
387
388
389
390 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
391 gpu->identity.model = chipModel_GC3000;
392 gpu->identity.revision &= 0xffff;
393 }
394
395 if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
396 gpu->identity.eco_id = 1;
397
398 if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
399 gpu->identity.eco_id = 1;
400 }
401
402 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
403 gpu->identity.model, gpu->identity.revision);
404
405 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
406
407
408
409
410 if (etnaviv_fill_identity_from_hwdb(gpu))
411 return;
412
413 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
414
415
416 if (gpu->identity.model == chipModel_GC700)
417 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
418
419 if ((gpu->identity.model == chipModel_GC500 &&
420 gpu->identity.revision < 2) ||
421 (gpu->identity.model == chipModel_GC300 &&
422 gpu->identity.revision < 0x2000)) {
423
424
425
426
427
428 gpu->identity.minor_features0 = 0;
429 gpu->identity.minor_features1 = 0;
430 gpu->identity.minor_features2 = 0;
431 gpu->identity.minor_features3 = 0;
432 gpu->identity.minor_features4 = 0;
433 gpu->identity.minor_features5 = 0;
434 } else
435 gpu->identity.minor_features0 =
436 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
437
438 if (gpu->identity.minor_features0 &
439 chipMinorFeatures0_MORE_MINOR_FEATURES) {
440 gpu->identity.minor_features1 =
441 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
442 gpu->identity.minor_features2 =
443 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
444 gpu->identity.minor_features3 =
445 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
446 gpu->identity.minor_features4 =
447 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
448 gpu->identity.minor_features5 =
449 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
450 }
451
452
453 if (gpu->identity.model == chipModel_GC600)
454 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
455 VIVS_HI_IDLE_STATE_RA |
456 VIVS_HI_IDLE_STATE_SE |
457 VIVS_HI_IDLE_STATE_PA |
458 VIVS_HI_IDLE_STATE_SH |
459 VIVS_HI_IDLE_STATE_PE |
460 VIVS_HI_IDLE_STATE_DE |
461 VIVS_HI_IDLE_STATE_FE;
462
463 etnaviv_hw_specs(gpu);
464}
465
466static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
467{
468 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
469 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
470 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
471}
472
473static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
474{
475 if (gpu->identity.minor_features2 &
476 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
477 clk_set_rate(gpu->clk_core,
478 gpu->base_rate_core >> gpu->freq_scale);
479 clk_set_rate(gpu->clk_shader,
480 gpu->base_rate_shader >> gpu->freq_scale);
481 } else {
482 unsigned int fscale = 1 << (6 - gpu->freq_scale);
483 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
484
485 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
486 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
487 etnaviv_gpu_load_clock(gpu, clock);
488 }
489}
490
491static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
492{
493 u32 control, idle;
494 unsigned long timeout;
495 bool failed = true;
496
497
498 timeout = jiffies + msecs_to_jiffies(1000);
499
500 while (time_is_after_jiffies(timeout)) {
501
502 unsigned int fscale = 1 << (6 - gpu->freq_scale);
503 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
504 etnaviv_gpu_load_clock(gpu, control);
505
506
507 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
508 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
509
510 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
511 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
512 VIVS_MMUv2_AHB_CONTROL_RESET);
513 } else {
514
515 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
516 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
517 }
518
519
520 usleep_range(10, 20);
521
522
523 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
524 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
525
526
527 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
528 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
529
530
531 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
532
533
534 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
535 dev_dbg(gpu->dev, "FE is not idle\n");
536 continue;
537 }
538
539
540 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
541
542
543 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
544 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
545 dev_dbg(gpu->dev, "GPU is not idle\n");
546 continue;
547 }
548
549
550 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
551 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
552
553 failed = false;
554 break;
555 }
556
557 if (failed) {
558 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
559 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
560
561 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
562 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
563 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
564 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
565
566 return -EBUSY;
567 }
568
569
570 etnaviv_gpu_update_clock(gpu);
571
572 return 0;
573}
574
575static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
576{
577 u32 pmc, ppc;
578
579
580 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
581 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
582
583
584 if (gpu->identity.revision == 0x4301 ||
585 gpu->identity.revision == 0x4302)
586 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
587
588 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
589
590 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
591
592
593 if (gpu->identity.model >= chipModel_GC400 &&
594 gpu->identity.model != chipModel_GC420 &&
595 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
596 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
597
598
599
600
601
602 if (gpu->identity.revision < 0x5000 &&
603 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
604 !(gpu->identity.minor_features1 &
605 chipMinorFeatures1_DISABLE_PE_GATING))
606 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
607
608 if (gpu->identity.revision < 0x5422)
609 pmc |= BIT(15);
610
611
612 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
613 etnaviv_is_model_rev(gpu, GC2000, 0x5108))
614 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
615
616 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
617 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
618
619 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
620}
621
622void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
623{
624 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
625 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
626 VIVS_FE_COMMAND_CONTROL_ENABLE |
627 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
628
629 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
630 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
631 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
632 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
633 }
634}
635
636static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu)
637{
638 u32 address = etnaviv_cmdbuf_get_va(&gpu->buffer,
639 &gpu->mmu_context->cmdbuf_mapping);
640 u16 prefetch;
641
642
643 etnaviv_iommu_restore(gpu, gpu->mmu_context);
644
645
646 prefetch = etnaviv_buffer_init(gpu);
647
648 etnaviv_gpu_start_fe(gpu, address, prefetch);
649}
650
651static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
652{
653
654
655
656
657 u32 pulse_eater = 0x01590880;
658
659 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
660 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
661 pulse_eater |= BIT(23);
662
663 }
664
665 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
666 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
667 pulse_eater &= ~BIT(16);
668 pulse_eater |= BIT(17);
669 }
670
671 if ((gpu->identity.revision > 0x5420) &&
672 (gpu->identity.features & chipFeatures_PIPE_3D))
673 {
674
675 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
676 pulse_eater |= BIT(18);
677 }
678
679 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
680}
681
682static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
683{
684 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
685 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
686 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
687 u32 mc_memory_debug;
688
689 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
690
691 if (gpu->identity.revision == 0x5007)
692 mc_memory_debug |= 0x0c;
693 else
694 mc_memory_debug |= 0x08;
695
696 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
697 }
698
699
700 etnaviv_gpu_enable_mlcg(gpu);
701
702
703
704
705
706 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
707 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
708 VIVS_HI_AXI_CONFIG_ARCACHE(2));
709
710
711 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
712 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
713 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
714 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
715 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
716 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
717 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
718 }
719
720 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
721 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
722 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
723 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
724 }
725
726
727 etnaviv_gpu_setup_pulse_eater(gpu);
728
729 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
730}
731
732int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
733{
734 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
735 dma_addr_t cmdbuf_paddr;
736 int ret, i;
737
738 ret = pm_runtime_get_sync(gpu->dev);
739 if (ret < 0) {
740 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
741 goto pm_put;
742 }
743
744 etnaviv_hw_identify(gpu);
745
746 if (gpu->identity.model == 0) {
747 dev_err(gpu->dev, "Unknown GPU model\n");
748 ret = -ENXIO;
749 goto fail;
750 }
751
752
753 if (gpu->identity.features & chipFeatures_PIPE_VG &&
754 gpu->identity.features & chipFeatures_FE20) {
755 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
756 ret = -ENXIO;
757 goto fail;
758 }
759
760
761
762
763
764 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
765 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
766 gpu->sec_mode = ETNA_SEC_KERNEL;
767
768 ret = etnaviv_hw_reset(gpu);
769 if (ret) {
770 dev_err(gpu->dev, "GPU reset failed\n");
771 goto fail;
772 }
773
774 ret = etnaviv_iommu_global_init(gpu);
775 if (ret)
776 goto fail;
777
778
779
780
781
782
783 if (dma_addressing_limited(gpu->dev))
784 priv->shm_gfp_mask |= GFP_DMA32;
785
786
787 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer,
788 PAGE_SIZE);
789 if (ret) {
790 dev_err(gpu->dev, "could not create command buffer\n");
791 goto fail;
792 }
793
794
795
796
797
798
799
800
801
802
803
804 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
805
806 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
807 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
808 if (cmdbuf_paddr >= SZ_2G)
809 priv->mmu_global->memory_base = SZ_2G;
810 else
811 priv->mmu_global->memory_base = cmdbuf_paddr;
812 } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {
813 dev_info(gpu->dev,
814 "Need to move linear window on MC1.0, disabling TS\n");
815 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
816 priv->mmu_global->memory_base = SZ_2G;
817 }
818
819
820 spin_lock_init(&gpu->event_spinlock);
821 init_completion(&gpu->event_free);
822 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
823 for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
824 complete(&gpu->event_free);
825
826
827 mutex_lock(&gpu->lock);
828 etnaviv_gpu_hw_init(gpu);
829 gpu->exec_state = -1;
830 mutex_unlock(&gpu->lock);
831
832 pm_runtime_mark_last_busy(gpu->dev);
833 pm_runtime_put_autosuspend(gpu->dev);
834
835 gpu->initialized = true;
836
837 return 0;
838
839fail:
840 pm_runtime_mark_last_busy(gpu->dev);
841pm_put:
842 pm_runtime_put_autosuspend(gpu->dev);
843
844 return ret;
845}
846
847#ifdef CONFIG_DEBUG_FS
848struct dma_debug {
849 u32 address[2];
850 u32 state[2];
851};
852
853static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
854{
855 u32 i;
856
857 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
858 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
859
860 for (i = 0; i < 500; i++) {
861 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
862 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
863
864 if (debug->address[0] != debug->address[1])
865 break;
866
867 if (debug->state[0] != debug->state[1])
868 break;
869 }
870}
871
872int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
873{
874 struct dma_debug debug;
875 u32 dma_lo, dma_hi, axi, idle;
876 int ret;
877
878 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
879
880 ret = pm_runtime_get_sync(gpu->dev);
881 if (ret < 0)
882 goto pm_put;
883
884 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
885 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
886 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
887 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
888
889 verify_dma(gpu, &debug);
890
891 seq_puts(m, "\tidentity\n");
892 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
893 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
894 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
895 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
896 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
897
898 seq_puts(m, "\tfeatures\n");
899 seq_printf(m, "\t major_features: 0x%08x\n",
900 gpu->identity.features);
901 seq_printf(m, "\t minor_features0: 0x%08x\n",
902 gpu->identity.minor_features0);
903 seq_printf(m, "\t minor_features1: 0x%08x\n",
904 gpu->identity.minor_features1);
905 seq_printf(m, "\t minor_features2: 0x%08x\n",
906 gpu->identity.minor_features2);
907 seq_printf(m, "\t minor_features3: 0x%08x\n",
908 gpu->identity.minor_features3);
909 seq_printf(m, "\t minor_features4: 0x%08x\n",
910 gpu->identity.minor_features4);
911 seq_printf(m, "\t minor_features5: 0x%08x\n",
912 gpu->identity.minor_features5);
913 seq_printf(m, "\t minor_features6: 0x%08x\n",
914 gpu->identity.minor_features6);
915 seq_printf(m, "\t minor_features7: 0x%08x\n",
916 gpu->identity.minor_features7);
917 seq_printf(m, "\t minor_features8: 0x%08x\n",
918 gpu->identity.minor_features8);
919 seq_printf(m, "\t minor_features9: 0x%08x\n",
920 gpu->identity.minor_features9);
921 seq_printf(m, "\t minor_features10: 0x%08x\n",
922 gpu->identity.minor_features10);
923 seq_printf(m, "\t minor_features11: 0x%08x\n",
924 gpu->identity.minor_features11);
925
926 seq_puts(m, "\tspecs\n");
927 seq_printf(m, "\t stream_count: %d\n",
928 gpu->identity.stream_count);
929 seq_printf(m, "\t register_max: %d\n",
930 gpu->identity.register_max);
931 seq_printf(m, "\t thread_count: %d\n",
932 gpu->identity.thread_count);
933 seq_printf(m, "\t vertex_cache_size: %d\n",
934 gpu->identity.vertex_cache_size);
935 seq_printf(m, "\t shader_core_count: %d\n",
936 gpu->identity.shader_core_count);
937 seq_printf(m, "\t pixel_pipes: %d\n",
938 gpu->identity.pixel_pipes);
939 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
940 gpu->identity.vertex_output_buffer_size);
941 seq_printf(m, "\t buffer_size: %d\n",
942 gpu->identity.buffer_size);
943 seq_printf(m, "\t instruction_count: %d\n",
944 gpu->identity.instruction_count);
945 seq_printf(m, "\t num_constants: %d\n",
946 gpu->identity.num_constants);
947 seq_printf(m, "\t varyings_count: %d\n",
948 gpu->identity.varyings_count);
949
950 seq_printf(m, "\taxi: 0x%08x\n", axi);
951 seq_printf(m, "\tidle: 0x%08x\n", idle);
952 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
953 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
954 seq_puts(m, "\t FE is not idle\n");
955 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
956 seq_puts(m, "\t DE is not idle\n");
957 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
958 seq_puts(m, "\t PE is not idle\n");
959 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
960 seq_puts(m, "\t SH is not idle\n");
961 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
962 seq_puts(m, "\t PA is not idle\n");
963 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
964 seq_puts(m, "\t SE is not idle\n");
965 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
966 seq_puts(m, "\t RA is not idle\n");
967 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
968 seq_puts(m, "\t TX is not idle\n");
969 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
970 seq_puts(m, "\t VG is not idle\n");
971 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
972 seq_puts(m, "\t IM is not idle\n");
973 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
974 seq_puts(m, "\t FP is not idle\n");
975 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
976 seq_puts(m, "\t TS is not idle\n");
977 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
978 seq_puts(m, "\t BL is not idle\n");
979 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
980 seq_puts(m, "\t ASYNCFE is not idle\n");
981 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
982 seq_puts(m, "\t MC is not idle\n");
983 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
984 seq_puts(m, "\t PPA is not idle\n");
985 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
986 seq_puts(m, "\t WD is not idle\n");
987 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
988 seq_puts(m, "\t NN is not idle\n");
989 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
990 seq_puts(m, "\t TP is not idle\n");
991 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
992 seq_puts(m, "\t AXI low power mode\n");
993
994 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
995 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
996 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
997 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
998
999 seq_puts(m, "\tMC\n");
1000 seq_printf(m, "\t read0: 0x%08x\n", read0);
1001 seq_printf(m, "\t read1: 0x%08x\n", read1);
1002 seq_printf(m, "\t write: 0x%08x\n", write);
1003 }
1004
1005 seq_puts(m, "\tDMA ");
1006
1007 if (debug.address[0] == debug.address[1] &&
1008 debug.state[0] == debug.state[1]) {
1009 seq_puts(m, "seems to be stuck\n");
1010 } else if (debug.address[0] == debug.address[1]) {
1011 seq_puts(m, "address is constant\n");
1012 } else {
1013 seq_puts(m, "is running\n");
1014 }
1015
1016 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1017 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1018 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1019 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1020 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1021 dma_lo, dma_hi);
1022
1023 ret = 0;
1024
1025 pm_runtime_mark_last_busy(gpu->dev);
1026pm_put:
1027 pm_runtime_put_autosuspend(gpu->dev);
1028
1029 return ret;
1030}
1031#endif
1032
1033void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
1034{
1035 unsigned int i = 0;
1036
1037 dev_err(gpu->dev, "recover hung GPU!\n");
1038
1039 if (pm_runtime_get_sync(gpu->dev) < 0)
1040 goto pm_put;
1041
1042 mutex_lock(&gpu->lock);
1043
1044 etnaviv_hw_reset(gpu);
1045
1046
1047 spin_lock(&gpu->event_spinlock);
1048 for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1049 complete(&gpu->event_free);
1050 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
1051 spin_unlock(&gpu->event_spinlock);
1052
1053 etnaviv_gpu_hw_init(gpu);
1054 gpu->exec_state = -1;
1055 gpu->mmu_context = NULL;
1056
1057 mutex_unlock(&gpu->lock);
1058 pm_runtime_mark_last_busy(gpu->dev);
1059pm_put:
1060 pm_runtime_put_autosuspend(gpu->dev);
1061}
1062
1063
1064struct etnaviv_fence {
1065 struct etnaviv_gpu *gpu;
1066 struct dma_fence base;
1067};
1068
1069static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1070{
1071 return container_of(fence, struct etnaviv_fence, base);
1072}
1073
1074static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1075{
1076 return "etnaviv";
1077}
1078
1079static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1080{
1081 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1082
1083 return dev_name(f->gpu->dev);
1084}
1085
1086static bool etnaviv_fence_signaled(struct dma_fence *fence)
1087{
1088 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1089
1090 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1091}
1092
1093static void etnaviv_fence_release(struct dma_fence *fence)
1094{
1095 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1096
1097 kfree_rcu(f, base.rcu);
1098}
1099
1100static const struct dma_fence_ops etnaviv_fence_ops = {
1101 .get_driver_name = etnaviv_fence_get_driver_name,
1102 .get_timeline_name = etnaviv_fence_get_timeline_name,
1103 .signaled = etnaviv_fence_signaled,
1104 .release = etnaviv_fence_release,
1105};
1106
1107static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1108{
1109 struct etnaviv_fence *f;
1110
1111
1112
1113
1114
1115 lockdep_assert_held(&gpu->lock);
1116
1117 f = kzalloc(sizeof(*f), GFP_KERNEL);
1118 if (!f)
1119 return NULL;
1120
1121 f->gpu = gpu;
1122
1123 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1124 gpu->fence_context, ++gpu->next_fence);
1125
1126 return &f->base;
1127}
1128
1129
1130static inline bool fence_after(u32 a, u32 b)
1131{
1132 return (s32)(a - b) > 0;
1133}
1134
1135
1136
1137
1138
1139static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1140 unsigned int *events)
1141{
1142 unsigned long timeout = msecs_to_jiffies(10 * 10000);
1143 unsigned i, acquired = 0;
1144
1145 for (i = 0; i < nr_events; i++) {
1146 unsigned long ret;
1147
1148 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1149
1150 if (!ret) {
1151 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1152 goto out;
1153 }
1154
1155 acquired++;
1156 timeout = ret;
1157 }
1158
1159 spin_lock(&gpu->event_spinlock);
1160
1161 for (i = 0; i < nr_events; i++) {
1162 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1163
1164 events[i] = event;
1165 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1166 set_bit(event, gpu->event_bitmap);
1167 }
1168
1169 spin_unlock(&gpu->event_spinlock);
1170
1171 return 0;
1172
1173out:
1174 for (i = 0; i < acquired; i++)
1175 complete(&gpu->event_free);
1176
1177 return -EBUSY;
1178}
1179
1180static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1181{
1182 if (!test_bit(event, gpu->event_bitmap)) {
1183 dev_warn(gpu->dev, "event %u is already marked as free",
1184 event);
1185 } else {
1186 clear_bit(event, gpu->event_bitmap);
1187 complete(&gpu->event_free);
1188 }
1189}
1190
1191
1192
1193
1194int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1195 u32 id, struct drm_etnaviv_timespec *timeout)
1196{
1197 struct dma_fence *fence;
1198 int ret;
1199
1200
1201
1202
1203
1204
1205 rcu_read_lock();
1206 fence = idr_find(&gpu->fence_idr, id);
1207 if (fence)
1208 fence = dma_fence_get_rcu(fence);
1209 rcu_read_unlock();
1210
1211 if (!fence)
1212 return 0;
1213
1214 if (!timeout) {
1215
1216 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1217 } else {
1218 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1219
1220 ret = dma_fence_wait_timeout(fence, true, remaining);
1221 if (ret == 0)
1222 ret = -ETIMEDOUT;
1223 else if (ret != -ERESTARTSYS)
1224 ret = 0;
1225
1226 }
1227
1228 dma_fence_put(fence);
1229 return ret;
1230}
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1242 struct etnaviv_gem_object *etnaviv_obj,
1243 struct drm_etnaviv_timespec *timeout)
1244{
1245 unsigned long remaining;
1246 long ret;
1247
1248 if (!timeout)
1249 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1250
1251 remaining = etnaviv_timeout_to_jiffies(timeout);
1252
1253 ret = wait_event_interruptible_timeout(gpu->fence_event,
1254 !is_active(etnaviv_obj),
1255 remaining);
1256 if (ret > 0)
1257 return 0;
1258 else if (ret == -ERESTARTSYS)
1259 return -ERESTARTSYS;
1260 else
1261 return -ETIMEDOUT;
1262}
1263
1264static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1265 struct etnaviv_event *event, unsigned int flags)
1266{
1267 const struct etnaviv_gem_submit *submit = event->submit;
1268 unsigned int i;
1269
1270 for (i = 0; i < submit->nr_pmrs; i++) {
1271 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1272
1273 if (pmr->flags == flags)
1274 etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1275 }
1276}
1277
1278static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1279 struct etnaviv_event *event)
1280{
1281 u32 val;
1282
1283
1284 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1285 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1286 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1287
1288
1289 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1290 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1291 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1292
1293 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1294}
1295
1296static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1297 struct etnaviv_event *event)
1298{
1299 const struct etnaviv_gem_submit *submit = event->submit;
1300 unsigned int i;
1301 u32 val;
1302
1303 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1304
1305 for (i = 0; i < submit->nr_pmrs; i++) {
1306 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1307
1308 *pmr->bo_vma = pmr->sequence;
1309 }
1310
1311
1312 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1313 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1314 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1315
1316
1317 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1318 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1319 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1320}
1321
1322
1323
1324struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1325{
1326 struct etnaviv_gpu *gpu = submit->gpu;
1327 struct dma_fence *gpu_fence;
1328 unsigned int i, nr_events = 1, event[3];
1329 int ret;
1330
1331 if (!submit->runtime_resumed) {
1332 ret = pm_runtime_get_sync(gpu->dev);
1333 if (ret < 0) {
1334 pm_runtime_put_noidle(gpu->dev);
1335 return NULL;
1336 }
1337 submit->runtime_resumed = true;
1338 }
1339
1340
1341
1342
1343
1344
1345
1346
1347 if (submit->nr_pmrs)
1348 nr_events = 3;
1349
1350 ret = event_alloc(gpu, nr_events, event);
1351 if (ret) {
1352 DRM_ERROR("no free events\n");
1353 pm_runtime_put_noidle(gpu->dev);
1354 return NULL;
1355 }
1356
1357 mutex_lock(&gpu->lock);
1358
1359 gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1360 if (!gpu_fence) {
1361 for (i = 0; i < nr_events; i++)
1362 event_free(gpu, event[i]);
1363
1364 goto out_unlock;
1365 }
1366
1367 if (!gpu->mmu_context) {
1368 etnaviv_iommu_context_get(submit->mmu_context);
1369 gpu->mmu_context = submit->mmu_context;
1370 etnaviv_gpu_start_fe_idleloop(gpu);
1371 } else {
1372 etnaviv_iommu_context_get(gpu->mmu_context);
1373 submit->prev_mmu_context = gpu->mmu_context;
1374 }
1375
1376 if (submit->nr_pmrs) {
1377 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1378 kref_get(&submit->refcount);
1379 gpu->event[event[1]].submit = submit;
1380 etnaviv_sync_point_queue(gpu, event[1]);
1381 }
1382
1383 gpu->event[event[0]].fence = gpu_fence;
1384 submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1385 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1386 event[0], &submit->cmdbuf);
1387
1388 if (submit->nr_pmrs) {
1389 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1390 kref_get(&submit->refcount);
1391 gpu->event[event[2]].submit = submit;
1392 etnaviv_sync_point_queue(gpu, event[2]);
1393 }
1394
1395out_unlock:
1396 mutex_unlock(&gpu->lock);
1397
1398 return gpu_fence;
1399}
1400
1401static void sync_point_worker(struct work_struct *work)
1402{
1403 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1404 sync_point_work);
1405 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1406 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1407
1408 event->sync_point(gpu, event);
1409 etnaviv_submit_put(event->submit);
1410 event_free(gpu, gpu->sync_point_event);
1411
1412
1413 etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1414}
1415
1416static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1417{
1418 u32 status_reg, status;
1419 int i;
1420
1421 if (gpu->sec_mode == ETNA_SEC_NONE)
1422 status_reg = VIVS_MMUv2_STATUS;
1423 else
1424 status_reg = VIVS_MMUv2_SEC_STATUS;
1425
1426 status = gpu_read(gpu, status_reg);
1427 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1428
1429 for (i = 0; i < 4; i++) {
1430 u32 address_reg;
1431
1432 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1433 continue;
1434
1435 if (gpu->sec_mode == ETNA_SEC_NONE)
1436 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1437 else
1438 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1439
1440 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1441 gpu_read(gpu, address_reg));
1442 }
1443}
1444
1445static irqreturn_t irq_handler(int irq, void *data)
1446{
1447 struct etnaviv_gpu *gpu = data;
1448 irqreturn_t ret = IRQ_NONE;
1449
1450 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1451
1452 if (intr != 0) {
1453 int event;
1454
1455 pm_runtime_mark_last_busy(gpu->dev);
1456
1457 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1458
1459 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1460 dev_err(gpu->dev, "AXI bus error\n");
1461 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1462 }
1463
1464 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1465 dump_mmu_fault(gpu);
1466 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1467 }
1468
1469 while ((event = ffs(intr)) != 0) {
1470 struct dma_fence *fence;
1471
1472 event -= 1;
1473
1474 intr &= ~(1 << event);
1475
1476 dev_dbg(gpu->dev, "event %u\n", event);
1477
1478 if (gpu->event[event].sync_point) {
1479 gpu->sync_point_event = event;
1480 queue_work(gpu->wq, &gpu->sync_point_work);
1481 }
1482
1483 fence = gpu->event[event].fence;
1484 if (!fence)
1485 continue;
1486
1487 gpu->event[event].fence = NULL;
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498 if (fence_after(fence->seqno, gpu->completed_fence))
1499 gpu->completed_fence = fence->seqno;
1500 dma_fence_signal(fence);
1501
1502 event_free(gpu, event);
1503 }
1504
1505 ret = IRQ_HANDLED;
1506 }
1507
1508 return ret;
1509}
1510
1511static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1512{
1513 int ret;
1514
1515 ret = clk_prepare_enable(gpu->clk_reg);
1516 if (ret)
1517 return ret;
1518
1519 ret = clk_prepare_enable(gpu->clk_bus);
1520 if (ret)
1521 goto disable_clk_reg;
1522
1523 ret = clk_prepare_enable(gpu->clk_core);
1524 if (ret)
1525 goto disable_clk_bus;
1526
1527 ret = clk_prepare_enable(gpu->clk_shader);
1528 if (ret)
1529 goto disable_clk_core;
1530
1531 return 0;
1532
1533disable_clk_core:
1534 clk_disable_unprepare(gpu->clk_core);
1535disable_clk_bus:
1536 clk_disable_unprepare(gpu->clk_bus);
1537disable_clk_reg:
1538 clk_disable_unprepare(gpu->clk_reg);
1539
1540 return ret;
1541}
1542
1543static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1544{
1545 clk_disable_unprepare(gpu->clk_shader);
1546 clk_disable_unprepare(gpu->clk_core);
1547 clk_disable_unprepare(gpu->clk_bus);
1548 clk_disable_unprepare(gpu->clk_reg);
1549
1550 return 0;
1551}
1552
1553int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1554{
1555 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1556
1557 do {
1558 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1559
1560 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1561 return 0;
1562
1563 if (time_is_before_jiffies(timeout)) {
1564 dev_warn(gpu->dev,
1565 "timed out waiting for idle: idle=0x%x\n",
1566 idle);
1567 return -ETIMEDOUT;
1568 }
1569
1570 udelay(5);
1571 } while (1);
1572}
1573
1574static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1575{
1576 if (gpu->initialized && gpu->mmu_context) {
1577
1578 mutex_lock(&gpu->lock);
1579 etnaviv_buffer_end(gpu);
1580 mutex_unlock(&gpu->lock);
1581
1582
1583
1584
1585
1586
1587 etnaviv_gpu_wait_idle(gpu, 100);
1588
1589 etnaviv_iommu_context_put(gpu->mmu_context);
1590 gpu->mmu_context = NULL;
1591 }
1592
1593 gpu->exec_state = -1;
1594
1595 return etnaviv_gpu_clk_disable(gpu);
1596}
1597
1598#ifdef CONFIG_PM
1599static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1600{
1601 int ret;
1602
1603 ret = mutex_lock_killable(&gpu->lock);
1604 if (ret)
1605 return ret;
1606
1607 etnaviv_gpu_update_clock(gpu);
1608 etnaviv_gpu_hw_init(gpu);
1609
1610 mutex_unlock(&gpu->lock);
1611
1612 return 0;
1613}
1614#endif
1615
1616static int
1617etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1618 unsigned long *state)
1619{
1620 *state = 6;
1621
1622 return 0;
1623}
1624
1625static int
1626etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1627 unsigned long *state)
1628{
1629 struct etnaviv_gpu *gpu = cdev->devdata;
1630
1631 *state = gpu->freq_scale;
1632
1633 return 0;
1634}
1635
1636static int
1637etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1638 unsigned long state)
1639{
1640 struct etnaviv_gpu *gpu = cdev->devdata;
1641
1642 mutex_lock(&gpu->lock);
1643 gpu->freq_scale = state;
1644 if (!pm_runtime_suspended(gpu->dev))
1645 etnaviv_gpu_update_clock(gpu);
1646 mutex_unlock(&gpu->lock);
1647
1648 return 0;
1649}
1650
1651static struct thermal_cooling_device_ops cooling_ops = {
1652 .get_max_state = etnaviv_gpu_cooling_get_max_state,
1653 .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1654 .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1655};
1656
1657static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1658 void *data)
1659{
1660 struct drm_device *drm = data;
1661 struct etnaviv_drm_private *priv = drm->dev_private;
1662 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1663 int ret;
1664
1665 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1666 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1667 (char *)dev_name(dev), gpu, &cooling_ops);
1668 if (IS_ERR(gpu->cooling))
1669 return PTR_ERR(gpu->cooling);
1670 }
1671
1672 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1673 if (!gpu->wq) {
1674 ret = -ENOMEM;
1675 goto out_thermal;
1676 }
1677
1678 ret = etnaviv_sched_init(gpu);
1679 if (ret)
1680 goto out_workqueue;
1681
1682#ifdef CONFIG_PM
1683 ret = pm_runtime_get_sync(gpu->dev);
1684#else
1685 ret = etnaviv_gpu_clk_enable(gpu);
1686#endif
1687 if (ret < 0)
1688 goto out_sched;
1689
1690
1691 gpu->drm = drm;
1692 gpu->fence_context = dma_fence_context_alloc(1);
1693 idr_init(&gpu->fence_idr);
1694 spin_lock_init(&gpu->fence_spinlock);
1695
1696 INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1697 init_waitqueue_head(&gpu->fence_event);
1698
1699 priv->gpu[priv->num_gpus++] = gpu;
1700
1701 pm_runtime_mark_last_busy(gpu->dev);
1702 pm_runtime_put_autosuspend(gpu->dev);
1703
1704 return 0;
1705
1706out_sched:
1707 etnaviv_sched_fini(gpu);
1708
1709out_workqueue:
1710 destroy_workqueue(gpu->wq);
1711
1712out_thermal:
1713 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1714 thermal_cooling_device_unregister(gpu->cooling);
1715
1716 return ret;
1717}
1718
1719static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1720 void *data)
1721{
1722 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1723
1724 DBG("%s", dev_name(gpu->dev));
1725
1726 flush_workqueue(gpu->wq);
1727 destroy_workqueue(gpu->wq);
1728
1729 etnaviv_sched_fini(gpu);
1730
1731#ifdef CONFIG_PM
1732 pm_runtime_get_sync(gpu->dev);
1733 pm_runtime_put_sync_suspend(gpu->dev);
1734#else
1735 etnaviv_gpu_hw_suspend(gpu);
1736#endif
1737
1738 if (gpu->initialized) {
1739 etnaviv_cmdbuf_free(&gpu->buffer);
1740 etnaviv_iommu_global_fini(gpu);
1741 gpu->initialized = false;
1742 }
1743
1744 gpu->drm = NULL;
1745 idr_destroy(&gpu->fence_idr);
1746
1747 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1748 thermal_cooling_device_unregister(gpu->cooling);
1749 gpu->cooling = NULL;
1750}
1751
1752static const struct component_ops gpu_ops = {
1753 .bind = etnaviv_gpu_bind,
1754 .unbind = etnaviv_gpu_unbind,
1755};
1756
1757static const struct of_device_id etnaviv_gpu_match[] = {
1758 {
1759 .compatible = "vivante,gc"
1760 },
1761 { }
1762};
1763MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1764
1765static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1766{
1767 struct device *dev = &pdev->dev;
1768 struct etnaviv_gpu *gpu;
1769 int err;
1770
1771 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1772 if (!gpu)
1773 return -ENOMEM;
1774
1775 gpu->dev = &pdev->dev;
1776 mutex_init(&gpu->lock);
1777 mutex_init(&gpu->fence_lock);
1778
1779
1780 gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1781 if (IS_ERR(gpu->mmio))
1782 return PTR_ERR(gpu->mmio);
1783
1784
1785 gpu->irq = platform_get_irq(pdev, 0);
1786 if (gpu->irq < 0)
1787 return gpu->irq;
1788
1789 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1790 dev_name(gpu->dev), gpu);
1791 if (err) {
1792 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1793 return err;
1794 }
1795
1796
1797 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
1798 DBG("clk_reg: %p", gpu->clk_reg);
1799 if (IS_ERR(gpu->clk_reg))
1800 return PTR_ERR(gpu->clk_reg);
1801
1802 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
1803 DBG("clk_bus: %p", gpu->clk_bus);
1804 if (IS_ERR(gpu->clk_bus))
1805 return PTR_ERR(gpu->clk_bus);
1806
1807 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1808 DBG("clk_core: %p", gpu->clk_core);
1809 if (IS_ERR(gpu->clk_core))
1810 return PTR_ERR(gpu->clk_core);
1811 gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1812
1813 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
1814 DBG("clk_shader: %p", gpu->clk_shader);
1815 if (IS_ERR(gpu->clk_shader))
1816 return PTR_ERR(gpu->clk_shader);
1817 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1818
1819
1820 dev_set_drvdata(dev, gpu);
1821
1822
1823
1824
1825
1826
1827 pm_runtime_use_autosuspend(gpu->dev);
1828 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1829 pm_runtime_enable(gpu->dev);
1830
1831 err = component_add(&pdev->dev, &gpu_ops);
1832 if (err < 0) {
1833 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1834 return err;
1835 }
1836
1837 return 0;
1838}
1839
1840static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1841{
1842 component_del(&pdev->dev, &gpu_ops);
1843 pm_runtime_disable(&pdev->dev);
1844 return 0;
1845}
1846
1847#ifdef CONFIG_PM
1848static int etnaviv_gpu_rpm_suspend(struct device *dev)
1849{
1850 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1851 u32 idle, mask;
1852
1853
1854 if (atomic_read(&gpu->sched.hw_rq_count))
1855 return -EBUSY;
1856
1857
1858 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1859 VIVS_HI_IDLE_STATE_MC);
1860 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1861 if (idle != mask) {
1862 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1863 idle);
1864 return -EBUSY;
1865 }
1866
1867 return etnaviv_gpu_hw_suspend(gpu);
1868}
1869
1870static int etnaviv_gpu_rpm_resume(struct device *dev)
1871{
1872 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1873 int ret;
1874
1875 ret = etnaviv_gpu_clk_enable(gpu);
1876 if (ret)
1877 return ret;
1878
1879
1880 if (gpu->drm && gpu->initialized) {
1881 ret = etnaviv_gpu_hw_resume(gpu);
1882 if (ret) {
1883 etnaviv_gpu_clk_disable(gpu);
1884 return ret;
1885 }
1886 }
1887
1888 return 0;
1889}
1890#endif
1891
1892static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1893 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1894 NULL)
1895};
1896
1897struct platform_driver etnaviv_gpu_driver = {
1898 .driver = {
1899 .name = "etnaviv-gpu",
1900 .owner = THIS_MODULE,
1901 .pm = &etnaviv_gpu_pm_ops,
1902 .of_match_table = etnaviv_gpu_match,
1903 },
1904 .probe = etnaviv_gpu_platform_probe,
1905 .remove = etnaviv_gpu_platform_remove,
1906 .id_table = gpu_ids,
1907};
1908
