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9
10#include <linux/clk.h>
11#include <linux/component.h>
12#include <linux/kernel.h>
13#include <linux/mfd/syscon.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18
19#include <drm/drm_fourcc.h>
20#include <drm/drm_print.h>
21#include <drm/exynos_drm.h>
22
23#include "exynos_drm_drv.h"
24#include "exynos_drm_ipp.h"
25#include "regs-gsc.h"
26
27
28
29
30
31
32
33
34
35
36#define GSC_MAX_CLOCKS 8
37#define GSC_MAX_SRC 4
38#define GSC_MAX_DST 16
39#define GSC_RESET_TIMEOUT 50
40#define GSC_BUF_STOP 1
41#define GSC_BUF_START 2
42#define GSC_REG_SZ 16
43#define GSC_WIDTH_ITU_709 1280
44#define GSC_SC_UP_MAX_RATIO 65536
45#define GSC_SC_DOWN_RATIO_7_8 74898
46#define GSC_SC_DOWN_RATIO_6_8 87381
47#define GSC_SC_DOWN_RATIO_5_8 104857
48#define GSC_SC_DOWN_RATIO_4_8 131072
49#define GSC_SC_DOWN_RATIO_3_8 174762
50#define GSC_SC_DOWN_RATIO_2_8 262144
51#define GSC_CROP_MAX 8192
52#define GSC_CROP_MIN 32
53#define GSC_SCALE_MAX 4224
54#define GSC_SCALE_MIN 32
55#define GSC_COEF_RATIO 7
56#define GSC_COEF_PHASE 9
57#define GSC_COEF_ATTR 16
58#define GSC_COEF_H_8T 8
59#define GSC_COEF_V_4T 4
60#define GSC_COEF_DEPTH 3
61#define GSC_AUTOSUSPEND_DELAY 2000
62
63#define get_gsc_context(dev) dev_get_drvdata(dev)
64#define gsc_read(offset) readl(ctx->regs + (offset))
65#define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
66
67
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75
76
77struct gsc_scaler {
78 bool range;
79 u32 pre_shfactor;
80 u32 pre_hratio;
81 u32 pre_vratio;
82 unsigned long main_hratio;
83 unsigned long main_vratio;
84};
85
86
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94
95
96
97struct gsc_context {
98 struct exynos_drm_ipp ipp;
99 struct drm_device *drm_dev;
100 void *dma_priv;
101 struct device *dev;
102 struct exynos_drm_ipp_task *task;
103 struct exynos_drm_ipp_formats *formats;
104 unsigned int num_formats;
105
106 struct resource *regs_res;
107 void __iomem *regs;
108 const char **clk_names;
109 struct clk *clocks[GSC_MAX_CLOCKS];
110 int num_clocks;
111 struct gsc_scaler sc;
112 int id;
113 int irq;
114 bool rotation;
115};
116
117
118
119
120
121
122
123
124
125struct gsc_driverdata {
126 const struct drm_exynos_ipp_limit *limits;
127 int num_limits;
128 const char *clk_names[GSC_MAX_CLOCKS];
129 int num_clocks;
130};
131
132
133static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = {
134 {
135 { 0, 0, 0, 128, 0, 0, 0, 0 },
136 { -1, 2, -6, 127, 7, -2, 1, 0 },
137 { -1, 4, -12, 125, 16, -5, 1, 0 },
138 { -1, 5, -15, 120, 25, -8, 2, 0 },
139 { -1, 6, -18, 114, 35, -10, 3, -1 },
140 { -1, 6, -20, 107, 46, -13, 4, -1 },
141 { -2, 7, -21, 99, 57, -16, 5, -1 },
142 { -1, 6, -20, 89, 68, -18, 5, -1 },
143 { -1, 6, -20, 79, 79, -20, 6, -1 },
144 { -1, 5, -18, 68, 89, -20, 6, -1 },
145 { -1, 5, -16, 57, 99, -21, 7, -2 },
146 { -1, 4, -13, 46, 107, -20, 6, -1 },
147 { -1, 3, -10, 35, 114, -18, 6, -1 },
148 { 0, 2, -8, 25, 120, -15, 5, -1 },
149 { 0, 1, -5, 16, 125, -12, 4, -1 },
150 { 0, 1, -2, 7, 127, -6, 2, -1 }
151 }, {
152 { 3, -8, 14, 111, 13, -8, 3, 0 },
153 { 2, -6, 7, 112, 21, -10, 3, -1 },
154 { 2, -4, 1, 110, 28, -12, 4, -1 },
155 { 1, -2, -3, 106, 36, -13, 4, -1 },
156 { 1, -1, -7, 103, 44, -15, 4, -1 },
157 { 1, 1, -11, 97, 53, -16, 4, -1 },
158 { 0, 2, -13, 91, 61, -16, 4, -1 },
159 { 0, 3, -15, 85, 69, -17, 4, -1 },
160 { 0, 3, -16, 77, 77, -16, 3, 0 },
161 { -1, 4, -17, 69, 85, -15, 3, 0 },
162 { -1, 4, -16, 61, 91, -13, 2, 0 },
163 { -1, 4, -16, 53, 97, -11, 1, 1 },
164 { -1, 4, -15, 44, 103, -7, -1, 1 },
165 { -1, 4, -13, 36, 106, -3, -2, 1 },
166 { -1, 4, -12, 28, 110, 1, -4, 2 },
167 { -1, 3, -10, 21, 112, 7, -6, 2 }
168 }, {
169 { 2, -11, 25, 96, 25, -11, 2, 0 },
170 { 2, -10, 19, 96, 31, -12, 2, 0 },
171 { 2, -9, 14, 94, 37, -12, 2, 0 },
172 { 2, -8, 10, 92, 43, -12, 1, 0 },
173 { 2, -7, 5, 90, 49, -12, 1, 0 },
174 { 2, -5, 1, 86, 55, -12, 0, 1 },
175 { 2, -4, -2, 82, 61, -11, -1, 1 },
176 { 1, -3, -5, 77, 67, -9, -1, 1 },
177 { 1, -2, -7, 72, 72, -7, -2, 1 },
178 { 1, -1, -9, 67, 77, -5, -3, 1 },
179 { 1, -1, -11, 61, 82, -2, -4, 2 },
180 { 1, 0, -12, 55, 86, 1, -5, 2 },
181 { 0, 1, -12, 49, 90, 5, -7, 2 },
182 { 0, 1, -12, 43, 92, 10, -8, 2 },
183 { 0, 2, -12, 37, 94, 14, -9, 2 },
184 { 0, 2, -12, 31, 96, 19, -10, 2 }
185 }, {
186 { -1, -8, 33, 80, 33, -8, -1, 0 },
187 { -1, -8, 28, 80, 37, -7, -2, 1 },
188 { 0, -8, 24, 79, 41, -7, -2, 1 },
189 { 0, -8, 20, 78, 46, -6, -3, 1 },
190 { 0, -8, 16, 76, 50, -4, -3, 1 },
191 { 0, -7, 13, 74, 54, -3, -4, 1 },
192 { 1, -7, 10, 71, 58, -1, -5, 1 },
193 { 1, -6, 6, 68, 62, 1, -5, 1 },
194 { 1, -6, 4, 65, 65, 4, -6, 1 },
195 { 1, -5, 1, 62, 68, 6, -6, 1 },
196 { 1, -5, -1, 58, 71, 10, -7, 1 },
197 { 1, -4, -3, 54, 74, 13, -7, 0 },
198 { 1, -3, -4, 50, 76, 16, -8, 0 },
199 { 1, -3, -6, 46, 78, 20, -8, 0 },
200 { 1, -2, -7, 41, 79, 24, -8, 0 },
201 { 1, -2, -7, 37, 80, 28, -8, -1 }
202 }, {
203 { -3, 0, 35, 64, 35, 0, -3, 0 },
204 { -3, -1, 32, 64, 38, 1, -3, 0 },
205 { -2, -2, 29, 63, 41, 2, -3, 0 },
206 { -2, -3, 27, 63, 43, 4, -4, 0 },
207 { -2, -3, 24, 61, 46, 6, -4, 0 },
208 { -2, -3, 21, 60, 49, 7, -4, 0 },
209 { -1, -4, 19, 59, 51, 9, -4, -1 },
210 { -1, -4, 16, 57, 53, 12, -4, -1 },
211 { -1, -4, 14, 55, 55, 14, -4, -1 },
212 { -1, -4, 12, 53, 57, 16, -4, -1 },
213 { -1, -4, 9, 51, 59, 19, -4, -1 },
214 { 0, -4, 7, 49, 60, 21, -3, -2 },
215 { 0, -4, 6, 46, 61, 24, -3, -2 },
216 { 0, -4, 4, 43, 63, 27, -3, -2 },
217 { 0, -3, 2, 41, 63, 29, -2, -2 },
218 { 0, -3, 1, 38, 64, 32, -1, -3 }
219 }, {
220 { -1, 8, 33, 48, 33, 8, -1, 0 },
221 { -1, 7, 31, 49, 35, 9, -1, -1 },
222 { -1, 6, 30, 49, 36, 10, -1, -1 },
223 { -1, 5, 28, 48, 38, 12, -1, -1 },
224 { -1, 4, 26, 48, 39, 13, 0, -1 },
225 { -1, 3, 24, 47, 41, 15, 0, -1 },
226 { -1, 2, 23, 47, 42, 16, 0, -1 },
227 { -1, 2, 21, 45, 43, 18, 1, -1 },
228 { -1, 1, 19, 45, 45, 19, 1, -1 },
229 { -1, 1, 18, 43, 45, 21, 2, -1 },
230 { -1, 0, 16, 42, 47, 23, 2, -1 },
231 { -1, 0, 15, 41, 47, 24, 3, -1 },
232 { -1, 0, 13, 39, 48, 26, 4, -1 },
233 { -1, -1, 12, 38, 48, 28, 5, -1 },
234 { -1, -1, 10, 36, 49, 30, 6, -1 },
235 { -1, -1, 9, 35, 49, 31, 7, -1 }
236 }, {
237 { 2, 13, 30, 38, 30, 13, 2, 0 },
238 { 2, 12, 29, 38, 30, 14, 3, 0 },
239 { 2, 11, 28, 38, 31, 15, 3, 0 },
240 { 2, 10, 26, 38, 32, 16, 4, 0 },
241 { 1, 10, 26, 37, 33, 17, 4, 0 },
242 { 1, 9, 24, 37, 34, 18, 5, 0 },
243 { 1, 8, 24, 37, 34, 19, 5, 0 },
244 { 1, 7, 22, 36, 35, 20, 6, 1 },
245 { 1, 6, 21, 36, 36, 21, 6, 1 },
246 { 1, 6, 20, 35, 36, 22, 7, 1 },
247 { 0, 5, 19, 34, 37, 24, 8, 1 },
248 { 0, 5, 18, 34, 37, 24, 9, 1 },
249 { 0, 4, 17, 33, 37, 26, 10, 1 },
250 { 0, 4, 16, 32, 38, 26, 10, 2 },
251 { 0, 3, 15, 31, 38, 28, 11, 2 },
252 { 0, 3, 14, 30, 38, 29, 12, 2 }
253 }
254};
255
256
257static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = {
258 {
259 { 0, 128, 0, 0 },
260 { -4, 127, 5, 0 },
261 { -6, 124, 11, -1 },
262 { -8, 118, 19, -1 },
263 { -8, 111, 27, -2 },
264 { -8, 102, 37, -3 },
265 { -8, 92, 48, -4 },
266 { -7, 81, 59, -5 },
267 { -6, 70, 70, -6 },
268 { -5, 59, 81, -7 },
269 { -4, 48, 92, -8 },
270 { -3, 37, 102, -8 },
271 { -2, 27, 111, -8 },
272 { -1, 19, 118, -8 },
273 { -1, 11, 124, -6 },
274 { 0, 5, 127, -4 }
275 }, {
276 { 8, 112, 8, 0 },
277 { 4, 111, 14, -1 },
278 { 1, 109, 20, -2 },
279 { -2, 105, 27, -2 },
280 { -3, 100, 34, -3 },
281 { -5, 93, 43, -3 },
282 { -5, 86, 51, -4 },
283 { -5, 77, 60, -4 },
284 { -5, 69, 69, -5 },
285 { -4, 60, 77, -5 },
286 { -4, 51, 86, -5 },
287 { -3, 43, 93, -5 },
288 { -3, 34, 100, -3 },
289 { -2, 27, 105, -2 },
290 { -2, 20, 109, 1 },
291 { -1, 14, 111, 4 }
292 }, {
293 { 16, 96, 16, 0 },
294 { 12, 97, 21, -2 },
295 { 8, 96, 26, -2 },
296 { 5, 93, 32, -2 },
297 { 2, 89, 39, -2 },
298 { 0, 84, 46, -2 },
299 { -1, 79, 53, -3 },
300 { -2, 73, 59, -2 },
301 { -2, 66, 66, -2 },
302 { -2, 59, 73, -2 },
303 { -3, 53, 79, -1 },
304 { -2, 46, 84, 0 },
305 { -2, 39, 89, 2 },
306 { -2, 32, 93, 5 },
307 { -2, 26, 96, 8 },
308 { -2, 21, 97, 12 }
309 }, {
310 { 22, 84, 22, 0 },
311 { 18, 85, 26, -1 },
312 { 14, 84, 31, -1 },
313 { 11, 82, 36, -1 },
314 { 8, 79, 42, -1 },
315 { 6, 76, 47, -1 },
316 { 4, 72, 52, 0 },
317 { 2, 68, 58, 0 },
318 { 1, 63, 63, 1 },
319 { 0, 58, 68, 2 },
320 { 0, 52, 72, 4 },
321 { -1, 47, 76, 6 },
322 { -1, 42, 79, 8 },
323 { -1, 36, 82, 11 },
324 { -1, 31, 84, 14 },
325 { -1, 26, 85, 18 }
326 }, {
327 { 26, 76, 26, 0 },
328 { 22, 76, 30, 0 },
329 { 19, 75, 34, 0 },
330 { 16, 73, 38, 1 },
331 { 13, 71, 43, 1 },
332 { 10, 69, 47, 2 },
333 { 8, 66, 51, 3 },
334 { 6, 63, 55, 4 },
335 { 5, 59, 59, 5 },
336 { 4, 55, 63, 6 },
337 { 3, 51, 66, 8 },
338 { 2, 47, 69, 10 },
339 { 1, 43, 71, 13 },
340 { 1, 38, 73, 16 },
341 { 0, 34, 75, 19 },
342 { 0, 30, 76, 22 }
343 }, {
344 { 29, 70, 29, 0 },
345 { 26, 68, 32, 2 },
346 { 23, 67, 36, 2 },
347 { 20, 66, 39, 3 },
348 { 17, 65, 43, 3 },
349 { 15, 63, 46, 4 },
350 { 12, 61, 50, 5 },
351 { 10, 58, 53, 7 },
352 { 8, 56, 56, 8 },
353 { 7, 53, 58, 10 },
354 { 5, 50, 61, 12 },
355 { 4, 46, 63, 15 },
356 { 3, 43, 65, 17 },
357 { 3, 39, 66, 20 },
358 { 2, 36, 67, 23 },
359 { 2, 32, 68, 26 }
360 }, {
361 { 32, 64, 32, 0 },
362 { 28, 63, 34, 3 },
363 { 25, 62, 37, 4 },
364 { 22, 62, 40, 4 },
365 { 19, 61, 43, 5 },
366 { 17, 59, 46, 6 },
367 { 15, 58, 48, 7 },
368 { 13, 55, 51, 9 },
369 { 11, 53, 53, 11 },
370 { 9, 51, 55, 13 },
371 { 7, 48, 58, 15 },
372 { 6, 46, 59, 17 },
373 { 5, 43, 61, 19 },
374 { 4, 40, 62, 22 },
375 { 4, 37, 62, 25 },
376 { 3, 34, 63, 28 }
377 }
378};
379
380static int gsc_sw_reset(struct gsc_context *ctx)
381{
382 u32 cfg;
383 int count = GSC_RESET_TIMEOUT;
384
385
386 cfg = (GSC_SW_RESET_SRESET);
387 gsc_write(cfg, GSC_SW_RESET);
388
389
390 while (count--) {
391 cfg = gsc_read(GSC_SW_RESET);
392 if (!cfg)
393 break;
394 usleep_range(1000, 2000);
395 }
396
397 if (cfg) {
398 DRM_DEV_ERROR(ctx->dev, "failed to reset gsc h/w.\n");
399 return -EBUSY;
400 }
401
402
403 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
404 cfg |= (GSC_IN_BASE_ADDR_MASK |
405 GSC_IN_BASE_ADDR_PINGPONG(0));
406 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
407 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
408 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
409
410 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
411 cfg |= (GSC_OUT_BASE_ADDR_MASK |
412 GSC_OUT_BASE_ADDR_PINGPONG(0));
413 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
414 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
415 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
416
417 return 0;
418}
419
420static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
421 bool overflow, bool done)
422{
423 u32 cfg;
424
425 DRM_DEV_DEBUG_KMS(ctx->dev, "enable[%d]overflow[%d]level[%d]\n",
426 enable, overflow, done);
427
428 cfg = gsc_read(GSC_IRQ);
429 cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
430
431 if (enable)
432 cfg |= GSC_IRQ_ENABLE;
433 else
434 cfg &= ~GSC_IRQ_ENABLE;
435
436 if (overflow)
437 cfg &= ~GSC_IRQ_OR_MASK;
438 else
439 cfg |= GSC_IRQ_OR_MASK;
440
441 if (done)
442 cfg &= ~GSC_IRQ_FRMDONE_MASK;
443 else
444 cfg |= GSC_IRQ_FRMDONE_MASK;
445
446 gsc_write(cfg, GSC_IRQ);
447}
448
449
450static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
451{
452 u32 cfg;
453
454 DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
455
456 cfg = gsc_read(GSC_IN_CON);
457 cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
458 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
459 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
460 GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);
461
462 switch (fmt) {
463 case DRM_FORMAT_RGB565:
464 cfg |= GSC_IN_RGB565;
465 break;
466 case DRM_FORMAT_XRGB8888:
467 case DRM_FORMAT_ARGB8888:
468 cfg |= GSC_IN_XRGB8888;
469 break;
470 case DRM_FORMAT_BGRX8888:
471 cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);
472 break;
473 case DRM_FORMAT_YUYV:
474 cfg |= (GSC_IN_YUV422_1P |
475 GSC_IN_YUV422_1P_ORDER_LSB_Y |
476 GSC_IN_CHROMA_ORDER_CBCR);
477 break;
478 case DRM_FORMAT_YVYU:
479 cfg |= (GSC_IN_YUV422_1P |
480 GSC_IN_YUV422_1P_ORDER_LSB_Y |
481 GSC_IN_CHROMA_ORDER_CRCB);
482 break;
483 case DRM_FORMAT_UYVY:
484 cfg |= (GSC_IN_YUV422_1P |
485 GSC_IN_YUV422_1P_OEDER_LSB_C |
486 GSC_IN_CHROMA_ORDER_CBCR);
487 break;
488 case DRM_FORMAT_VYUY:
489 cfg |= (GSC_IN_YUV422_1P |
490 GSC_IN_YUV422_1P_OEDER_LSB_C |
491 GSC_IN_CHROMA_ORDER_CRCB);
492 break;
493 case DRM_FORMAT_NV21:
494 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_2P);
495 break;
496 case DRM_FORMAT_NV61:
497 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV422_2P);
498 break;
499 case DRM_FORMAT_YUV422:
500 cfg |= GSC_IN_YUV422_3P;
501 break;
502 case DRM_FORMAT_YUV420:
503 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);
504 break;
505 case DRM_FORMAT_YVU420:
506 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P);
507 break;
508 case DRM_FORMAT_NV12:
509 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P);
510 break;
511 case DRM_FORMAT_NV16:
512 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV422_2P);
513 break;
514 }
515
516 if (tiled)
517 cfg |= (GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE);
518
519 gsc_write(cfg, GSC_IN_CON);
520}
521
522static void gsc_src_set_transf(struct gsc_context *ctx, unsigned int rotation)
523{
524 unsigned int degree = rotation & DRM_MODE_ROTATE_MASK;
525 u32 cfg;
526
527 cfg = gsc_read(GSC_IN_CON);
528 cfg &= ~GSC_IN_ROT_MASK;
529
530 switch (degree) {
531 case DRM_MODE_ROTATE_0:
532 if (rotation & DRM_MODE_REFLECT_X)
533 cfg |= GSC_IN_ROT_XFLIP;
534 if (rotation & DRM_MODE_REFLECT_Y)
535 cfg |= GSC_IN_ROT_YFLIP;
536 break;
537 case DRM_MODE_ROTATE_90:
538 cfg |= GSC_IN_ROT_90;
539 if (rotation & DRM_MODE_REFLECT_X)
540 cfg |= GSC_IN_ROT_XFLIP;
541 if (rotation & DRM_MODE_REFLECT_Y)
542 cfg |= GSC_IN_ROT_YFLIP;
543 break;
544 case DRM_MODE_ROTATE_180:
545 cfg |= GSC_IN_ROT_180;
546 if (rotation & DRM_MODE_REFLECT_X)
547 cfg &= ~GSC_IN_ROT_XFLIP;
548 if (rotation & DRM_MODE_REFLECT_Y)
549 cfg &= ~GSC_IN_ROT_YFLIP;
550 break;
551 case DRM_MODE_ROTATE_270:
552 cfg |= GSC_IN_ROT_270;
553 if (rotation & DRM_MODE_REFLECT_X)
554 cfg &= ~GSC_IN_ROT_XFLIP;
555 if (rotation & DRM_MODE_REFLECT_Y)
556 cfg &= ~GSC_IN_ROT_YFLIP;
557 break;
558 }
559
560 gsc_write(cfg, GSC_IN_CON);
561
562 ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
563}
564
565static void gsc_src_set_size(struct gsc_context *ctx,
566 struct exynos_drm_ipp_buffer *buf)
567{
568 struct gsc_scaler *sc = &ctx->sc;
569 u32 cfg;
570
571
572 cfg = (GSC_SRCIMG_OFFSET_X(buf->rect.x) |
573 GSC_SRCIMG_OFFSET_Y(buf->rect.y));
574 gsc_write(cfg, GSC_SRCIMG_OFFSET);
575
576
577 cfg = (GSC_CROPPED_WIDTH(buf->rect.w) |
578 GSC_CROPPED_HEIGHT(buf->rect.h));
579 gsc_write(cfg, GSC_CROPPED_SIZE);
580
581
582 cfg = gsc_read(GSC_SRCIMG_SIZE);
583 cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
584 GSC_SRCIMG_WIDTH_MASK);
585
586 cfg |= (GSC_SRCIMG_WIDTH(buf->buf.pitch[0] / buf->format->cpp[0]) |
587 GSC_SRCIMG_HEIGHT(buf->buf.height));
588
589 gsc_write(cfg, GSC_SRCIMG_SIZE);
590
591 cfg = gsc_read(GSC_IN_CON);
592 cfg &= ~GSC_IN_RGB_TYPE_MASK;
593
594 if (buf->rect.w >= GSC_WIDTH_ITU_709)
595 if (sc->range)
596 cfg |= GSC_IN_RGB_HD_WIDE;
597 else
598 cfg |= GSC_IN_RGB_HD_NARROW;
599 else
600 if (sc->range)
601 cfg |= GSC_IN_RGB_SD_WIDE;
602 else
603 cfg |= GSC_IN_RGB_SD_NARROW;
604
605 gsc_write(cfg, GSC_IN_CON);
606}
607
608static void gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
609 bool enqueue)
610{
611 bool masked = !enqueue;
612 u32 cfg;
613 u32 mask = 0x00000001 << buf_id;
614
615
616 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
617
618
619 cfg &= ~mask;
620 cfg |= masked << buf_id;
621 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
622 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
623 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
624}
625
626static void gsc_src_set_addr(struct gsc_context *ctx, u32 buf_id,
627 struct exynos_drm_ipp_buffer *buf)
628{
629
630 gsc_write(buf->dma_addr[0], GSC_IN_BASE_ADDR_Y(buf_id));
631 gsc_write(buf->dma_addr[1], GSC_IN_BASE_ADDR_CB(buf_id));
632 gsc_write(buf->dma_addr[2], GSC_IN_BASE_ADDR_CR(buf_id));
633
634 gsc_src_set_buf_seq(ctx, buf_id, true);
635}
636
637static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
638{
639 u32 cfg;
640
641 DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
642
643 cfg = gsc_read(GSC_OUT_CON);
644 cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
645 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
646 GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |
647 GSC_OUT_GLOBAL_ALPHA_MASK);
648
649 switch (fmt) {
650 case DRM_FORMAT_RGB565:
651 cfg |= GSC_OUT_RGB565;
652 break;
653 case DRM_FORMAT_ARGB8888:
654 case DRM_FORMAT_XRGB8888:
655 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_GLOBAL_ALPHA(0xff));
656 break;
657 case DRM_FORMAT_BGRX8888:
658 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);
659 break;
660 case DRM_FORMAT_YUYV:
661 cfg |= (GSC_OUT_YUV422_1P |
662 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
663 GSC_OUT_CHROMA_ORDER_CBCR);
664 break;
665 case DRM_FORMAT_YVYU:
666 cfg |= (GSC_OUT_YUV422_1P |
667 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
668 GSC_OUT_CHROMA_ORDER_CRCB);
669 break;
670 case DRM_FORMAT_UYVY:
671 cfg |= (GSC_OUT_YUV422_1P |
672 GSC_OUT_YUV422_1P_OEDER_LSB_C |
673 GSC_OUT_CHROMA_ORDER_CBCR);
674 break;
675 case DRM_FORMAT_VYUY:
676 cfg |= (GSC_OUT_YUV422_1P |
677 GSC_OUT_YUV422_1P_OEDER_LSB_C |
678 GSC_OUT_CHROMA_ORDER_CRCB);
679 break;
680 case DRM_FORMAT_NV21:
681 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
682 break;
683 case DRM_FORMAT_NV61:
684 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV422_2P);
685 break;
686 case DRM_FORMAT_YUV422:
687 cfg |= GSC_OUT_YUV422_3P;
688 break;
689 case DRM_FORMAT_YUV420:
690 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);
691 break;
692 case DRM_FORMAT_YVU420:
693 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P);
694 break;
695 case DRM_FORMAT_NV12:
696 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P);
697 break;
698 case DRM_FORMAT_NV16:
699 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV422_2P);
700 break;
701 }
702
703 if (tiled)
704 cfg |= (GSC_IN_TILE_C_16x8 | GSC_OUT_TILE_MODE);
705
706 gsc_write(cfg, GSC_OUT_CON);
707}
708
709static int gsc_get_ratio_shift(struct gsc_context *ctx, u32 src, u32 dst,
710 u32 *ratio)
711{
712 DRM_DEV_DEBUG_KMS(ctx->dev, "src[%d]dst[%d]\n", src, dst);
713
714 if (src >= dst * 8) {
715 DRM_DEV_ERROR(ctx->dev, "failed to make ratio and shift.\n");
716 return -EINVAL;
717 } else if (src >= dst * 4)
718 *ratio = 4;
719 else if (src >= dst * 2)
720 *ratio = 2;
721 else
722 *ratio = 1;
723
724 return 0;
725}
726
727static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor)
728{
729 if (hratio == 4 && vratio == 4)
730 *shfactor = 4;
731 else if ((hratio == 4 && vratio == 2) ||
732 (hratio == 2 && vratio == 4))
733 *shfactor = 3;
734 else if ((hratio == 4 && vratio == 1) ||
735 (hratio == 1 && vratio == 4) ||
736 (hratio == 2 && vratio == 2))
737 *shfactor = 2;
738 else if (hratio == 1 && vratio == 1)
739 *shfactor = 0;
740 else
741 *shfactor = 1;
742}
743
744static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
745 struct drm_exynos_ipp_task_rect *src,
746 struct drm_exynos_ipp_task_rect *dst)
747{
748 u32 cfg;
749 u32 src_w, src_h, dst_w, dst_h;
750 int ret = 0;
751
752 src_w = src->w;
753 src_h = src->h;
754
755 if (ctx->rotation) {
756 dst_w = dst->h;
757 dst_h = dst->w;
758 } else {
759 dst_w = dst->w;
760 dst_h = dst->h;
761 }
762
763 ret = gsc_get_ratio_shift(ctx, src_w, dst_w, &sc->pre_hratio);
764 if (ret) {
765 DRM_DEV_ERROR(ctx->dev, "failed to get ratio horizontal.\n");
766 return ret;
767 }
768
769 ret = gsc_get_ratio_shift(ctx, src_h, dst_h, &sc->pre_vratio);
770 if (ret) {
771 DRM_DEV_ERROR(ctx->dev, "failed to get ratio vertical.\n");
772 return ret;
773 }
774
775 DRM_DEV_DEBUG_KMS(ctx->dev, "pre_hratio[%d]pre_vratio[%d]\n",
776 sc->pre_hratio, sc->pre_vratio);
777
778 sc->main_hratio = (src_w << 16) / dst_w;
779 sc->main_vratio = (src_h << 16) / dst_h;
780
781 DRM_DEV_DEBUG_KMS(ctx->dev, "main_hratio[%ld]main_vratio[%ld]\n",
782 sc->main_hratio, sc->main_vratio);
783
784 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
785 &sc->pre_shfactor);
786
787 DRM_DEV_DEBUG_KMS(ctx->dev, "pre_shfactor[%d]\n", sc->pre_shfactor);
788
789 cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
790 GSC_PRESC_H_RATIO(sc->pre_hratio) |
791 GSC_PRESC_V_RATIO(sc->pre_vratio));
792 gsc_write(cfg, GSC_PRE_SCALE_RATIO);
793
794 return ret;
795}
796
797static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio)
798{
799 int i, j, k, sc_ratio;
800
801 if (main_hratio <= GSC_SC_UP_MAX_RATIO)
802 sc_ratio = 0;
803 else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
804 sc_ratio = 1;
805 else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
806 sc_ratio = 2;
807 else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
808 sc_ratio = 3;
809 else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
810 sc_ratio = 4;
811 else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
812 sc_ratio = 5;
813 else
814 sc_ratio = 6;
815
816 for (i = 0; i < GSC_COEF_PHASE; i++)
817 for (j = 0; j < GSC_COEF_H_8T; j++)
818 for (k = 0; k < GSC_COEF_DEPTH; k++)
819 gsc_write(h_coef_8t[sc_ratio][i][j],
820 GSC_HCOEF(i, j, k));
821}
822
823static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio)
824{
825 int i, j, k, sc_ratio;
826
827 if (main_vratio <= GSC_SC_UP_MAX_RATIO)
828 sc_ratio = 0;
829 else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
830 sc_ratio = 1;
831 else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
832 sc_ratio = 2;
833 else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
834 sc_ratio = 3;
835 else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
836 sc_ratio = 4;
837 else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
838 sc_ratio = 5;
839 else
840 sc_ratio = 6;
841
842 for (i = 0; i < GSC_COEF_PHASE; i++)
843 for (j = 0; j < GSC_COEF_V_4T; j++)
844 for (k = 0; k < GSC_COEF_DEPTH; k++)
845 gsc_write(v_coef_4t[sc_ratio][i][j],
846 GSC_VCOEF(i, j, k));
847}
848
849static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc)
850{
851 u32 cfg;
852
853 DRM_DEV_DEBUG_KMS(ctx->dev, "main_hratio[%ld]main_vratio[%ld]\n",
854 sc->main_hratio, sc->main_vratio);
855
856 gsc_set_h_coef(ctx, sc->main_hratio);
857 cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
858 gsc_write(cfg, GSC_MAIN_H_RATIO);
859
860 gsc_set_v_coef(ctx, sc->main_vratio);
861 cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
862 gsc_write(cfg, GSC_MAIN_V_RATIO);
863}
864
865static void gsc_dst_set_size(struct gsc_context *ctx,
866 struct exynos_drm_ipp_buffer *buf)
867{
868 struct gsc_scaler *sc = &ctx->sc;
869 u32 cfg;
870
871
872 cfg = (GSC_DSTIMG_OFFSET_X(buf->rect.x) |
873 GSC_DSTIMG_OFFSET_Y(buf->rect.y));
874 gsc_write(cfg, GSC_DSTIMG_OFFSET);
875
876
877 if (ctx->rotation)
878 cfg = (GSC_SCALED_WIDTH(buf->rect.h) |
879 GSC_SCALED_HEIGHT(buf->rect.w));
880 else
881 cfg = (GSC_SCALED_WIDTH(buf->rect.w) |
882 GSC_SCALED_HEIGHT(buf->rect.h));
883 gsc_write(cfg, GSC_SCALED_SIZE);
884
885
886 cfg = gsc_read(GSC_DSTIMG_SIZE);
887 cfg &= ~(GSC_DSTIMG_HEIGHT_MASK | GSC_DSTIMG_WIDTH_MASK);
888 cfg |= GSC_DSTIMG_WIDTH(buf->buf.pitch[0] / buf->format->cpp[0]) |
889 GSC_DSTIMG_HEIGHT(buf->buf.height);
890 gsc_write(cfg, GSC_DSTIMG_SIZE);
891
892 cfg = gsc_read(GSC_OUT_CON);
893 cfg &= ~GSC_OUT_RGB_TYPE_MASK;
894
895 if (buf->rect.w >= GSC_WIDTH_ITU_709)
896 if (sc->range)
897 cfg |= GSC_OUT_RGB_HD_WIDE;
898 else
899 cfg |= GSC_OUT_RGB_HD_NARROW;
900 else
901 if (sc->range)
902 cfg |= GSC_OUT_RGB_SD_WIDE;
903 else
904 cfg |= GSC_OUT_RGB_SD_NARROW;
905
906 gsc_write(cfg, GSC_OUT_CON);
907}
908
909static int gsc_dst_get_buf_seq(struct gsc_context *ctx)
910{
911 u32 cfg, i, buf_num = GSC_REG_SZ;
912 u32 mask = 0x00000001;
913
914 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
915
916 for (i = 0; i < GSC_REG_SZ; i++)
917 if (cfg & (mask << i))
918 buf_num--;
919
920 DRM_DEV_DEBUG_KMS(ctx->dev, "buf_num[%d]\n", buf_num);
921
922 return buf_num;
923}
924
925static void gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
926 bool enqueue)
927{
928 bool masked = !enqueue;
929 u32 cfg;
930 u32 mask = 0x00000001 << buf_id;
931
932
933 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
934
935
936 cfg &= ~mask;
937 cfg |= masked << buf_id;
938 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
939 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
940 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
941
942
943 if (enqueue && gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)
944 gsc_handle_irq(ctx, true, false, true);
945
946
947 if (!enqueue && gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)
948 gsc_handle_irq(ctx, false, false, true);
949}
950
951static void gsc_dst_set_addr(struct gsc_context *ctx,
952 u32 buf_id, struct exynos_drm_ipp_buffer *buf)
953{
954
955 gsc_write(buf->dma_addr[0], GSC_OUT_BASE_ADDR_Y(buf_id));
956 gsc_write(buf->dma_addr[1], GSC_OUT_BASE_ADDR_CB(buf_id));
957 gsc_write(buf->dma_addr[2], GSC_OUT_BASE_ADDR_CR(buf_id));
958
959 gsc_dst_set_buf_seq(ctx, buf_id, true);
960}
961
962static int gsc_get_src_buf_index(struct gsc_context *ctx)
963{
964 u32 cfg, curr_index, i;
965 u32 buf_id = GSC_MAX_SRC;
966
967 DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
968
969 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
970 curr_index = GSC_IN_CURR_GET_INDEX(cfg);
971
972 for (i = curr_index; i < GSC_MAX_SRC; i++) {
973 if (!((cfg >> i) & 0x1)) {
974 buf_id = i;
975 break;
976 }
977 }
978
979 DRM_DEV_DEBUG_KMS(ctx->dev, "cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
980 curr_index, buf_id);
981
982 if (buf_id == GSC_MAX_SRC) {
983 DRM_DEV_ERROR(ctx->dev, "failed to get in buffer index.\n");
984 return -EINVAL;
985 }
986
987 gsc_src_set_buf_seq(ctx, buf_id, false);
988
989 return buf_id;
990}
991
992static int gsc_get_dst_buf_index(struct gsc_context *ctx)
993{
994 u32 cfg, curr_index, i;
995 u32 buf_id = GSC_MAX_DST;
996
997 DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
998
999 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1000 curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
1001
1002 for (i = curr_index; i < GSC_MAX_DST; i++) {
1003 if (!((cfg >> i) & 0x1)) {
1004 buf_id = i;
1005 break;
1006 }
1007 }
1008
1009 if (buf_id == GSC_MAX_DST) {
1010 DRM_DEV_ERROR(ctx->dev, "failed to get out buffer index.\n");
1011 return -EINVAL;
1012 }
1013
1014 gsc_dst_set_buf_seq(ctx, buf_id, false);
1015
1016 DRM_DEV_DEBUG_KMS(ctx->dev, "cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1017 curr_index, buf_id);
1018
1019 return buf_id;
1020}
1021
1022static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
1023{
1024 struct gsc_context *ctx = dev_id;
1025 u32 status;
1026 int err = 0;
1027
1028 DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
1029
1030 status = gsc_read(GSC_IRQ);
1031 if (status & GSC_IRQ_STATUS_OR_IRQ) {
1032 dev_err(ctx->dev, "occurred overflow at %d, status 0x%x.\n",
1033 ctx->id, status);
1034 err = -EINVAL;
1035 }
1036
1037 if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
1038 int src_buf_id, dst_buf_id;
1039
1040 dev_dbg(ctx->dev, "occurred frame done at %d, status 0x%x.\n",
1041 ctx->id, status);
1042
1043 src_buf_id = gsc_get_src_buf_index(ctx);
1044 dst_buf_id = gsc_get_dst_buf_index(ctx);
1045
1046 DRM_DEV_DEBUG_KMS(ctx->dev, "buf_id_src[%d]buf_id_dst[%d]\n",
1047 src_buf_id, dst_buf_id);
1048
1049 if (src_buf_id < 0 || dst_buf_id < 0)
1050 err = -EINVAL;
1051 }
1052
1053 if (ctx->task) {
1054 struct exynos_drm_ipp_task *task = ctx->task;
1055
1056 ctx->task = NULL;
1057 pm_runtime_mark_last_busy(ctx->dev);
1058 pm_runtime_put_autosuspend(ctx->dev);
1059 exynos_drm_ipp_task_done(task, err);
1060 }
1061
1062 return IRQ_HANDLED;
1063}
1064
1065static int gsc_reset(struct gsc_context *ctx)
1066{
1067 struct gsc_scaler *sc = &ctx->sc;
1068 int ret;
1069
1070
1071 ret = gsc_sw_reset(ctx);
1072 if (ret < 0) {
1073 dev_err(ctx->dev, "failed to reset hardware.\n");
1074 return ret;
1075 }
1076
1077
1078 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1079 sc->range = true;
1080
1081 return 0;
1082}
1083
1084static void gsc_start(struct gsc_context *ctx)
1085{
1086 u32 cfg;
1087
1088 gsc_handle_irq(ctx, true, false, true);
1089
1090
1091 cfg = gsc_read(GSC_ENABLE);
1092 cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |
1093 GSC_ENABLE_CLK_GATE_MODE_MASK);
1094 cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
1095 gsc_write(cfg, GSC_ENABLE);
1096
1097
1098 cfg = gsc_read(GSC_IN_CON);
1099 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1100 cfg |= GSC_IN_PATH_MEMORY;
1101 gsc_write(cfg, GSC_IN_CON);
1102
1103
1104 cfg = gsc_read(GSC_OUT_CON);
1105 cfg |= GSC_OUT_PATH_MEMORY;
1106 gsc_write(cfg, GSC_OUT_CON);
1107
1108 gsc_set_scaler(ctx, &ctx->sc);
1109
1110 cfg = gsc_read(GSC_ENABLE);
1111 cfg |= GSC_ENABLE_ON;
1112 gsc_write(cfg, GSC_ENABLE);
1113}
1114
1115static int gsc_commit(struct exynos_drm_ipp *ipp,
1116 struct exynos_drm_ipp_task *task)
1117{
1118 struct gsc_context *ctx = container_of(ipp, struct gsc_context, ipp);
1119 int ret;
1120
1121 ret = pm_runtime_resume_and_get(ctx->dev);
1122 if (ret < 0) {
1123 dev_err(ctx->dev, "failed to enable GScaler device.\n");
1124 return ret;
1125 }
1126
1127 ctx->task = task;
1128
1129 ret = gsc_reset(ctx);
1130 if (ret) {
1131 pm_runtime_put_autosuspend(ctx->dev);
1132 ctx->task = NULL;
1133 return ret;
1134 }
1135
1136 gsc_src_set_fmt(ctx, task->src.buf.fourcc, task->src.buf.modifier);
1137 gsc_src_set_transf(ctx, task->transform.rotation);
1138 gsc_src_set_size(ctx, &task->src);
1139 gsc_src_set_addr(ctx, 0, &task->src);
1140 gsc_dst_set_fmt(ctx, task->dst.buf.fourcc, task->dst.buf.modifier);
1141 gsc_dst_set_size(ctx, &task->dst);
1142 gsc_dst_set_addr(ctx, 0, &task->dst);
1143 gsc_set_prescaler(ctx, &ctx->sc, &task->src.rect, &task->dst.rect);
1144 gsc_start(ctx);
1145
1146 return 0;
1147}
1148
1149static void gsc_abort(struct exynos_drm_ipp *ipp,
1150 struct exynos_drm_ipp_task *task)
1151{
1152 struct gsc_context *ctx =
1153 container_of(ipp, struct gsc_context, ipp);
1154
1155 gsc_reset(ctx);
1156 if (ctx->task) {
1157 struct exynos_drm_ipp_task *task = ctx->task;
1158
1159 ctx->task = NULL;
1160 pm_runtime_mark_last_busy(ctx->dev);
1161 pm_runtime_put_autosuspend(ctx->dev);
1162 exynos_drm_ipp_task_done(task, -EIO);
1163 }
1164}
1165
1166static struct exynos_drm_ipp_funcs ipp_funcs = {
1167 .commit = gsc_commit,
1168 .abort = gsc_abort,
1169};
1170
1171static int gsc_bind(struct device *dev, struct device *master, void *data)
1172{
1173 struct gsc_context *ctx = dev_get_drvdata(dev);
1174 struct drm_device *drm_dev = data;
1175 struct exynos_drm_ipp *ipp = &ctx->ipp;
1176
1177 ctx->drm_dev = drm_dev;
1178 ctx->drm_dev = drm_dev;
1179 exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
1180
1181 exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
1182 DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
1183 DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
1184 ctx->formats, ctx->num_formats, "gsc");
1185
1186 dev_info(dev, "The exynos gscaler has been probed successfully\n");
1187
1188 return 0;
1189}
1190
1191static void gsc_unbind(struct device *dev, struct device *master,
1192 void *data)
1193{
1194 struct gsc_context *ctx = dev_get_drvdata(dev);
1195 struct drm_device *drm_dev = data;
1196 struct exynos_drm_ipp *ipp = &ctx->ipp;
1197
1198 exynos_drm_ipp_unregister(dev, ipp);
1199 exynos_drm_unregister_dma(drm_dev, dev, &ctx->dma_priv);
1200}
1201
1202static const struct component_ops gsc_component_ops = {
1203 .bind = gsc_bind,
1204 .unbind = gsc_unbind,
1205};
1206
1207static const unsigned int gsc_formats[] = {
1208 DRM_FORMAT_ARGB8888,
1209 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, DRM_FORMAT_BGRX8888,
1210 DRM_FORMAT_NV12, DRM_FORMAT_NV16, DRM_FORMAT_NV21, DRM_FORMAT_NV61,
1211 DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU,
1212 DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, DRM_FORMAT_YUV422,
1213};
1214
1215static const unsigned int gsc_tiled_formats[] = {
1216 DRM_FORMAT_NV12, DRM_FORMAT_NV21,
1217};
1218
1219static int gsc_probe(struct platform_device *pdev)
1220{
1221 struct device *dev = &pdev->dev;
1222 struct gsc_driverdata *driver_data;
1223 struct exynos_drm_ipp_formats *formats;
1224 struct gsc_context *ctx;
1225 struct resource *res;
1226 int num_formats, ret, i, j;
1227
1228 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1229 if (!ctx)
1230 return -ENOMEM;
1231
1232 driver_data = (struct gsc_driverdata *)of_device_get_match_data(dev);
1233 ctx->dev = dev;
1234 ctx->num_clocks = driver_data->num_clocks;
1235 ctx->clk_names = driver_data->clk_names;
1236
1237
1238 num_formats = ARRAY_SIZE(gsc_formats) + ARRAY_SIZE(gsc_tiled_formats);
1239 formats = devm_kcalloc(dev, num_formats, sizeof(*formats), GFP_KERNEL);
1240 if (!formats)
1241 return -ENOMEM;
1242
1243
1244 for (i = 0; i < ARRAY_SIZE(gsc_formats); i++) {
1245 formats[i].fourcc = gsc_formats[i];
1246 formats[i].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
1247 DRM_EXYNOS_IPP_FORMAT_DESTINATION;
1248 formats[i].limits = driver_data->limits;
1249 formats[i].num_limits = driver_data->num_limits;
1250 }
1251
1252
1253 for (j = i, i = 0; i < ARRAY_SIZE(gsc_tiled_formats); j++, i++) {
1254 formats[j].fourcc = gsc_tiled_formats[i];
1255 formats[j].modifier = DRM_FORMAT_MOD_SAMSUNG_16_16_TILE;
1256 formats[j].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
1257 DRM_EXYNOS_IPP_FORMAT_DESTINATION;
1258 formats[j].limits = driver_data->limits;
1259 formats[j].num_limits = driver_data->num_limits;
1260 }
1261
1262 ctx->formats = formats;
1263 ctx->num_formats = num_formats;
1264
1265
1266 for (i = 0; i < ctx->num_clocks; i++) {
1267 ctx->clocks[i] = devm_clk_get(dev, ctx->clk_names[i]);
1268 if (IS_ERR(ctx->clocks[i])) {
1269 dev_err(dev, "failed to get clock: %s\n",
1270 ctx->clk_names[i]);
1271 return PTR_ERR(ctx->clocks[i]);
1272 }
1273 }
1274
1275
1276 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1277 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1278 if (IS_ERR(ctx->regs))
1279 return PTR_ERR(ctx->regs);
1280
1281
1282 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1283 if (!res) {
1284 dev_err(dev, "failed to request irq resource.\n");
1285 return -ENOENT;
1286 }
1287
1288 ctx->irq = res->start;
1289 ret = devm_request_irq(dev, ctx->irq, gsc_irq_handler, 0,
1290 dev_name(dev), ctx);
1291 if (ret < 0) {
1292 dev_err(dev, "failed to request irq.\n");
1293 return ret;
1294 }
1295
1296
1297 ctx->id = pdev->id;
1298
1299 platform_set_drvdata(pdev, ctx);
1300
1301 pm_runtime_use_autosuspend(dev);
1302 pm_runtime_set_autosuspend_delay(dev, GSC_AUTOSUSPEND_DELAY);
1303 pm_runtime_enable(dev);
1304
1305 ret = component_add(dev, &gsc_component_ops);
1306 if (ret)
1307 goto err_pm_dis;
1308
1309 dev_info(dev, "drm gsc registered successfully.\n");
1310
1311 return 0;
1312
1313err_pm_dis:
1314 pm_runtime_dont_use_autosuspend(dev);
1315 pm_runtime_disable(dev);
1316 return ret;
1317}
1318
1319static int gsc_remove(struct platform_device *pdev)
1320{
1321 struct device *dev = &pdev->dev;
1322
1323 component_del(dev, &gsc_component_ops);
1324 pm_runtime_dont_use_autosuspend(dev);
1325 pm_runtime_disable(dev);
1326
1327 return 0;
1328}
1329
1330static int __maybe_unused gsc_runtime_suspend(struct device *dev)
1331{
1332 struct gsc_context *ctx = get_gsc_context(dev);
1333 int i;
1334
1335 DRM_DEV_DEBUG_KMS(dev, "id[%d]\n", ctx->id);
1336
1337 for (i = ctx->num_clocks - 1; i >= 0; i--)
1338 clk_disable_unprepare(ctx->clocks[i]);
1339
1340 return 0;
1341}
1342
1343static int __maybe_unused gsc_runtime_resume(struct device *dev)
1344{
1345 struct gsc_context *ctx = get_gsc_context(dev);
1346 int i, ret;
1347
1348 DRM_DEV_DEBUG_KMS(dev, "id[%d]\n", ctx->id);
1349
1350 for (i = 0; i < ctx->num_clocks; i++) {
1351 ret = clk_prepare_enable(ctx->clocks[i]);
1352 if (ret) {
1353 while (--i > 0)
1354 clk_disable_unprepare(ctx->clocks[i]);
1355 return ret;
1356 }
1357 }
1358 return 0;
1359}
1360
1361static const struct dev_pm_ops gsc_pm_ops = {
1362 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1363 pm_runtime_force_resume)
1364 SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
1365};
1366
1367static const struct drm_exynos_ipp_limit gsc_5250_limits[] = {
1368 { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
1369 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
1370 { IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2048 }, .v = { 16, 2048 }) },
1371 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1372 .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1373};
1374
1375static const struct drm_exynos_ipp_limit gsc_5420_limits[] = {
1376 { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
1377 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
1378 { IPP_SIZE_LIMIT(ROTATED, .h = { 16, 2016 }, .v = { 8, 2016 }) },
1379 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1380 .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1381};
1382
1383static const struct drm_exynos_ipp_limit gsc_5433_limits[] = {
1384 { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 8191, 16 }, .v = { 16, 8191, 2 }) },
1385 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 1 }, .v = { 8, 3344, 1 }) },
1386 { IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2047 }, .v = { 8, 8191 }) },
1387 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1388 .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1389};
1390
1391static struct gsc_driverdata gsc_exynos5250_drvdata = {
1392 .clk_names = {"gscl"},
1393 .num_clocks = 1,
1394 .limits = gsc_5250_limits,
1395 .num_limits = ARRAY_SIZE(gsc_5250_limits),
1396};
1397
1398static struct gsc_driverdata gsc_exynos5420_drvdata = {
1399 .clk_names = {"gscl"},
1400 .num_clocks = 1,
1401 .limits = gsc_5420_limits,
1402 .num_limits = ARRAY_SIZE(gsc_5420_limits),
1403};
1404
1405static struct gsc_driverdata gsc_exynos5433_drvdata = {
1406 .clk_names = {"pclk", "aclk", "aclk_xiu", "aclk_gsclbend"},
1407 .num_clocks = 4,
1408 .limits = gsc_5433_limits,
1409 .num_limits = ARRAY_SIZE(gsc_5433_limits),
1410};
1411
1412static const struct of_device_id exynos_drm_gsc_of_match[] = {
1413 {
1414 .compatible = "samsung,exynos5-gsc",
1415 .data = &gsc_exynos5250_drvdata,
1416 }, {
1417 .compatible = "samsung,exynos5250-gsc",
1418 .data = &gsc_exynos5250_drvdata,
1419 }, {
1420 .compatible = "samsung,exynos5420-gsc",
1421 .data = &gsc_exynos5420_drvdata,
1422 }, {
1423 .compatible = "samsung,exynos5433-gsc",
1424 .data = &gsc_exynos5433_drvdata,
1425 }, {
1426 },
1427};
1428MODULE_DEVICE_TABLE(of, exynos_drm_gsc_of_match);
1429
1430struct platform_driver gsc_driver = {
1431 .probe = gsc_probe,
1432 .remove = gsc_remove,
1433 .driver = {
1434 .name = "exynos-drm-gsc",
1435 .owner = THIS_MODULE,
1436 .pm = &gsc_pm_ops,
1437 .of_match_table = of_match_ptr(exynos_drm_gsc_of_match),
1438 },
1439};
1440
