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26#ifndef __INTEL_DISPLAY_TYPES_H__
27#define __INTEL_DISPLAY_TYPES_H__
28
29#include <linux/async.h>
30#include <linux/i2c.h>
31#include <linux/pwm.h>
32#include <linux/sched/clock.h>
33
34#include <drm/drm_atomic.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_dp_dual_mode_helper.h>
37#include <drm/drm_dp_mst_helper.h>
38#include <drm/drm_encoder.h>
39#include <drm/drm_fb_helper.h>
40#include <drm/drm_fourcc.h>
41#include <drm/drm_probe_helper.h>
42#include <drm/drm_rect.h>
43#include <drm/drm_vblank.h>
44#include <drm/i915_mei_hdcp_interface.h>
45#include <media/cec-notifier.h>
46
47#include "i915_drv.h"
48
49struct drm_printer;
50struct __intel_global_objs_state;
51
52
53
54
55
56
57
58enum intel_output_type {
59 INTEL_OUTPUT_UNUSED = 0,
60 INTEL_OUTPUT_ANALOG = 1,
61 INTEL_OUTPUT_DVO = 2,
62 INTEL_OUTPUT_SDVO = 3,
63 INTEL_OUTPUT_LVDS = 4,
64 INTEL_OUTPUT_TVOUT = 5,
65 INTEL_OUTPUT_HDMI = 6,
66 INTEL_OUTPUT_DP = 7,
67 INTEL_OUTPUT_EDP = 8,
68 INTEL_OUTPUT_DSI = 9,
69 INTEL_OUTPUT_DDI = 10,
70 INTEL_OUTPUT_DP_MST = 11,
71};
72
73enum hdmi_force_audio {
74 HDMI_AUDIO_OFF_DVI = -2,
75 HDMI_AUDIO_OFF,
76 HDMI_AUDIO_AUTO,
77 HDMI_AUDIO_ON,
78};
79
80
81enum intel_broadcast_rgb {
82 INTEL_BROADCAST_RGB_AUTO,
83 INTEL_BROADCAST_RGB_FULL,
84 INTEL_BROADCAST_RGB_LIMITED,
85};
86
87struct intel_fb_view {
88
89
90
91
92
93
94
95
96
97 struct i915_ggtt_view gtt;
98
99
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108
109
110
111 struct i915_color_plane_view {
112 u32 offset;
113 unsigned int x, y;
114
115
116
117
118
119 unsigned int stride;
120 } color_plane[4];
121};
122
123struct intel_framebuffer {
124 struct drm_framebuffer base;
125 struct intel_frontbuffer *frontbuffer;
126
127
128 struct intel_fb_view normal_view;
129 union {
130 struct intel_fb_view rotated_view;
131 struct intel_fb_view remapped_view;
132 };
133
134 struct i915_address_space *dpt_vm;
135};
136
137struct intel_fbdev {
138 struct drm_fb_helper helper;
139 struct intel_framebuffer *fb;
140 struct i915_vma *vma;
141 unsigned long vma_flags;
142 async_cookie_t cookie;
143 int preferred_bpp;
144
145
146 bool hpd_suspended : 1;
147
148
149
150 bool hpd_waiting : 1;
151
152
153 struct mutex hpd_lock;
154};
155
156enum intel_hotplug_state {
157 INTEL_HOTPLUG_UNCHANGED,
158 INTEL_HOTPLUG_CHANGED,
159 INTEL_HOTPLUG_RETRY,
160};
161
162struct intel_encoder {
163 struct drm_encoder base;
164
165 enum intel_output_type type;
166 enum port port;
167 u16 cloneable;
168 u8 pipe_mask;
169 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
170 struct intel_connector *connector);
171 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
172 struct intel_crtc_state *,
173 struct drm_connector_state *);
174 int (*compute_config)(struct intel_encoder *,
175 struct intel_crtc_state *,
176 struct drm_connector_state *);
177 int (*compute_config_late)(struct intel_encoder *,
178 struct intel_crtc_state *,
179 struct drm_connector_state *);
180 void (*update_prepare)(struct intel_atomic_state *,
181 struct intel_encoder *,
182 struct intel_crtc *);
183 void (*pre_pll_enable)(struct intel_atomic_state *,
184 struct intel_encoder *,
185 const struct intel_crtc_state *,
186 const struct drm_connector_state *);
187 void (*pre_enable)(struct intel_atomic_state *,
188 struct intel_encoder *,
189 const struct intel_crtc_state *,
190 const struct drm_connector_state *);
191 void (*enable)(struct intel_atomic_state *,
192 struct intel_encoder *,
193 const struct intel_crtc_state *,
194 const struct drm_connector_state *);
195 void (*update_complete)(struct intel_atomic_state *,
196 struct intel_encoder *,
197 struct intel_crtc *);
198 void (*disable)(struct intel_atomic_state *,
199 struct intel_encoder *,
200 const struct intel_crtc_state *,
201 const struct drm_connector_state *);
202 void (*post_disable)(struct intel_atomic_state *,
203 struct intel_encoder *,
204 const struct intel_crtc_state *,
205 const struct drm_connector_state *);
206 void (*post_pll_disable)(struct intel_atomic_state *,
207 struct intel_encoder *,
208 const struct intel_crtc_state *,
209 const struct drm_connector_state *);
210 void (*update_pipe)(struct intel_atomic_state *,
211 struct intel_encoder *,
212 const struct intel_crtc_state *,
213 const struct drm_connector_state *);
214
215
216
217 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
218
219
220
221
222 void (*get_config)(struct intel_encoder *,
223 struct intel_crtc_state *pipe_config);
224
225
226
227
228
229 void (*sync_state)(struct intel_encoder *encoder,
230 const struct intel_crtc_state *crtc_state);
231
232
233
234
235
236 bool (*initial_fastset_check)(struct intel_encoder *encoder,
237 struct intel_crtc_state *crtc_state);
238
239
240
241
242
243 void (*get_power_domains)(struct intel_encoder *encoder,
244 struct intel_crtc_state *crtc_state);
245
246
247
248
249
250 void (*suspend)(struct intel_encoder *);
251
252
253
254
255 void (*shutdown)(struct intel_encoder *encoder);
256
257
258
259 void (*enable_clock)(struct intel_encoder *encoder,
260 const struct intel_crtc_state *crtc_state);
261 void (*disable_clock)(struct intel_encoder *encoder);
262
263
264
265 bool (*is_clock_enabled)(struct intel_encoder *encoder);
266 enum hpd_pin hpd_pin;
267 enum intel_display_power_domain power_domain;
268
269 const struct drm_connector *audio_connector;
270
271
272 const struct intel_bios_encoder_data *devdata;
273};
274
275struct intel_panel_bl_funcs {
276
277 int (*setup)(struct intel_connector *connector, enum pipe pipe);
278 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
279 void (*set)(const struct drm_connector_state *conn_state, u32 level);
280 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
281 void (*enable)(const struct intel_crtc_state *crtc_state,
282 const struct drm_connector_state *conn_state, u32 level);
283 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
284};
285
286struct intel_panel {
287 struct drm_display_mode *fixed_mode;
288 struct drm_display_mode *downclock_mode;
289
290
291 struct {
292 bool present;
293 u32 level;
294 u32 min;
295 u32 max;
296 bool enabled;
297 bool combination_mode;
298 bool active_low_pwm;
299 bool alternate_pwm_increment;
300
301
302 u32 pwm_level_min;
303 u32 pwm_level_max;
304 bool pwm_enabled;
305 bool util_pin_active_low;
306 u8 controller;
307 struct pwm_device *pwm;
308 struct pwm_state pwm_state;
309
310
311 union {
312 struct {
313 u8 pwmgen_bit_count;
314 } vesa;
315 struct {
316 bool sdr_uses_aux;
317 } intel;
318 } edp;
319
320 struct backlight_device *device;
321
322 const struct intel_panel_bl_funcs *funcs;
323 const struct intel_panel_bl_funcs *pwm_funcs;
324 void (*power)(struct intel_connector *, bool enable);
325 } backlight;
326};
327
328struct intel_digital_port;
329
330enum check_link_response {
331 HDCP_LINK_PROTECTED = 0,
332 HDCP_TOPOLOGY_CHANGE,
333 HDCP_LINK_INTEGRITY_FAILURE,
334 HDCP_REAUTH_REQUEST
335};
336
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363
364struct intel_hdcp_shim {
365
366 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
367
368
369 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
370
371
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373
374
375
376
377 int (*read_bstatus)(struct intel_digital_port *dig_port,
378 u8 *bstatus);
379
380
381 int (*repeater_present)(struct intel_digital_port *dig_port,
382 bool *repeater_present);
383
384
385 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
386
387
388 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
389 bool *ksv_ready);
390
391
392 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
393 int num_downstream, u8 *ksv_fifo);
394
395
396 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
397 int i, u32 *part);
398
399
400 int (*toggle_signalling)(struct intel_digital_port *dig_port,
401 enum transcoder cpu_transcoder,
402 bool enable);
403
404
405 int (*stream_encryption)(struct intel_connector *connector,
406 bool enable);
407
408
409 bool (*check_link)(struct intel_digital_port *dig_port,
410 struct intel_connector *connector);
411
412
413 int (*hdcp_capable)(struct intel_digital_port *dig_port,
414 bool *hdcp_capable);
415
416
417 enum hdcp_wired_protocol protocol;
418
419
420 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
421 bool *capable);
422
423
424 int (*streams_type1_capable)(struct intel_connector *connector,
425 bool *capable);
426
427
428 int (*write_2_2_msg)(struct intel_digital_port *dig_port,
429 void *buf, size_t size);
430
431
432 int (*read_2_2_msg)(struct intel_digital_port *dig_port,
433 u8 msg_id, void *buf, size_t size);
434
435
436
437
438
439
440 int (*config_stream_type)(struct intel_digital_port *dig_port,
441 bool is_repeater, u8 type);
442
443
444 int (*stream_2_2_encryption)(struct intel_connector *connector,
445 bool enable);
446
447
448 int (*check_2_2_link)(struct intel_digital_port *dig_port,
449 struct intel_connector *connector);
450};
451
452struct intel_hdcp {
453 const struct intel_hdcp_shim *shim;
454
455 struct mutex mutex;
456 u64 value;
457 struct delayed_work check_work;
458 struct work_struct prop_work;
459
460
461 bool hdcp_encrypted;
462
463
464
465 bool hdcp2_supported;
466
467
468 bool hdcp2_encrypted;
469
470
471
472
473
474
475 u8 content_type;
476
477 bool is_paired;
478 bool is_repeater;
479
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483
484
485 u32 seq_num_v;
486
487
488
489
490
491
492
493 u32 seq_num_m;
494
495
496
497
498
499 wait_queue_head_t cp_irq_queue;
500 atomic_t cp_irq_count;
501 int cp_irq_count_cached;
502
503
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505
506
507
508 enum transcoder cpu_transcoder;
509
510 enum transcoder stream_transcoder;
511};
512
513struct intel_connector {
514 struct drm_connector base;
515
516
517
518 struct intel_encoder *encoder;
519
520
521 u32 acpi_device_id;
522
523
524
525 bool (*get_hw_state)(struct intel_connector *);
526
527
528 struct intel_panel panel;
529
530
531 struct edid *edid;
532 struct edid *detect_edid;
533
534
535 int hotplug_retries;
536
537
538
539 u8 polled;
540
541 struct drm_dp_mst_port *port;
542
543 struct intel_dp *mst_port;
544
545
546 struct work_struct modeset_retry_work;
547
548 struct intel_hdcp hdcp;
549};
550
551struct intel_digital_connector_state {
552 struct drm_connector_state base;
553
554 enum hdmi_force_audio force_audio;
555 int broadcast_rgb;
556};
557
558#define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
559
560struct dpll {
561
562 int n;
563 int m1, m2;
564 int p1, p2;
565
566 int dot;
567 int vco;
568 int m;
569 int p;
570};
571
572struct intel_atomic_state {
573 struct drm_atomic_state base;
574
575 intel_wakeref_t wakeref;
576
577 struct __intel_global_objs_state *global_objs;
578 int num_global_objs;
579
580 bool dpll_set, modeset;
581
582 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
583
584
585
586
587
588 bool skip_intermediate_wm;
589
590 bool rps_interactive;
591
592 struct i915_sw_fence commit_ready;
593
594 struct llist_node freed;
595};
596
597struct intel_plane_state {
598 struct drm_plane_state uapi;
599
600
601
602
603
604
605 struct {
606 struct drm_crtc *crtc;
607 struct drm_framebuffer *fb;
608
609 u16 alpha;
610 u16 pixel_blend_mode;
611 unsigned int rotation;
612 enum drm_color_encoding color_encoding;
613 enum drm_color_range color_range;
614 enum drm_scaling_filter scaling_filter;
615 } hw;
616
617 struct i915_vma *ggtt_vma;
618 struct i915_vma *dpt_vma;
619 unsigned long flags;
620#define PLANE_HAS_FENCE BIT(0)
621
622 struct intel_fb_view view;
623
624
625 u32 ctl;
626
627
628 u32 color_ctl;
629
630
631 u32 cus_ctl;
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651 int scaler_id;
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660
661 struct intel_plane *planar_linked_plane;
662
663
664
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666
667
668
669
670
671 u32 planar_slave;
672
673 struct drm_intel_sprite_colorkey ckey;
674
675 struct drm_rect psr2_sel_fetch_area;
676
677
678 u64 ccval;
679};
680
681struct intel_initial_plane_config {
682 struct intel_framebuffer *fb;
683 struct i915_vma *vma;
684 unsigned int tiling;
685 int size;
686 u32 base;
687 u8 rotation;
688};
689
690struct intel_scaler {
691 int in_use;
692 u32 mode;
693};
694
695struct intel_crtc_scaler_state {
696#define SKL_NUM_SCALERS 2
697 struct intel_scaler scalers[SKL_NUM_SCALERS];
698
699
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715
716#define SKL_CRTC_INDEX 31
717 unsigned scaler_users;
718
719
720 int scaler_id;
721};
722
723
724
725#define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
726
727#define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
728
729
730
731
732
733#define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
734
735#define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
736
737#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
738
739#define I915_MODE_FLAG_VRR (1<<6)
740
741struct intel_wm_level {
742 bool enable;
743 u32 pri_val;
744 u32 spr_val;
745 u32 cur_val;
746 u32 fbc_val;
747};
748
749struct intel_pipe_wm {
750 struct intel_wm_level wm[5];
751 bool fbc_wm_enabled;
752 bool pipe_enabled;
753 bool sprites_enabled;
754 bool sprites_scaled;
755};
756
757struct skl_wm_level {
758 u16 min_ddb_alloc;
759 u16 blocks;
760 u8 lines;
761 bool enable;
762 bool ignore_lines;
763 bool can_sagv;
764};
765
766struct skl_plane_wm {
767 struct skl_wm_level wm[8];
768 struct skl_wm_level uv_wm[8];
769 struct skl_wm_level trans_wm;
770 struct {
771 struct skl_wm_level wm0;
772 struct skl_wm_level trans_wm;
773 } sagv;
774 bool is_planar;
775};
776
777struct skl_pipe_wm {
778 struct skl_plane_wm planes[I915_MAX_PLANES];
779 bool use_sagv_wm;
780};
781
782enum vlv_wm_level {
783 VLV_WM_LEVEL_PM2,
784 VLV_WM_LEVEL_PM5,
785 VLV_WM_LEVEL_DDR_DVFS,
786 NUM_VLV_WM_LEVELS,
787};
788
789struct vlv_wm_state {
790 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
791 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
792 u8 num_levels;
793 bool cxsr;
794};
795
796struct vlv_fifo_state {
797 u16 plane[I915_MAX_PLANES];
798};
799
800enum g4x_wm_level {
801 G4X_WM_LEVEL_NORMAL,
802 G4X_WM_LEVEL_SR,
803 G4X_WM_LEVEL_HPLL,
804 NUM_G4X_WM_LEVELS,
805};
806
807struct g4x_wm_state {
808 struct g4x_pipe_wm wm;
809 struct g4x_sr_wm sr;
810 struct g4x_sr_wm hpll;
811 bool cxsr;
812 bool hpll_en;
813 bool fbc_en;
814};
815
816struct intel_crtc_wm_state {
817 union {
818
819
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822
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838
839
840 struct {
841 struct intel_pipe_wm intermediate;
842 struct intel_pipe_wm optimal;
843 } ilk;
844
845 struct {
846 struct skl_pipe_wm raw;
847
848 struct skl_pipe_wm optimal;
849 struct skl_ddb_entry ddb;
850 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
851 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
852 } skl;
853
854 struct {
855 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
856 struct vlv_wm_state intermediate;
857 struct vlv_wm_state optimal;
858 struct vlv_fifo_state fifo_state;
859 } vlv;
860
861 struct {
862 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
863 struct g4x_wm_state intermediate;
864 struct g4x_wm_state optimal;
865 } g4x;
866 };
867
868
869
870
871
872
873
874 bool need_postvbl_update;
875};
876
877enum intel_output_format {
878 INTEL_OUTPUT_FORMAT_RGB,
879 INTEL_OUTPUT_FORMAT_YCBCR420,
880 INTEL_OUTPUT_FORMAT_YCBCR444,
881};
882
883struct intel_crtc_state {
884
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890
891
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893
894 struct drm_crtc_state uapi;
895
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912
913 struct {
914 bool active, enable;
915 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
916 struct drm_display_mode mode, pipe_mode, adjusted_mode;
917 enum drm_scaling_filter scaling_filter;
918 } hw;
919
920
921
922
923
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925
926
927
928#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0)
929#define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1)
930 unsigned long quirks;
931
932 unsigned fb_bits;
933 bool update_pipe;
934 bool disable_cxsr;
935 bool update_wm_pre, update_wm_post;
936 bool fifo_changed;
937 bool preload_luts;
938 bool inherited;
939
940
941
942
943 int pipe_src_w, pipe_src_h;
944
945
946
947
948
949 unsigned int pixel_rate;
950
951
952
953 bool has_pch_encoder;
954
955
956 bool has_infoframe;
957
958
959
960
961 enum transcoder cpu_transcoder;
962
963
964
965
966
967 bool limited_color_range;
968
969
970
971
972 unsigned int output_types;
973
974
975 bool has_hdmi_sink;
976
977
978
979 bool has_audio;
980
981
982
983
984
985 bool dither;
986
987
988
989
990
991
992
993 bool dither_force_disable;
994
995
996 bool clock_set;
997
998
999
1000 bool sdvo_tv_clock;
1001
1002
1003
1004
1005
1006
1007 bool bw_constrained;
1008
1009
1010
1011 struct dpll dpll;
1012
1013
1014 struct intel_shared_dpll *shared_dpll;
1015
1016
1017 struct intel_dpll_hw_state dpll_hw_state;
1018
1019
1020
1021
1022
1023 struct icl_port_dpll {
1024 struct intel_shared_dpll *pll;
1025 struct intel_dpll_hw_state hw_state;
1026 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
1027
1028
1029 struct {
1030 u32 ctrl, div;
1031 } dsi_pll;
1032
1033 int pipe_bpp;
1034 struct intel_link_m_n dp_m_n;
1035
1036
1037 struct intel_link_m_n dp_m2_n2;
1038 bool has_drrs;
1039
1040 bool has_psr;
1041 bool has_psr2;
1042 bool enable_psr2_sel_fetch;
1043 u32 dc3co_exitline;
1044
1045
1046
1047
1048
1049
1050 int port_clock;
1051
1052
1053 unsigned pixel_multiplier;
1054
1055
1056 u8 mode_flags;
1057
1058 u8 lane_count;
1059
1060
1061
1062
1063
1064 u8 lane_lat_optim_mask;
1065
1066
1067 u8 min_voltage_level;
1068
1069
1070 struct {
1071 u32 control;
1072 u32 pgm_ratios;
1073 u32 lvds_border_bits;
1074 } gmch_pfit;
1075
1076
1077 struct {
1078 struct drm_rect dst;
1079 bool enabled;
1080 bool force_thru;
1081 } pch_pfit;
1082
1083
1084 int fdi_lanes;
1085 struct intel_link_m_n fdi_m_n;
1086
1087 bool ips_enabled;
1088
1089 bool crc_enabled;
1090
1091 bool enable_fbc;
1092
1093 bool double_wide;
1094
1095 int pbn;
1096
1097 struct intel_crtc_scaler_state scaler_state;
1098
1099
1100 enum pipe hsw_workaround_pipe;
1101
1102
1103 bool disable_lp_wm;
1104
1105 struct intel_crtc_wm_state wm;
1106
1107 int min_cdclk[I915_MAX_PLANES];
1108
1109 u32 data_rate[I915_MAX_PLANES];
1110
1111
1112 u64 plane_data_rate[I915_MAX_PLANES];
1113 u64 uv_plane_data_rate[I915_MAX_PLANES];
1114
1115
1116 u32 gamma_mode;
1117
1118 union {
1119
1120 u32 csc_mode;
1121
1122
1123 u32 cgm_mode;
1124 };
1125
1126
1127 u8 enabled_planes;
1128
1129
1130 u8 active_planes;
1131 u8 nv12_planes;
1132 u8 c8_planes;
1133
1134
1135 u8 update_planes;
1136
1137 struct {
1138 u32 enable;
1139 u32 gcp;
1140 union hdmi_infoframe avi;
1141 union hdmi_infoframe spd;
1142 union hdmi_infoframe hdmi;
1143 union hdmi_infoframe drm;
1144 struct drm_dp_vsc_sdp vsc;
1145 } infoframes;
1146
1147
1148 bool hdmi_scrambling;
1149
1150
1151 bool hdmi_high_tmds_clock_ratio;
1152
1153
1154 enum intel_output_format output_format;
1155
1156
1157 bool gamma_enable;
1158
1159
1160 bool csc_enable;
1161
1162
1163 bool bigjoiner;
1164
1165
1166 bool bigjoiner_slave;
1167
1168
1169 struct intel_crtc *bigjoiner_linked_crtc;
1170
1171
1172 struct {
1173 bool compression_enable;
1174 bool dsc_split;
1175 u16 compressed_bpp;
1176 u8 slice_count;
1177 struct drm_dsc_config config;
1178 } dsc;
1179
1180
1181 u16 linetime;
1182 u16 ips_linetime;
1183
1184
1185 bool fec_enable;
1186
1187
1188 enum transcoder master_transcoder;
1189
1190
1191 u8 sync_mode_slaves_mask;
1192
1193
1194 enum transcoder mst_master_transcoder;
1195
1196
1197 struct intel_dsb *dsb;
1198
1199 u32 psr2_man_track_ctl;
1200
1201
1202 struct {
1203 bool enable;
1204 u8 pipeline_full;
1205 u16 flipline, vmin, vmax, guardband;
1206 } vrr;
1207
1208
1209 struct {
1210 bool enable;
1211 u8 link_count;
1212 u8 pixel_overlap;
1213 } splitter;
1214};
1215
1216enum intel_pipe_crc_source {
1217 INTEL_PIPE_CRC_SOURCE_NONE,
1218 INTEL_PIPE_CRC_SOURCE_PLANE1,
1219 INTEL_PIPE_CRC_SOURCE_PLANE2,
1220 INTEL_PIPE_CRC_SOURCE_PLANE3,
1221 INTEL_PIPE_CRC_SOURCE_PLANE4,
1222 INTEL_PIPE_CRC_SOURCE_PLANE5,
1223 INTEL_PIPE_CRC_SOURCE_PLANE6,
1224 INTEL_PIPE_CRC_SOURCE_PLANE7,
1225 INTEL_PIPE_CRC_SOURCE_PIPE,
1226
1227 INTEL_PIPE_CRC_SOURCE_TV,
1228 INTEL_PIPE_CRC_SOURCE_DP_B,
1229 INTEL_PIPE_CRC_SOURCE_DP_C,
1230 INTEL_PIPE_CRC_SOURCE_DP_D,
1231 INTEL_PIPE_CRC_SOURCE_AUTO,
1232 INTEL_PIPE_CRC_SOURCE_MAX,
1233};
1234
1235#define INTEL_PIPE_CRC_ENTRIES_NR 128
1236struct intel_pipe_crc {
1237 spinlock_t lock;
1238 int skipped;
1239 enum intel_pipe_crc_source source;
1240};
1241
1242struct intel_crtc {
1243 struct drm_crtc base;
1244 enum pipe pipe;
1245
1246
1247
1248
1249
1250 bool active;
1251 u8 plane_ids_mask;
1252
1253
1254 u8 mode_flags;
1255
1256 u16 vmax_vblank_start;
1257
1258 struct intel_display_power_domain_set enabled_power_domains;
1259 struct intel_overlay *overlay;
1260
1261 struct intel_crtc_state *config;
1262
1263
1264 bool cpu_fifo_underrun_disabled;
1265 bool pch_fifo_underrun_disabled;
1266
1267
1268 struct {
1269
1270 union {
1271 struct intel_pipe_wm ilk;
1272 struct vlv_wm_state vlv;
1273 struct g4x_wm_state g4x;
1274 } active;
1275 } wm;
1276
1277 int scanline_offset;
1278
1279 struct {
1280 unsigned start_vbl_count;
1281 ktime_t start_vbl_time;
1282 int min_vbl, max_vbl;
1283 int scanline_start;
1284#ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1285 struct {
1286 u64 min;
1287 u64 max;
1288 u64 sum;
1289 unsigned int over;
1290 unsigned int times[17];
1291 } vbl;
1292#endif
1293 } debug;
1294
1295
1296 int num_scalers;
1297
1298#ifdef CONFIG_DEBUG_FS
1299 struct intel_pipe_crc pipe_crc;
1300#endif
1301};
1302
1303struct intel_plane {
1304 struct drm_plane base;
1305 enum i9xx_plane_id i9xx_plane;
1306 enum plane_id id;
1307 enum pipe pipe;
1308 bool has_fbc;
1309 bool has_ccs;
1310 bool need_async_flip_disable_wa;
1311 u32 frontbuffer_bit;
1312
1313 struct {
1314 u32 base, cntl, size;
1315 } cursor;
1316
1317
1318
1319
1320
1321
1322
1323 int (*min_width)(const struct drm_framebuffer *fb,
1324 int color_plane,
1325 unsigned int rotation);
1326 int (*max_width)(const struct drm_framebuffer *fb,
1327 int color_plane,
1328 unsigned int rotation);
1329 int (*max_height)(const struct drm_framebuffer *fb,
1330 int color_plane,
1331 unsigned int rotation);
1332 unsigned int (*max_stride)(struct intel_plane *plane,
1333 u32 pixel_format, u64 modifier,
1334 unsigned int rotation);
1335 void (*update_plane)(struct intel_plane *plane,
1336 const struct intel_crtc_state *crtc_state,
1337 const struct intel_plane_state *plane_state);
1338 void (*disable_plane)(struct intel_plane *plane,
1339 const struct intel_crtc_state *crtc_state);
1340 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1341 int (*check_plane)(struct intel_crtc_state *crtc_state,
1342 struct intel_plane_state *plane_state);
1343 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1344 const struct intel_plane_state *plane_state);
1345 void (*async_flip)(struct intel_plane *plane,
1346 const struct intel_crtc_state *crtc_state,
1347 const struct intel_plane_state *plane_state,
1348 bool async_flip);
1349 void (*enable_flip_done)(struct intel_plane *plane);
1350 void (*disable_flip_done)(struct intel_plane *plane);
1351};
1352
1353struct intel_watermark_params {
1354 u16 fifo_size;
1355 u16 max_wm;
1356 u8 default_wm;
1357 u8 guard_size;
1358 u8 cacheline_size;
1359};
1360
1361struct cxsr_latency {
1362 bool is_desktop : 1;
1363 bool is_ddr3 : 1;
1364 u16 fsb_freq;
1365 u16 mem_freq;
1366 u16 display_sr;
1367 u16 display_hpll_disable;
1368 u16 cursor_sr;
1369 u16 cursor_hpll_disable;
1370};
1371
1372#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1373#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1374#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1375#define to_intel_connector(x) container_of(x, struct intel_connector, base)
1376#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1377#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1378#define to_intel_plane(x) container_of(x, struct intel_plane, base)
1379#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1380#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1381
1382struct intel_hdmi {
1383 i915_reg_t hdmi_reg;
1384 int ddc_bus;
1385 struct {
1386 enum drm_dp_dual_mode_type type;
1387 int max_tmds_clock;
1388 } dp_dual_mode;
1389 bool has_hdmi_sink;
1390 bool has_audio;
1391 struct intel_connector *attached_connector;
1392 struct cec_notifier *cec_notifier;
1393};
1394
1395struct intel_dp_mst_encoder;
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410enum link_m_n_set {
1411
1412 M1_N1 = 0,
1413 M2_N2
1414};
1415
1416struct intel_dp_compliance_data {
1417 unsigned long edid;
1418 u8 video_pattern;
1419 u16 hdisplay, vdisplay;
1420 u8 bpc;
1421 struct drm_dp_phy_test_params phytest;
1422};
1423
1424struct intel_dp_compliance {
1425 unsigned long test_type;
1426 struct intel_dp_compliance_data test_data;
1427 bool test_active;
1428 int test_link_rate;
1429 u8 test_lane_count;
1430};
1431
1432struct intel_dp_pcon_frl {
1433 bool is_trained;
1434 int trained_rate_gbps;
1435};
1436
1437struct intel_pps {
1438 int panel_power_up_delay;
1439 int panel_power_down_delay;
1440 int panel_power_cycle_delay;
1441 int backlight_on_delay;
1442 int backlight_off_delay;
1443 struct delayed_work panel_vdd_work;
1444 bool want_panel_vdd;
1445 unsigned long last_power_on;
1446 unsigned long last_backlight_off;
1447 ktime_t panel_power_off_time;
1448 intel_wakeref_t vdd_wakeref;
1449
1450
1451
1452
1453
1454 enum pipe pps_pipe;
1455
1456
1457
1458
1459
1460 enum pipe active_pipe;
1461
1462
1463
1464
1465 bool pps_reset;
1466 struct edp_power_seq pps_delays;
1467};
1468
1469struct intel_psr {
1470
1471 struct mutex lock;
1472
1473#define I915_PSR_DEBUG_MODE_MASK 0x0f
1474#define I915_PSR_DEBUG_DEFAULT 0x00
1475#define I915_PSR_DEBUG_DISABLE 0x01
1476#define I915_PSR_DEBUG_ENABLE 0x02
1477#define I915_PSR_DEBUG_FORCE_PSR1 0x03
1478#define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1479#define I915_PSR_DEBUG_IRQ 0x10
1480
1481 u32 debug;
1482 bool sink_support;
1483 bool source_support;
1484 bool enabled;
1485 bool paused;
1486 enum pipe pipe;
1487 enum transcoder transcoder;
1488 bool active;
1489 struct work_struct work;
1490 unsigned int busy_frontbuffer_bits;
1491 bool sink_psr2_support;
1492 bool link_standby;
1493 bool colorimetry_support;
1494 bool psr2_enabled;
1495 bool psr2_sel_fetch_enabled;
1496 u8 sink_sync_latency;
1497 ktime_t last_entry_attempt;
1498 ktime_t last_exit;
1499 bool sink_not_reliable;
1500 bool irq_aux_error;
1501 u16 su_x_granularity;
1502 u32 dc3co_exitline;
1503 u32 dc3co_exit_delay;
1504 struct delayed_work dc3co_work;
1505 struct drm_dp_vsc_sdp vsc;
1506};
1507
1508struct intel_dp {
1509 i915_reg_t output_reg;
1510 u32 DP;
1511 int link_rate;
1512 u8 lane_count;
1513 u8 sink_count;
1514 bool link_trained;
1515 bool has_hdmi_sink;
1516 bool has_audio;
1517 bool reset_link_params;
1518 bool use_max_params;
1519 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1520 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1521 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1522 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1523 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1524 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1525 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1526 u8 fec_capable;
1527 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1528
1529 int num_source_rates;
1530 const int *source_rates;
1531
1532 int num_sink_rates;
1533 int sink_rates[DP_MAX_SUPPORTED_RATES];
1534 bool use_rate_select;
1535
1536 int num_common_rates;
1537 int common_rates[DP_MAX_SUPPORTED_RATES];
1538
1539 int max_link_lane_count;
1540
1541 int max_link_rate;
1542 int mso_link_count;
1543 int mso_pixel_overlap;
1544
1545 struct drm_dp_desc desc;
1546 struct drm_dp_aux aux;
1547 u32 aux_busy_last_status;
1548 u8 train_set[4];
1549
1550 struct intel_pps pps;
1551
1552 bool can_mst;
1553 bool is_mst;
1554 int active_mst_links;
1555
1556
1557 struct intel_connector *attached_connector;
1558
1559
1560 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1561 struct drm_dp_mst_topology_mgr mst_mgr;
1562
1563 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1564
1565
1566
1567
1568 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1569 u32 aux_clock_divider);
1570
1571 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1572 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1573
1574
1575 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1576 const struct intel_crtc_state *crtc_state);
1577 void (*set_link_train)(struct intel_dp *intel_dp,
1578 const struct intel_crtc_state *crtc_state,
1579 u8 dp_train_pat);
1580 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1581 const struct intel_crtc_state *crtc_state);
1582 void (*set_signal_levels)(struct intel_dp *intel_dp,
1583 const struct intel_crtc_state *crtc_state);
1584
1585 u8 (*preemph_max)(struct intel_dp *intel_dp);
1586 u8 (*voltage_max)(struct intel_dp *intel_dp,
1587 const struct intel_crtc_state *crtc_state);
1588
1589
1590 struct intel_dp_compliance compliance;
1591
1592
1593 struct {
1594 int min_tmds_clock, max_tmds_clock;
1595 int max_dotclock;
1596 int pcon_max_frl_bw;
1597 u8 max_bpc;
1598 bool ycbcr_444_to_420;
1599 bool rgb_to_ycbcr;
1600 } dfp;
1601
1602
1603 struct pm_qos_request pm_qos;
1604
1605
1606 bool force_dsc_en;
1607
1608 bool hobl_failed;
1609 bool hobl_active;
1610
1611 struct intel_dp_pcon_frl frl;
1612
1613 struct intel_psr psr;
1614};
1615
1616enum lspcon_vendor {
1617 LSPCON_VENDOR_MCA,
1618 LSPCON_VENDOR_PARADE
1619};
1620
1621struct intel_lspcon {
1622 bool active;
1623 bool hdr_supported;
1624 enum drm_lspcon_mode mode;
1625 enum lspcon_vendor vendor;
1626};
1627
1628struct intel_digital_port {
1629 struct intel_encoder base;
1630 u32 saved_port_bits;
1631 struct intel_dp dp;
1632 struct intel_hdmi hdmi;
1633 struct intel_lspcon lspcon;
1634 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1635 bool release_cl2_override;
1636 u8 max_lanes;
1637
1638 enum aux_ch aux_ch;
1639 enum intel_display_power_domain ddi_io_power_domain;
1640 intel_wakeref_t ddi_io_wakeref;
1641 intel_wakeref_t aux_wakeref;
1642 struct mutex tc_lock;
1643 intel_wakeref_t tc_lock_wakeref;
1644 int tc_link_refcount;
1645 bool tc_legacy_port:1;
1646 char tc_port_name[8];
1647 enum tc_port_mode tc_mode;
1648 enum phy_fia tc_phy_fia;
1649 u8 tc_phy_fia_idx;
1650
1651
1652 struct mutex hdcp_mutex;
1653
1654 unsigned int num_hdcp_streams;
1655
1656 bool hdcp_auth_status;
1657
1658 struct hdcp_port_data hdcp_port_data;
1659
1660 void (*write_infoframe)(struct intel_encoder *encoder,
1661 const struct intel_crtc_state *crtc_state,
1662 unsigned int type,
1663 const void *frame, ssize_t len);
1664 void (*read_infoframe)(struct intel_encoder *encoder,
1665 const struct intel_crtc_state *crtc_state,
1666 unsigned int type,
1667 void *frame, ssize_t len);
1668 void (*set_infoframes)(struct intel_encoder *encoder,
1669 bool enable,
1670 const struct intel_crtc_state *crtc_state,
1671 const struct drm_connector_state *conn_state);
1672 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1673 const struct intel_crtc_state *pipe_config);
1674 bool (*connected)(struct intel_encoder *encoder);
1675};
1676
1677struct intel_dp_mst_encoder {
1678 struct intel_encoder base;
1679 enum pipe pipe;
1680 struct intel_digital_port *primary;
1681 struct intel_connector *connector;
1682};
1683
1684static inline enum dpio_channel
1685vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
1686{
1687 switch (dig_port->base.port) {
1688 case PORT_B:
1689 case PORT_D:
1690 return DPIO_CH0;
1691 case PORT_C:
1692 return DPIO_CH1;
1693 default:
1694 BUG();
1695 }
1696}
1697
1698static inline enum dpio_phy
1699vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
1700{
1701 switch (dig_port->base.port) {
1702 case PORT_B:
1703 case PORT_C:
1704 return DPIO_PHY0;
1705 case PORT_D:
1706 return DPIO_PHY1;
1707 default:
1708 BUG();
1709 }
1710}
1711
1712static inline enum dpio_channel
1713vlv_pipe_to_channel(enum pipe pipe)
1714{
1715 switch (pipe) {
1716 case PIPE_A:
1717 case PIPE_C:
1718 return DPIO_CH0;
1719 case PIPE_B:
1720 return DPIO_CH1;
1721 default:
1722 BUG();
1723 }
1724}
1725
1726static inline bool intel_pipe_valid(struct drm_i915_private *i915, enum pipe pipe)
1727{
1728 return (pipe >= 0 &&
1729 pipe < ARRAY_SIZE(i915->pipe_to_crtc_mapping) &&
1730 INTEL_INFO(i915)->pipe_mask & BIT(pipe) &&
1731 i915->pipe_to_crtc_mapping[pipe]);
1732}
1733
1734static inline struct intel_crtc *
1735intel_get_first_crtc(struct drm_i915_private *dev_priv)
1736{
1737 return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0));
1738}
1739
1740static inline struct intel_crtc *
1741intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1742{
1743
1744 drm_WARN_ON(&dev_priv->drm,
1745 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe)));
1746 return dev_priv->pipe_to_crtc_mapping[pipe];
1747}
1748
1749static inline struct intel_crtc *
1750intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1751{
1752 return dev_priv->plane_to_crtc_mapping[plane];
1753}
1754
1755struct intel_load_detect_pipe {
1756 struct drm_atomic_state *restore_state;
1757};
1758
1759static inline struct intel_encoder *
1760intel_attached_encoder(struct intel_connector *connector)
1761{
1762 return connector->encoder;
1763}
1764
1765static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1766{
1767 switch (encoder->type) {
1768 case INTEL_OUTPUT_DDI:
1769 case INTEL_OUTPUT_DP:
1770 case INTEL_OUTPUT_EDP:
1771 case INTEL_OUTPUT_HDMI:
1772 return true;
1773 default:
1774 return false;
1775 }
1776}
1777
1778static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1779{
1780 return encoder->type == INTEL_OUTPUT_DP_MST;
1781}
1782
1783static inline struct intel_dp_mst_encoder *
1784enc_to_mst(struct intel_encoder *encoder)
1785{
1786 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1787 base.base);
1788}
1789
1790static inline struct intel_digital_port *
1791enc_to_dig_port(struct intel_encoder *encoder)
1792{
1793 struct intel_encoder *intel_encoder = encoder;
1794
1795 if (intel_encoder_is_dig_port(intel_encoder))
1796 return container_of(&encoder->base, struct intel_digital_port,
1797 base.base);
1798 else if (intel_encoder_is_mst(intel_encoder))
1799 return enc_to_mst(encoder)->primary;
1800 else
1801 return NULL;
1802}
1803
1804static inline struct intel_digital_port *
1805intel_attached_dig_port(struct intel_connector *connector)
1806{
1807 return enc_to_dig_port(intel_attached_encoder(connector));
1808}
1809
1810static inline struct intel_hdmi *
1811enc_to_intel_hdmi(struct intel_encoder *encoder)
1812{
1813 return &enc_to_dig_port(encoder)->hdmi;
1814}
1815
1816static inline struct intel_hdmi *
1817intel_attached_hdmi(struct intel_connector *connector)
1818{
1819 return enc_to_intel_hdmi(intel_attached_encoder(connector));
1820}
1821
1822static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1823{
1824 return &enc_to_dig_port(encoder)->dp;
1825}
1826
1827static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1828{
1829 return enc_to_intel_dp(intel_attached_encoder(connector));
1830}
1831
1832static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1833{
1834 switch (encoder->type) {
1835 case INTEL_OUTPUT_DP:
1836 case INTEL_OUTPUT_EDP:
1837 return true;
1838 case INTEL_OUTPUT_DDI:
1839
1840 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1841 default:
1842 return false;
1843 }
1844}
1845
1846static inline struct intel_lspcon *
1847enc_to_intel_lspcon(struct intel_encoder *encoder)
1848{
1849 return &enc_to_dig_port(encoder)->lspcon;
1850}
1851
1852static inline struct intel_digital_port *
1853dp_to_dig_port(struct intel_dp *intel_dp)
1854{
1855 return container_of(intel_dp, struct intel_digital_port, dp);
1856}
1857
1858static inline struct intel_lspcon *
1859dp_to_lspcon(struct intel_dp *intel_dp)
1860{
1861 return &dp_to_dig_port(intel_dp)->lspcon;
1862}
1863
1864static inline struct drm_i915_private *
1865dp_to_i915(struct intel_dp *intel_dp)
1866{
1867 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1868}
1869
1870#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
1871 (intel_dp)->psr.source_support)
1872
1873static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
1874{
1875 if (!intel_encoder_is_dp(encoder))
1876 return false;
1877
1878 return CAN_PSR(enc_to_intel_dp(encoder));
1879}
1880
1881static inline struct intel_digital_port *
1882hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1883{
1884 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1885}
1886
1887static inline struct intel_plane_state *
1888intel_atomic_get_plane_state(struct intel_atomic_state *state,
1889 struct intel_plane *plane)
1890{
1891 struct drm_plane_state *ret =
1892 drm_atomic_get_plane_state(&state->base, &plane->base);
1893
1894 if (IS_ERR(ret))
1895 return ERR_CAST(ret);
1896
1897 return to_intel_plane_state(ret);
1898}
1899
1900static inline struct intel_plane_state *
1901intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1902 struct intel_plane *plane)
1903{
1904 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1905 &plane->base));
1906}
1907
1908static inline struct intel_plane_state *
1909intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1910 struct intel_plane *plane)
1911{
1912 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1913 &plane->base));
1914}
1915
1916static inline struct intel_crtc_state *
1917intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1918 struct intel_crtc *crtc)
1919{
1920 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1921 &crtc->base));
1922}
1923
1924static inline struct intel_crtc_state *
1925intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1926 struct intel_crtc *crtc)
1927{
1928 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1929 &crtc->base));
1930}
1931
1932static inline struct intel_digital_connector_state *
1933intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
1934 struct intel_connector *connector)
1935{
1936 return to_intel_digital_connector_state(
1937 drm_atomic_get_new_connector_state(&state->base,
1938 &connector->base));
1939}
1940
1941static inline struct intel_digital_connector_state *
1942intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
1943 struct intel_connector *connector)
1944{
1945 return to_intel_digital_connector_state(
1946 drm_atomic_get_old_connector_state(&state->base,
1947 &connector->base));
1948}
1949
1950
1951static inline bool
1952intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1953 enum intel_output_type type)
1954{
1955 return crtc_state->output_types & (1 << type);
1956}
1957static inline bool
1958intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1959{
1960 return crtc_state->output_types &
1961 ((1 << INTEL_OUTPUT_DP) |
1962 (1 << INTEL_OUTPUT_DP_MST) |
1963 (1 << INTEL_OUTPUT_EDP));
1964}
1965
1966static inline bool
1967intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
1968{
1969 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
1970}
1971
1972static inline void
1973intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1974{
1975 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1976
1977 drm_crtc_wait_one_vblank(&crtc->base);
1978}
1979
1980static inline void
1981intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
1982{
1983 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1984
1985 if (crtc->active)
1986 intel_wait_for_vblank(dev_priv, pipe);
1987}
1988
1989static inline bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
1990{
1991 return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR;
1992}
1993
1994static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
1995{
1996 return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
1997}
1998
1999static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
2000{
2001 return i915_ggtt_offset(plane_state->ggtt_vma);
2002}
2003
2004static inline struct intel_frontbuffer *
2005to_intel_frontbuffer(struct drm_framebuffer *fb)
2006{
2007 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
2008}
2009
2010static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
2011{
2012 if (dev_priv->params.panel_use_ssc >= 0)
2013 return dev_priv->params.panel_use_ssc != 0;
2014 return dev_priv->vbt.lvds_use_ssc
2015 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
2016}
2017
2018static inline u32 i9xx_dpll_compute_fp(struct dpll *dpll)
2019{
2020 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
2021}
2022
2023static inline u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
2024 const struct intel_crtc_state *pipe_config)
2025{
2026 if (HAS_DDI(dev_priv))
2027 return pipe_config->port_clock;
2028 else
2029 return dev_priv->fdi_pll_freq;
2030}
2031
2032static inline bool is_ccs_modifier(u64 modifier)
2033{
2034 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2035 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
2036 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2037 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2038 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2039}
2040
2041static inline bool is_gen12_ccs_modifier(u64 modifier)
2042{
2043 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2044 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
2045 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
2046}
2047
2048#endif
2049