1
2
3
4
5
6#include <linux/sched/mm.h>
7#include <linux/stop_machine.h>
8
9#include "display/intel_display_types.h"
10#include "display/intel_overlay.h"
11
12#include "gem/i915_gem_context.h"
13
14#include "i915_drv.h"
15#include "i915_gpu_error.h"
16#include "i915_irq.h"
17#include "intel_breadcrumbs.h"
18#include "intel_engine_pm.h"
19#include "intel_gt.h"
20#include "intel_gt_pm.h"
21#include "intel_gt_requests.h"
22#include "intel_reset.h"
23
24#include "uc/intel_guc.h"
25#include "uc/intel_guc_submission.h"
26
27#define RESET_MAX_RETRIES 3
28
29
30#define RESET_UNDER_STOP_MACHINE 0
31
32static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
33{
34 intel_uncore_rmw_fw(uncore, reg, 0, set);
35}
36
37static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
38{
39 intel_uncore_rmw_fw(uncore, reg, clr, 0);
40}
41
42static void skip_context(struct i915_request *rq)
43{
44 struct intel_context *hung_ctx = rq->context;
45
46 list_for_each_entry_from_rcu(rq, &hung_ctx->timeline->requests, link) {
47 if (!i915_request_is_active(rq))
48 return;
49
50 if (rq->context == hung_ctx) {
51 i915_request_set_error_once(rq, -EIO);
52 __i915_request_skip(rq);
53 }
54 }
55}
56
57static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
58{
59 struct drm_i915_file_private *file_priv = ctx->file_priv;
60 unsigned long prev_hang;
61 unsigned int score;
62
63 if (IS_ERR_OR_NULL(file_priv))
64 return;
65
66 score = 0;
67 if (banned)
68 score = I915_CLIENT_SCORE_CONTEXT_BAN;
69
70 prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
71 if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
72 score += I915_CLIENT_SCORE_HANG_FAST;
73
74 if (score) {
75 atomic_add(score, &file_priv->ban_score);
76
77 drm_dbg(&ctx->i915->drm,
78 "client %s: gained %u ban score, now %u\n",
79 ctx->name, score,
80 atomic_read(&file_priv->ban_score));
81 }
82}
83
84static bool mark_guilty(struct i915_request *rq)
85{
86 struct i915_gem_context *ctx;
87 unsigned long prev_hang;
88 bool banned;
89 int i;
90
91 if (intel_context_is_closed(rq->context)) {
92 intel_context_set_banned(rq->context);
93 return true;
94 }
95
96 rcu_read_lock();
97 ctx = rcu_dereference(rq->context->gem_context);
98 if (ctx && !kref_get_unless_zero(&ctx->ref))
99 ctx = NULL;
100 rcu_read_unlock();
101 if (!ctx)
102 return intel_context_is_banned(rq->context);
103
104 atomic_inc(&ctx->guilty_count);
105
106
107 if (!i915_gem_context_is_bannable(ctx)) {
108 banned = false;
109 goto out;
110 }
111
112 drm_notice(&ctx->i915->drm,
113 "%s context reset due to GPU hang\n",
114 ctx->name);
115
116
117 prev_hang = ctx->hang_timestamp[0];
118 for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp) - 1; i++)
119 ctx->hang_timestamp[i] = ctx->hang_timestamp[i + 1];
120 ctx->hang_timestamp[i] = jiffies;
121
122
123 banned = !i915_gem_context_is_recoverable(ctx);
124 if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
125 banned = true;
126 if (banned) {
127 drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n",
128 ctx->name, atomic_read(&ctx->guilty_count));
129 intel_context_set_banned(rq->context);
130 }
131
132 client_mark_guilty(ctx, banned);
133
134out:
135 i915_gem_context_put(ctx);
136 return banned;
137}
138
139static void mark_innocent(struct i915_request *rq)
140{
141 struct i915_gem_context *ctx;
142
143 rcu_read_lock();
144 ctx = rcu_dereference(rq->context->gem_context);
145 if (ctx)
146 atomic_inc(&ctx->active_count);
147 rcu_read_unlock();
148}
149
150void __i915_request_reset(struct i915_request *rq, bool guilty)
151{
152 RQ_TRACE(rq, "guilty? %s\n", yesno(guilty));
153 GEM_BUG_ON(__i915_request_is_complete(rq));
154
155 rcu_read_lock();
156 if (guilty) {
157 i915_request_set_error_once(rq, -EIO);
158 __i915_request_skip(rq);
159 if (mark_guilty(rq))
160 skip_context(rq);
161 } else {
162 i915_request_set_error_once(rq, -EAGAIN);
163 mark_innocent(rq);
164 }
165 rcu_read_unlock();
166}
167
168static bool i915_in_reset(struct pci_dev *pdev)
169{
170 u8 gdrst;
171
172 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
173 return gdrst & GRDOM_RESET_STATUS;
174}
175
176static int i915_do_reset(struct intel_gt *gt,
177 intel_engine_mask_t engine_mask,
178 unsigned int retry)
179{
180 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
181 int err;
182
183
184 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
185 udelay(50);
186 err = wait_for_atomic(i915_in_reset(pdev), 50);
187
188
189 pci_write_config_byte(pdev, I915_GDRST, 0);
190 udelay(50);
191 if (!err)
192 err = wait_for_atomic(!i915_in_reset(pdev), 50);
193
194 return err;
195}
196
197static bool g4x_reset_complete(struct pci_dev *pdev)
198{
199 u8 gdrst;
200
201 pci_read_config_byte(pdev, I915_GDRST, &gdrst);
202 return (gdrst & GRDOM_RESET_ENABLE) == 0;
203}
204
205static int g33_do_reset(struct intel_gt *gt,
206 intel_engine_mask_t engine_mask,
207 unsigned int retry)
208{
209 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
210
211 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
212 return wait_for_atomic(g4x_reset_complete(pdev), 50);
213}
214
215static int g4x_do_reset(struct intel_gt *gt,
216 intel_engine_mask_t engine_mask,
217 unsigned int retry)
218{
219 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
220 struct intel_uncore *uncore = gt->uncore;
221 int ret;
222
223
224 rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
225 intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
226
227 pci_write_config_byte(pdev, I915_GDRST,
228 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
229 ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
230 if (ret) {
231 GT_TRACE(gt, "Wait for media reset failed\n");
232 goto out;
233 }
234
235 pci_write_config_byte(pdev, I915_GDRST,
236 GRDOM_RENDER | GRDOM_RESET_ENABLE);
237 ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
238 if (ret) {
239 GT_TRACE(gt, "Wait for render reset failed\n");
240 goto out;
241 }
242
243out:
244 pci_write_config_byte(pdev, I915_GDRST, 0);
245
246 rmw_clear_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
247 intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
248
249 return ret;
250}
251
252static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
253 unsigned int retry)
254{
255 struct intel_uncore *uncore = gt->uncore;
256 int ret;
257
258 intel_uncore_write_fw(uncore, ILK_GDSR,
259 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
260 ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
261 ILK_GRDOM_RESET_ENABLE, 0,
262 5000, 0,
263 NULL);
264 if (ret) {
265 GT_TRACE(gt, "Wait for render reset failed\n");
266 goto out;
267 }
268
269 intel_uncore_write_fw(uncore, ILK_GDSR,
270 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
271 ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
272 ILK_GRDOM_RESET_ENABLE, 0,
273 5000, 0,
274 NULL);
275 if (ret) {
276 GT_TRACE(gt, "Wait for media reset failed\n");
277 goto out;
278 }
279
280out:
281 intel_uncore_write_fw(uncore, ILK_GDSR, 0);
282 intel_uncore_posting_read_fw(uncore, ILK_GDSR);
283 return ret;
284}
285
286
287static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
288{
289 struct intel_uncore *uncore = gt->uncore;
290 int err;
291
292
293
294
295
296
297 intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
298
299
300 err = __intel_wait_for_register_fw(uncore,
301 GEN6_GDRST, hw_domain_mask, 0,
302 500, 0,
303 NULL);
304 if (err)
305 GT_TRACE(gt,
306 "Wait for 0x%08x engines reset failed\n",
307 hw_domain_mask);
308
309 return err;
310}
311
312static int gen6_reset_engines(struct intel_gt *gt,
313 intel_engine_mask_t engine_mask,
314 unsigned int retry)
315{
316 static const u32 hw_engine_mask[] = {
317 [RCS0] = GEN6_GRDOM_RENDER,
318 [BCS0] = GEN6_GRDOM_BLT,
319 [VCS0] = GEN6_GRDOM_MEDIA,
320 [VCS1] = GEN8_GRDOM_MEDIA2,
321 [VECS0] = GEN6_GRDOM_VECS,
322 };
323 struct intel_engine_cs *engine;
324 u32 hw_mask;
325
326 if (engine_mask == ALL_ENGINES) {
327 hw_mask = GEN6_GRDOM_FULL;
328 } else {
329 intel_engine_mask_t tmp;
330
331 hw_mask = 0;
332 for_each_engine_masked(engine, gt, engine_mask, tmp) {
333 GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
334 hw_mask |= hw_engine_mask[engine->id];
335 }
336 }
337
338 return gen6_hw_domain_reset(gt, hw_mask);
339}
340
341static struct intel_engine_cs *find_sfc_paired_vecs_engine(struct intel_engine_cs *engine)
342{
343 int vecs_id;
344
345 GEM_BUG_ON(engine->class != VIDEO_DECODE_CLASS);
346
347 vecs_id = _VECS((engine->instance) / 2);
348
349 return engine->gt->engine[vecs_id];
350}
351
352struct sfc_lock_data {
353 i915_reg_t lock_reg;
354 i915_reg_t ack_reg;
355 i915_reg_t usage_reg;
356 u32 lock_bit;
357 u32 ack_bit;
358 u32 usage_bit;
359 u32 reset_bit;
360};
361
362static void get_sfc_forced_lock_data(struct intel_engine_cs *engine,
363 struct sfc_lock_data *sfc_lock)
364{
365 switch (engine->class) {
366 default:
367 MISSING_CASE(engine->class);
368 fallthrough;
369 case VIDEO_DECODE_CLASS:
370 sfc_lock->lock_reg = GEN11_VCS_SFC_FORCED_LOCK(engine);
371 sfc_lock->lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
372
373 sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine);
374 sfc_lock->ack_bit = GEN11_VCS_SFC_LOCK_ACK_BIT;
375
376 sfc_lock->usage_reg = GEN11_VCS_SFC_LOCK_STATUS(engine);
377 sfc_lock->usage_bit = GEN11_VCS_SFC_USAGE_BIT;
378 sfc_lock->reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
379
380 break;
381 case VIDEO_ENHANCEMENT_CLASS:
382 sfc_lock->lock_reg = GEN11_VECS_SFC_FORCED_LOCK(engine);
383 sfc_lock->lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
384
385 sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine);
386 sfc_lock->ack_bit = GEN11_VECS_SFC_LOCK_ACK_BIT;
387
388 sfc_lock->usage_reg = GEN11_VECS_SFC_USAGE(engine);
389 sfc_lock->usage_bit = GEN11_VECS_SFC_USAGE_BIT;
390 sfc_lock->reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
391
392 break;
393 }
394}
395
396static int gen11_lock_sfc(struct intel_engine_cs *engine,
397 u32 *reset_mask,
398 u32 *unlock_mask)
399{
400 struct intel_uncore *uncore = engine->uncore;
401 u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
402 struct sfc_lock_data sfc_lock;
403 bool lock_obtained, lock_to_other = false;
404 int ret;
405
406 switch (engine->class) {
407 case VIDEO_DECODE_CLASS:
408 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
409 return 0;
410
411 fallthrough;
412 case VIDEO_ENHANCEMENT_CLASS:
413 get_sfc_forced_lock_data(engine, &sfc_lock);
414
415 break;
416 default:
417 return 0;
418 }
419
420 if (!(intel_uncore_read_fw(uncore, sfc_lock.usage_reg) & sfc_lock.usage_bit)) {
421 struct intel_engine_cs *paired_vecs;
422
423 if (engine->class != VIDEO_DECODE_CLASS ||
424 GRAPHICS_VER(engine->i915) != 12)
425 return 0;
426
427
428
429
430
431
432
433
434 if (!(intel_uncore_read_fw(uncore,
435 GEN12_HCP_SFC_LOCK_STATUS(engine)) &
436 GEN12_HCP_SFC_USAGE_BIT))
437 return 0;
438
439 paired_vecs = find_sfc_paired_vecs_engine(engine);
440 get_sfc_forced_lock_data(paired_vecs, &sfc_lock);
441 lock_to_other = true;
442 *unlock_mask |= paired_vecs->mask;
443 } else {
444 *unlock_mask |= engine->mask;
445 }
446
447
448
449
450
451
452
453
454 rmw_set_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit);
455
456 ret = __intel_wait_for_register_fw(uncore,
457 sfc_lock.ack_reg,
458 sfc_lock.ack_bit,
459 sfc_lock.ack_bit,
460 1000, 0, NULL);
461
462
463
464
465
466
467
468
469
470
471
472
473
474 lock_obtained = (intel_uncore_read_fw(uncore, sfc_lock.usage_reg) &
475 sfc_lock.usage_bit) != 0;
476 if (lock_obtained == lock_to_other)
477 return 0;
478
479 if (ret) {
480 ENGINE_TRACE(engine, "Wait for SFC forced lock ack failed\n");
481 return ret;
482 }
483
484 *reset_mask |= sfc_lock.reset_bit;
485 return 0;
486}
487
488static void gen11_unlock_sfc(struct intel_engine_cs *engine)
489{
490 struct intel_uncore *uncore = engine->uncore;
491 u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
492 struct sfc_lock_data sfc_lock = {};
493
494 if (engine->class != VIDEO_DECODE_CLASS &&
495 engine->class != VIDEO_ENHANCEMENT_CLASS)
496 return;
497
498 if (engine->class == VIDEO_DECODE_CLASS &&
499 (BIT(engine->instance) & vdbox_sfc_access) == 0)
500 return;
501
502 get_sfc_forced_lock_data(engine, &sfc_lock);
503
504 rmw_clear_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit);
505}
506
507static int gen11_reset_engines(struct intel_gt *gt,
508 intel_engine_mask_t engine_mask,
509 unsigned int retry)
510{
511 static const u32 hw_engine_mask[] = {
512 [RCS0] = GEN11_GRDOM_RENDER,
513 [BCS0] = GEN11_GRDOM_BLT,
514 [VCS0] = GEN11_GRDOM_MEDIA,
515 [VCS1] = GEN11_GRDOM_MEDIA2,
516 [VCS2] = GEN11_GRDOM_MEDIA3,
517 [VCS3] = GEN11_GRDOM_MEDIA4,
518 [VECS0] = GEN11_GRDOM_VECS,
519 [VECS1] = GEN11_GRDOM_VECS2,
520 };
521 struct intel_engine_cs *engine;
522 intel_engine_mask_t tmp;
523 u32 reset_mask, unlock_mask = 0;
524 int ret;
525
526 if (engine_mask == ALL_ENGINES) {
527 reset_mask = GEN11_GRDOM_FULL;
528 } else {
529 reset_mask = 0;
530 for_each_engine_masked(engine, gt, engine_mask, tmp) {
531 GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
532 reset_mask |= hw_engine_mask[engine->id];
533 ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask);
534 if (ret)
535 goto sfc_unlock;
536 }
537 }
538
539 ret = gen6_hw_domain_reset(gt, reset_mask);
540
541sfc_unlock:
542
543
544
545
546
547
548
549
550
551
552
553 for_each_engine_masked(engine, gt, unlock_mask, tmp)
554 gen11_unlock_sfc(engine);
555
556 return ret;
557}
558
559static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
560{
561 struct intel_uncore *uncore = engine->uncore;
562 const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
563 u32 request, mask, ack;
564 int ret;
565
566 if (I915_SELFTEST_ONLY(should_fail(&engine->reset_timeout, 1)))
567 return -ETIMEDOUT;
568
569 ack = intel_uncore_read_fw(uncore, reg);
570 if (ack & RESET_CTL_CAT_ERROR) {
571
572
573
574
575 request = RESET_CTL_CAT_ERROR;
576 mask = RESET_CTL_CAT_ERROR;
577
578
579 ack = 0;
580 } else if (!(ack & RESET_CTL_READY_TO_RESET)) {
581 request = RESET_CTL_REQUEST_RESET;
582 mask = RESET_CTL_READY_TO_RESET;
583 ack = RESET_CTL_READY_TO_RESET;
584 } else {
585 return 0;
586 }
587
588 intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
589 ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
590 700, 0, NULL);
591 if (ret)
592 drm_err(&engine->i915->drm,
593 "%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
594 engine->name, request,
595 intel_uncore_read_fw(uncore, reg));
596
597 return ret;
598}
599
600static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
601{
602 intel_uncore_write_fw(engine->uncore,
603 RING_RESET_CTL(engine->mmio_base),
604 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
605}
606
607static int gen8_reset_engines(struct intel_gt *gt,
608 intel_engine_mask_t engine_mask,
609 unsigned int retry)
610{
611 struct intel_engine_cs *engine;
612 const bool reset_non_ready = retry >= 1;
613 intel_engine_mask_t tmp;
614 int ret;
615
616 for_each_engine_masked(engine, gt, engine_mask, tmp) {
617 ret = gen8_engine_reset_prepare(engine);
618 if (ret && !reset_non_ready)
619 goto skip_reset;
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634 }
635
636 if (GRAPHICS_VER(gt->i915) >= 11)
637 ret = gen11_reset_engines(gt, engine_mask, retry);
638 else
639 ret = gen6_reset_engines(gt, engine_mask, retry);
640
641skip_reset:
642 for_each_engine_masked(engine, gt, engine_mask, tmp)
643 gen8_engine_reset_cancel(engine);
644
645 return ret;
646}
647
648static int mock_reset(struct intel_gt *gt,
649 intel_engine_mask_t mask,
650 unsigned int retry)
651{
652 return 0;
653}
654
655typedef int (*reset_func)(struct intel_gt *,
656 intel_engine_mask_t engine_mask,
657 unsigned int retry);
658
659static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
660{
661 struct drm_i915_private *i915 = gt->i915;
662
663 if (is_mock_gt(gt))
664 return mock_reset;
665 else if (GRAPHICS_VER(i915) >= 8)
666 return gen8_reset_engines;
667 else if (GRAPHICS_VER(i915) >= 6)
668 return gen6_reset_engines;
669 else if (GRAPHICS_VER(i915) >= 5)
670 return ilk_do_reset;
671 else if (IS_G4X(i915))
672 return g4x_do_reset;
673 else if (IS_G33(i915) || IS_PINEVIEW(i915))
674 return g33_do_reset;
675 else if (GRAPHICS_VER(i915) >= 3)
676 return i915_do_reset;
677 else
678 return NULL;
679}
680
681int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
682{
683 const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
684 reset_func reset;
685 int ret = -ETIMEDOUT;
686 int retry;
687
688 reset = intel_get_gpu_reset(gt);
689 if (!reset)
690 return -ENODEV;
691
692
693
694
695
696 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
697 for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
698 GT_TRACE(gt, "engine_mask=%x\n", engine_mask);
699 preempt_disable();
700 ret = reset(gt, engine_mask, retry);
701 preempt_enable();
702 }
703 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
704
705 return ret;
706}
707
708bool intel_has_gpu_reset(const struct intel_gt *gt)
709{
710 if (!gt->i915->params.reset)
711 return NULL;
712
713 return intel_get_gpu_reset(gt);
714}
715
716bool intel_has_reset_engine(const struct intel_gt *gt)
717{
718 if (gt->i915->params.reset < 2)
719 return false;
720
721 return INTEL_INFO(gt->i915)->has_reset_engine;
722}
723
724int intel_reset_guc(struct intel_gt *gt)
725{
726 u32 guc_domain =
727 GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
728 int ret;
729
730 GEM_BUG_ON(!HAS_GT_UC(gt->i915));
731
732 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
733 ret = gen6_hw_domain_reset(gt, guc_domain);
734 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
735
736 return ret;
737}
738
739
740
741
742
743static void reset_prepare_engine(struct intel_engine_cs *engine)
744{
745
746
747
748
749
750
751
752 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
753 if (engine->reset.prepare)
754 engine->reset.prepare(engine);
755}
756
757static void revoke_mmaps(struct intel_gt *gt)
758{
759 int i;
760
761 for (i = 0; i < gt->ggtt->num_fences; i++) {
762 struct drm_vma_offset_node *node;
763 struct i915_vma *vma;
764 u64 vma_offset;
765
766 vma = READ_ONCE(gt->ggtt->fence_regs[i].vma);
767 if (!vma)
768 continue;
769
770 if (!i915_vma_has_userfault(vma))
771 continue;
772
773 GEM_BUG_ON(vma->fence != >->ggtt->fence_regs[i]);
774
775 if (!vma->mmo)
776 continue;
777
778 node = &vma->mmo->vma_node;
779 vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;
780
781 unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
782 drm_vma_node_offset_addr(node) + vma_offset,
783 vma->size,
784 1);
785 }
786}
787
788static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
789{
790 struct intel_engine_cs *engine;
791 intel_engine_mask_t awake = 0;
792 enum intel_engine_id id;
793
794 for_each_engine(engine, gt, id) {
795 if (intel_engine_pm_get_if_awake(engine))
796 awake |= engine->mask;
797 reset_prepare_engine(engine);
798 }
799
800 intel_uc_reset_prepare(>->uc);
801
802 return awake;
803}
804
805static void gt_revoke(struct intel_gt *gt)
806{
807 revoke_mmaps(gt);
808}
809
810static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
811{
812 struct intel_engine_cs *engine;
813 enum intel_engine_id id;
814 int err;
815
816
817
818
819
820 err = i915_ggtt_enable_hw(gt->i915);
821 if (err)
822 return err;
823
824 local_bh_disable();
825 for_each_engine(engine, gt, id)
826 __intel_engine_reset(engine, stalled_mask & engine->mask);
827 local_bh_enable();
828
829 intel_ggtt_restore_fences(gt->ggtt);
830
831 return err;
832}
833
834static void reset_finish_engine(struct intel_engine_cs *engine)
835{
836 if (engine->reset.finish)
837 engine->reset.finish(engine);
838 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
839
840 intel_engine_signal_breadcrumbs(engine);
841}
842
843static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
844{
845 struct intel_engine_cs *engine;
846 enum intel_engine_id id;
847
848 for_each_engine(engine, gt, id) {
849 reset_finish_engine(engine);
850 if (awake & engine->mask)
851 intel_engine_pm_put(engine);
852 }
853}
854
855static void nop_submit_request(struct i915_request *request)
856{
857 RQ_TRACE(request, "-EIO\n");
858
859 request = i915_request_mark_eio(request);
860 if (request) {
861 i915_request_submit(request);
862 intel_engine_signal_breadcrumbs(request->engine);
863
864 i915_request_put(request);
865 }
866}
867
868static void __intel_gt_set_wedged(struct intel_gt *gt)
869{
870 struct intel_engine_cs *engine;
871 intel_engine_mask_t awake;
872 enum intel_engine_id id;
873
874 if (test_bit(I915_WEDGED, >->reset.flags))
875 return;
876
877 GT_TRACE(gt, "start\n");
878
879
880
881
882
883
884 awake = reset_prepare(gt);
885
886
887 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
888 __intel_gt_reset(gt, ALL_ENGINES);
889
890 for_each_engine(engine, gt, id)
891 engine->submit_request = nop_submit_request;
892
893
894
895
896
897
898 synchronize_rcu_expedited();
899 set_bit(I915_WEDGED, >->reset.flags);
900
901
902 local_bh_disable();
903 for_each_engine(engine, gt, id)
904 if (engine->reset.cancel)
905 engine->reset.cancel(engine);
906 local_bh_enable();
907
908 reset_finish(gt, awake);
909
910 GT_TRACE(gt, "end\n");
911}
912
913void intel_gt_set_wedged(struct intel_gt *gt)
914{
915 intel_wakeref_t wakeref;
916
917 if (test_bit(I915_WEDGED, >->reset.flags))
918 return;
919
920 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
921 mutex_lock(>->reset.mutex);
922
923 if (GEM_SHOW_DEBUG()) {
924 struct drm_printer p = drm_debug_printer(__func__);
925 struct intel_engine_cs *engine;
926 enum intel_engine_id id;
927
928 drm_printf(&p, "called from %pS\n", (void *)_RET_IP_);
929 for_each_engine(engine, gt, id) {
930 if (intel_engine_is_idle(engine))
931 continue;
932
933 intel_engine_dump(engine, &p, "%s\n", engine->name);
934 }
935 }
936
937 __intel_gt_set_wedged(gt);
938
939 mutex_unlock(>->reset.mutex);
940 intel_runtime_pm_put(gt->uncore->rpm, wakeref);
941}
942
943static bool __intel_gt_unset_wedged(struct intel_gt *gt)
944{
945 struct intel_gt_timelines *timelines = >->timelines;
946 struct intel_timeline *tl;
947 bool ok;
948
949 if (!test_bit(I915_WEDGED, >->reset.flags))
950 return true;
951
952
953 if (intel_gt_has_unrecoverable_error(gt))
954 return false;
955
956 GT_TRACE(gt, "start\n");
957
958
959
960
961
962
963
964
965
966
967
968 spin_lock(&timelines->lock);
969 list_for_each_entry(tl, &timelines->active_list, link) {
970 struct dma_fence *fence;
971
972 fence = i915_active_fence_get(&tl->last_request);
973 if (!fence)
974 continue;
975
976 spin_unlock(&timelines->lock);
977
978
979
980
981
982
983
984
985 dma_fence_default_wait(fence, false, MAX_SCHEDULE_TIMEOUT);
986 dma_fence_put(fence);
987
988
989 spin_lock(&timelines->lock);
990 tl = list_entry(&timelines->active_list, typeof(*tl), link);
991 }
992 spin_unlock(&timelines->lock);
993
994
995 ok = !HAS_EXECLISTS(gt->i915);
996 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
997 ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
998 if (!ok) {
999
1000
1001
1002
1003 add_taint_for_CI(gt->i915, TAINT_WARN);
1004 return false;
1005 }
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016 intel_engines_reset_default_submission(gt);
1017
1018 GT_TRACE(gt, "end\n");
1019
1020 smp_mb__before_atomic();
1021 clear_bit(I915_WEDGED, >->reset.flags);
1022
1023 return true;
1024}
1025
1026bool intel_gt_unset_wedged(struct intel_gt *gt)
1027{
1028 bool result;
1029
1030 mutex_lock(>->reset.mutex);
1031 result = __intel_gt_unset_wedged(gt);
1032 mutex_unlock(>->reset.mutex);
1033
1034 return result;
1035}
1036
1037static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
1038{
1039 int err, i;
1040
1041 err = __intel_gt_reset(gt, ALL_ENGINES);
1042 for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
1043 msleep(10 * (i + 1));
1044 err = __intel_gt_reset(gt, ALL_ENGINES);
1045 }
1046 if (err)
1047 return err;
1048
1049 return gt_reset(gt, stalled_mask);
1050}
1051
1052static int resume(struct intel_gt *gt)
1053{
1054 struct intel_engine_cs *engine;
1055 enum intel_engine_id id;
1056 int ret;
1057
1058 for_each_engine(engine, gt, id) {
1059 ret = intel_engine_resume(engine);
1060 if (ret)
1061 return ret;
1062 }
1063
1064 return 0;
1065}
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084void intel_gt_reset(struct intel_gt *gt,
1085 intel_engine_mask_t stalled_mask,
1086 const char *reason)
1087{
1088 intel_engine_mask_t awake;
1089 int ret;
1090
1091 GT_TRACE(gt, "flags=%lx\n", gt->reset.flags);
1092
1093 might_sleep();
1094 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, >->reset.flags));
1095
1096
1097
1098
1099
1100 gt_revoke(gt);
1101
1102 mutex_lock(>->reset.mutex);
1103
1104
1105 if (!__intel_gt_unset_wedged(gt))
1106 goto unlock;
1107
1108 if (reason)
1109 drm_notice(>->i915->drm,
1110 "Resetting chip for %s\n", reason);
1111 atomic_inc(>->i915->gpu_error.reset_count);
1112
1113 awake = reset_prepare(gt);
1114
1115 if (!intel_has_gpu_reset(gt)) {
1116 if (gt->i915->params.reset)
1117 drm_err(>->i915->drm, "GPU reset not supported\n");
1118 else
1119 drm_dbg(>->i915->drm, "GPU reset disabled\n");
1120 goto error;
1121 }
1122
1123 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1124 intel_runtime_pm_disable_interrupts(gt->i915);
1125
1126 if (do_reset(gt, stalled_mask)) {
1127 drm_err(>->i915->drm, "Failed to reset chip\n");
1128 goto taint;
1129 }
1130
1131 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1132 intel_runtime_pm_enable_interrupts(gt->i915);
1133
1134 intel_overlay_reset(gt->i915);
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144 ret = intel_gt_init_hw(gt);
1145 if (ret) {
1146 drm_err(>->i915->drm,
1147 "Failed to initialise HW following reset (%d)\n",
1148 ret);
1149 goto taint;
1150 }
1151
1152 ret = resume(gt);
1153 if (ret)
1154 goto taint;
1155
1156finish:
1157 reset_finish(gt, awake);
1158unlock:
1159 mutex_unlock(>->reset.mutex);
1160 return;
1161
1162taint:
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175 add_taint_for_CI(gt->i915, TAINT_WARN);
1176error:
1177 __intel_gt_set_wedged(gt);
1178 goto finish;
1179}
1180
1181static int intel_gt_reset_engine(struct intel_engine_cs *engine)
1182{
1183 return __intel_gt_reset(engine->gt, engine->mask);
1184}
1185
1186int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)
1187{
1188 struct intel_gt *gt = engine->gt;
1189 int ret;
1190
1191 ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags);
1192 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, >->reset.flags));
1193
1194 if (!intel_engine_pm_get_if_awake(engine))
1195 return 0;
1196
1197 reset_prepare_engine(engine);
1198
1199 if (msg)
1200 drm_notice(&engine->i915->drm,
1201 "Resetting %s for %s\n", engine->name, msg);
1202 atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
1203
1204 if (intel_engine_uses_guc(engine))
1205 ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
1206 else
1207 ret = intel_gt_reset_engine(engine);
1208 if (ret) {
1209
1210 ENGINE_TRACE(engine, "Failed to reset, err: %d\n", ret);
1211 goto out;
1212 }
1213
1214
1215
1216
1217
1218
1219 __intel_engine_reset(engine, true);
1220
1221
1222
1223
1224
1225
1226 ret = intel_engine_resume(engine);
1227
1228out:
1229 intel_engine_cancel_stop_cs(engine);
1230 reset_finish_engine(engine);
1231 intel_engine_pm_put_async(engine);
1232 return ret;
1233}
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
1249{
1250 int err;
1251
1252 local_bh_disable();
1253 err = __intel_engine_reset_bh(engine, msg);
1254 local_bh_enable();
1255
1256 return err;
1257}
1258
1259static void intel_gt_reset_global(struct intel_gt *gt,
1260 u32 engine_mask,
1261 const char *reason)
1262{
1263 struct kobject *kobj = >->i915->drm.primary->kdev->kobj;
1264 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1265 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1266 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1267 struct intel_wedge_me w;
1268
1269 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
1270
1271 GT_TRACE(gt, "resetting chip, engines=%x\n", engine_mask);
1272 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
1273
1274
1275 intel_wedge_on_timeout(&w, gt, 5 * HZ) {
1276 intel_display_prepare_reset(gt->i915);
1277
1278
1279 synchronize_srcu_expedited(>->reset.backoff_srcu);
1280
1281 intel_gt_reset(gt, engine_mask, reason);
1282
1283 intel_display_finish_reset(gt->i915);
1284 }
1285
1286 if (!test_bit(I915_WEDGED, >->reset.flags))
1287 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
1288}
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303void intel_gt_handle_error(struct intel_gt *gt,
1304 intel_engine_mask_t engine_mask,
1305 unsigned long flags,
1306 const char *fmt, ...)
1307{
1308 struct intel_engine_cs *engine;
1309 intel_wakeref_t wakeref;
1310 intel_engine_mask_t tmp;
1311 char error_msg[80];
1312 char *msg = NULL;
1313
1314 if (fmt) {
1315 va_list args;
1316
1317 va_start(args, fmt);
1318 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
1319 va_end(args);
1320
1321 msg = error_msg;
1322 }
1323
1324
1325
1326
1327
1328
1329
1330
1331 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
1332
1333 engine_mask &= gt->info.engine_mask;
1334
1335 if (flags & I915_ERROR_CAPTURE) {
1336 i915_capture_error_state(gt, engine_mask);
1337 intel_gt_clear_error_registers(gt, engine_mask);
1338 }
1339
1340
1341
1342
1343
1344 if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
1345 local_bh_disable();
1346 for_each_engine_masked(engine, gt, engine_mask, tmp) {
1347 BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
1348 if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1349 >->reset.flags))
1350 continue;
1351
1352 if (__intel_engine_reset_bh(engine, msg) == 0)
1353 engine_mask &= ~engine->mask;
1354
1355 clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
1356 >->reset.flags);
1357 }
1358 local_bh_enable();
1359 }
1360
1361 if (!engine_mask)
1362 goto out;
1363
1364
1365 if (test_and_set_bit(I915_RESET_BACKOFF, >->reset.flags)) {
1366 wait_event(gt->reset.queue,
1367 !test_bit(I915_RESET_BACKOFF, >->reset.flags));
1368 goto out;
1369 }
1370
1371
1372 synchronize_rcu_expedited();
1373
1374
1375 for_each_engine(engine, gt, tmp) {
1376 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1377 >->reset.flags))
1378 wait_on_bit(>->reset.flags,
1379 I915_RESET_ENGINE + engine->id,
1380 TASK_UNINTERRUPTIBLE);
1381 }
1382
1383 intel_gt_reset_global(gt, engine_mask, msg);
1384
1385 for_each_engine(engine, gt, tmp)
1386 clear_bit_unlock(I915_RESET_ENGINE + engine->id,
1387 >->reset.flags);
1388 clear_bit_unlock(I915_RESET_BACKOFF, >->reset.flags);
1389 smp_mb__after_atomic();
1390 wake_up_all(>->reset.queue);
1391
1392out:
1393 intel_runtime_pm_put(gt->uncore->rpm, wakeref);
1394}
1395
1396int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
1397{
1398 might_lock(>->reset.backoff_srcu);
1399 might_sleep();
1400
1401 rcu_read_lock();
1402 while (test_bit(I915_RESET_BACKOFF, >->reset.flags)) {
1403 rcu_read_unlock();
1404
1405 if (wait_event_interruptible(gt->reset.queue,
1406 !test_bit(I915_RESET_BACKOFF,
1407 >->reset.flags)))
1408 return -EINTR;
1409
1410 rcu_read_lock();
1411 }
1412 *srcu = srcu_read_lock(>->reset.backoff_srcu);
1413 rcu_read_unlock();
1414
1415 return 0;
1416}
1417
1418void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
1419__releases(>->reset.backoff_srcu)
1420{
1421 srcu_read_unlock(>->reset.backoff_srcu, tag);
1422}
1423
1424int intel_gt_terminally_wedged(struct intel_gt *gt)
1425{
1426 might_sleep();
1427
1428 if (!intel_gt_is_wedged(gt))
1429 return 0;
1430
1431 if (intel_gt_has_unrecoverable_error(gt))
1432 return -EIO;
1433
1434
1435 if (wait_event_interruptible(gt->reset.queue,
1436 !test_bit(I915_RESET_BACKOFF,
1437 >->reset.flags)))
1438 return -EINTR;
1439
1440 return intel_gt_is_wedged(gt) ? -EIO : 0;
1441}
1442
1443void intel_gt_set_wedged_on_init(struct intel_gt *gt)
1444{
1445 BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES >
1446 I915_WEDGED_ON_INIT);
1447 intel_gt_set_wedged(gt);
1448 set_bit(I915_WEDGED_ON_INIT, >->reset.flags);
1449
1450
1451 add_taint_for_CI(gt->i915, TAINT_WARN);
1452}
1453
1454void intel_gt_set_wedged_on_fini(struct intel_gt *gt)
1455{
1456 intel_gt_set_wedged(gt);
1457 set_bit(I915_WEDGED_ON_FINI, >->reset.flags);
1458 intel_gt_retire_requests(gt);
1459}
1460
1461void intel_gt_init_reset(struct intel_gt *gt)
1462{
1463 init_waitqueue_head(>->reset.queue);
1464 mutex_init(>->reset.mutex);
1465 init_srcu_struct(>->reset.backoff_srcu);
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476 i915_gem_shrinker_taints_mutex(gt->i915, >->reset.mutex);
1477
1478
1479 __set_bit(I915_WEDGED, >->reset.flags);
1480}
1481
1482void intel_gt_fini_reset(struct intel_gt *gt)
1483{
1484 cleanup_srcu_struct(>->reset.backoff_srcu);
1485}
1486
1487static void intel_wedge_me(struct work_struct *work)
1488{
1489 struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
1490
1491 drm_err(&w->gt->i915->drm,
1492 "%s timed out, cancelling all in-flight rendering.\n",
1493 w->name);
1494 intel_gt_set_wedged(w->gt);
1495}
1496
1497void __intel_init_wedge(struct intel_wedge_me *w,
1498 struct intel_gt *gt,
1499 long timeout,
1500 const char *name)
1501{
1502 w->gt = gt;
1503 w->name = name;
1504
1505 INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me);
1506 schedule_delayed_work(&w->work, timeout);
1507}
1508
1509void __intel_fini_wedge(struct intel_wedge_me *w)
1510{
1511 cancel_delayed_work_sync(&w->work);
1512 destroy_delayed_work_on_stack(&w->work);
1513 w->gt = NULL;
1514}
1515
1516#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1517#include "selftest_reset.c"
1518#include "selftest_hangcheck.c"
1519#endif
1520