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9#include "adreno_gpu.h"
10
11#define ANY_ID 0xff
12
13bool hang_debug = false;
14MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
15module_param_named(hang_debug, hang_debug, bool, 0600);
16
17bool snapshot_debugbus = false;
18MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
19module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
20
21bool allow_vram_carveout = false;
22MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
23module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
24
25static const struct adreno_info gpulist[] = {
26 {
27 .rev = ADRENO_REV(2, 0, 0, 0),
28 .revn = 200,
29 .name = "A200",
30 .fw = {
31 [ADRENO_FW_PM4] = "yamato_pm4.fw",
32 [ADRENO_FW_PFP] = "yamato_pfp.fw",
33 },
34 .gmem = SZ_256K,
35 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
36 .init = a2xx_gpu_init,
37 }, {
38 .rev = ADRENO_REV(2, 0, 0, 1),
39 .revn = 201,
40 .name = "A200",
41 .fw = {
42 [ADRENO_FW_PM4] = "yamato_pm4.fw",
43 [ADRENO_FW_PFP] = "yamato_pfp.fw",
44 },
45 .gmem = SZ_128K,
46 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
47 .init = a2xx_gpu_init,
48 }, {
49 .rev = ADRENO_REV(2, 2, 0, ANY_ID),
50 .revn = 220,
51 .name = "A220",
52 .fw = {
53 [ADRENO_FW_PM4] = "leia_pm4_470.fw",
54 [ADRENO_FW_PFP] = "leia_pfp_470.fw",
55 },
56 .gmem = SZ_512K,
57 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
58 .init = a2xx_gpu_init,
59 }, {
60 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
61 .revn = 305,
62 .name = "A305",
63 .fw = {
64 [ADRENO_FW_PM4] = "a300_pm4.fw",
65 [ADRENO_FW_PFP] = "a300_pfp.fw",
66 },
67 .gmem = SZ_256K,
68 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
69 .init = a3xx_gpu_init,
70 }, {
71 .rev = ADRENO_REV(3, 0, 6, 0),
72 .revn = 307,
73 .name = "A306",
74 .fw = {
75 [ADRENO_FW_PM4] = "a300_pm4.fw",
76 [ADRENO_FW_PFP] = "a300_pfp.fw",
77 },
78 .gmem = SZ_128K,
79 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
80 .init = a3xx_gpu_init,
81 }, {
82 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
83 .revn = 320,
84 .name = "A320",
85 .fw = {
86 [ADRENO_FW_PM4] = "a300_pm4.fw",
87 [ADRENO_FW_PFP] = "a300_pfp.fw",
88 },
89 .gmem = SZ_512K,
90 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
91 .init = a3xx_gpu_init,
92 }, {
93 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
94 .revn = 330,
95 .name = "A330",
96 .fw = {
97 [ADRENO_FW_PM4] = "a330_pm4.fw",
98 [ADRENO_FW_PFP] = "a330_pfp.fw",
99 },
100 .gmem = SZ_1M,
101 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
102 .init = a3xx_gpu_init,
103 }, {
104 .rev = ADRENO_REV(4, 0, 5, ANY_ID),
105 .revn = 405,
106 .name = "A405",
107 .fw = {
108 [ADRENO_FW_PM4] = "a420_pm4.fw",
109 [ADRENO_FW_PFP] = "a420_pfp.fw",
110 },
111 .gmem = SZ_256K,
112 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
113 .init = a4xx_gpu_init,
114 }, {
115 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
116 .revn = 420,
117 .name = "A420",
118 .fw = {
119 [ADRENO_FW_PM4] = "a420_pm4.fw",
120 [ADRENO_FW_PFP] = "a420_pfp.fw",
121 },
122 .gmem = (SZ_1M + SZ_512K),
123 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
124 .init = a4xx_gpu_init,
125 }, {
126 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
127 .revn = 430,
128 .name = "A430",
129 .fw = {
130 [ADRENO_FW_PM4] = "a420_pm4.fw",
131 [ADRENO_FW_PFP] = "a420_pfp.fw",
132 },
133 .gmem = (SZ_1M + SZ_512K),
134 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
135 .init = a4xx_gpu_init,
136 }, {
137 .rev = ADRENO_REV(5, 0, 8, ANY_ID),
138 .revn = 508,
139 .name = "A508",
140 .fw = {
141 [ADRENO_FW_PM4] = "a530_pm4.fw",
142 [ADRENO_FW_PFP] = "a530_pfp.fw",
143 },
144 .gmem = (SZ_128K + SZ_8K),
145
146
147
148
149 .inactive_period = 250,
150 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
151 .init = a5xx_gpu_init,
152 .zapfw = "a508_zap.mdt",
153 }, {
154 .rev = ADRENO_REV(5, 0, 9, ANY_ID),
155 .revn = 509,
156 .name = "A509",
157 .fw = {
158 [ADRENO_FW_PM4] = "a530_pm4.fw",
159 [ADRENO_FW_PFP] = "a530_pfp.fw",
160 },
161 .gmem = (SZ_256K + SZ_16K),
162
163
164
165
166 .inactive_period = 250,
167 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
168 .init = a5xx_gpu_init,
169
170 .zapfw = "a512_zap.mdt",
171 }, {
172 .rev = ADRENO_REV(5, 1, 0, ANY_ID),
173 .revn = 510,
174 .name = "A510",
175 .fw = {
176 [ADRENO_FW_PM4] = "a530_pm4.fw",
177 [ADRENO_FW_PFP] = "a530_pfp.fw",
178 },
179 .gmem = SZ_256K,
180
181
182
183
184 .inactive_period = 250,
185 .init = a5xx_gpu_init,
186 }, {
187 .rev = ADRENO_REV(5, 1, 2, ANY_ID),
188 .revn = 512,
189 .name = "A512",
190 .fw = {
191 [ADRENO_FW_PM4] = "a530_pm4.fw",
192 [ADRENO_FW_PFP] = "a530_pfp.fw",
193 },
194 .gmem = (SZ_256K + SZ_16K),
195
196
197
198
199 .inactive_period = 250,
200 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
201 .init = a5xx_gpu_init,
202 .zapfw = "a512_zap.mdt",
203 }, {
204 .rev = ADRENO_REV(5, 3, 0, 2),
205 .revn = 530,
206 .name = "A530",
207 .fw = {
208 [ADRENO_FW_PM4] = "a530_pm4.fw",
209 [ADRENO_FW_PFP] = "a530_pfp.fw",
210 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
211 },
212 .gmem = SZ_1M,
213
214
215
216
217 .inactive_period = 250,
218 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
219 ADRENO_QUIRK_FAULT_DETECT_MASK,
220 .init = a5xx_gpu_init,
221 .zapfw = "a530_zap.mdt",
222 }, {
223 .rev = ADRENO_REV(5, 4, 0, ANY_ID),
224 .revn = 540,
225 .name = "A540",
226 .fw = {
227 [ADRENO_FW_PM4] = "a530_pm4.fw",
228 [ADRENO_FW_PFP] = "a530_pfp.fw",
229 [ADRENO_FW_GPMU] = "a540_gpmu.fw2",
230 },
231 .gmem = SZ_1M,
232
233
234
235
236 .inactive_period = 250,
237 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
238 .init = a5xx_gpu_init,
239 .zapfw = "a540_zap.mdt",
240 }, {
241 .rev = ADRENO_REV(6, 1, 8, ANY_ID),
242 .revn = 618,
243 .name = "A618",
244 .fw = {
245 [ADRENO_FW_SQE] = "a630_sqe.fw",
246 [ADRENO_FW_GMU] = "a630_gmu.bin",
247 },
248 .gmem = SZ_512K,
249 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
250 .init = a6xx_gpu_init,
251 }, {
252 .rev = ADRENO_REV(6, 3, 0, ANY_ID),
253 .revn = 630,
254 .name = "A630",
255 .fw = {
256 [ADRENO_FW_SQE] = "a630_sqe.fw",
257 [ADRENO_FW_GMU] = "a630_gmu.bin",
258 },
259 .gmem = SZ_1M,
260 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
261 .init = a6xx_gpu_init,
262 .zapfw = "a630_zap.mdt",
263 .hwcg = a630_hwcg,
264 }, {
265 .rev = ADRENO_REV(6, 4, 0, ANY_ID),
266 .revn = 640,
267 .name = "A640",
268 .fw = {
269 [ADRENO_FW_SQE] = "a630_sqe.fw",
270 [ADRENO_FW_GMU] = "a640_gmu.bin",
271 },
272 .gmem = SZ_1M,
273 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
274 .init = a6xx_gpu_init,
275 .zapfw = "a640_zap.mdt",
276 .hwcg = a640_hwcg,
277 }, {
278 .rev = ADRENO_REV(6, 5, 0, ANY_ID),
279 .revn = 650,
280 .name = "A650",
281 .fw = {
282 [ADRENO_FW_SQE] = "a650_sqe.fw",
283 [ADRENO_FW_GMU] = "a650_gmu.bin",
284 },
285 .gmem = SZ_1M + SZ_128K,
286 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
287 .init = a6xx_gpu_init,
288 .zapfw = "a650_zap.mdt",
289 .hwcg = a650_hwcg,
290 }, {
291 .rev = ADRENO_REV(6, 6, 0, ANY_ID),
292 .revn = 660,
293 .name = "A660",
294 .fw = {
295 [ADRENO_FW_SQE] = "a660_sqe.fw",
296 [ADRENO_FW_GMU] = "a660_gmu.bin",
297 },
298 .gmem = SZ_1M + SZ_512K,
299 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
300 .init = a6xx_gpu_init,
301 .zapfw = "a660_zap.mdt",
302 .hwcg = a660_hwcg,
303 },
304};
305
306MODULE_FIRMWARE("qcom/a300_pm4.fw");
307MODULE_FIRMWARE("qcom/a300_pfp.fw");
308MODULE_FIRMWARE("qcom/a330_pm4.fw");
309MODULE_FIRMWARE("qcom/a330_pfp.fw");
310MODULE_FIRMWARE("qcom/a420_pm4.fw");
311MODULE_FIRMWARE("qcom/a420_pfp.fw");
312MODULE_FIRMWARE("qcom/a530_pm4.fw");
313MODULE_FIRMWARE("qcom/a530_pfp.fw");
314MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
315MODULE_FIRMWARE("qcom/a530_zap.mdt");
316MODULE_FIRMWARE("qcom/a530_zap.b00");
317MODULE_FIRMWARE("qcom/a530_zap.b01");
318MODULE_FIRMWARE("qcom/a530_zap.b02");
319MODULE_FIRMWARE("qcom/a630_sqe.fw");
320MODULE_FIRMWARE("qcom/a630_gmu.bin");
321MODULE_FIRMWARE("qcom/a630_zap.mbn");
322
323static inline bool _rev_match(uint8_t entry, uint8_t id)
324{
325 return (entry == ANY_ID) || (entry == id);
326}
327
328const struct adreno_info *adreno_info(struct adreno_rev rev)
329{
330 int i;
331
332
333 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
334 const struct adreno_info *info = &gpulist[i];
335 if (_rev_match(info->rev.core, rev.core) &&
336 _rev_match(info->rev.major, rev.major) &&
337 _rev_match(info->rev.minor, rev.minor) &&
338 _rev_match(info->rev.patchid, rev.patchid))
339 return info;
340 }
341
342 return NULL;
343}
344
345struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
346{
347 struct msm_drm_private *priv = dev->dev_private;
348 struct platform_device *pdev = priv->gpu_pdev;
349 struct msm_gpu *gpu = NULL;
350 struct adreno_gpu *adreno_gpu;
351 int ret;
352
353 if (pdev)
354 gpu = dev_to_gpu(&pdev->dev);
355
356 if (!gpu) {
357 dev_err_once(dev->dev, "no GPU device was found\n");
358 return NULL;
359 }
360
361 adreno_gpu = to_adreno_gpu(gpu);
362
363
364
365
366
367
368
369 ret = adreno_load_fw(adreno_gpu);
370 if (ret)
371 return NULL;
372
373
374 pm_runtime_set_active(&pdev->dev);
375
376 ret = pm_runtime_get_sync(&pdev->dev);
377 if (ret < 0) {
378 pm_runtime_put_sync(&pdev->dev);
379 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
380 return NULL;
381 }
382
383 mutex_lock(&dev->struct_mutex);
384 ret = msm_gpu_hw_init(gpu);
385 mutex_unlock(&dev->struct_mutex);
386 pm_runtime_put_autosuspend(&pdev->dev);
387 if (ret) {
388 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
389 return NULL;
390 }
391
392#ifdef CONFIG_DEBUG_FS
393 if (gpu->funcs->debugfs_init) {
394 gpu->funcs->debugfs_init(gpu, dev->primary);
395 gpu->funcs->debugfs_init(gpu, dev->render);
396 }
397#endif
398
399 return gpu;
400}
401
402static void set_gpu_pdev(struct drm_device *dev,
403 struct platform_device *pdev)
404{
405 struct msm_drm_private *priv = dev->dev_private;
406 priv->gpu_pdev = pdev;
407}
408
409static int find_chipid(struct device *dev, struct adreno_rev *rev)
410{
411 struct device_node *node = dev->of_node;
412 const char *compat;
413 int ret;
414 u32 chipid;
415
416
417 ret = of_property_read_string_index(node, "compatible", 0, &compat);
418 if (ret == 0) {
419 unsigned int r, patch;
420
421 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
422 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
423 rev->core = r / 100;
424 r %= 100;
425 rev->major = r / 10;
426 r %= 10;
427 rev->minor = r;
428 rev->patchid = patch;
429
430 return 0;
431 }
432 }
433
434
435 ret = of_property_read_u32(node, "qcom,chipid", &chipid);
436 if (ret) {
437 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
438 return ret;
439 }
440
441 rev->core = (chipid >> 24) & 0xff;
442 rev->major = (chipid >> 16) & 0xff;
443 rev->minor = (chipid >> 8) & 0xff;
444 rev->patchid = (chipid & 0xff);
445
446 dev_warn(dev, "Using legacy qcom,chipid binding!\n");
447 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
448 rev->core, rev->major, rev->minor, rev->patchid);
449
450 return 0;
451}
452
453static int adreno_bind(struct device *dev, struct device *master, void *data)
454{
455 static struct adreno_platform_config config = {};
456 const struct adreno_info *info;
457 struct drm_device *drm = dev_get_drvdata(master);
458 struct msm_drm_private *priv = drm->dev_private;
459 struct msm_gpu *gpu;
460 int ret;
461
462 ret = find_chipid(dev, &config.rev);
463 if (ret)
464 return ret;
465
466 dev->platform_data = &config;
467 set_gpu_pdev(drm, to_platform_device(dev));
468
469 info = adreno_info(config.rev);
470
471 if (!info) {
472 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
473 config.rev.core, config.rev.major,
474 config.rev.minor, config.rev.patchid);
475 return -ENXIO;
476 }
477
478 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
479 config.rev.minor, config.rev.patchid);
480
481 priv->is_a2xx = config.rev.core == 2;
482 priv->has_cached_coherent = config.rev.core >= 6;
483
484 gpu = info->init(drm);
485 if (IS_ERR(gpu)) {
486 dev_warn(drm->dev, "failed to load adreno gpu\n");
487 return PTR_ERR(gpu);
488 }
489
490 return 0;
491}
492
493static void adreno_unbind(struct device *dev, struct device *master,
494 void *data)
495{
496 struct msm_gpu *gpu = dev_to_gpu(dev);
497
498 pm_runtime_force_suspend(dev);
499 gpu->funcs->destroy(gpu);
500
501 set_gpu_pdev(dev_get_drvdata(master), NULL);
502}
503
504static const struct component_ops a3xx_ops = {
505 .bind = adreno_bind,
506 .unbind = adreno_unbind,
507};
508
509static void adreno_device_register_headless(void)
510{
511
512
513
514 struct platform_device_info dummy_info = {
515 .parent = NULL,
516 .name = "msm",
517 .id = -1,
518 .res = NULL,
519 .num_res = 0,
520 .data = NULL,
521 .size_data = 0,
522 .dma_mask = ~0,
523 };
524 platform_device_register_full(&dummy_info);
525}
526
527static int adreno_probe(struct platform_device *pdev)
528{
529
530 int ret;
531
532 ret = component_add(&pdev->dev, &a3xx_ops);
533 if (ret)
534 return ret;
535
536 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
537 adreno_device_register_headless();
538
539 return 0;
540}
541
542static int adreno_remove(struct platform_device *pdev)
543{
544 component_del(&pdev->dev, &a3xx_ops);
545 return 0;
546}
547
548static void adreno_shutdown(struct platform_device *pdev)
549{
550 pm_runtime_force_suspend(&pdev->dev);
551}
552
553static const struct of_device_id dt_match[] = {
554 { .compatible = "qcom,adreno" },
555 { .compatible = "qcom,adreno-3xx" },
556
557 { .compatible = "amd,imageon" },
558
559 { .compatible = "qcom,kgsl-3d0" },
560 {}
561};
562
563#ifdef CONFIG_PM
564static int adreno_resume(struct device *dev)
565{
566 struct msm_gpu *gpu = dev_to_gpu(dev);
567
568 return gpu->funcs->pm_resume(gpu);
569}
570
571static int adreno_suspend(struct device *dev)
572{
573 struct msm_gpu *gpu = dev_to_gpu(dev);
574
575 return gpu->funcs->pm_suspend(gpu);
576}
577#endif
578
579static const struct dev_pm_ops adreno_pm_ops = {
580 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
581 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
582};
583
584static struct platform_driver adreno_driver = {
585 .probe = adreno_probe,
586 .remove = adreno_remove,
587 .shutdown = adreno_shutdown,
588 .driver = {
589 .name = "adreno",
590 .of_match_table = dt_match,
591 .pm = &adreno_pm_ops,
592 },
593};
594
595void __init adreno_register(void)
596{
597 platform_driver_register(&adreno_driver);
598}
599
600void __exit adreno_unregister(void)
601{
602 platform_driver_unregister(&adreno_driver);
603}
604
