LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.c

   1/*
   2 * Copyright 2019 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 */
  22#include "ctxgf100.h"
  23
  24static void
  25tu102_grctx_generate_r419c0c(struct gf100_gr *gr)
  26{
  27        struct nvkm_device *device = gr->base.engine.subdev.device;
  28        nvkm_mask(device, 0x419c0c, 0x80000000, 0x80000000);
  29        nvkm_mask(device, 0x40584c, 0x00000008, 0x00000000);
  30        nvkm_mask(device, 0x400080, 0x00000000, 0x00000000);
  31}
  32
  33static void
  34tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
  35{
  36        struct nvkm_device *device = gr->base.engine.subdev.device;
  37        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
  38        nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
  39}
  40
  41static const struct gf100_gr_init
  42tu102_grctx_init_unknown_bundle_init_0[] = {
  43        { 0x00001000,  1, 0x00000001, 0x00000004 },
  44        { 0x00002020, 64, 0x00000001, 0x00000000 },
  45        { 0x0001e100,  1, 0x00000001, 0x00000001 },
  46        {}
  47};
  48
  49static const struct gf100_gr_pack
  50tu102_grctx_pack_sw_veid_bundle_init[] = {
  51        { gv100_grctx_init_sw_veid_bundle_init_0 },
  52        { tu102_grctx_init_unknown_bundle_init_0 },
  53        {}
  54};
  55
  56static void
  57tu102_grctx_generate_attrib(struct gf100_grctx *info)
  58{
  59        const u64 size = 0x80000; /*XXX: educated guess */
  60        const int s = 8;
  61        const int b = mmio_vram(info, size, (1 << s), true);
  62
  63        gv100_grctx_generate_attrib(info);
  64
  65        mmio_refn(info, 0x408070, 0x00000000, s, b);
  66        mmio_wr32(info, 0x408074, size >> s); /*XXX: guess */
  67        mmio_refn(info, 0x419034, 0x00000000, s, b);
  68        mmio_wr32(info, 0x408078, 0x00000000);
  69}
  70
  71const struct gf100_grctx_func
  72tu102_grctx = {
  73        .unkn88c = gv100_grctx_unkn88c,
  74        .main = gf100_grctx_generate_main,
  75        .unkn = gv100_grctx_generate_unkn,
  76        .sw_veid_bundle_init = tu102_grctx_pack_sw_veid_bundle_init,
  77        .bundle = gm107_grctx_generate_bundle,
  78        .bundle_size = 0x3000,
  79        .bundle_min_gpm_fifo_depth = 0x180,
  80        .bundle_token_limit = 0xa80,
  81        .pagepool = gp100_grctx_generate_pagepool,
  82        .pagepool_size = 0x20000,
  83        .attrib = tu102_grctx_generate_attrib,
  84        .attrib_nr_max = 0x800,
  85        .attrib_nr = 0x700,
  86        .alpha_nr_max = 0xc00,
  87        .alpha_nr = 0x800,
  88        .gfxp_nr = 0xfa8,
  89        .sm_id = tu102_grctx_generate_sm_id,
  90        .skip_pd_num_tpc_per_gpc = true,
  91        .rop_mapping = gv100_grctx_generate_rop_mapping,
  92        .r406500 = gm200_grctx_generate_r406500,
  93        .r400088 = gv100_grctx_generate_r400088,
  94        .r419c0c = tu102_grctx_generate_r419c0c,
  95};
  96