linux/drivers/gpu/drm/tegra/drm.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2012 Avionic Design GmbH
   4 * Copyright (C) 2012-2016 NVIDIA CORPORATION.  All rights reserved.
   5 */
   6
   7#include <linux/bitops.h>
   8#include <linux/host1x.h>
   9#include <linux/idr.h>
  10#include <linux/iommu.h>
  11#include <linux/module.h>
  12#include <linux/platform_device.h>
  13
  14#include <drm/drm_aperture.h>
  15#include <drm/drm_atomic.h>
  16#include <drm/drm_atomic_helper.h>
  17#include <drm/drm_debugfs.h>
  18#include <drm/drm_drv.h>
  19#include <drm/drm_fourcc.h>
  20#include <drm/drm_ioctl.h>
  21#include <drm/drm_prime.h>
  22#include <drm/drm_vblank.h>
  23
  24#include "drm.h"
  25#include "gem.h"
  26
  27#define DRIVER_NAME "tegra"
  28#define DRIVER_DESC "NVIDIA Tegra graphics"
  29#define DRIVER_DATE "20120330"
  30#define DRIVER_MAJOR 0
  31#define DRIVER_MINOR 0
  32#define DRIVER_PATCHLEVEL 0
  33
  34#define CARVEOUT_SZ SZ_64M
  35#define CDMA_GATHER_FETCHES_MAX_NB 16383
  36
  37struct tegra_drm_file {
  38        struct idr contexts;
  39        struct mutex lock;
  40};
  41
  42static int tegra_atomic_check(struct drm_device *drm,
  43                              struct drm_atomic_state *state)
  44{
  45        int err;
  46
  47        err = drm_atomic_helper_check(drm, state);
  48        if (err < 0)
  49                return err;
  50
  51        return tegra_display_hub_atomic_check(drm, state);
  52}
  53
  54static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
  55        .fb_create = tegra_fb_create,
  56#ifdef CONFIG_DRM_FBDEV_EMULATION
  57        .output_poll_changed = drm_fb_helper_output_poll_changed,
  58#endif
  59        .atomic_check = tegra_atomic_check,
  60        .atomic_commit = drm_atomic_helper_commit,
  61};
  62
  63static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
  64{
  65        struct drm_device *drm = old_state->dev;
  66        struct tegra_drm *tegra = drm->dev_private;
  67
  68        if (tegra->hub) {
  69                bool fence_cookie = dma_fence_begin_signalling();
  70
  71                drm_atomic_helper_commit_modeset_disables(drm, old_state);
  72                tegra_display_hub_atomic_commit(drm, old_state);
  73                drm_atomic_helper_commit_planes(drm, old_state, 0);
  74                drm_atomic_helper_commit_modeset_enables(drm, old_state);
  75                drm_atomic_helper_commit_hw_done(old_state);
  76                dma_fence_end_signalling(fence_cookie);
  77                drm_atomic_helper_wait_for_vblanks(drm, old_state);
  78                drm_atomic_helper_cleanup_planes(drm, old_state);
  79        } else {
  80                drm_atomic_helper_commit_tail_rpm(old_state);
  81        }
  82}
  83
  84static const struct drm_mode_config_helper_funcs
  85tegra_drm_mode_config_helpers = {
  86        .atomic_commit_tail = tegra_atomic_commit_tail,
  87};
  88
  89static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
  90{
  91        struct tegra_drm_file *fpriv;
  92
  93        fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
  94        if (!fpriv)
  95                return -ENOMEM;
  96
  97        idr_init_base(&fpriv->contexts, 1);
  98        mutex_init(&fpriv->lock);
  99        filp->driver_priv = fpriv;
 100
 101        return 0;
 102}
 103
 104static void tegra_drm_context_free(struct tegra_drm_context *context)
 105{
 106        context->client->ops->close_channel(context);
 107        kfree(context);
 108}
 109
 110static struct host1x_bo *
 111host1x_bo_lookup(struct drm_file *file, u32 handle)
 112{
 113        struct drm_gem_object *gem;
 114        struct tegra_bo *bo;
 115
 116        gem = drm_gem_object_lookup(file, handle);
 117        if (!gem)
 118                return NULL;
 119
 120        bo = to_tegra_bo(gem);
 121        return &bo->base;
 122}
 123
 124static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
 125                                       struct drm_tegra_reloc __user *src,
 126                                       struct drm_device *drm,
 127                                       struct drm_file *file)
 128{
 129        u32 cmdbuf, target;
 130        int err;
 131
 132        err = get_user(cmdbuf, &src->cmdbuf.handle);
 133        if (err < 0)
 134                return err;
 135
 136        err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
 137        if (err < 0)
 138                return err;
 139
 140        err = get_user(target, &src->target.handle);
 141        if (err < 0)
 142                return err;
 143
 144        err = get_user(dest->target.offset, &src->target.offset);
 145        if (err < 0)
 146                return err;
 147
 148        err = get_user(dest->shift, &src->shift);
 149        if (err < 0)
 150                return err;
 151
 152        dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE;
 153
 154        dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
 155        if (!dest->cmdbuf.bo)
 156                return -ENOENT;
 157
 158        dest->target.bo = host1x_bo_lookup(file, target);
 159        if (!dest->target.bo)
 160                return -ENOENT;
 161
 162        return 0;
 163}
 164
 165int tegra_drm_submit(struct tegra_drm_context *context,
 166                     struct drm_tegra_submit *args, struct drm_device *drm,
 167                     struct drm_file *file)
 168{
 169        struct host1x_client *client = &context->client->base;
 170        unsigned int num_cmdbufs = args->num_cmdbufs;
 171        unsigned int num_relocs = args->num_relocs;
 172        struct drm_tegra_cmdbuf __user *user_cmdbufs;
 173        struct drm_tegra_reloc __user *user_relocs;
 174        struct drm_tegra_syncpt __user *user_syncpt;
 175        struct drm_tegra_syncpt syncpt;
 176        struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
 177        struct drm_gem_object **refs;
 178        struct host1x_syncpt *sp = NULL;
 179        struct host1x_job *job;
 180        unsigned int num_refs;
 181        int err;
 182
 183        user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
 184        user_relocs = u64_to_user_ptr(args->relocs);
 185        user_syncpt = u64_to_user_ptr(args->syncpts);
 186
 187        /* We don't yet support other than one syncpt_incr struct per submit */
 188        if (args->num_syncpts != 1)
 189                return -EINVAL;
 190
 191        /* We don't yet support waitchks */
 192        if (args->num_waitchks != 0)
 193                return -EINVAL;
 194
 195        job = host1x_job_alloc(context->channel, args->num_cmdbufs,
 196                               args->num_relocs);
 197        if (!job)
 198                return -ENOMEM;
 199
 200        job->num_relocs = args->num_relocs;
 201        job->client = client;
 202        job->class = client->class;
 203        job->serialize = true;
 204
 205        /*
 206         * Track referenced BOs so that they can be unreferenced after the
 207         * submission is complete.
 208         */
 209        num_refs = num_cmdbufs + num_relocs * 2;
 210
 211        refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
 212        if (!refs) {
 213                err = -ENOMEM;
 214                goto put;
 215        }
 216
 217        /* reuse as an iterator later */
 218        num_refs = 0;
 219
 220        while (num_cmdbufs) {
 221                struct drm_tegra_cmdbuf cmdbuf;
 222                struct host1x_bo *bo;
 223                struct tegra_bo *obj;
 224                u64 offset;
 225
 226                if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
 227                        err = -EFAULT;
 228                        goto fail;
 229                }
 230
 231                /*
 232                 * The maximum number of CDMA gather fetches is 16383, a higher
 233                 * value means the words count is malformed.
 234                 */
 235                if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
 236                        err = -EINVAL;
 237                        goto fail;
 238                }
 239
 240                bo = host1x_bo_lookup(file, cmdbuf.handle);
 241                if (!bo) {
 242                        err = -ENOENT;
 243                        goto fail;
 244                }
 245
 246                offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
 247                obj = host1x_to_tegra_bo(bo);
 248                refs[num_refs++] = &obj->gem;
 249
 250                /*
 251                 * Gather buffer base address must be 4-bytes aligned,
 252                 * unaligned offset is malformed and cause commands stream
 253                 * corruption on the buffer address relocation.
 254                 */
 255                if (offset & 3 || offset > obj->gem.size) {
 256                        err = -EINVAL;
 257                        goto fail;
 258                }
 259
 260                host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
 261                num_cmdbufs--;
 262                user_cmdbufs++;
 263        }
 264
 265        /* copy and resolve relocations from submit */
 266        while (num_relocs--) {
 267                struct host1x_reloc *reloc;
 268                struct tegra_bo *obj;
 269
 270                err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
 271                                                  &user_relocs[num_relocs], drm,
 272                                                  file);
 273                if (err < 0)
 274                        goto fail;
 275
 276                reloc = &job->relocs[num_relocs];
 277                obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
 278                refs[num_refs++] = &obj->gem;
 279
 280                /*
 281                 * The unaligned cmdbuf offset will cause an unaligned write
 282                 * during of the relocations patching, corrupting the commands
 283                 * stream.
 284                 */
 285                if (reloc->cmdbuf.offset & 3 ||
 286                    reloc->cmdbuf.offset >= obj->gem.size) {
 287                        err = -EINVAL;
 288                        goto fail;
 289                }
 290
 291                obj = host1x_to_tegra_bo(reloc->target.bo);
 292                refs[num_refs++] = &obj->gem;
 293
 294                if (reloc->target.offset >= obj->gem.size) {
 295                        err = -EINVAL;
 296                        goto fail;
 297                }
 298        }
 299
 300        if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
 301                err = -EFAULT;
 302                goto fail;
 303        }
 304
 305        /* Syncpoint ref will be dropped on job release. */
 306        sp = host1x_syncpt_get_by_id(host1x, syncpt.id);
 307        if (!sp) {
 308                err = -ENOENT;
 309                goto fail;
 310        }
 311
 312        job->is_addr_reg = context->client->ops->is_addr_reg;
 313        job->is_valid_class = context->client->ops->is_valid_class;
 314        job->syncpt_incrs = syncpt.incrs;
 315        job->syncpt = sp;
 316        job->timeout = 10000;
 317
 318        if (args->timeout && args->timeout < 10000)
 319                job->timeout = args->timeout;
 320
 321        err = host1x_job_pin(job, context->client->base.dev);
 322        if (err)
 323                goto fail;
 324
 325        err = host1x_job_submit(job);
 326        if (err) {
 327                host1x_job_unpin(job);
 328                goto fail;
 329        }
 330
 331        args->fence = job->syncpt_end;
 332
 333fail:
 334        while (num_refs--)
 335                drm_gem_object_put(refs[num_refs]);
 336
 337        kfree(refs);
 338
 339put:
 340        host1x_job_put(job);
 341        return err;
 342}
 343
 344
 345#ifdef CONFIG_DRM_TEGRA_STAGING
 346static int tegra_gem_create(struct drm_device *drm, void *data,
 347                            struct drm_file *file)
 348{
 349        struct drm_tegra_gem_create *args = data;
 350        struct tegra_bo *bo;
 351
 352        bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
 353                                         &args->handle);
 354        if (IS_ERR(bo))
 355                return PTR_ERR(bo);
 356
 357        return 0;
 358}
 359
 360static int tegra_gem_mmap(struct drm_device *drm, void *data,
 361                          struct drm_file *file)
 362{
 363        struct drm_tegra_gem_mmap *args = data;
 364        struct drm_gem_object *gem;
 365        struct tegra_bo *bo;
 366
 367        gem = drm_gem_object_lookup(file, args->handle);
 368        if (!gem)
 369                return -EINVAL;
 370
 371        bo = to_tegra_bo(gem);
 372
 373        args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
 374
 375        drm_gem_object_put(gem);
 376
 377        return 0;
 378}
 379
 380static int tegra_syncpt_read(struct drm_device *drm, void *data,
 381                             struct drm_file *file)
 382{
 383        struct host1x *host = dev_get_drvdata(drm->dev->parent);
 384        struct drm_tegra_syncpt_read *args = data;
 385        struct host1x_syncpt *sp;
 386
 387        sp = host1x_syncpt_get_by_id_noref(host, args->id);
 388        if (!sp)
 389                return -EINVAL;
 390
 391        args->value = host1x_syncpt_read_min(sp);
 392        return 0;
 393}
 394
 395static int tegra_syncpt_incr(struct drm_device *drm, void *data,
 396                             struct drm_file *file)
 397{
 398        struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
 399        struct drm_tegra_syncpt_incr *args = data;
 400        struct host1x_syncpt *sp;
 401
 402        sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
 403        if (!sp)
 404                return -EINVAL;
 405
 406        return host1x_syncpt_incr(sp);
 407}
 408
 409static int tegra_syncpt_wait(struct drm_device *drm, void *data,
 410                             struct drm_file *file)
 411{
 412        struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
 413        struct drm_tegra_syncpt_wait *args = data;
 414        struct host1x_syncpt *sp;
 415
 416        sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
 417        if (!sp)
 418                return -EINVAL;
 419
 420        return host1x_syncpt_wait(sp, args->thresh,
 421                                  msecs_to_jiffies(args->timeout),
 422                                  &args->value);
 423}
 424
 425static int tegra_client_open(struct tegra_drm_file *fpriv,
 426                             struct tegra_drm_client *client,
 427                             struct tegra_drm_context *context)
 428{
 429        int err;
 430
 431        err = client->ops->open_channel(client, context);
 432        if (err < 0)
 433                return err;
 434
 435        err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
 436        if (err < 0) {
 437                client->ops->close_channel(context);
 438                return err;
 439        }
 440
 441        context->client = client;
 442        context->id = err;
 443
 444        return 0;
 445}
 446
 447static int tegra_open_channel(struct drm_device *drm, void *data,
 448                              struct drm_file *file)
 449{
 450        struct tegra_drm_file *fpriv = file->driver_priv;
 451        struct tegra_drm *tegra = drm->dev_private;
 452        struct drm_tegra_open_channel *args = data;
 453        struct tegra_drm_context *context;
 454        struct tegra_drm_client *client;
 455        int err = -ENODEV;
 456
 457        context = kzalloc(sizeof(*context), GFP_KERNEL);
 458        if (!context)
 459                return -ENOMEM;
 460
 461        mutex_lock(&fpriv->lock);
 462
 463        list_for_each_entry(client, &tegra->clients, list)
 464                if (client->base.class == args->client) {
 465                        err = tegra_client_open(fpriv, client, context);
 466                        if (err < 0)
 467                                break;
 468
 469                        args->context = context->id;
 470                        break;
 471                }
 472
 473        if (err < 0)
 474                kfree(context);
 475
 476        mutex_unlock(&fpriv->lock);
 477        return err;
 478}
 479
 480static int tegra_close_channel(struct drm_device *drm, void *data,
 481                               struct drm_file *file)
 482{
 483        struct tegra_drm_file *fpriv = file->driver_priv;
 484        struct drm_tegra_close_channel *args = data;
 485        struct tegra_drm_context *context;
 486        int err = 0;
 487
 488        mutex_lock(&fpriv->lock);
 489
 490        context = idr_find(&fpriv->contexts, args->context);
 491        if (!context) {
 492                err = -EINVAL;
 493                goto unlock;
 494        }
 495
 496        idr_remove(&fpriv->contexts, context->id);
 497        tegra_drm_context_free(context);
 498
 499unlock:
 500        mutex_unlock(&fpriv->lock);
 501        return err;
 502}
 503
 504static int tegra_get_syncpt(struct drm_device *drm, void *data,
 505                            struct drm_file *file)
 506{
 507        struct tegra_drm_file *fpriv = file->driver_priv;
 508        struct drm_tegra_get_syncpt *args = data;
 509        struct tegra_drm_context *context;
 510        struct host1x_syncpt *syncpt;
 511        int err = 0;
 512
 513        mutex_lock(&fpriv->lock);
 514
 515        context = idr_find(&fpriv->contexts, args->context);
 516        if (!context) {
 517                err = -ENODEV;
 518                goto unlock;
 519        }
 520
 521        if (args->index >= context->client->base.num_syncpts) {
 522                err = -EINVAL;
 523                goto unlock;
 524        }
 525
 526        syncpt = context->client->base.syncpts[args->index];
 527        args->id = host1x_syncpt_id(syncpt);
 528
 529unlock:
 530        mutex_unlock(&fpriv->lock);
 531        return err;
 532}
 533
 534static int tegra_submit(struct drm_device *drm, void *data,
 535                        struct drm_file *file)
 536{
 537        struct tegra_drm_file *fpriv = file->driver_priv;
 538        struct drm_tegra_submit *args = data;
 539        struct tegra_drm_context *context;
 540        int err;
 541
 542        mutex_lock(&fpriv->lock);
 543
 544        context = idr_find(&fpriv->contexts, args->context);
 545        if (!context) {
 546                err = -ENODEV;
 547                goto unlock;
 548        }
 549
 550        err = context->client->ops->submit(context, args, drm, file);
 551
 552unlock:
 553        mutex_unlock(&fpriv->lock);
 554        return err;
 555}
 556
 557static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
 558                                 struct drm_file *file)
 559{
 560        struct tegra_drm_file *fpriv = file->driver_priv;
 561        struct drm_tegra_get_syncpt_base *args = data;
 562        struct tegra_drm_context *context;
 563        struct host1x_syncpt_base *base;
 564        struct host1x_syncpt *syncpt;
 565        int err = 0;
 566
 567        mutex_lock(&fpriv->lock);
 568
 569        context = idr_find(&fpriv->contexts, args->context);
 570        if (!context) {
 571                err = -ENODEV;
 572                goto unlock;
 573        }
 574
 575        if (args->syncpt >= context->client->base.num_syncpts) {
 576                err = -EINVAL;
 577                goto unlock;
 578        }
 579
 580        syncpt = context->client->base.syncpts[args->syncpt];
 581
 582        base = host1x_syncpt_get_base(syncpt);
 583        if (!base) {
 584                err = -ENXIO;
 585                goto unlock;
 586        }
 587
 588        args->id = host1x_syncpt_base_id(base);
 589
 590unlock:
 591        mutex_unlock(&fpriv->lock);
 592        return err;
 593}
 594
 595static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
 596                                struct drm_file *file)
 597{
 598        struct drm_tegra_gem_set_tiling *args = data;
 599        enum tegra_bo_tiling_mode mode;
 600        struct drm_gem_object *gem;
 601        unsigned long value = 0;
 602        struct tegra_bo *bo;
 603
 604        switch (args->mode) {
 605        case DRM_TEGRA_GEM_TILING_MODE_PITCH:
 606                mode = TEGRA_BO_TILING_MODE_PITCH;
 607
 608                if (args->value != 0)
 609                        return -EINVAL;
 610
 611                break;
 612
 613        case DRM_TEGRA_GEM_TILING_MODE_TILED:
 614                mode = TEGRA_BO_TILING_MODE_TILED;
 615
 616                if (args->value != 0)
 617                        return -EINVAL;
 618
 619                break;
 620
 621        case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
 622                mode = TEGRA_BO_TILING_MODE_BLOCK;
 623
 624                if (args->value > 5)
 625                        return -EINVAL;
 626
 627                value = args->value;
 628                break;
 629
 630        default:
 631                return -EINVAL;
 632        }
 633
 634        gem = drm_gem_object_lookup(file, args->handle);
 635        if (!gem)
 636                return -ENOENT;
 637
 638        bo = to_tegra_bo(gem);
 639
 640        bo->tiling.mode = mode;
 641        bo->tiling.value = value;
 642
 643        drm_gem_object_put(gem);
 644
 645        return 0;
 646}
 647
 648static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
 649                                struct drm_file *file)
 650{
 651        struct drm_tegra_gem_get_tiling *args = data;
 652        struct drm_gem_object *gem;
 653        struct tegra_bo *bo;
 654        int err = 0;
 655
 656        gem = drm_gem_object_lookup(file, args->handle);
 657        if (!gem)
 658                return -ENOENT;
 659
 660        bo = to_tegra_bo(gem);
 661
 662        switch (bo->tiling.mode) {
 663        case TEGRA_BO_TILING_MODE_PITCH:
 664                args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
 665                args->value = 0;
 666                break;
 667
 668        case TEGRA_BO_TILING_MODE_TILED:
 669                args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
 670                args->value = 0;
 671                break;
 672
 673        case TEGRA_BO_TILING_MODE_BLOCK:
 674                args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
 675                args->value = bo->tiling.value;
 676                break;
 677
 678        default:
 679                err = -EINVAL;
 680                break;
 681        }
 682
 683        drm_gem_object_put(gem);
 684
 685        return err;
 686}
 687
 688static int tegra_gem_set_flags(struct drm_device *drm, void *data,
 689                               struct drm_file *file)
 690{
 691        struct drm_tegra_gem_set_flags *args = data;
 692        struct drm_gem_object *gem;
 693        struct tegra_bo *bo;
 694
 695        if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
 696                return -EINVAL;
 697
 698        gem = drm_gem_object_lookup(file, args->handle);
 699        if (!gem)
 700                return -ENOENT;
 701
 702        bo = to_tegra_bo(gem);
 703        bo->flags = 0;
 704
 705        if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
 706                bo->flags |= TEGRA_BO_BOTTOM_UP;
 707
 708        drm_gem_object_put(gem);
 709
 710        return 0;
 711}
 712
 713static int tegra_gem_get_flags(struct drm_device *drm, void *data,
 714                               struct drm_file *file)
 715{
 716        struct drm_tegra_gem_get_flags *args = data;
 717        struct drm_gem_object *gem;
 718        struct tegra_bo *bo;
 719
 720        gem = drm_gem_object_lookup(file, args->handle);
 721        if (!gem)
 722                return -ENOENT;
 723
 724        bo = to_tegra_bo(gem);
 725        args->flags = 0;
 726
 727        if (bo->flags & TEGRA_BO_BOTTOM_UP)
 728                args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
 729
 730        drm_gem_object_put(gem);
 731
 732        return 0;
 733}
 734#endif
 735
 736static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
 737#ifdef CONFIG_DRM_TEGRA_STAGING
 738        DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
 739                          DRM_RENDER_ALLOW),
 740        DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
 741                          DRM_RENDER_ALLOW),
 742        DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
 743                          DRM_RENDER_ALLOW),
 744        DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
 745                          DRM_RENDER_ALLOW),
 746        DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
 747                          DRM_RENDER_ALLOW),
 748        DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
 749                          DRM_RENDER_ALLOW),
 750        DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
 751                          DRM_RENDER_ALLOW),
 752        DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
 753                          DRM_RENDER_ALLOW),
 754        DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
 755                          DRM_RENDER_ALLOW),
 756        DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
 757                          DRM_RENDER_ALLOW),
 758        DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
 759                          DRM_RENDER_ALLOW),
 760        DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
 761                          DRM_RENDER_ALLOW),
 762        DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
 763                          DRM_RENDER_ALLOW),
 764        DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
 765                          DRM_RENDER_ALLOW),
 766#endif
 767};
 768
 769static const struct file_operations tegra_drm_fops = {
 770        .owner = THIS_MODULE,
 771        .open = drm_open,
 772        .release = drm_release,
 773        .unlocked_ioctl = drm_ioctl,
 774        .mmap = tegra_drm_mmap,
 775        .poll = drm_poll,
 776        .read = drm_read,
 777        .compat_ioctl = drm_compat_ioctl,
 778        .llseek = noop_llseek,
 779};
 780
 781static int tegra_drm_context_cleanup(int id, void *p, void *data)
 782{
 783        struct tegra_drm_context *context = p;
 784
 785        tegra_drm_context_free(context);
 786
 787        return 0;
 788}
 789
 790static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
 791{
 792        struct tegra_drm_file *fpriv = file->driver_priv;
 793
 794        mutex_lock(&fpriv->lock);
 795        idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
 796        mutex_unlock(&fpriv->lock);
 797
 798        idr_destroy(&fpriv->contexts);
 799        mutex_destroy(&fpriv->lock);
 800        kfree(fpriv);
 801}
 802
 803#ifdef CONFIG_DEBUG_FS
 804static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
 805{
 806        struct drm_info_node *node = (struct drm_info_node *)s->private;
 807        struct drm_device *drm = node->minor->dev;
 808        struct drm_framebuffer *fb;
 809
 810        mutex_lock(&drm->mode_config.fb_lock);
 811
 812        list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
 813                seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
 814                           fb->base.id, fb->width, fb->height,
 815                           fb->format->depth,
 816                           fb->format->cpp[0] * 8,
 817                           drm_framebuffer_read_refcount(fb));
 818        }
 819
 820        mutex_unlock(&drm->mode_config.fb_lock);
 821
 822        return 0;
 823}
 824
 825static int tegra_debugfs_iova(struct seq_file *s, void *data)
 826{
 827        struct drm_info_node *node = (struct drm_info_node *)s->private;
 828        struct drm_device *drm = node->minor->dev;
 829        struct tegra_drm *tegra = drm->dev_private;
 830        struct drm_printer p = drm_seq_file_printer(s);
 831
 832        if (tegra->domain) {
 833                mutex_lock(&tegra->mm_lock);
 834                drm_mm_print(&tegra->mm, &p);
 835                mutex_unlock(&tegra->mm_lock);
 836        }
 837
 838        return 0;
 839}
 840
 841static struct drm_info_list tegra_debugfs_list[] = {
 842        { "framebuffers", tegra_debugfs_framebuffers, 0 },
 843        { "iova", tegra_debugfs_iova, 0 },
 844};
 845
 846static void tegra_debugfs_init(struct drm_minor *minor)
 847{
 848        drm_debugfs_create_files(tegra_debugfs_list,
 849                                 ARRAY_SIZE(tegra_debugfs_list),
 850                                 minor->debugfs_root, minor);
 851}
 852#endif
 853
 854static const struct drm_driver tegra_drm_driver = {
 855        .driver_features = DRIVER_MODESET | DRIVER_GEM |
 856                           DRIVER_ATOMIC | DRIVER_RENDER,
 857        .open = tegra_drm_open,
 858        .postclose = tegra_drm_postclose,
 859        .lastclose = drm_fb_helper_lastclose,
 860
 861#if defined(CONFIG_DEBUG_FS)
 862        .debugfs_init = tegra_debugfs_init,
 863#endif
 864
 865        .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 866        .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 867        .gem_prime_import = tegra_gem_prime_import,
 868
 869        .dumb_create = tegra_bo_dumb_create,
 870
 871        .ioctls = tegra_drm_ioctls,
 872        .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
 873        .fops = &tegra_drm_fops,
 874
 875        .name = DRIVER_NAME,
 876        .desc = DRIVER_DESC,
 877        .date = DRIVER_DATE,
 878        .major = DRIVER_MAJOR,
 879        .minor = DRIVER_MINOR,
 880        .patchlevel = DRIVER_PATCHLEVEL,
 881};
 882
 883int tegra_drm_register_client(struct tegra_drm *tegra,
 884                              struct tegra_drm_client *client)
 885{
 886        mutex_lock(&tegra->clients_lock);
 887        list_add_tail(&client->list, &tegra->clients);
 888        client->drm = tegra;
 889        mutex_unlock(&tegra->clients_lock);
 890
 891        return 0;
 892}
 893
 894int tegra_drm_unregister_client(struct tegra_drm *tegra,
 895                                struct tegra_drm_client *client)
 896{
 897        mutex_lock(&tegra->clients_lock);
 898        list_del_init(&client->list);
 899        client->drm = NULL;
 900        mutex_unlock(&tegra->clients_lock);
 901
 902        return 0;
 903}
 904
 905int host1x_client_iommu_attach(struct host1x_client *client)
 906{
 907        struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev);
 908        struct drm_device *drm = dev_get_drvdata(client->host);
 909        struct tegra_drm *tegra = drm->dev_private;
 910        struct iommu_group *group = NULL;
 911        int err;
 912
 913        /*
 914         * If the host1x client is already attached to an IOMMU domain that is
 915         * not the shared IOMMU domain, don't try to attach it to a different
 916         * domain. This allows using the IOMMU-backed DMA API.
 917         */
 918        if (domain && domain != tegra->domain)
 919                return 0;
 920
 921        if (tegra->domain) {
 922                group = iommu_group_get(client->dev);
 923                if (!group)
 924                        return -ENODEV;
 925
 926                if (domain != tegra->domain) {
 927                        err = iommu_attach_group(tegra->domain, group);
 928                        if (err < 0) {
 929                                iommu_group_put(group);
 930                                return err;
 931                        }
 932                }
 933
 934                tegra->use_explicit_iommu = true;
 935        }
 936
 937        client->group = group;
 938
 939        return 0;
 940}
 941
 942void host1x_client_iommu_detach(struct host1x_client *client)
 943{
 944        struct drm_device *drm = dev_get_drvdata(client->host);
 945        struct tegra_drm *tegra = drm->dev_private;
 946        struct iommu_domain *domain;
 947
 948        if (client->group) {
 949                /*
 950                 * Devices that are part of the same group may no longer be
 951                 * attached to a domain at this point because their group may
 952                 * have been detached by an earlier client.
 953                 */
 954                domain = iommu_get_domain_for_dev(client->dev);
 955                if (domain)
 956                        iommu_detach_group(tegra->domain, client->group);
 957
 958                iommu_group_put(client->group);
 959                client->group = NULL;
 960        }
 961}
 962
 963void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
 964{
 965        struct iova *alloc;
 966        void *virt;
 967        gfp_t gfp;
 968        int err;
 969
 970        if (tegra->domain)
 971                size = iova_align(&tegra->carveout.domain, size);
 972        else
 973                size = PAGE_ALIGN(size);
 974
 975        gfp = GFP_KERNEL | __GFP_ZERO;
 976        if (!tegra->domain) {
 977                /*
 978                 * Many units only support 32-bit addresses, even on 64-bit
 979                 * SoCs. If there is no IOMMU to translate into a 32-bit IO
 980                 * virtual address space, force allocations to be in the
 981                 * lower 32-bit range.
 982                 */
 983                gfp |= GFP_DMA;
 984        }
 985
 986        virt = (void *)__get_free_pages(gfp, get_order(size));
 987        if (!virt)
 988                return ERR_PTR(-ENOMEM);
 989
 990        if (!tegra->domain) {
 991                /*
 992                 * If IOMMU is disabled, devices address physical memory
 993                 * directly.
 994                 */
 995                *dma = virt_to_phys(virt);
 996                return virt;
 997        }
 998
 999        alloc = alloc_iova(&tegra->carveout.domain,
1000                           size >> tegra->carveout.shift,
1001                           tegra->carveout.limit, true);
1002        if (!alloc) {
1003                err = -EBUSY;
1004                goto free_pages;
1005        }
1006
1007        *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1008        err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1009                        size, IOMMU_READ | IOMMU_WRITE);
1010        if (err < 0)
1011                goto free_iova;
1012
1013        return virt;
1014
1015free_iova:
1016        __free_iova(&tegra->carveout.domain, alloc);
1017free_pages:
1018        free_pages((unsigned long)virt, get_order(size));
1019
1020        return ERR_PTR(err);
1021}
1022
1023void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1024                    dma_addr_t dma)
1025{
1026        if (tegra->domain)
1027                size = iova_align(&tegra->carveout.domain, size);
1028        else
1029                size = PAGE_ALIGN(size);
1030
1031        if (tegra->domain) {
1032                iommu_unmap(tegra->domain, dma, size);
1033                free_iova(&tegra->carveout.domain,
1034                          iova_pfn(&tegra->carveout.domain, dma));
1035        }
1036
1037        free_pages((unsigned long)virt, get_order(size));
1038}
1039
1040static bool host1x_drm_wants_iommu(struct host1x_device *dev)
1041{
1042        struct host1x *host1x = dev_get_drvdata(dev->dev.parent);
1043        struct iommu_domain *domain;
1044
1045        /*
1046         * If the Tegra DRM clients are backed by an IOMMU, push buffers are
1047         * likely to be allocated beyond the 32-bit boundary if sufficient
1048         * system memory is available. This is problematic on earlier Tegra
1049         * generations where host1x supports a maximum of 32 address bits in
1050         * the GATHER opcode. In this case, unless host1x is behind an IOMMU
1051         * as well it won't be able to process buffers allocated beyond the
1052         * 32-bit boundary.
1053         *
1054         * The DMA API will use bounce buffers in this case, so that could
1055         * perhaps still be made to work, even if less efficient, but there
1056         * is another catch: in order to perform cache maintenance on pages
1057         * allocated for discontiguous buffers we need to map and unmap the
1058         * SG table representing these buffers. This is fine for something
1059         * small like a push buffer, but it exhausts the bounce buffer pool
1060         * (typically on the order of a few MiB) for framebuffers (many MiB
1061         * for any modern resolution).
1062         *
1063         * Work around this by making sure that Tegra DRM clients only use
1064         * an IOMMU if the parent host1x also uses an IOMMU.
1065         *
1066         * Note that there's still a small gap here that we don't cover: if
1067         * the DMA API is backed by an IOMMU there's no way to control which
1068         * device is attached to an IOMMU and which isn't, except via wiring
1069         * up the device tree appropriately. This is considered an problem
1070         * of integration, so care must be taken for the DT to be consistent.
1071         */
1072        domain = iommu_get_domain_for_dev(dev->dev.parent);
1073
1074        /*
1075         * Tegra20 and Tegra30 don't support addressing memory beyond the
1076         * 32-bit boundary, so the regular GATHER opcodes will always be
1077         * sufficient and whether or not the host1x is attached to an IOMMU
1078         * doesn't matter.
1079         */
1080        if (!domain && host1x_get_dma_mask(host1x) <= DMA_BIT_MASK(32))
1081                return true;
1082
1083        return domain != NULL;
1084}
1085
1086static int host1x_drm_probe(struct host1x_device *dev)
1087{
1088        struct tegra_drm *tegra;
1089        struct drm_device *drm;
1090        int err;
1091
1092        drm = drm_dev_alloc(&tegra_drm_driver, &dev->dev);
1093        if (IS_ERR(drm))
1094                return PTR_ERR(drm);
1095
1096        tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
1097        if (!tegra) {
1098                err = -ENOMEM;
1099                goto put;
1100        }
1101
1102        if (host1x_drm_wants_iommu(dev) && iommu_present(&platform_bus_type)) {
1103                tegra->domain = iommu_domain_alloc(&platform_bus_type);
1104                if (!tegra->domain) {
1105                        err = -ENOMEM;
1106                        goto free;
1107                }
1108
1109                err = iova_cache_get();
1110                if (err < 0)
1111                        goto domain;
1112        }
1113
1114        mutex_init(&tegra->clients_lock);
1115        INIT_LIST_HEAD(&tegra->clients);
1116
1117        dev_set_drvdata(&dev->dev, drm);
1118        drm->dev_private = tegra;
1119        tegra->drm = drm;
1120
1121        drm_mode_config_init(drm);
1122
1123        drm->mode_config.min_width = 0;
1124        drm->mode_config.min_height = 0;
1125        drm->mode_config.max_width = 0;
1126        drm->mode_config.max_height = 0;
1127
1128        drm->mode_config.normalize_zpos = true;
1129
1130        drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
1131        drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
1132
1133        err = tegra_drm_fb_prepare(drm);
1134        if (err < 0)
1135                goto config;
1136
1137        drm_kms_helper_poll_init(drm);
1138
1139        err = host1x_device_init(dev);
1140        if (err < 0)
1141                goto fbdev;
1142
1143        /*
1144         * Now that all display controller have been initialized, the maximum
1145         * supported resolution is known and the bitmask for horizontal and
1146         * vertical bitfields can be computed.
1147         */
1148        tegra->hmask = drm->mode_config.max_width - 1;
1149        tegra->vmask = drm->mode_config.max_height - 1;
1150
1151        if (tegra->use_explicit_iommu) {
1152                u64 carveout_start, carveout_end, gem_start, gem_end;
1153                u64 dma_mask = dma_get_mask(&dev->dev);
1154                dma_addr_t start, end;
1155                unsigned long order;
1156
1157                start = tegra->domain->geometry.aperture_start & dma_mask;
1158                end = tegra->domain->geometry.aperture_end & dma_mask;
1159
1160                gem_start = start;
1161                gem_end = end - CARVEOUT_SZ;
1162                carveout_start = gem_end + 1;
1163                carveout_end = end;
1164
1165                order = __ffs(tegra->domain->pgsize_bitmap);
1166                init_iova_domain(&tegra->carveout.domain, 1UL << order,
1167                                 carveout_start >> order);
1168
1169                tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
1170                tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
1171
1172                drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
1173                mutex_init(&tegra->mm_lock);
1174
1175                DRM_DEBUG_DRIVER("IOMMU apertures:\n");
1176                DRM_DEBUG_DRIVER("  GEM: %#llx-%#llx\n", gem_start, gem_end);
1177                DRM_DEBUG_DRIVER("  Carveout: %#llx-%#llx\n", carveout_start,
1178                                 carveout_end);
1179        } else if (tegra->domain) {
1180                iommu_domain_free(tegra->domain);
1181                tegra->domain = NULL;
1182                iova_cache_put();
1183        }
1184
1185        if (tegra->hub) {
1186                err = tegra_display_hub_prepare(tegra->hub);
1187                if (err < 0)
1188                        goto device;
1189        }
1190
1191        /*
1192         * We don't use the drm_irq_install() helpers provided by the DRM
1193         * core, so we need to set this manually in order to allow the
1194         * DRM_IOCTL_WAIT_VBLANK to operate correctly.
1195         */
1196        drm->irq_enabled = true;
1197
1198        /* syncpoints are used for full 32-bit hardware VBLANK counters */
1199        drm->max_vblank_count = 0xffffffff;
1200
1201        err = drm_vblank_init(drm, drm->mode_config.num_crtc);
1202        if (err < 0)
1203                goto hub;
1204
1205        drm_mode_config_reset(drm);
1206
1207        err = drm_aperture_remove_framebuffers(false, "tegradrmfb");
1208        if (err < 0)
1209                goto hub;
1210
1211        err = tegra_drm_fb_init(drm);
1212        if (err < 0)
1213                goto hub;
1214
1215        err = drm_dev_register(drm, 0);
1216        if (err < 0)
1217                goto fb;
1218
1219        return 0;
1220
1221fb:
1222        tegra_drm_fb_exit(drm);
1223hub:
1224        if (tegra->hub)
1225                tegra_display_hub_cleanup(tegra->hub);
1226device:
1227        if (tegra->domain) {
1228                mutex_destroy(&tegra->mm_lock);
1229                drm_mm_takedown(&tegra->mm);
1230                put_iova_domain(&tegra->carveout.domain);
1231                iova_cache_put();
1232        }
1233
1234        host1x_device_exit(dev);
1235fbdev:
1236        drm_kms_helper_poll_fini(drm);
1237        tegra_drm_fb_free(drm);
1238config:
1239        drm_mode_config_cleanup(drm);
1240domain:
1241        if (tegra->domain)
1242                iommu_domain_free(tegra->domain);
1243free:
1244        kfree(tegra);
1245put:
1246        drm_dev_put(drm);
1247        return err;
1248}
1249
1250static int host1x_drm_remove(struct host1x_device *dev)
1251{
1252        struct drm_device *drm = dev_get_drvdata(&dev->dev);
1253        struct tegra_drm *tegra = drm->dev_private;
1254        int err;
1255
1256        drm_dev_unregister(drm);
1257
1258        drm_kms_helper_poll_fini(drm);
1259        tegra_drm_fb_exit(drm);
1260        drm_atomic_helper_shutdown(drm);
1261        drm_mode_config_cleanup(drm);
1262
1263        if (tegra->hub)
1264                tegra_display_hub_cleanup(tegra->hub);
1265
1266        err = host1x_device_exit(dev);
1267        if (err < 0)
1268                dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err);
1269
1270        if (tegra->domain) {
1271                mutex_destroy(&tegra->mm_lock);
1272                drm_mm_takedown(&tegra->mm);
1273                put_iova_domain(&tegra->carveout.domain);
1274                iova_cache_put();
1275                iommu_domain_free(tegra->domain);
1276        }
1277
1278        kfree(tegra);
1279        drm_dev_put(drm);
1280
1281        return 0;
1282}
1283
1284#ifdef CONFIG_PM_SLEEP
1285static int host1x_drm_suspend(struct device *dev)
1286{
1287        struct drm_device *drm = dev_get_drvdata(dev);
1288
1289        return drm_mode_config_helper_suspend(drm);
1290}
1291
1292static int host1x_drm_resume(struct device *dev)
1293{
1294        struct drm_device *drm = dev_get_drvdata(dev);
1295
1296        return drm_mode_config_helper_resume(drm);
1297}
1298#endif
1299
1300static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1301                         host1x_drm_resume);
1302
1303static const struct of_device_id host1x_drm_subdevs[] = {
1304        { .compatible = "nvidia,tegra20-dc", },
1305        { .compatible = "nvidia,tegra20-hdmi", },
1306        { .compatible = "nvidia,tegra20-gr2d", },
1307        { .compatible = "nvidia,tegra20-gr3d", },
1308        { .compatible = "nvidia,tegra30-dc", },
1309        { .compatible = "nvidia,tegra30-hdmi", },
1310        { .compatible = "nvidia,tegra30-gr2d", },
1311        { .compatible = "nvidia,tegra30-gr3d", },
1312        { .compatible = "nvidia,tegra114-dc", },
1313        { .compatible = "nvidia,tegra114-dsi", },
1314        { .compatible = "nvidia,tegra114-hdmi", },
1315        { .compatible = "nvidia,tegra114-gr2d", },
1316        { .compatible = "nvidia,tegra114-gr3d", },
1317        { .compatible = "nvidia,tegra124-dc", },
1318        { .compatible = "nvidia,tegra124-sor", },
1319        { .compatible = "nvidia,tegra124-hdmi", },
1320        { .compatible = "nvidia,tegra124-dsi", },
1321        { .compatible = "nvidia,tegra124-vic", },
1322        { .compatible = "nvidia,tegra132-dsi", },
1323        { .compatible = "nvidia,tegra210-dc", },
1324        { .compatible = "nvidia,tegra210-dsi", },
1325        { .compatible = "nvidia,tegra210-sor", },
1326        { .compatible = "nvidia,tegra210-sor1", },
1327        { .compatible = "nvidia,tegra210-vic", },
1328        { .compatible = "nvidia,tegra186-display", },
1329        { .compatible = "nvidia,tegra186-dc", },
1330        { .compatible = "nvidia,tegra186-sor", },
1331        { .compatible = "nvidia,tegra186-sor1", },
1332        { .compatible = "nvidia,tegra186-vic", },
1333        { .compatible = "nvidia,tegra194-display", },
1334        { .compatible = "nvidia,tegra194-dc", },
1335        { .compatible = "nvidia,tegra194-sor", },
1336        { .compatible = "nvidia,tegra194-vic", },
1337        { /* sentinel */ }
1338};
1339
1340static struct host1x_driver host1x_drm_driver = {
1341        .driver = {
1342                .name = "drm",
1343                .pm = &host1x_drm_pm_ops,
1344        },
1345        .probe = host1x_drm_probe,
1346        .remove = host1x_drm_remove,
1347        .subdevs = host1x_drm_subdevs,
1348};
1349
1350static struct platform_driver * const drivers[] = {
1351        &tegra_display_hub_driver,
1352        &tegra_dc_driver,
1353        &tegra_hdmi_driver,
1354        &tegra_dsi_driver,
1355        &tegra_dpaux_driver,
1356        &tegra_sor_driver,
1357        &tegra_gr2d_driver,
1358        &tegra_gr3d_driver,
1359        &tegra_vic_driver,
1360};
1361
1362static int __init host1x_drm_init(void)
1363{
1364        int err;
1365
1366        err = host1x_driver_register(&host1x_drm_driver);
1367        if (err < 0)
1368                return err;
1369
1370        err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1371        if (err < 0)
1372                goto unregister_host1x;
1373
1374        return 0;
1375
1376unregister_host1x:
1377        host1x_driver_unregister(&host1x_drm_driver);
1378        return err;
1379}
1380module_init(host1x_drm_init);
1381
1382static void __exit host1x_drm_exit(void)
1383{
1384        platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1385        host1x_driver_unregister(&host1x_drm_driver);
1386}
1387module_exit(host1x_drm_exit);
1388
1389MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1390MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1391MODULE_LICENSE("GPL v2");
1392