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54#include "vmwgfx_drv.h"
55#include "vmwgfx_binding.h"
56#include "device_include/svga3d_reg.h"
57
58#define VMW_BINDING_RT_BIT 0
59#define VMW_BINDING_PS_BIT 1
60#define VMW_BINDING_SO_T_BIT 2
61#define VMW_BINDING_VB_BIT 3
62#define VMW_BINDING_UAV_BIT 4
63#define VMW_BINDING_CS_UAV_BIT 5
64#define VMW_BINDING_NUM_BITS 6
65
66#define VMW_BINDING_PS_SR_BIT 0
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95
96struct vmw_ctx_binding_state {
97 struct vmw_private *dev_priv;
98 struct list_head list;
99 struct vmw_ctx_bindinfo_view render_targets[SVGA3D_RT_MAX];
100 struct vmw_ctx_bindinfo_tex texture_units[SVGA3D_NUM_TEXTURE_UNITS];
101 struct vmw_ctx_bindinfo_view ds_view;
102 struct vmw_ctx_bindinfo_so_target so_targets[SVGA3D_DX_MAX_SOTARGETS];
103 struct vmw_ctx_bindinfo_vb vertex_buffers[SVGA3D_DX_MAX_VERTEXBUFFERS];
104 struct vmw_ctx_bindinfo_ib index_buffer;
105 struct vmw_dx_shader_bindings per_shader[SVGA3D_NUM_SHADERTYPE];
106 struct vmw_ctx_bindinfo_uav ua_views[VMW_MAX_UAV_BIND_TYPE];
107 struct vmw_ctx_bindinfo_so so_state;
108
109 unsigned long dirty;
110 DECLARE_BITMAP(dirty_vb, SVGA3D_DX_MAX_VERTEXBUFFERS);
111
112 u32 bind_cmd_buffer[VMW_MAX_VIEW_BINDINGS];
113 u32 bind_cmd_count;
114 u32 bind_first_slot;
115};
116
117static int vmw_binding_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind);
118static int vmw_binding_scrub_render_target(struct vmw_ctx_bindinfo *bi,
119 bool rebind);
120static int vmw_binding_scrub_texture(struct vmw_ctx_bindinfo *bi, bool rebind);
121static int vmw_binding_scrub_cb(struct vmw_ctx_bindinfo *bi, bool rebind);
122static int vmw_binding_scrub_dx_rt(struct vmw_ctx_bindinfo *bi, bool rebind);
123static int vmw_binding_scrub_sr(struct vmw_ctx_bindinfo *bi, bool rebind);
124static int vmw_binding_scrub_so_target(struct vmw_ctx_bindinfo *bi, bool rebind);
125static int vmw_binding_emit_dirty(struct vmw_ctx_binding_state *cbs);
126static int vmw_binding_scrub_dx_shader(struct vmw_ctx_bindinfo *bi,
127 bool rebind);
128static int vmw_binding_scrub_ib(struct vmw_ctx_bindinfo *bi, bool rebind);
129static int vmw_binding_scrub_vb(struct vmw_ctx_bindinfo *bi, bool rebind);
130static int vmw_binding_scrub_uav(struct vmw_ctx_bindinfo *bi, bool rebind);
131static int vmw_binding_scrub_cs_uav(struct vmw_ctx_bindinfo *bi, bool rebind);
132static int vmw_binding_scrub_so(struct vmw_ctx_bindinfo *bi, bool rebind);
133
134static void vmw_binding_build_asserts(void) __attribute__ ((unused));
135
136typedef int (*vmw_scrub_func)(struct vmw_ctx_bindinfo *, bool);
137
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150struct vmw_binding_info {
151 size_t size;
152 const size_t *offsets;
153 vmw_scrub_func scrub_func;
154};
155
156
157
158
159
160static const size_t vmw_binding_shader_offsets[] = {
161 offsetof(struct vmw_ctx_binding_state, per_shader[0].shader),
162 offsetof(struct vmw_ctx_binding_state, per_shader[1].shader),
163 offsetof(struct vmw_ctx_binding_state, per_shader[2].shader),
164 offsetof(struct vmw_ctx_binding_state, per_shader[3].shader),
165 offsetof(struct vmw_ctx_binding_state, per_shader[4].shader),
166 offsetof(struct vmw_ctx_binding_state, per_shader[5].shader),
167};
168static const size_t vmw_binding_rt_offsets[] = {
169 offsetof(struct vmw_ctx_binding_state, render_targets),
170};
171static const size_t vmw_binding_tex_offsets[] = {
172 offsetof(struct vmw_ctx_binding_state, texture_units),
173};
174static const size_t vmw_binding_cb_offsets[] = {
175 offsetof(struct vmw_ctx_binding_state, per_shader[0].const_buffers),
176 offsetof(struct vmw_ctx_binding_state, per_shader[1].const_buffers),
177 offsetof(struct vmw_ctx_binding_state, per_shader[2].const_buffers),
178 offsetof(struct vmw_ctx_binding_state, per_shader[3].const_buffers),
179 offsetof(struct vmw_ctx_binding_state, per_shader[4].const_buffers),
180 offsetof(struct vmw_ctx_binding_state, per_shader[5].const_buffers),
181};
182static const size_t vmw_binding_dx_ds_offsets[] = {
183 offsetof(struct vmw_ctx_binding_state, ds_view),
184};
185static const size_t vmw_binding_sr_offsets[] = {
186 offsetof(struct vmw_ctx_binding_state, per_shader[0].shader_res),
187 offsetof(struct vmw_ctx_binding_state, per_shader[1].shader_res),
188 offsetof(struct vmw_ctx_binding_state, per_shader[2].shader_res),
189 offsetof(struct vmw_ctx_binding_state, per_shader[3].shader_res),
190 offsetof(struct vmw_ctx_binding_state, per_shader[4].shader_res),
191 offsetof(struct vmw_ctx_binding_state, per_shader[5].shader_res),
192};
193static const size_t vmw_binding_so_target_offsets[] = {
194 offsetof(struct vmw_ctx_binding_state, so_targets),
195};
196static const size_t vmw_binding_vb_offsets[] = {
197 offsetof(struct vmw_ctx_binding_state, vertex_buffers),
198};
199static const size_t vmw_binding_ib_offsets[] = {
200 offsetof(struct vmw_ctx_binding_state, index_buffer),
201};
202static const size_t vmw_binding_uav_offsets[] = {
203 offsetof(struct vmw_ctx_binding_state, ua_views[0].views),
204};
205static const size_t vmw_binding_cs_uav_offsets[] = {
206 offsetof(struct vmw_ctx_binding_state, ua_views[1].views),
207};
208static const size_t vmw_binding_so_offsets[] = {
209 offsetof(struct vmw_ctx_binding_state, so_state),
210};
211
212static const struct vmw_binding_info vmw_binding_infos[] = {
213 [vmw_ctx_binding_shader] = {
214 .size = sizeof(struct vmw_ctx_bindinfo_shader),
215 .offsets = vmw_binding_shader_offsets,
216 .scrub_func = vmw_binding_scrub_shader},
217 [vmw_ctx_binding_rt] = {
218 .size = sizeof(struct vmw_ctx_bindinfo_view),
219 .offsets = vmw_binding_rt_offsets,
220 .scrub_func = vmw_binding_scrub_render_target},
221 [vmw_ctx_binding_tex] = {
222 .size = sizeof(struct vmw_ctx_bindinfo_tex),
223 .offsets = vmw_binding_tex_offsets,
224 .scrub_func = vmw_binding_scrub_texture},
225 [vmw_ctx_binding_cb] = {
226 .size = sizeof(struct vmw_ctx_bindinfo_cb),
227 .offsets = vmw_binding_cb_offsets,
228 .scrub_func = vmw_binding_scrub_cb},
229 [vmw_ctx_binding_dx_shader] = {
230 .size = sizeof(struct vmw_ctx_bindinfo_shader),
231 .offsets = vmw_binding_shader_offsets,
232 .scrub_func = vmw_binding_scrub_dx_shader},
233 [vmw_ctx_binding_dx_rt] = {
234 .size = sizeof(struct vmw_ctx_bindinfo_view),
235 .offsets = vmw_binding_rt_offsets,
236 .scrub_func = vmw_binding_scrub_dx_rt},
237 [vmw_ctx_binding_sr] = {
238 .size = sizeof(struct vmw_ctx_bindinfo_view),
239 .offsets = vmw_binding_sr_offsets,
240 .scrub_func = vmw_binding_scrub_sr},
241 [vmw_ctx_binding_ds] = {
242 .size = sizeof(struct vmw_ctx_bindinfo_view),
243 .offsets = vmw_binding_dx_ds_offsets,
244 .scrub_func = vmw_binding_scrub_dx_rt},
245 [vmw_ctx_binding_so_target] = {
246 .size = sizeof(struct vmw_ctx_bindinfo_so_target),
247 .offsets = vmw_binding_so_target_offsets,
248 .scrub_func = vmw_binding_scrub_so_target},
249 [vmw_ctx_binding_vb] = {
250 .size = sizeof(struct vmw_ctx_bindinfo_vb),
251 .offsets = vmw_binding_vb_offsets,
252 .scrub_func = vmw_binding_scrub_vb},
253 [vmw_ctx_binding_ib] = {
254 .size = sizeof(struct vmw_ctx_bindinfo_ib),
255 .offsets = vmw_binding_ib_offsets,
256 .scrub_func = vmw_binding_scrub_ib},
257 [vmw_ctx_binding_uav] = {
258 .size = sizeof(struct vmw_ctx_bindinfo_view),
259 .offsets = vmw_binding_uav_offsets,
260 .scrub_func = vmw_binding_scrub_uav},
261 [vmw_ctx_binding_cs_uav] = {
262 .size = sizeof(struct vmw_ctx_bindinfo_view),
263 .offsets = vmw_binding_cs_uav_offsets,
264 .scrub_func = vmw_binding_scrub_cs_uav},
265 [vmw_ctx_binding_so] = {
266 .size = sizeof(struct vmw_ctx_bindinfo_so),
267 .offsets = vmw_binding_so_offsets,
268 .scrub_func = vmw_binding_scrub_so},
269};
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283static const struct vmw_resource *
284vmw_cbs_context(const struct vmw_ctx_binding_state *cbs)
285{
286 if (list_empty(&cbs->list))
287 return NULL;
288
289 return list_first_entry(&cbs->list, struct vmw_ctx_bindinfo,
290 ctx_list)->ctx;
291}
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300
301static struct vmw_ctx_bindinfo *
302vmw_binding_loc(struct vmw_ctx_binding_state *cbs,
303 enum vmw_ctx_binding_type bt, u32 shader_slot, u32 slot)
304{
305 const struct vmw_binding_info *b = &vmw_binding_infos[bt];
306 size_t offset = b->offsets[shader_slot] + b->size*slot;
307
308 return (struct vmw_ctx_bindinfo *)((u8 *) cbs + offset);
309}
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320static void vmw_binding_drop(struct vmw_ctx_bindinfo *bi)
321{
322 list_del(&bi->ctx_list);
323 if (!list_empty(&bi->res_list))
324 list_del(&bi->res_list);
325 bi->ctx = NULL;
326}
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338
339void vmw_binding_add(struct vmw_ctx_binding_state *cbs,
340 const struct vmw_ctx_bindinfo *bi,
341 u32 shader_slot, u32 slot)
342{
343 struct vmw_ctx_bindinfo *loc =
344 vmw_binding_loc(cbs, bi->bt, shader_slot, slot);
345 const struct vmw_binding_info *b = &vmw_binding_infos[bi->bt];
346
347 if (loc->ctx != NULL)
348 vmw_binding_drop(loc);
349
350 memcpy(loc, bi, b->size);
351 loc->scrubbed = false;
352 list_add(&loc->ctx_list, &cbs->list);
353 INIT_LIST_HEAD(&loc->res_list);
354}
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361
362void vmw_binding_add_uav_index(struct vmw_ctx_binding_state *cbs, uint32 slot,
363 uint32 index)
364{
365 cbs->ua_views[slot].index = index;
366}
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375
376static void vmw_binding_transfer(struct vmw_ctx_binding_state *cbs,
377 const struct vmw_ctx_binding_state *from,
378 const struct vmw_ctx_bindinfo *bi)
379{
380 size_t offset = (unsigned long)bi - (unsigned long)from;
381 struct vmw_ctx_bindinfo *loc = (struct vmw_ctx_bindinfo *)
382 ((unsigned long) cbs + offset);
383
384 if (loc->ctx != NULL) {
385 WARN_ON(bi->scrubbed);
386
387 vmw_binding_drop(loc);
388 }
389
390 if (bi->res != NULL) {
391 memcpy(loc, bi, vmw_binding_infos[bi->bt].size);
392 list_add_tail(&loc->ctx_list, &cbs->list);
393 list_add_tail(&loc->res_list, &loc->res->binding_head);
394 }
395}
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406void vmw_binding_state_kill(struct vmw_ctx_binding_state *cbs)
407{
408 struct vmw_ctx_bindinfo *entry, *next;
409
410 vmw_binding_state_scrub(cbs);
411 list_for_each_entry_safe(entry, next, &cbs->list, ctx_list)
412 vmw_binding_drop(entry);
413}
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423
424void vmw_binding_state_scrub(struct vmw_ctx_binding_state *cbs)
425{
426 struct vmw_ctx_bindinfo *entry;
427
428 list_for_each_entry(entry, &cbs->list, ctx_list) {
429 if (!entry->scrubbed) {
430 (void) vmw_binding_infos[entry->bt].scrub_func
431 (entry, false);
432 entry->scrubbed = true;
433 }
434 }
435
436 (void) vmw_binding_emit_dirty(cbs);
437}
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448void vmw_binding_res_list_kill(struct list_head *head)
449{
450 struct vmw_ctx_bindinfo *entry, *next;
451
452 vmw_binding_res_list_scrub(head);
453 list_for_each_entry_safe(entry, next, head, res_list)
454 vmw_binding_drop(entry);
455}
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466void vmw_binding_res_list_scrub(struct list_head *head)
467{
468 struct vmw_ctx_bindinfo *entry;
469
470 list_for_each_entry(entry, head, res_list) {
471 if (!entry->scrubbed) {
472 (void) vmw_binding_infos[entry->bt].scrub_func
473 (entry, false);
474 entry->scrubbed = true;
475 }
476 }
477
478 list_for_each_entry(entry, head, res_list) {
479 struct vmw_ctx_binding_state *cbs =
480 vmw_context_binding_state(entry->ctx);
481
482 (void) vmw_binding_emit_dirty(cbs);
483 }
484}
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498void vmw_binding_state_commit(struct vmw_ctx_binding_state *to,
499 struct vmw_ctx_binding_state *from)
500{
501 struct vmw_ctx_bindinfo *entry, *next;
502
503 list_for_each_entry_safe(entry, next, &from->list, ctx_list) {
504 vmw_binding_transfer(to, from, entry);
505 vmw_binding_drop(entry);
506 }
507
508
509 to->ua_views[0].index = from->ua_views[0].index;
510 to->ua_views[1].index = from->ua_views[1].index;
511}
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520
521int vmw_binding_rebind_all(struct vmw_ctx_binding_state *cbs)
522{
523 struct vmw_ctx_bindinfo *entry;
524 int ret;
525
526 list_for_each_entry(entry, &cbs->list, ctx_list) {
527 if (likely(!entry->scrubbed))
528 continue;
529
530 if ((entry->res == NULL || entry->res->id ==
531 SVGA3D_INVALID_ID))
532 continue;
533
534 ret = vmw_binding_infos[entry->bt].scrub_func(entry, true);
535 if (unlikely(ret != 0))
536 return ret;
537
538 entry->scrubbed = false;
539 }
540
541 return vmw_binding_emit_dirty(cbs);
542}
543
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549
550static int vmw_binding_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind)
551{
552 struct vmw_ctx_bindinfo_shader *binding =
553 container_of(bi, typeof(*binding), bi);
554 struct vmw_private *dev_priv = bi->ctx->dev_priv;
555 struct {
556 SVGA3dCmdHeader header;
557 SVGA3dCmdSetShader body;
558 } *cmd;
559
560 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
561 if (unlikely(cmd == NULL))
562 return -ENOMEM;
563
564 cmd->header.id = SVGA_3D_CMD_SET_SHADER;
565 cmd->header.size = sizeof(cmd->body);
566 cmd->body.cid = bi->ctx->id;
567 cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;
568 cmd->body.shid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
569 vmw_cmd_commit(dev_priv, sizeof(*cmd));
570
571 return 0;
572}
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581static int vmw_binding_scrub_render_target(struct vmw_ctx_bindinfo *bi,
582 bool rebind)
583{
584 struct vmw_ctx_bindinfo_view *binding =
585 container_of(bi, typeof(*binding), bi);
586 struct vmw_private *dev_priv = bi->ctx->dev_priv;
587 struct {
588 SVGA3dCmdHeader header;
589 SVGA3dCmdSetRenderTarget body;
590 } *cmd;
591
592 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
593 if (unlikely(cmd == NULL))
594 return -ENOMEM;
595
596 cmd->header.id = SVGA_3D_CMD_SETRENDERTARGET;
597 cmd->header.size = sizeof(cmd->body);
598 cmd->body.cid = bi->ctx->id;
599 cmd->body.type = binding->slot;
600 cmd->body.target.sid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
601 cmd->body.target.face = 0;
602 cmd->body.target.mipmap = 0;
603 vmw_cmd_commit(dev_priv, sizeof(*cmd));
604
605 return 0;
606}
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616
617static int vmw_binding_scrub_texture(struct vmw_ctx_bindinfo *bi,
618 bool rebind)
619{
620 struct vmw_ctx_bindinfo_tex *binding =
621 container_of(bi, typeof(*binding), bi);
622 struct vmw_private *dev_priv = bi->ctx->dev_priv;
623 struct {
624 SVGA3dCmdHeader header;
625 struct {
626 SVGA3dCmdSetTextureState c;
627 SVGA3dTextureState s1;
628 } body;
629 } *cmd;
630
631 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
632 if (unlikely(cmd == NULL))
633 return -ENOMEM;
634
635 cmd->header.id = SVGA_3D_CMD_SETTEXTURESTATE;
636 cmd->header.size = sizeof(cmd->body);
637 cmd->body.c.cid = bi->ctx->id;
638 cmd->body.s1.stage = binding->texture_stage;
639 cmd->body.s1.name = SVGA3D_TS_BIND_TEXTURE;
640 cmd->body.s1.value = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
641 vmw_cmd_commit(dev_priv, sizeof(*cmd));
642
643 return 0;
644}
645
646
647
648
649
650
651
652static int vmw_binding_scrub_dx_shader(struct vmw_ctx_bindinfo *bi, bool rebind)
653{
654 struct vmw_ctx_bindinfo_shader *binding =
655 container_of(bi, typeof(*binding), bi);
656 struct vmw_private *dev_priv = bi->ctx->dev_priv;
657 struct {
658 SVGA3dCmdHeader header;
659 SVGA3dCmdDXSetShader body;
660 } *cmd;
661
662 cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);
663 if (unlikely(cmd == NULL))
664 return -ENOMEM;
665
666 cmd->header.id = SVGA_3D_CMD_DX_SET_SHADER;
667 cmd->header.size = sizeof(cmd->body);
668 cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;
669 cmd->body.shaderId = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
670 vmw_cmd_commit(dev_priv, sizeof(*cmd));
671
672 return 0;
673}
674
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678
679
680
681static int vmw_binding_scrub_cb(struct vmw_ctx_bindinfo *bi, bool rebind)
682{
683 struct vmw_ctx_bindinfo_cb *binding =
684 container_of(bi, typeof(*binding), bi);
685 struct vmw_private *dev_priv = bi->ctx->dev_priv;
686 struct {
687 SVGA3dCmdHeader header;
688 SVGA3dCmdDXSetSingleConstantBuffer body;
689 } *cmd;
690
691 cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);
692 if (unlikely(cmd == NULL))
693 return -ENOMEM;
694
695 cmd->header.id = SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER;
696 cmd->header.size = sizeof(cmd->body);
697 cmd->body.slot = binding->slot;
698 cmd->body.type = binding->shader_slot + SVGA3D_SHADERTYPE_MIN;
699 if (rebind) {
700 cmd->body.offsetInBytes = binding->offset;
701 cmd->body.sizeInBytes = binding->size;
702 cmd->body.sid = bi->res->id;
703 } else {
704 cmd->body.offsetInBytes = 0;
705 cmd->body.sizeInBytes = 0;
706 cmd->body.sid = SVGA3D_INVALID_ID;
707 }
708 vmw_cmd_commit(dev_priv, sizeof(*cmd));
709
710 return 0;
711}
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727static void vmw_collect_view_ids(struct vmw_ctx_binding_state *cbs,
728 const struct vmw_ctx_bindinfo *bi,
729 u32 max_num)
730{
731 const struct vmw_ctx_bindinfo_view *biv =
732 container_of(bi, struct vmw_ctx_bindinfo_view, bi);
733 unsigned long i;
734
735 cbs->bind_cmd_count = 0;
736 cbs->bind_first_slot = 0;
737
738 for (i = 0; i < max_num; ++i, ++biv) {
739 if (!biv->bi.ctx)
740 break;
741
742 cbs->bind_cmd_buffer[cbs->bind_cmd_count++] =
743 ((biv->bi.scrubbed) ?
744 SVGA3D_INVALID_ID : biv->bi.res->id);
745 }
746}
747
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762static void vmw_collect_dirty_view_ids(struct vmw_ctx_binding_state *cbs,
763 const struct vmw_ctx_bindinfo *bi,
764 unsigned long *dirty,
765 u32 max_num)
766{
767 const struct vmw_ctx_bindinfo_view *biv =
768 container_of(bi, struct vmw_ctx_bindinfo_view, bi);
769 unsigned long i, next_bit;
770
771 cbs->bind_cmd_count = 0;
772 i = find_first_bit(dirty, max_num);
773 next_bit = i;
774 cbs->bind_first_slot = i;
775
776 biv += i;
777 for (; i < max_num; ++i, ++biv) {
778 cbs->bind_cmd_buffer[cbs->bind_cmd_count++] =
779 ((!biv->bi.ctx || biv->bi.scrubbed) ?
780 SVGA3D_INVALID_ID : biv->bi.res->id);
781
782 if (next_bit == i) {
783 next_bit = find_next_bit(dirty, max_num, i + 1);
784 if (next_bit >= max_num)
785 break;
786 }
787 }
788}
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794
795
796static int vmw_emit_set_sr(struct vmw_ctx_binding_state *cbs,
797 int shader_slot)
798{
799 const struct vmw_ctx_bindinfo *loc =
800 &cbs->per_shader[shader_slot].shader_res[0].bi;
801 struct {
802 SVGA3dCmdHeader header;
803 SVGA3dCmdDXSetShaderResources body;
804 } *cmd;
805 size_t cmd_size, view_id_size;
806 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
807
808 vmw_collect_dirty_view_ids(cbs, loc,
809 cbs->per_shader[shader_slot].dirty_sr,
810 SVGA3D_DX_MAX_SRVIEWS);
811 if (cbs->bind_cmd_count == 0)
812 return 0;
813
814 view_id_size = cbs->bind_cmd_count*sizeof(uint32);
815 cmd_size = sizeof(*cmd) + view_id_size;
816 cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
817 if (unlikely(cmd == NULL))
818 return -ENOMEM;
819
820 cmd->header.id = SVGA_3D_CMD_DX_SET_SHADER_RESOURCES;
821 cmd->header.size = sizeof(cmd->body) + view_id_size;
822 cmd->body.type = shader_slot + SVGA3D_SHADERTYPE_MIN;
823 cmd->body.startView = cbs->bind_first_slot;
824
825 memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
826
827 vmw_cmd_commit(ctx->dev_priv, cmd_size);
828 bitmap_clear(cbs->per_shader[shader_slot].dirty_sr,
829 cbs->bind_first_slot, cbs->bind_cmd_count);
830
831 return 0;
832}
833
834
835
836
837
838
839static int vmw_emit_set_rt(struct vmw_ctx_binding_state *cbs)
840{
841 const struct vmw_ctx_bindinfo *loc = &cbs->render_targets[0].bi;
842 struct {
843 SVGA3dCmdHeader header;
844 SVGA3dCmdDXSetRenderTargets body;
845 } *cmd;
846 size_t cmd_size, view_id_size;
847 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
848
849 vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS);
850 view_id_size = cbs->bind_cmd_count*sizeof(uint32);
851 cmd_size = sizeof(*cmd) + view_id_size;
852 cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
853 if (unlikely(cmd == NULL))
854 return -ENOMEM;
855
856 cmd->header.id = SVGA_3D_CMD_DX_SET_RENDERTARGETS;
857 cmd->header.size = sizeof(cmd->body) + view_id_size;
858
859 if (cbs->ds_view.bi.ctx && !cbs->ds_view.bi.scrubbed)
860 cmd->body.depthStencilViewId = cbs->ds_view.bi.res->id;
861 else
862 cmd->body.depthStencilViewId = SVGA3D_INVALID_ID;
863
864 memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
865
866 vmw_cmd_commit(ctx->dev_priv, cmd_size);
867
868 return 0;
869
870}
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886static void vmw_collect_so_targets(struct vmw_ctx_binding_state *cbs,
887 const struct vmw_ctx_bindinfo *bi,
888 u32 max_num)
889{
890 const struct vmw_ctx_bindinfo_so_target *biso =
891 container_of(bi, struct vmw_ctx_bindinfo_so_target, bi);
892 unsigned long i;
893 SVGA3dSoTarget *so_buffer = (SVGA3dSoTarget *) cbs->bind_cmd_buffer;
894
895 cbs->bind_cmd_count = 0;
896 cbs->bind_first_slot = 0;
897
898 for (i = 0; i < max_num; ++i, ++biso, ++so_buffer,
899 ++cbs->bind_cmd_count) {
900 if (!biso->bi.ctx)
901 break;
902
903 if (!biso->bi.scrubbed) {
904 so_buffer->sid = biso->bi.res->id;
905 so_buffer->offset = biso->offset;
906 so_buffer->sizeInBytes = biso->size;
907 } else {
908 so_buffer->sid = SVGA3D_INVALID_ID;
909 so_buffer->offset = 0;
910 so_buffer->sizeInBytes = 0;
911 }
912 }
913}
914
915
916
917
918
919
920static int vmw_emit_set_so_target(struct vmw_ctx_binding_state *cbs)
921{
922 const struct vmw_ctx_bindinfo *loc = &cbs->so_targets[0].bi;
923 struct {
924 SVGA3dCmdHeader header;
925 SVGA3dCmdDXSetSOTargets body;
926 } *cmd;
927 size_t cmd_size, so_target_size;
928 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
929
930 vmw_collect_so_targets(cbs, loc, SVGA3D_DX_MAX_SOTARGETS);
931 if (cbs->bind_cmd_count == 0)
932 return 0;
933
934 so_target_size = cbs->bind_cmd_count*sizeof(SVGA3dSoTarget);
935 cmd_size = sizeof(*cmd) + so_target_size;
936 cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
937 if (unlikely(cmd == NULL))
938 return -ENOMEM;
939
940 cmd->header.id = SVGA_3D_CMD_DX_SET_SOTARGETS;
941 cmd->header.size = sizeof(cmd->body) + so_target_size;
942 memcpy(&cmd[1], cbs->bind_cmd_buffer, so_target_size);
943
944 vmw_cmd_commit(ctx->dev_priv, cmd_size);
945
946 return 0;
947
948}
949
950
951
952
953
954
955
956static int vmw_binding_emit_dirty_ps(struct vmw_ctx_binding_state *cbs)
957{
958 struct vmw_dx_shader_bindings *sb = &cbs->per_shader[0];
959 u32 i;
960 int ret;
961
962 for (i = 0; i < SVGA3D_NUM_SHADERTYPE_DX10; ++i, ++sb) {
963 if (!test_bit(VMW_BINDING_PS_SR_BIT, &sb->dirty))
964 continue;
965
966 ret = vmw_emit_set_sr(cbs, i);
967 if (ret)
968 break;
969
970 __clear_bit(VMW_BINDING_PS_SR_BIT, &sb->dirty);
971 }
972
973 return 0;
974}
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991static void vmw_collect_dirty_vbs(struct vmw_ctx_binding_state *cbs,
992 const struct vmw_ctx_bindinfo *bi,
993 unsigned long *dirty,
994 u32 max_num)
995{
996 const struct vmw_ctx_bindinfo_vb *biv =
997 container_of(bi, struct vmw_ctx_bindinfo_vb, bi);
998 unsigned long i, next_bit;
999 SVGA3dVertexBuffer *vbs = (SVGA3dVertexBuffer *) &cbs->bind_cmd_buffer;
1000
1001 cbs->bind_cmd_count = 0;
1002 i = find_first_bit(dirty, max_num);
1003 next_bit = i;
1004 cbs->bind_first_slot = i;
1005
1006 biv += i;
1007 for (; i < max_num; ++i, ++biv, ++vbs) {
1008 if (!biv->bi.ctx || biv->bi.scrubbed) {
1009 vbs->sid = SVGA3D_INVALID_ID;
1010 vbs->stride = 0;
1011 vbs->offset = 0;
1012 } else {
1013 vbs->sid = biv->bi.res->id;
1014 vbs->stride = biv->stride;
1015 vbs->offset = biv->offset;
1016 }
1017 cbs->bind_cmd_count++;
1018 if (next_bit == i) {
1019 next_bit = find_next_bit(dirty, max_num, i + 1);
1020 if (next_bit >= max_num)
1021 break;
1022 }
1023 }
1024}
1025
1026
1027
1028
1029
1030
1031
1032static int vmw_emit_set_vb(struct vmw_ctx_binding_state *cbs)
1033{
1034 const struct vmw_ctx_bindinfo *loc =
1035 &cbs->vertex_buffers[0].bi;
1036 struct {
1037 SVGA3dCmdHeader header;
1038 SVGA3dCmdDXSetVertexBuffers body;
1039 } *cmd;
1040 size_t cmd_size, set_vb_size;
1041 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
1042
1043 vmw_collect_dirty_vbs(cbs, loc, cbs->dirty_vb,
1044 SVGA3D_DX_MAX_VERTEXBUFFERS);
1045 if (cbs->bind_cmd_count == 0)
1046 return 0;
1047
1048 set_vb_size = cbs->bind_cmd_count*sizeof(SVGA3dVertexBuffer);
1049 cmd_size = sizeof(*cmd) + set_vb_size;
1050 cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
1051 if (unlikely(cmd == NULL))
1052 return -ENOMEM;
1053
1054 cmd->header.id = SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS;
1055 cmd->header.size = sizeof(cmd->body) + set_vb_size;
1056 cmd->body.startBuffer = cbs->bind_first_slot;
1057
1058 memcpy(&cmd[1], cbs->bind_cmd_buffer, set_vb_size);
1059
1060 vmw_cmd_commit(ctx->dev_priv, cmd_size);
1061 bitmap_clear(cbs->dirty_vb,
1062 cbs->bind_first_slot, cbs->bind_cmd_count);
1063
1064 return 0;
1065}
1066
1067static int vmw_emit_set_uav(struct vmw_ctx_binding_state *cbs)
1068{
1069 const struct vmw_ctx_bindinfo *loc = &cbs->ua_views[0].views[0].bi;
1070 struct {
1071 SVGA3dCmdHeader header;
1072 SVGA3dCmdDXSetUAViews body;
1073 } *cmd;
1074 size_t cmd_size, view_id_size;
1075 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
1076
1077 vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_UAVIEWS);
1078 view_id_size = cbs->bind_cmd_count*sizeof(uint32);
1079 cmd_size = sizeof(*cmd) + view_id_size;
1080 cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
1081 if (!cmd)
1082 return -ENOMEM;
1083
1084 cmd->header.id = SVGA_3D_CMD_DX_SET_UA_VIEWS;
1085 cmd->header.size = sizeof(cmd->body) + view_id_size;
1086
1087
1088 cmd->body.uavSpliceIndex = cbs->ua_views[0].index;
1089
1090 memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
1091
1092 vmw_cmd_commit(ctx->dev_priv, cmd_size);
1093
1094 return 0;
1095}
1096
1097static int vmw_emit_set_cs_uav(struct vmw_ctx_binding_state *cbs)
1098{
1099 const struct vmw_ctx_bindinfo *loc = &cbs->ua_views[1].views[0].bi;
1100 struct {
1101 SVGA3dCmdHeader header;
1102 SVGA3dCmdDXSetCSUAViews body;
1103 } *cmd;
1104 size_t cmd_size, view_id_size;
1105 const struct vmw_resource *ctx = vmw_cbs_context(cbs);
1106
1107 vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_UAVIEWS);
1108 view_id_size = cbs->bind_cmd_count*sizeof(uint32);
1109 cmd_size = sizeof(*cmd) + view_id_size;
1110 cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
1111 if (!cmd)
1112 return -ENOMEM;
1113
1114 cmd->header.id = SVGA_3D_CMD_DX_SET_CS_UA_VIEWS;
1115 cmd->header.size = sizeof(cmd->body) + view_id_size;
1116
1117
1118 cmd->body.startIndex = cbs->ua_views[1].index;
1119
1120 memcpy(&cmd[1], cbs->bind_cmd_buffer, view_id_size);
1121
1122 vmw_cmd_commit(ctx->dev_priv, cmd_size);
1123
1124 return 0;
1125}
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137static int vmw_binding_emit_dirty(struct vmw_ctx_binding_state *cbs)
1138{
1139 int ret = 0;
1140 unsigned long hit = 0;
1141
1142 while ((hit = find_next_bit(&cbs->dirty, VMW_BINDING_NUM_BITS, hit))
1143 < VMW_BINDING_NUM_BITS) {
1144
1145 switch (hit) {
1146 case VMW_BINDING_RT_BIT:
1147 ret = vmw_emit_set_rt(cbs);
1148 break;
1149 case VMW_BINDING_PS_BIT:
1150 ret = vmw_binding_emit_dirty_ps(cbs);
1151 break;
1152 case VMW_BINDING_SO_T_BIT:
1153 ret = vmw_emit_set_so_target(cbs);
1154 break;
1155 case VMW_BINDING_VB_BIT:
1156 ret = vmw_emit_set_vb(cbs);
1157 break;
1158 case VMW_BINDING_UAV_BIT:
1159 ret = vmw_emit_set_uav(cbs);
1160 break;
1161 case VMW_BINDING_CS_UAV_BIT:
1162 ret = vmw_emit_set_cs_uav(cbs);
1163 break;
1164 default:
1165 BUG();
1166 }
1167 if (ret)
1168 return ret;
1169
1170 __clear_bit(hit, &cbs->dirty);
1171 hit++;
1172 }
1173
1174 return 0;
1175}
1176
1177
1178
1179
1180
1181
1182
1183
1184static int vmw_binding_scrub_sr(struct vmw_ctx_bindinfo *bi, bool rebind)
1185{
1186 struct vmw_ctx_bindinfo_view *biv =
1187 container_of(bi, struct vmw_ctx_bindinfo_view, bi);
1188 struct vmw_ctx_binding_state *cbs =
1189 vmw_context_binding_state(bi->ctx);
1190
1191 __set_bit(biv->slot, cbs->per_shader[biv->shader_slot].dirty_sr);
1192 __set_bit(VMW_BINDING_PS_SR_BIT,
1193 &cbs->per_shader[biv->shader_slot].dirty);
1194 __set_bit(VMW_BINDING_PS_BIT, &cbs->dirty);
1195
1196 return 0;
1197}
1198
1199
1200
1201
1202
1203
1204
1205
1206static int vmw_binding_scrub_dx_rt(struct vmw_ctx_bindinfo *bi, bool rebind)
1207{
1208 struct vmw_ctx_binding_state *cbs =
1209 vmw_context_binding_state(bi->ctx);
1210
1211 __set_bit(VMW_BINDING_RT_BIT, &cbs->dirty);
1212
1213 return 0;
1214}
1215
1216
1217
1218
1219
1220
1221
1222
1223static int vmw_binding_scrub_so_target(struct vmw_ctx_bindinfo *bi, bool rebind)
1224{
1225 struct vmw_ctx_binding_state *cbs =
1226 vmw_context_binding_state(bi->ctx);
1227
1228 __set_bit(VMW_BINDING_SO_T_BIT, &cbs->dirty);
1229
1230 return 0;
1231}
1232
1233
1234
1235
1236
1237
1238
1239
1240static int vmw_binding_scrub_vb(struct vmw_ctx_bindinfo *bi, bool rebind)
1241{
1242 struct vmw_ctx_bindinfo_vb *bivb =
1243 container_of(bi, struct vmw_ctx_bindinfo_vb, bi);
1244 struct vmw_ctx_binding_state *cbs =
1245 vmw_context_binding_state(bi->ctx);
1246
1247 __set_bit(bivb->slot, cbs->dirty_vb);
1248 __set_bit(VMW_BINDING_VB_BIT, &cbs->dirty);
1249
1250 return 0;
1251}
1252
1253
1254
1255
1256
1257
1258
1259static int vmw_binding_scrub_ib(struct vmw_ctx_bindinfo *bi, bool rebind)
1260{
1261 struct vmw_ctx_bindinfo_ib *binding =
1262 container_of(bi, typeof(*binding), bi);
1263 struct vmw_private *dev_priv = bi->ctx->dev_priv;
1264 struct {
1265 SVGA3dCmdHeader header;
1266 SVGA3dCmdDXSetIndexBuffer body;
1267 } *cmd;
1268
1269 cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);
1270 if (unlikely(cmd == NULL))
1271 return -ENOMEM;
1272
1273 cmd->header.id = SVGA_3D_CMD_DX_SET_INDEX_BUFFER;
1274 cmd->header.size = sizeof(cmd->body);
1275 if (rebind) {
1276 cmd->body.sid = bi->res->id;
1277 cmd->body.format = binding->format;
1278 cmd->body.offset = binding->offset;
1279 } else {
1280 cmd->body.sid = SVGA3D_INVALID_ID;
1281 cmd->body.format = 0;
1282 cmd->body.offset = 0;
1283 }
1284
1285 vmw_cmd_commit(dev_priv, sizeof(*cmd));
1286
1287 return 0;
1288}
1289
1290static int vmw_binding_scrub_uav(struct vmw_ctx_bindinfo *bi, bool rebind)
1291{
1292 struct vmw_ctx_binding_state *cbs = vmw_context_binding_state(bi->ctx);
1293
1294 __set_bit(VMW_BINDING_UAV_BIT, &cbs->dirty);
1295 return 0;
1296}
1297
1298static int vmw_binding_scrub_cs_uav(struct vmw_ctx_bindinfo *bi, bool rebind)
1299{
1300 struct vmw_ctx_binding_state *cbs = vmw_context_binding_state(bi->ctx);
1301
1302 __set_bit(VMW_BINDING_CS_UAV_BIT, &cbs->dirty);
1303 return 0;
1304}
1305
1306
1307
1308
1309
1310
1311static int vmw_binding_scrub_so(struct vmw_ctx_bindinfo *bi, bool rebind)
1312{
1313 struct vmw_ctx_bindinfo_so *binding =
1314 container_of(bi, typeof(*binding), bi);
1315 struct vmw_private *dev_priv = bi->ctx->dev_priv;
1316 struct {
1317 SVGA3dCmdHeader header;
1318 SVGA3dCmdDXSetStreamOutput body;
1319 } *cmd;
1320
1321 cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), bi->ctx->id);
1322 if (!cmd)
1323 return -ENOMEM;
1324
1325 cmd->header.id = SVGA_3D_CMD_DX_SET_STREAMOUTPUT;
1326 cmd->header.size = sizeof(cmd->body);
1327 cmd->body.soid = rebind ? bi->res->id : SVGA3D_INVALID_ID;
1328 vmw_cmd_commit(dev_priv, sizeof(*cmd));
1329
1330 return 0;
1331}
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341struct vmw_ctx_binding_state *
1342vmw_binding_state_alloc(struct vmw_private *dev_priv)
1343{
1344 struct vmw_ctx_binding_state *cbs;
1345 struct ttm_operation_ctx ctx = {
1346 .interruptible = false,
1347 .no_wait_gpu = false
1348 };
1349 int ret;
1350
1351 ret = ttm_mem_global_alloc(vmw_mem_glob(dev_priv), sizeof(*cbs),
1352 &ctx);
1353 if (ret)
1354 return ERR_PTR(ret);
1355
1356 cbs = vzalloc(sizeof(*cbs));
1357 if (!cbs) {
1358 ttm_mem_global_free(vmw_mem_glob(dev_priv), sizeof(*cbs));
1359 return ERR_PTR(-ENOMEM);
1360 }
1361
1362 cbs->dev_priv = dev_priv;
1363 INIT_LIST_HEAD(&cbs->list);
1364
1365 return cbs;
1366}
1367
1368
1369
1370
1371
1372
1373
1374void vmw_binding_state_free(struct vmw_ctx_binding_state *cbs)
1375{
1376 struct vmw_private *dev_priv = cbs->dev_priv;
1377
1378 vfree(cbs);
1379 ttm_mem_global_free(vmw_mem_glob(dev_priv), sizeof(*cbs));
1380}
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391struct list_head *vmw_binding_state_list(struct vmw_ctx_binding_state *cbs)
1392{
1393 return &cbs->list;
1394}
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404void vmw_binding_state_reset(struct vmw_ctx_binding_state *cbs)
1405{
1406 struct vmw_ctx_bindinfo *entry, *next;
1407
1408 list_for_each_entry_safe(entry, next, &cbs->list, ctx_list)
1409 vmw_binding_drop(entry);
1410}
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424u32 vmw_binding_dirtying(enum vmw_ctx_binding_type binding_type)
1425{
1426 static u32 is_binding_dirtying[vmw_ctx_binding_max] = {
1427 [vmw_ctx_binding_rt] = VMW_RES_DIRTY_SET,
1428 [vmw_ctx_binding_dx_rt] = VMW_RES_DIRTY_SET,
1429 [vmw_ctx_binding_ds] = VMW_RES_DIRTY_SET,
1430 [vmw_ctx_binding_so_target] = VMW_RES_DIRTY_SET,
1431 [vmw_ctx_binding_uav] = VMW_RES_DIRTY_SET,
1432 [vmw_ctx_binding_cs_uav] = VMW_RES_DIRTY_SET,
1433 };
1434
1435
1436 BUILD_BUG_ON(vmw_ctx_binding_max != 14);
1437 return is_binding_dirtying[binding_type];
1438}
1439
1440
1441
1442
1443
1444static void vmw_binding_build_asserts(void)
1445{
1446 BUILD_BUG_ON(SVGA3D_NUM_SHADERTYPE_DX10 != 3);
1447 BUILD_BUG_ON(SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS > SVGA3D_RT_MAX);
1448 BUILD_BUG_ON(sizeof(uint32) != sizeof(u32));
1449
1450
1451
1452
1453
1454 BUILD_BUG_ON(VMW_MAX_VIEW_BINDINGS < SVGA3D_RT_MAX);
1455 BUILD_BUG_ON(VMW_MAX_VIEW_BINDINGS < SVGA3D_DX_MAX_SRVIEWS);
1456 BUILD_BUG_ON(VMW_MAX_VIEW_BINDINGS < SVGA3D_DX_MAX_CONSTBUFFERS);
1457
1458
1459
1460
1461
1462 BUILD_BUG_ON(SVGA3D_DX_MAX_SOTARGETS*sizeof(SVGA3dSoTarget) >
1463 VMW_MAX_VIEW_BINDINGS*sizeof(u32));
1464 BUILD_BUG_ON(SVGA3D_DX_MAX_VERTEXBUFFERS*sizeof(SVGA3dVertexBuffer) >
1465 VMW_MAX_VIEW_BINDINGS*sizeof(u32));
1466}
1467