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11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/errno.h>
14#include <linux/export.h>
15#include <linux/gpio/consumer.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
22#include <linux/reset.h>
23
24#include "i2c-designware-core.h"
25
26#define AMD_TIMEOUT_MIN_US 25
27#define AMD_TIMEOUT_MAX_US 250
28#define AMD_MASTERCFG_MASK GENMASK(15, 0)
29
30static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
31{
32
33 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
34 regmap_write(dev->map, DW_IC_RX_TL, 0);
35
36
37 regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
38}
39
40static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
41{
42 u32 comp_param1;
43 u32 sda_falling_time, scl_falling_time;
44 struct i2c_timings *t = &dev->timings;
45 const char *fp_str = "";
46 u32 ic_clk;
47 int ret;
48
49 ret = i2c_dw_acquire_lock(dev);
50 if (ret)
51 return ret;
52
53 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
54 i2c_dw_release_lock(dev);
55 if (ret)
56 return ret;
57
58
59 sda_falling_time = t->sda_fall_ns ?: 300;
60 scl_falling_time = t->scl_fall_ns ?: 300;
61
62
63 if (!dev->ss_hcnt || !dev->ss_lcnt) {
64 ic_clk = i2c_dw_clk_rate(dev);
65 dev->ss_hcnt =
66 i2c_dw_scl_hcnt(ic_clk,
67 4000,
68 sda_falling_time,
69 0,
70 0);
71 dev->ss_lcnt =
72 i2c_dw_scl_lcnt(ic_clk,
73 4700,
74 scl_falling_time,
75 0);
76 }
77 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
78 dev->ss_hcnt, dev->ss_lcnt);
79
80
81
82
83
84
85 if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) {
86
87
88
89
90 if (dev->fp_hcnt && dev->fp_lcnt) {
91 dev->fs_hcnt = dev->fp_hcnt;
92 dev->fs_lcnt = dev->fp_lcnt;
93 } else {
94 ic_clk = i2c_dw_clk_rate(dev);
95 dev->fs_hcnt =
96 i2c_dw_scl_hcnt(ic_clk,
97 260,
98 sda_falling_time,
99 0,
100 0);
101 dev->fs_lcnt =
102 i2c_dw_scl_lcnt(ic_clk,
103 500,
104 scl_falling_time,
105 0);
106 }
107 fp_str = " Plus";
108 }
109
110
111
112
113 if (!dev->fs_hcnt || !dev->fs_lcnt) {
114 ic_clk = i2c_dw_clk_rate(dev);
115 dev->fs_hcnt =
116 i2c_dw_scl_hcnt(ic_clk,
117 600,
118 sda_falling_time,
119 0,
120 0);
121 dev->fs_lcnt =
122 i2c_dw_scl_lcnt(ic_clk,
123 1300,
124 scl_falling_time,
125 0);
126 }
127 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
128 fp_str, dev->fs_hcnt, dev->fs_lcnt);
129
130
131 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
132 DW_IC_CON_SPEED_HIGH) {
133 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
134 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
135 dev_err(dev->dev, "High Speed not supported!\n");
136 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
137 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
138 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
139 dev->hs_hcnt = 0;
140 dev->hs_lcnt = 0;
141 } else if (!dev->hs_hcnt || !dev->hs_lcnt) {
142 ic_clk = i2c_dw_clk_rate(dev);
143 dev->hs_hcnt =
144 i2c_dw_scl_hcnt(ic_clk,
145 160,
146 sda_falling_time,
147 0,
148 0);
149 dev->hs_lcnt =
150 i2c_dw_scl_lcnt(ic_clk,
151 320,
152 scl_falling_time,
153 0);
154 }
155 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
156 dev->hs_hcnt, dev->hs_lcnt);
157 }
158
159 ret = i2c_dw_set_sda_hold(dev);
160 if (ret)
161 return ret;
162
163 dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz));
164 return 0;
165}
166
167
168
169
170
171
172
173
174
175static int i2c_dw_init_master(struct dw_i2c_dev *dev)
176{
177 int ret;
178
179 ret = i2c_dw_acquire_lock(dev);
180 if (ret)
181 return ret;
182
183
184 __i2c_dw_disable(dev);
185
186
187 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
188 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
189
190
191 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
192 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
193
194
195 if (dev->hs_hcnt && dev->hs_lcnt) {
196 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
197 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
198 }
199
200
201 if (dev->sda_hold_time)
202 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
203
204 i2c_dw_configure_fifo_master(dev);
205 i2c_dw_release_lock(dev);
206
207 return 0;
208}
209
210static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
211{
212 struct i2c_msg *msgs = dev->msgs;
213 u32 ic_con = 0, ic_tar = 0;
214 u32 dummy;
215
216
217 __i2c_dw_disable(dev);
218
219
220 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
221 ic_con = DW_IC_CON_10BITADDR_MASTER;
222
223
224
225
226
227
228 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
229 }
230
231 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
232 ic_con);
233
234
235
236
237
238 regmap_write(dev->map, DW_IC_TAR,
239 msgs[dev->msg_write_idx].addr | ic_tar);
240
241
242 i2c_dw_disable_int(dev);
243
244
245 __i2c_dw_enable(dev);
246
247
248 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
249
250
251 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
252 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
253}
254
255static int i2c_dw_check_stopbit(struct dw_i2c_dev *dev)
256{
257 u32 val;
258 int ret;
259
260 ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val,
261 !(val & DW_IC_INTR_STOP_DET),
262 1100, 20000);
263 if (ret)
264 dev_err(dev->dev, "i2c timeout error %d\n", ret);
265
266 return ret;
267}
268
269static int i2c_dw_status(struct dw_i2c_dev *dev)
270{
271 int status;
272
273 status = i2c_dw_wait_bus_not_busy(dev);
274 if (status)
275 return status;
276
277 return i2c_dw_check_stopbit(dev);
278}
279
280
281
282
283
284static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs)
285{
286 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
287 int msg_wrt_idx, msg_itr_lmt, buf_len, data_idx;
288 int cmd = 0, status;
289 u8 *tx_buf;
290 u32 val;
291
292
293
294
295
296
297 regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN);
298
299 dev->msgs = msgs;
300 dev->msgs_num = num_msgs;
301 i2c_dw_xfer_init(dev);
302 i2c_dw_disable_int(dev);
303
304
305 for (msg_wrt_idx = 0; msg_wrt_idx < num_msgs; msg_wrt_idx++) {
306 tx_buf = msgs[msg_wrt_idx].buf;
307 buf_len = msgs[msg_wrt_idx].len;
308
309 if (!(msgs[msg_wrt_idx].flags & I2C_M_RD))
310 regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1);
311
312
313
314
315
316 for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) {
317 if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1)
318 cmd |= BIT(9);
319
320 if (msgs[msg_wrt_idx].flags & I2C_M_RD) {
321
322 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100);
323 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd);
324 if (cmd) {
325 regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1));
326 regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1));
327
328
329
330
331
332 status = i2c_dw_status(dev);
333 if (status)
334 return status;
335
336 for (data_idx = 0; data_idx < buf_len; data_idx++) {
337 regmap_read(dev->map, DW_IC_DATA_CMD, &val);
338 tx_buf[data_idx] = val;
339 }
340 status = i2c_dw_check_stopbit(dev);
341 if (status)
342 return status;
343 }
344 } else {
345 regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd);
346 usleep_range(AMD_TIMEOUT_MIN_US, AMD_TIMEOUT_MAX_US);
347 }
348 }
349 status = i2c_dw_check_stopbit(dev);
350 if (status)
351 return status;
352 }
353
354 return 0;
355}
356
357
358
359
360
361
362
363static void
364i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
365{
366 struct i2c_msg *msgs = dev->msgs;
367 u32 intr_mask;
368 int tx_limit, rx_limit;
369 u32 addr = msgs[dev->msg_write_idx].addr;
370 u32 buf_len = dev->tx_buf_len;
371 u8 *buf = dev->tx_buf;
372 bool need_restart = false;
373 unsigned int flr;
374
375 intr_mask = DW_IC_INTR_MASTER_MASK;
376
377 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
378 u32 flags = msgs[dev->msg_write_idx].flags;
379
380
381
382
383
384
385 if (msgs[dev->msg_write_idx].addr != addr) {
386 dev_err(dev->dev,
387 "%s: invalid target address\n", __func__);
388 dev->msg_err = -EINVAL;
389 break;
390 }
391
392 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
393
394 buf = msgs[dev->msg_write_idx].buf;
395 buf_len = msgs[dev->msg_write_idx].len;
396
397
398
399
400
401 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
402 (dev->msg_write_idx > 0))
403 need_restart = true;
404 }
405
406 regmap_read(dev->map, DW_IC_TXFLR, &flr);
407 tx_limit = dev->tx_fifo_depth - flr;
408
409 regmap_read(dev->map, DW_IC_RXFLR, &flr);
410 rx_limit = dev->rx_fifo_depth - flr;
411
412 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
413 u32 cmd = 0;
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428 if (dev->msg_write_idx == dev->msgs_num - 1 &&
429 buf_len == 1 && !(flags & I2C_M_RECV_LEN))
430 cmd |= BIT(9);
431
432 if (need_restart) {
433 cmd |= BIT(10);
434 need_restart = false;
435 }
436
437 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
438
439
440 if (dev->rx_outstanding >= dev->rx_fifo_depth)
441 break;
442
443 regmap_write(dev->map, DW_IC_DATA_CMD,
444 cmd | 0x100);
445 rx_limit--;
446 dev->rx_outstanding++;
447 } else {
448 regmap_write(dev->map, DW_IC_DATA_CMD,
449 cmd | *buf++);
450 }
451 tx_limit--; buf_len--;
452 }
453
454 dev->tx_buf = buf;
455 dev->tx_buf_len = buf_len;
456
457
458
459
460
461
462 if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
463
464 dev->status |= STATUS_WRITE_IN_PROGRESS;
465 break;
466 } else
467 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
468 }
469
470
471
472
473
474 if (dev->msg_write_idx == dev->msgs_num)
475 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
476
477 if (dev->msg_err)
478 intr_mask = 0;
479
480 regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask);
481}
482
483static u8
484i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
485{
486 struct i2c_msg *msgs = dev->msgs;
487 u32 flags = msgs[dev->msg_read_idx].flags;
488
489
490
491
492
493 len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
494 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
495 msgs[dev->msg_read_idx].len = len;
496 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
497
498 return len;
499}
500
501static void
502i2c_dw_read(struct dw_i2c_dev *dev)
503{
504 struct i2c_msg *msgs = dev->msgs;
505 unsigned int rx_valid;
506
507 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
508 u32 len, tmp;
509 u8 *buf;
510
511 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
512 continue;
513
514 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
515 len = msgs[dev->msg_read_idx].len;
516 buf = msgs[dev->msg_read_idx].buf;
517 } else {
518 len = dev->rx_buf_len;
519 buf = dev->rx_buf;
520 }
521
522 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
523
524 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
525 u32 flags = msgs[dev->msg_read_idx].flags;
526
527 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
528
529 if (flags & I2C_M_RECV_LEN &&
530 (tmp & DW_IC_DATA_CMD_DAT) <= I2C_SMBUS_BLOCK_MAX && tmp > 0) {
531 len = i2c_dw_recv_len(dev, tmp);
532 }
533 *buf++ = tmp;
534 dev->rx_outstanding--;
535 }
536
537 if (len > 0) {
538 dev->status |= STATUS_READ_IN_PROGRESS;
539 dev->rx_buf_len = len;
540 dev->rx_buf = buf;
541 return;
542 } else
543 dev->status &= ~STATUS_READ_IN_PROGRESS;
544 }
545}
546
547
548
549
550static int
551i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
552{
553 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
554 int ret;
555
556 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
557
558 pm_runtime_get_sync(dev->dev);
559
560
561
562
563
564
565 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) {
566 ret = amd_i2c_dw_xfer_quirk(adap, msgs, num);
567 goto done_nolock;
568 }
569
570 if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) {
571 ret = -ESHUTDOWN;
572 goto done_nolock;
573 }
574
575 reinit_completion(&dev->cmd_complete);
576 dev->msgs = msgs;
577 dev->msgs_num = num;
578 dev->cmd_err = 0;
579 dev->msg_write_idx = 0;
580 dev->msg_read_idx = 0;
581 dev->msg_err = 0;
582 dev->status = STATUS_IDLE;
583 dev->abort_source = 0;
584 dev->rx_outstanding = 0;
585
586 ret = i2c_dw_acquire_lock(dev);
587 if (ret)
588 goto done_nolock;
589
590 ret = i2c_dw_wait_bus_not_busy(dev);
591 if (ret < 0)
592 goto done;
593
594
595 i2c_dw_xfer_init(dev);
596
597
598 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
599 dev_err(dev->dev, "controller timed out\n");
600
601 i2c_recover_bus(&dev->adapter);
602 i2c_dw_init_master(dev);
603 ret = -ETIMEDOUT;
604 goto done;
605 }
606
607
608
609
610
611
612
613
614
615 __i2c_dw_disable_nowait(dev);
616
617 if (dev->msg_err) {
618 ret = dev->msg_err;
619 goto done;
620 }
621
622
623 if (likely(!dev->cmd_err && !dev->status)) {
624 ret = num;
625 goto done;
626 }
627
628
629 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
630 ret = i2c_dw_handle_tx_abort(dev);
631 goto done;
632 }
633
634 if (dev->status)
635 dev_err(dev->dev,
636 "transfer terminated early - interrupt latency too high?\n");
637
638 ret = -EIO;
639
640done:
641 i2c_dw_release_lock(dev);
642
643done_nolock:
644 pm_runtime_mark_last_busy(dev->dev);
645 pm_runtime_put_autosuspend(dev->dev);
646
647 return ret;
648}
649
650static const struct i2c_algorithm i2c_dw_algo = {
651 .master_xfer = i2c_dw_xfer,
652 .functionality = i2c_dw_func,
653};
654
655static const struct i2c_adapter_quirks i2c_dw_quirks = {
656 .flags = I2C_AQ_NO_ZERO_LEN,
657};
658
659static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
660{
661 u32 stat, dummy;
662
663
664
665
666
667
668
669
670
671
672
673
674
675 regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
676
677
678
679
680
681
682
683
684 if (stat & DW_IC_INTR_RX_UNDER)
685 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
686 if (stat & DW_IC_INTR_RX_OVER)
687 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
688 if (stat & DW_IC_INTR_TX_OVER)
689 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
690 if (stat & DW_IC_INTR_RD_REQ)
691 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
692 if (stat & DW_IC_INTR_TX_ABRT) {
693
694
695
696
697 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
698 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
699 }
700 if (stat & DW_IC_INTR_RX_DONE)
701 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
702 if (stat & DW_IC_INTR_ACTIVITY)
703 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
704 if (stat & DW_IC_INTR_STOP_DET)
705 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
706 if (stat & DW_IC_INTR_START_DET)
707 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
708 if (stat & DW_IC_INTR_GEN_CALL)
709 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
710
711 return stat;
712}
713
714
715
716
717
718static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
719{
720 u32 stat;
721
722 stat = i2c_dw_read_clear_intrbits(dev);
723 if (stat & DW_IC_INTR_TX_ABRT) {
724 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
725 dev->status = STATUS_IDLE;
726
727
728
729
730
731 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
732 goto tx_aborted;
733 }
734
735 if (stat & DW_IC_INTR_RX_FULL)
736 i2c_dw_read(dev);
737
738 if (stat & DW_IC_INTR_TX_EMPTY)
739 i2c_dw_xfer_msg(dev);
740
741
742
743
744
745
746
747tx_aborted:
748 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
749 complete(&dev->cmd_complete);
750 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
751
752 regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
753 i2c_dw_disable_int(dev);
754 regmap_write(dev->map, DW_IC_INTR_MASK, stat);
755 }
756
757 return 0;
758}
759
760static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
761{
762 struct dw_i2c_dev *dev = dev_id;
763 u32 stat, enabled;
764
765 regmap_read(dev->map, DW_IC_ENABLE, &enabled);
766 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
767 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
768 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
769 return IRQ_NONE;
770
771 i2c_dw_irq_handler_master(dev);
772
773 return IRQ_HANDLED;
774}
775
776void i2c_dw_configure_master(struct dw_i2c_dev *dev)
777{
778 struct i2c_timings *t = &dev->timings;
779
780 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
781
782 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
783 DW_IC_CON_RESTART_EN;
784
785 dev->mode = DW_IC_MASTER;
786
787 switch (t->bus_freq_hz) {
788 case I2C_MAX_STANDARD_MODE_FREQ:
789 dev->master_cfg |= DW_IC_CON_SPEED_STD;
790 break;
791 case I2C_MAX_HIGH_SPEED_MODE_FREQ:
792 dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
793 break;
794 default:
795 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
796 }
797}
798EXPORT_SYMBOL_GPL(i2c_dw_configure_master);
799
800static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
801{
802 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
803
804 i2c_dw_disable(dev);
805 reset_control_assert(dev->rst);
806 i2c_dw_prepare_clk(dev, false);
807}
808
809static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
810{
811 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
812
813 i2c_dw_prepare_clk(dev, true);
814 reset_control_deassert(dev->rst);
815 i2c_dw_init_master(dev);
816}
817
818static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
819{
820 struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
821 struct i2c_adapter *adap = &dev->adapter;
822 struct gpio_desc *gpio;
823
824 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
825 if (IS_ERR_OR_NULL(gpio))
826 return PTR_ERR_OR_ZERO(gpio);
827
828 rinfo->scl_gpiod = gpio;
829
830 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
831 if (IS_ERR(gpio))
832 return PTR_ERR(gpio);
833 rinfo->sda_gpiod = gpio;
834
835 rinfo->recover_bus = i2c_generic_scl_recovery;
836 rinfo->prepare_recovery = i2c_dw_prepare_recovery;
837 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
838 adap->bus_recovery_info = rinfo;
839
840 dev_info(dev->dev, "running with gpio recovery mode! scl%s",
841 rinfo->sda_gpiod ? ",sda" : "");
842
843 return 0;
844}
845
846static int amd_i2c_adap_quirk(struct dw_i2c_dev *dev)
847{
848 struct i2c_adapter *adap = &dev->adapter;
849 int ret;
850
851 pm_runtime_get_noresume(dev->dev);
852 ret = i2c_add_numbered_adapter(adap);
853 if (ret)
854 dev_err(dev->dev, "Failed to add adapter: %d\n", ret);
855 pm_runtime_put_noidle(dev->dev);
856
857 return ret;
858}
859
860int i2c_dw_probe_master(struct dw_i2c_dev *dev)
861{
862 struct i2c_adapter *adap = &dev->adapter;
863 unsigned long irq_flags;
864 int ret;
865
866 init_completion(&dev->cmd_complete);
867
868 dev->init = i2c_dw_init_master;
869 dev->disable = i2c_dw_disable;
870 dev->disable_int = i2c_dw_disable_int;
871
872 ret = i2c_dw_init_regmap(dev);
873 if (ret)
874 return ret;
875
876 ret = i2c_dw_set_timings_master(dev);
877 if (ret)
878 return ret;
879
880 ret = i2c_dw_set_fifo_size(dev);
881 if (ret)
882 return ret;
883
884 ret = dev->init(dev);
885 if (ret)
886 return ret;
887
888 snprintf(adap->name, sizeof(adap->name),
889 "Synopsys DesignWare I2C adapter");
890 adap->retries = 3;
891 adap->algo = &i2c_dw_algo;
892 adap->quirks = &i2c_dw_quirks;
893 adap->dev.parent = dev->dev;
894 i2c_set_adapdata(adap, dev);
895
896 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU)
897 return amd_i2c_adap_quirk(dev);
898
899 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
900 irq_flags = IRQF_NO_SUSPEND;
901 } else {
902 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
903 }
904
905 i2c_dw_disable_int(dev);
906 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
907 dev_name(dev->dev), dev);
908 if (ret) {
909 dev_err(dev->dev, "failure requesting irq %i: %d\n",
910 dev->irq, ret);
911 return ret;
912 }
913
914 ret = i2c_dw_init_recovery_info(dev);
915 if (ret)
916 return ret;
917
918
919
920
921
922
923
924 pm_runtime_get_noresume(dev->dev);
925 ret = i2c_add_numbered_adapter(adap);
926 if (ret)
927 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
928 pm_runtime_put_noidle(dev->dev);
929
930 return ret;
931}
932EXPORT_SYMBOL_GPL(i2c_dw_probe_master);
933
934MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
935MODULE_LICENSE("GPL");
936