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17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/i2c.h>
21#include <linux/i2c-smbus.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/iopoll.h>
25#include <linux/mfd/syscon.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/of_address.h>
29#include <linux/of_platform.h>
30#include <linux/platform_device.h>
31#include <linux/pinctrl/consumer.h>
32#include <linux/pm_runtime.h>
33#include <linux/pm_wakeirq.h>
34#include <linux/regmap.h>
35#include <linux/reset.h>
36#include <linux/slab.h>
37
38#include "i2c-stm32.h"
39
40
41#define STM32F7_I2C_CR1 0x00
42#define STM32F7_I2C_CR2 0x04
43#define STM32F7_I2C_OAR1 0x08
44#define STM32F7_I2C_OAR2 0x0C
45#define STM32F7_I2C_PECR 0x20
46#define STM32F7_I2C_TIMINGR 0x10
47#define STM32F7_I2C_ISR 0x18
48#define STM32F7_I2C_ICR 0x1C
49#define STM32F7_I2C_RXDR 0x24
50#define STM32F7_I2C_TXDR 0x28
51
52
53#define STM32F7_I2C_CR1_PECEN BIT(23)
54#define STM32F7_I2C_CR1_ALERTEN BIT(22)
55#define STM32F7_I2C_CR1_SMBHEN BIT(20)
56#define STM32F7_I2C_CR1_WUPEN BIT(18)
57#define STM32F7_I2C_CR1_SBC BIT(16)
58#define STM32F7_I2C_CR1_RXDMAEN BIT(15)
59#define STM32F7_I2C_CR1_TXDMAEN BIT(14)
60#define STM32F7_I2C_CR1_ANFOFF BIT(12)
61#define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
62#define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
63#define STM32F7_I2C_CR1_ERRIE BIT(7)
64#define STM32F7_I2C_CR1_TCIE BIT(6)
65#define STM32F7_I2C_CR1_STOPIE BIT(5)
66#define STM32F7_I2C_CR1_NACKIE BIT(4)
67#define STM32F7_I2C_CR1_ADDRIE BIT(3)
68#define STM32F7_I2C_CR1_RXIE BIT(2)
69#define STM32F7_I2C_CR1_TXIE BIT(1)
70#define STM32F7_I2C_CR1_PE BIT(0)
71#define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
72 | STM32F7_I2C_CR1_TCIE \
73 | STM32F7_I2C_CR1_STOPIE \
74 | STM32F7_I2C_CR1_NACKIE \
75 | STM32F7_I2C_CR1_RXIE \
76 | STM32F7_I2C_CR1_TXIE)
77#define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
78 | STM32F7_I2C_CR1_STOPIE \
79 | STM32F7_I2C_CR1_NACKIE \
80 | STM32F7_I2C_CR1_RXIE \
81 | STM32F7_I2C_CR1_TXIE)
82
83
84#define STM32F7_I2C_CR2_PECBYTE BIT(26)
85#define STM32F7_I2C_CR2_RELOAD BIT(24)
86#define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
87#define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
88#define STM32F7_I2C_CR2_NACK BIT(15)
89#define STM32F7_I2C_CR2_STOP BIT(14)
90#define STM32F7_I2C_CR2_START BIT(13)
91#define STM32F7_I2C_CR2_HEAD10R BIT(12)
92#define STM32F7_I2C_CR2_ADD10 BIT(11)
93#define STM32F7_I2C_CR2_RD_WRN BIT(10)
94#define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
95#define STM32F7_I2C_CR2_SADD10(n) (((n) & \
96 STM32F7_I2C_CR2_SADD10_MASK))
97#define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
98#define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
99
100
101#define STM32F7_I2C_OAR1_OA1EN BIT(15)
102#define STM32F7_I2C_OAR1_OA1MODE BIT(10)
103#define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
104#define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
105 STM32F7_I2C_OAR1_OA1_10_MASK))
106#define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
107#define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
108#define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
109 | STM32F7_I2C_OAR1_OA1_10_MASK \
110 | STM32F7_I2C_OAR1_OA1EN \
111 | STM32F7_I2C_OAR1_OA1MODE)
112
113
114#define STM32F7_I2C_OAR2_OA2EN BIT(15)
115#define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
116#define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
117#define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
118#define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
119#define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
120 | STM32F7_I2C_OAR2_OA2_7_MASK \
121 | STM32F7_I2C_OAR2_OA2EN)
122
123
124#define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
125#define STM32F7_I2C_ISR_ADDCODE_GET(n) \
126 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
127#define STM32F7_I2C_ISR_DIR BIT(16)
128#define STM32F7_I2C_ISR_BUSY BIT(15)
129#define STM32F7_I2C_ISR_ALERT BIT(13)
130#define STM32F7_I2C_ISR_PECERR BIT(11)
131#define STM32F7_I2C_ISR_ARLO BIT(9)
132#define STM32F7_I2C_ISR_BERR BIT(8)
133#define STM32F7_I2C_ISR_TCR BIT(7)
134#define STM32F7_I2C_ISR_TC BIT(6)
135#define STM32F7_I2C_ISR_STOPF BIT(5)
136#define STM32F7_I2C_ISR_NACKF BIT(4)
137#define STM32F7_I2C_ISR_ADDR BIT(3)
138#define STM32F7_I2C_ISR_RXNE BIT(2)
139#define STM32F7_I2C_ISR_TXIS BIT(1)
140#define STM32F7_I2C_ISR_TXE BIT(0)
141
142
143#define STM32F7_I2C_ICR_ALERTCF BIT(13)
144#define STM32F7_I2C_ICR_PECCF BIT(11)
145#define STM32F7_I2C_ICR_ARLOCF BIT(9)
146#define STM32F7_I2C_ICR_BERRCF BIT(8)
147#define STM32F7_I2C_ICR_STOPCF BIT(5)
148#define STM32F7_I2C_ICR_NACKCF BIT(4)
149#define STM32F7_I2C_ICR_ADDRCF BIT(3)
150
151
152#define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
153#define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
154#define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
155#define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
156#define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
157
158#define STM32F7_I2C_MAX_LEN 0xff
159#define STM32F7_I2C_DMA_LEN_MIN 0x16
160enum {
161 STM32F7_SLAVE_HOSTNOTIFY,
162 STM32F7_SLAVE_7_10_BITS_ADDR,
163 STM32F7_SLAVE_7_BITS_ADDR,
164 STM32F7_I2C_MAX_SLAVE
165};
166
167#define STM32F7_I2C_DNF_DEFAULT 0
168#define STM32F7_I2C_DNF_MAX 15
169
170#define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50
171#define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260
172
173#define STM32F7_I2C_RISE_TIME_DEFAULT 25
174#define STM32F7_I2C_FALL_TIME_DEFAULT 10
175
176#define STM32F7_PRESC_MAX BIT(4)
177#define STM32F7_SCLDEL_MAX BIT(4)
178#define STM32F7_SDADEL_MAX BIT(4)
179#define STM32F7_SCLH_MAX BIT(8)
180#define STM32F7_SCLL_MAX BIT(8)
181
182#define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
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191
192struct stm32f7_i2c_regs {
193 u32 cr1;
194 u32 cr2;
195 u32 oar1;
196 u32 oar2;
197 u32 tmgr;
198};
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211struct stm32f7_i2c_spec {
212 u32 rate;
213 u32 fall_max;
214 u32 rise_max;
215 u32 hddat_min;
216 u32 vddat_max;
217 u32 sudat_min;
218 u32 l_min;
219 u32 h_min;
220};
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230struct stm32f7_i2c_setup {
231 u32 speed_freq;
232 u32 clock_src;
233 u32 rise_time;
234 u32 fall_time;
235 u32 fmp_clr_offset;
236};
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247struct stm32f7_i2c_timings {
248 struct list_head node;
249 u8 presc;
250 u8 scldel;
251 u8 sdadel;
252 u8 sclh;
253 u8 scll;
254};
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272struct stm32f7_i2c_msg {
273 u16 addr;
274 u32 count;
275 u8 *buf;
276 int result;
277 bool stop;
278 bool smbus;
279 int size;
280 char read_write;
281 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
282};
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290struct stm32f7_i2c_alert {
291 struct i2c_smbus_alert_setup setup;
292 struct i2c_client *ara;
293};
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329struct stm32f7_i2c_dev {
330 struct i2c_adapter adap;
331 struct device *dev;
332 void __iomem *base;
333 struct completion complete;
334 struct clk *clk;
335 unsigned int bus_rate;
336 struct i2c_msg *msg;
337 unsigned int msg_num;
338 unsigned int msg_id;
339 struct stm32f7_i2c_msg f7_msg;
340 struct stm32f7_i2c_setup setup;
341 struct stm32f7_i2c_timings timing;
342 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
343 struct i2c_client *slave_running;
344 struct stm32f7_i2c_regs backup_regs;
345 u32 slave_dir;
346 bool master_mode;
347 struct stm32_i2c_dma *dma;
348 bool use_dma;
349 struct regmap *regmap;
350 u32 fmp_sreg;
351 u32 fmp_creg;
352 u32 fmp_mask;
353 bool wakeup_src;
354 bool smbus_mode;
355 struct i2c_client *host_notify_client;
356 bool analog_filter;
357 u32 dnf_dt;
358 u32 dnf;
359 struct stm32f7_i2c_alert *alert;
360};
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369static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
370 {
371 .rate = I2C_MAX_STANDARD_MODE_FREQ,
372 .fall_max = 300,
373 .rise_max = 1000,
374 .hddat_min = 0,
375 .vddat_max = 3450,
376 .sudat_min = 250,
377 .l_min = 4700,
378 .h_min = 4000,
379 },
380 {
381 .rate = I2C_MAX_FAST_MODE_FREQ,
382 .fall_max = 300,
383 .rise_max = 300,
384 .hddat_min = 0,
385 .vddat_max = 900,
386 .sudat_min = 100,
387 .l_min = 1300,
388 .h_min = 600,
389 },
390 {
391 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
392 .fall_max = 100,
393 .rise_max = 120,
394 .hddat_min = 0,
395 .vddat_max = 450,
396 .sudat_min = 50,
397 .l_min = 500,
398 .h_min = 260,
399 },
400};
401
402static const struct stm32f7_i2c_setup stm32f7_setup = {
403 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
404 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
405};
406
407static const struct stm32f7_i2c_setup stm32mp15_setup = {
408 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
409 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
410 .fmp_clr_offset = 0x40,
411};
412
413static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
414{
415 writel_relaxed(readl_relaxed(reg) | mask, reg);
416}
417
418static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
419{
420 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
421}
422
423static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
424{
425 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
426}
427
428static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
429{
430 int i;
431
432 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
433 if (rate <= stm32f7_i2c_specs[i].rate)
434 return &stm32f7_i2c_specs[i];
435
436 return ERR_PTR(-EINVAL);
437}
438
439#define RATE_MIN(rate) ((rate) * 8 / 10)
440static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
441 struct stm32f7_i2c_setup *setup,
442 struct stm32f7_i2c_timings *output)
443{
444 struct stm32f7_i2c_spec *specs;
445 u32 p_prev = STM32F7_PRESC_MAX;
446 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
447 setup->clock_src);
448 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
449 setup->speed_freq);
450 u32 clk_error_prev = i2cbus;
451 u32 tsync;
452 u32 af_delay_min, af_delay_max;
453 u32 dnf_delay;
454 u32 clk_min, clk_max;
455 int sdadel_min, sdadel_max;
456 int scldel_min;
457 struct stm32f7_i2c_timings *v, *_v, *s;
458 struct list_head solutions;
459 u16 p, l, a, h;
460 int ret = 0;
461
462 specs = stm32f7_get_specs(setup->speed_freq);
463 if (specs == ERR_PTR(-EINVAL)) {
464 dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
465 setup->speed_freq);
466 return -EINVAL;
467 }
468
469 if ((setup->rise_time > specs->rise_max) ||
470 (setup->fall_time > specs->fall_max)) {
471 dev_err(i2c_dev->dev,
472 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
473 setup->rise_time, specs->rise_max,
474 setup->fall_time, specs->fall_max);
475 return -EINVAL;
476 }
477
478 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk);
479 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) {
480 dev_err(i2c_dev->dev,
481 "DNF out of bound %d/%d\n",
482 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk);
483 return -EINVAL;
484 }
485
486
487 af_delay_min =
488 (i2c_dev->analog_filter ?
489 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
490 af_delay_max =
491 (i2c_dev->analog_filter ?
492 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
493 dnf_delay = i2c_dev->dnf * i2cclk;
494
495 sdadel_min = specs->hddat_min + setup->fall_time -
496 af_delay_min - (i2c_dev->dnf + 3) * i2cclk;
497
498 sdadel_max = specs->vddat_max - setup->rise_time -
499 af_delay_max - (i2c_dev->dnf + 4) * i2cclk;
500
501 scldel_min = setup->rise_time + specs->sudat_min;
502
503 if (sdadel_min < 0)
504 sdadel_min = 0;
505 if (sdadel_max < 0)
506 sdadel_max = 0;
507
508 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
509 sdadel_min, sdadel_max, scldel_min);
510
511 INIT_LIST_HEAD(&solutions);
512
513 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
514 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
515 u32 scldel = (l + 1) * (p + 1) * i2cclk;
516
517 if (scldel < scldel_min)
518 continue;
519
520 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
521 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
522
523 if (((sdadel >= sdadel_min) &&
524 (sdadel <= sdadel_max)) &&
525 (p != p_prev)) {
526 v = kmalloc(sizeof(*v), GFP_KERNEL);
527 if (!v) {
528 ret = -ENOMEM;
529 goto exit;
530 }
531
532 v->presc = p;
533 v->scldel = l;
534 v->sdadel = a;
535 p_prev = p;
536
537 list_add_tail(&v->node,
538 &solutions);
539 break;
540 }
541 }
542
543 if (p_prev == p)
544 break;
545 }
546 }
547
548 if (list_empty(&solutions)) {
549 dev_err(i2c_dev->dev, "no Prescaler solution\n");
550 ret = -EPERM;
551 goto exit;
552 }
553
554 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
555 s = NULL;
556 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
557 clk_min = NSEC_PER_SEC / setup->speed_freq;
558
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568
569 list_for_each_entry(v, &solutions, node) {
570 u32 prescaler = (v->presc + 1) * i2cclk;
571
572 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
573 u32 tscl_l = (l + 1) * prescaler + tsync;
574
575 if ((tscl_l < specs->l_min) ||
576 (i2cclk >=
577 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
578 continue;
579 }
580
581 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
582 u32 tscl_h = (h + 1) * prescaler + tsync;
583 u32 tscl = tscl_l + tscl_h +
584 setup->rise_time + setup->fall_time;
585
586 if ((tscl >= clk_min) && (tscl <= clk_max) &&
587 (tscl_h >= specs->h_min) &&
588 (i2cclk < tscl_h)) {
589 int clk_error = tscl - i2cbus;
590
591 if (clk_error < 0)
592 clk_error = -clk_error;
593
594 if (clk_error < clk_error_prev) {
595 clk_error_prev = clk_error;
596 v->scll = l;
597 v->sclh = h;
598 s = v;
599 }
600 }
601 }
602 }
603 }
604
605 if (!s) {
606 dev_err(i2c_dev->dev, "no solution at all\n");
607 ret = -EPERM;
608 goto exit;
609 }
610
611 output->presc = s->presc;
612 output->scldel = s->scldel;
613 output->sdadel = s->sdadel;
614 output->scll = s->scll;
615 output->sclh = s->sclh;
616
617 dev_dbg(i2c_dev->dev,
618 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
619 output->presc,
620 output->scldel, output->sdadel,
621 output->scll, output->sclh);
622
623exit:
624
625 list_for_each_entry_safe(v, _v, &solutions, node) {
626 list_del(&v->node);
627 kfree(v);
628 }
629
630 return ret;
631}
632
633static u32 stm32f7_get_lower_rate(u32 rate)
634{
635 int i = ARRAY_SIZE(stm32f7_i2c_specs);
636
637 while (--i)
638 if (stm32f7_i2c_specs[i].rate < rate)
639 break;
640
641 return stm32f7_i2c_specs[i].rate;
642}
643
644static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
645 struct stm32f7_i2c_setup *setup)
646{
647 struct i2c_timings timings, *t = &timings;
648 int ret = 0;
649
650 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
651 t->scl_rise_ns = i2c_dev->setup.rise_time;
652 t->scl_fall_ns = i2c_dev->setup.fall_time;
653
654 i2c_parse_fw_timings(i2c_dev->dev, t, false);
655
656 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
657 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
658 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
659 return -EINVAL;
660 }
661
662 setup->speed_freq = t->bus_freq_hz;
663 i2c_dev->setup.rise_time = t->scl_rise_ns;
664 i2c_dev->setup.fall_time = t->scl_fall_ns;
665 i2c_dev->dnf_dt = t->digital_filter_width_ns;
666 setup->clock_src = clk_get_rate(i2c_dev->clk);
667
668 if (!setup->clock_src) {
669 dev_err(i2c_dev->dev, "clock rate is 0\n");
670 return -EINVAL;
671 }
672
673 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter"))
674 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT;
675
676 do {
677 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
678 &i2c_dev->timing);
679 if (ret) {
680 dev_err(i2c_dev->dev,
681 "failed to compute I2C timings.\n");
682 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
683 break;
684 setup->speed_freq =
685 stm32f7_get_lower_rate(setup->speed_freq);
686 dev_warn(i2c_dev->dev,
687 "downgrade I2C Speed Freq to (%i)\n",
688 setup->speed_freq);
689 }
690 } while (ret);
691
692 if (ret) {
693 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
694 return ret;
695 }
696
697 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node,
698 "i2c-analog-filter");
699
700 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
701 setup->speed_freq, setup->clock_src);
702 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
703 setup->rise_time, setup->fall_time);
704 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
705 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf);
706
707 i2c_dev->bus_rate = setup->speed_freq;
708
709 return 0;
710}
711
712static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
713{
714 void __iomem *base = i2c_dev->base;
715 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
716
717 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
718}
719
720static void stm32f7_i2c_dma_callback(void *arg)
721{
722 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
723 struct stm32_i2c_dma *dma = i2c_dev->dma;
724 struct device *dev = dma->chan_using->device->dev;
725
726 stm32f7_i2c_disable_dma_req(i2c_dev);
727 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
728 complete(&dma->dma_complete);
729}
730
731static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
732{
733 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
734 u32 timing = 0;
735
736
737 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
738 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
739 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
740 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
741 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
742 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
743
744
745 if (i2c_dev->analog_filter)
746 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
747 STM32F7_I2C_CR1_ANFOFF);
748 else
749 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
750 STM32F7_I2C_CR1_ANFOFF);
751
752
753 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
754 STM32F7_I2C_CR1_DNF_MASK);
755 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
756 STM32F7_I2C_CR1_DNF(i2c_dev->dnf));
757
758 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
759 STM32F7_I2C_CR1_PE);
760}
761
762static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
763{
764 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
765 void __iomem *base = i2c_dev->base;
766
767 if (f7_msg->count) {
768 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
769 f7_msg->count--;
770 }
771}
772
773static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
774{
775 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
776 void __iomem *base = i2c_dev->base;
777
778 if (f7_msg->count) {
779 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
780 f7_msg->count--;
781 } else {
782
783 readb_relaxed(base + STM32F7_I2C_RXDR);
784 }
785}
786
787static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
788{
789 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
790 u32 cr2;
791
792 if (i2c_dev->use_dma)
793 f7_msg->count -= STM32F7_I2C_MAX_LEN;
794
795 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
796
797 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
798 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
799 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
800 } else {
801 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
802 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
803 }
804
805 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
806}
807
808static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
809{
810 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
811 u32 cr2;
812 u8 *val;
813
814
815
816
817
818 stm32f7_i2c_read_rx_data(i2c_dev);
819
820
821
822
823 val = f7_msg->buf - sizeof(u8);
824 f7_msg->count = *val;
825 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
826 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
827 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
828 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
829}
830
831static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
832{
833 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
834
835 dev_info(i2c_dev->dev, "Trying to recover bus\n");
836
837 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
838 STM32F7_I2C_CR1_PE);
839
840 stm32f7_i2c_hw_config(i2c_dev);
841
842 return 0;
843}
844
845static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
846{
847 u32 status;
848 int ret;
849
850 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
851 status,
852 !(status & STM32F7_I2C_ISR_BUSY),
853 10, 1000);
854 if (!ret)
855 return 0;
856
857 dev_info(i2c_dev->dev, "bus busy\n");
858
859 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
860 if (ret) {
861 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
862 return ret;
863 }
864
865 return -EBUSY;
866}
867
868static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
869 struct i2c_msg *msg)
870{
871 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
872 void __iomem *base = i2c_dev->base;
873 u32 cr1, cr2;
874 int ret;
875
876 f7_msg->addr = msg->addr;
877 f7_msg->buf = msg->buf;
878 f7_msg->count = msg->len;
879 f7_msg->result = 0;
880 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
881
882 reinit_completion(&i2c_dev->complete);
883
884 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
885 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
886
887
888 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
889 if (msg->flags & I2C_M_RD)
890 cr2 |= STM32F7_I2C_CR2_RD_WRN;
891
892
893 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
894 if (msg->flags & I2C_M_TEN) {
895 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
896 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
897 cr2 |= STM32F7_I2C_CR2_ADD10;
898 } else {
899 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
900 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
901 }
902
903
904 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
905 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
906 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
907 cr2 |= STM32F7_I2C_CR2_RELOAD;
908 } else {
909 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
910 }
911
912
913 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
914 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
915
916
917 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
918 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
919
920
921 i2c_dev->use_dma = false;
922 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
923 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
924 msg->flags & I2C_M_RD,
925 f7_msg->count, f7_msg->buf,
926 stm32f7_i2c_dma_callback,
927 i2c_dev);
928 if (!ret)
929 i2c_dev->use_dma = true;
930 else
931 dev_warn(i2c_dev->dev, "can't use DMA\n");
932 }
933
934 if (!i2c_dev->use_dma) {
935 if (msg->flags & I2C_M_RD)
936 cr1 |= STM32F7_I2C_CR1_RXIE;
937 else
938 cr1 |= STM32F7_I2C_CR1_TXIE;
939 } else {
940 if (msg->flags & I2C_M_RD)
941 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
942 else
943 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
944 }
945
946
947 cr2 |= STM32F7_I2C_CR2_START;
948
949 i2c_dev->master_mode = true;
950
951
952 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
953 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
954}
955
956static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
957 unsigned short flags, u8 command,
958 union i2c_smbus_data *data)
959{
960 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
961 struct device *dev = i2c_dev->dev;
962 void __iomem *base = i2c_dev->base;
963 u32 cr1, cr2;
964 int i, ret;
965
966 f7_msg->result = 0;
967 reinit_completion(&i2c_dev->complete);
968
969 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
970 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
971
972
973 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
974 if (f7_msg->read_write)
975 cr2 |= STM32F7_I2C_CR2_RD_WRN;
976
977
978 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
979 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
980
981 f7_msg->smbus_buf[0] = command;
982 switch (f7_msg->size) {
983 case I2C_SMBUS_QUICK:
984 f7_msg->stop = true;
985 f7_msg->count = 0;
986 break;
987 case I2C_SMBUS_BYTE:
988 f7_msg->stop = true;
989 f7_msg->count = 1;
990 break;
991 case I2C_SMBUS_BYTE_DATA:
992 if (f7_msg->read_write) {
993 f7_msg->stop = false;
994 f7_msg->count = 1;
995 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
996 } else {
997 f7_msg->stop = true;
998 f7_msg->count = 2;
999 f7_msg->smbus_buf[1] = data->byte;
1000 }
1001 break;
1002 case I2C_SMBUS_WORD_DATA:
1003 if (f7_msg->read_write) {
1004 f7_msg->stop = false;
1005 f7_msg->count = 1;
1006 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1007 } else {
1008 f7_msg->stop = true;
1009 f7_msg->count = 3;
1010 f7_msg->smbus_buf[1] = data->word & 0xff;
1011 f7_msg->smbus_buf[2] = data->word >> 8;
1012 }
1013 break;
1014 case I2C_SMBUS_BLOCK_DATA:
1015 if (f7_msg->read_write) {
1016 f7_msg->stop = false;
1017 f7_msg->count = 1;
1018 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1019 } else {
1020 f7_msg->stop = true;
1021 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1022 !data->block[0]) {
1023 dev_err(dev, "Invalid block write size %d\n",
1024 data->block[0]);
1025 return -EINVAL;
1026 }
1027 f7_msg->count = data->block[0] + 2;
1028 for (i = 1; i < f7_msg->count; i++)
1029 f7_msg->smbus_buf[i] = data->block[i - 1];
1030 }
1031 break;
1032 case I2C_SMBUS_PROC_CALL:
1033 f7_msg->stop = false;
1034 f7_msg->count = 3;
1035 f7_msg->smbus_buf[1] = data->word & 0xff;
1036 f7_msg->smbus_buf[2] = data->word >> 8;
1037 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1038 f7_msg->read_write = I2C_SMBUS_READ;
1039 break;
1040 case I2C_SMBUS_BLOCK_PROC_CALL:
1041 f7_msg->stop = false;
1042 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1043 dev_err(dev, "Invalid block write size %d\n",
1044 data->block[0]);
1045 return -EINVAL;
1046 }
1047 f7_msg->count = data->block[0] + 2;
1048 for (i = 1; i < f7_msg->count; i++)
1049 f7_msg->smbus_buf[i] = data->block[i - 1];
1050 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1051 f7_msg->read_write = I2C_SMBUS_READ;
1052 break;
1053 case I2C_SMBUS_I2C_BLOCK_DATA:
1054
1055 return -EOPNOTSUPP;
1056 default:
1057 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1058 return -EOPNOTSUPP;
1059 }
1060
1061 f7_msg->buf = f7_msg->smbus_buf;
1062
1063
1064 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1065 cr1 |= STM32F7_I2C_CR1_PECEN;
1066 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1067 if (!f7_msg->read_write)
1068 f7_msg->count++;
1069 } else {
1070 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1071 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1072 }
1073
1074
1075 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1076 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1077
1078
1079 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1080 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1081
1082
1083 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1084 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1085
1086
1087 i2c_dev->use_dma = false;
1088 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1089 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1090 cr2 & STM32F7_I2C_CR2_RD_WRN,
1091 f7_msg->count, f7_msg->buf,
1092 stm32f7_i2c_dma_callback,
1093 i2c_dev);
1094 if (!ret)
1095 i2c_dev->use_dma = true;
1096 else
1097 dev_warn(i2c_dev->dev, "can't use DMA\n");
1098 }
1099
1100 if (!i2c_dev->use_dma) {
1101 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1102 cr1 |= STM32F7_I2C_CR1_RXIE;
1103 else
1104 cr1 |= STM32F7_I2C_CR1_TXIE;
1105 } else {
1106 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1107 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1108 else
1109 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1110 }
1111
1112
1113 cr2 |= STM32F7_I2C_CR2_START;
1114
1115 i2c_dev->master_mode = true;
1116
1117
1118 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1119 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1120
1121 return 0;
1122}
1123
1124static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1125{
1126 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1127 void __iomem *base = i2c_dev->base;
1128 u32 cr1, cr2;
1129 int ret;
1130
1131 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1132 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1133
1134
1135 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1136
1137 switch (f7_msg->size) {
1138 case I2C_SMBUS_BYTE_DATA:
1139 f7_msg->count = 1;
1140 break;
1141 case I2C_SMBUS_WORD_DATA:
1142 case I2C_SMBUS_PROC_CALL:
1143 f7_msg->count = 2;
1144 break;
1145 case I2C_SMBUS_BLOCK_DATA:
1146 case I2C_SMBUS_BLOCK_PROC_CALL:
1147 f7_msg->count = 1;
1148 cr2 |= STM32F7_I2C_CR2_RELOAD;
1149 break;
1150 }
1151
1152 f7_msg->buf = f7_msg->smbus_buf;
1153 f7_msg->stop = true;
1154
1155
1156 if (cr1 & STM32F7_I2C_CR1_PECEN)
1157 f7_msg->count++;
1158
1159
1160 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1161 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1162
1163
1164
1165
1166 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1167 cr1 |= STM32F7_I2C_CR1_RXIE;
1168
1169
1170
1171
1172
1173
1174 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1175 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1176
1177 i2c_dev->use_dma = false;
1178 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1179 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1180 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1181 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1182 cr2 & STM32F7_I2C_CR2_RD_WRN,
1183 f7_msg->count, f7_msg->buf,
1184 stm32f7_i2c_dma_callback,
1185 i2c_dev);
1186
1187 if (!ret)
1188 i2c_dev->use_dma = true;
1189 else
1190 dev_warn(i2c_dev->dev, "can't use DMA\n");
1191 }
1192
1193 if (!i2c_dev->use_dma)
1194 cr1 |= STM32F7_I2C_CR1_RXIE;
1195 else
1196 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1197
1198
1199 cr2 |= STM32F7_I2C_CR2_START;
1200
1201
1202 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1203 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1204}
1205
1206static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1207{
1208 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1209 u8 count, internal_pec, received_pec;
1210
1211 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1212
1213 switch (f7_msg->size) {
1214 case I2C_SMBUS_BYTE:
1215 case I2C_SMBUS_BYTE_DATA:
1216 received_pec = f7_msg->smbus_buf[1];
1217 break;
1218 case I2C_SMBUS_WORD_DATA:
1219 case I2C_SMBUS_PROC_CALL:
1220 received_pec = f7_msg->smbus_buf[2];
1221 break;
1222 case I2C_SMBUS_BLOCK_DATA:
1223 case I2C_SMBUS_BLOCK_PROC_CALL:
1224 count = f7_msg->smbus_buf[0];
1225 received_pec = f7_msg->smbus_buf[count];
1226 break;
1227 default:
1228 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1229 return -EINVAL;
1230 }
1231
1232 if (internal_pec != received_pec) {
1233 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1234 internal_pec, received_pec);
1235 return -EBADMSG;
1236 }
1237
1238 return 0;
1239}
1240
1241static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1242{
1243 u32 addr;
1244
1245 if (!slave)
1246 return false;
1247
1248 if (slave->flags & I2C_CLIENT_TEN) {
1249
1250
1251
1252
1253
1254 addr = slave->addr >> 8;
1255 addr |= 0x78;
1256 if (addr == addcode)
1257 return true;
1258 } else {
1259 addr = slave->addr & 0x7f;
1260 if (addr == addcode)
1261 return true;
1262 }
1263
1264 return false;
1265}
1266
1267static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1268{
1269 struct i2c_client *slave = i2c_dev->slave_running;
1270 void __iomem *base = i2c_dev->base;
1271 u32 mask;
1272 u8 value = 0;
1273
1274 if (i2c_dev->slave_dir) {
1275
1276 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1277
1278
1279
1280
1281
1282 mask = STM32F7_I2C_CR2_RELOAD;
1283 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1284 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1285 STM32F7_I2C_CR1_TCIE;
1286 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1287
1288
1289 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1290 STM32F7_I2C_CR1_TXIE;
1291 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1292
1293
1294 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1295 } else {
1296
1297 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1298
1299
1300 mask = STM32F7_I2C_CR2_RELOAD;
1301 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1302
1303
1304
1305
1306
1307
1308 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1309 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1310 STM32F7_I2C_CR1_TCIE;
1311 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1312 }
1313}
1314
1315static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1316{
1317 void __iomem *base = i2c_dev->base;
1318 u32 isr, addcode, dir, mask;
1319 int i;
1320
1321 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1322 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1323 dir = isr & STM32F7_I2C_ISR_DIR;
1324
1325 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1326 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1327 i2c_dev->slave_running = i2c_dev->slave[i];
1328 i2c_dev->slave_dir = dir;
1329
1330
1331 stm32f7_i2c_slave_start(i2c_dev);
1332
1333
1334 mask = STM32F7_I2C_ICR_ADDRCF;
1335 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1336 break;
1337 }
1338 }
1339}
1340
1341static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1342 struct i2c_client *slave, int *id)
1343{
1344 int i;
1345
1346 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1347 if (i2c_dev->slave[i] == slave) {
1348 *id = i;
1349 return 0;
1350 }
1351 }
1352
1353 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1354
1355 return -ENODEV;
1356}
1357
1358static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1359 struct i2c_client *slave, int *id)
1360{
1361 struct device *dev = i2c_dev->dev;
1362 int i;
1363
1364
1365
1366
1367
1368
1369 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1370 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1371 goto fail;
1372 *id = STM32F7_SLAVE_HOSTNOTIFY;
1373 return 0;
1374 }
1375
1376 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1377 if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1378 (slave->flags & I2C_CLIENT_TEN))
1379 continue;
1380 if (!i2c_dev->slave[i]) {
1381 *id = i;
1382 return 0;
1383 }
1384 }
1385
1386fail:
1387 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1388
1389 return -EINVAL;
1390}
1391
1392static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1393{
1394 int i;
1395
1396 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1397 if (i2c_dev->slave[i])
1398 return true;
1399 }
1400
1401 return false;
1402}
1403
1404static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1405{
1406 int i, busy;
1407
1408 busy = 0;
1409 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1410 if (i2c_dev->slave[i])
1411 busy++;
1412 }
1413
1414 return i == busy;
1415}
1416
1417static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1418{
1419 void __iomem *base = i2c_dev->base;
1420 u32 cr2, status, mask;
1421 u8 val;
1422 int ret;
1423
1424 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1425
1426
1427 if (status & STM32F7_I2C_ISR_TXIS) {
1428 i2c_slave_event(i2c_dev->slave_running,
1429 I2C_SLAVE_READ_PROCESSED,
1430 &val);
1431
1432
1433 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1434 }
1435
1436
1437 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1438
1439
1440
1441
1442 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1443 ret = i2c_slave_event(i2c_dev->slave_running,
1444 I2C_SLAVE_WRITE_RECEIVED,
1445 &val);
1446 if (!ret) {
1447 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1448 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1449 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1450 } else {
1451 mask = STM32F7_I2C_CR2_NACK;
1452 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1453 }
1454 }
1455
1456
1457 if (status & STM32F7_I2C_ISR_NACKF) {
1458 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1459 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1460 }
1461
1462
1463 if (status & STM32F7_I2C_ISR_STOPF) {
1464
1465 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1466
1467 if (i2c_dev->slave_dir) {
1468
1469
1470
1471
1472 mask = STM32F7_I2C_ISR_TXE;
1473 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1474 }
1475
1476
1477 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1478
1479
1480 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1481
1482 i2c_dev->slave_running = NULL;
1483 }
1484
1485
1486 if (status & STM32F7_I2C_ISR_ADDR)
1487 stm32f7_i2c_slave_addr(i2c_dev);
1488
1489 return IRQ_HANDLED;
1490}
1491
1492static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1493{
1494 struct stm32f7_i2c_dev *i2c_dev = data;
1495 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1496 void __iomem *base = i2c_dev->base;
1497 u32 status, mask;
1498 int ret = IRQ_HANDLED;
1499
1500
1501 if (!i2c_dev->master_mode) {
1502 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1503 return ret;
1504 }
1505
1506 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1507
1508
1509 if (status & STM32F7_I2C_ISR_TXIS)
1510 stm32f7_i2c_write_tx_data(i2c_dev);
1511
1512
1513 if (status & STM32F7_I2C_ISR_RXNE)
1514 stm32f7_i2c_read_rx_data(i2c_dev);
1515
1516
1517 if (status & STM32F7_I2C_ISR_NACKF) {
1518 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1519 __func__, f7_msg->addr);
1520 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1521 f7_msg->result = -ENXIO;
1522 }
1523
1524
1525 if (status & STM32F7_I2C_ISR_STOPF) {
1526
1527 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1528 mask = STM32F7_I2C_XFER_IRQ_MASK;
1529 else
1530 mask = STM32F7_I2C_ALL_IRQ_MASK;
1531 stm32f7_i2c_disable_irq(i2c_dev, mask);
1532
1533
1534 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1535
1536 if (i2c_dev->use_dma) {
1537 ret = IRQ_WAKE_THREAD;
1538 } else {
1539 i2c_dev->master_mode = false;
1540 complete(&i2c_dev->complete);
1541 }
1542 }
1543
1544
1545 if (status & STM32F7_I2C_ISR_TC) {
1546 if (f7_msg->stop) {
1547 mask = STM32F7_I2C_CR2_STOP;
1548 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1549 } else if (i2c_dev->use_dma) {
1550 ret = IRQ_WAKE_THREAD;
1551 } else if (f7_msg->smbus) {
1552 stm32f7_i2c_smbus_rep_start(i2c_dev);
1553 } else {
1554 i2c_dev->msg_id++;
1555 i2c_dev->msg++;
1556 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1557 }
1558 }
1559
1560 if (status & STM32F7_I2C_ISR_TCR) {
1561 if (f7_msg->smbus)
1562 stm32f7_i2c_smbus_reload(i2c_dev);
1563 else
1564 stm32f7_i2c_reload(i2c_dev);
1565 }
1566
1567 return ret;
1568}
1569
1570static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1571{
1572 struct stm32f7_i2c_dev *i2c_dev = data;
1573 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1574 struct stm32_i2c_dma *dma = i2c_dev->dma;
1575 u32 status;
1576 int ret;
1577
1578
1579
1580
1581
1582 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1583 if (!ret) {
1584 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1585 stm32f7_i2c_disable_dma_req(i2c_dev);
1586 dmaengine_terminate_all(dma->chan_using);
1587 f7_msg->result = -ETIMEDOUT;
1588 }
1589
1590 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1591
1592 if (status & STM32F7_I2C_ISR_TC) {
1593 if (f7_msg->smbus) {
1594 stm32f7_i2c_smbus_rep_start(i2c_dev);
1595 } else {
1596 i2c_dev->msg_id++;
1597 i2c_dev->msg++;
1598 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1599 }
1600 } else {
1601 i2c_dev->master_mode = false;
1602 complete(&i2c_dev->complete);
1603 }
1604
1605 return IRQ_HANDLED;
1606}
1607
1608static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1609{
1610 struct stm32f7_i2c_dev *i2c_dev = data;
1611 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1612 void __iomem *base = i2c_dev->base;
1613 struct device *dev = i2c_dev->dev;
1614 struct stm32_i2c_dma *dma = i2c_dev->dma;
1615 u32 status;
1616
1617 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1618
1619
1620 if (status & STM32F7_I2C_ISR_BERR) {
1621 dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n",
1622 __func__, f7_msg->addr);
1623 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1624 stm32f7_i2c_release_bus(&i2c_dev->adap);
1625 f7_msg->result = -EIO;
1626 }
1627
1628
1629 if (status & STM32F7_I2C_ISR_ARLO) {
1630 dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n",
1631 __func__, f7_msg->addr);
1632 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1633 f7_msg->result = -EAGAIN;
1634 }
1635
1636 if (status & STM32F7_I2C_ISR_PECERR) {
1637 dev_err(dev, "<%s>: PEC error in reception accessing addr 0x%x\n",
1638 __func__, f7_msg->addr);
1639 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1640 f7_msg->result = -EINVAL;
1641 }
1642
1643 if (status & STM32F7_I2C_ISR_ALERT) {
1644 dev_dbg(dev, "<%s>: SMBus alert received\n", __func__);
1645 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
1646 i2c_handle_smbus_alert(i2c_dev->alert->ara);
1647 return IRQ_HANDLED;
1648 }
1649
1650 if (!i2c_dev->slave_running) {
1651 u32 mask;
1652
1653 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1654 mask = STM32F7_I2C_XFER_IRQ_MASK;
1655 else
1656 mask = STM32F7_I2C_ALL_IRQ_MASK;
1657 stm32f7_i2c_disable_irq(i2c_dev, mask);
1658 }
1659
1660
1661 if (i2c_dev->use_dma) {
1662 stm32f7_i2c_disable_dma_req(i2c_dev);
1663 dmaengine_terminate_all(dma->chan_using);
1664 }
1665
1666 i2c_dev->master_mode = false;
1667 complete(&i2c_dev->complete);
1668
1669 return IRQ_HANDLED;
1670}
1671
1672static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1673 struct i2c_msg msgs[], int num)
1674{
1675 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1676 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1677 struct stm32_i2c_dma *dma = i2c_dev->dma;
1678 unsigned long time_left;
1679 int ret;
1680
1681 i2c_dev->msg = msgs;
1682 i2c_dev->msg_num = num;
1683 i2c_dev->msg_id = 0;
1684 f7_msg->smbus = false;
1685
1686 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1687 if (ret < 0)
1688 return ret;
1689
1690 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1691 if (ret)
1692 goto pm_free;
1693
1694 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1695
1696 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1697 i2c_dev->adap.timeout);
1698 ret = f7_msg->result;
1699
1700 if (!time_left) {
1701 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1702 i2c_dev->msg->addr);
1703 if (i2c_dev->use_dma)
1704 dmaengine_terminate_all(dma->chan_using);
1705 ret = -ETIMEDOUT;
1706 }
1707
1708pm_free:
1709 pm_runtime_mark_last_busy(i2c_dev->dev);
1710 pm_runtime_put_autosuspend(i2c_dev->dev);
1711
1712 return (ret < 0) ? ret : num;
1713}
1714
1715static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1716 unsigned short flags, char read_write,
1717 u8 command, int size,
1718 union i2c_smbus_data *data)
1719{
1720 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1721 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1722 struct stm32_i2c_dma *dma = i2c_dev->dma;
1723 struct device *dev = i2c_dev->dev;
1724 unsigned long timeout;
1725 int i, ret;
1726
1727 f7_msg->addr = addr;
1728 f7_msg->size = size;
1729 f7_msg->read_write = read_write;
1730 f7_msg->smbus = true;
1731
1732 ret = pm_runtime_resume_and_get(dev);
1733 if (ret < 0)
1734 return ret;
1735
1736 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1737 if (ret)
1738 goto pm_free;
1739
1740 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1741 if (ret)
1742 goto pm_free;
1743
1744 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1745 i2c_dev->adap.timeout);
1746 ret = f7_msg->result;
1747 if (ret)
1748 goto pm_free;
1749
1750 if (!timeout) {
1751 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1752 if (i2c_dev->use_dma)
1753 dmaengine_terminate_all(dma->chan_using);
1754 ret = -ETIMEDOUT;
1755 goto pm_free;
1756 }
1757
1758
1759 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1760 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1761 if (ret)
1762 goto pm_free;
1763 }
1764
1765 if (read_write && size != I2C_SMBUS_QUICK) {
1766 switch (size) {
1767 case I2C_SMBUS_BYTE:
1768 case I2C_SMBUS_BYTE_DATA:
1769 data->byte = f7_msg->smbus_buf[0];
1770 break;
1771 case I2C_SMBUS_WORD_DATA:
1772 case I2C_SMBUS_PROC_CALL:
1773 data->word = f7_msg->smbus_buf[0] |
1774 (f7_msg->smbus_buf[1] << 8);
1775 break;
1776 case I2C_SMBUS_BLOCK_DATA:
1777 case I2C_SMBUS_BLOCK_PROC_CALL:
1778 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1779 data->block[i] = f7_msg->smbus_buf[i];
1780 break;
1781 default:
1782 dev_err(dev, "Unsupported smbus transaction\n");
1783 ret = -EINVAL;
1784 }
1785 }
1786
1787pm_free:
1788 pm_runtime_mark_last_busy(dev);
1789 pm_runtime_put_autosuspend(dev);
1790 return ret;
1791}
1792
1793static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1794 bool enable)
1795{
1796 void __iomem *base = i2c_dev->base;
1797 u32 mask = STM32F7_I2C_CR1_WUPEN;
1798
1799 if (!i2c_dev->wakeup_src)
1800 return;
1801
1802 if (enable) {
1803 device_set_wakeup_enable(i2c_dev->dev, true);
1804 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1805 } else {
1806 device_set_wakeup_enable(i2c_dev->dev, false);
1807 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1808 }
1809}
1810
1811static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1812{
1813 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1814 void __iomem *base = i2c_dev->base;
1815 struct device *dev = i2c_dev->dev;
1816 u32 oar1, oar2, mask;
1817 int id, ret;
1818
1819 if (slave->flags & I2C_CLIENT_PEC) {
1820 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1821 return -EINVAL;
1822 }
1823
1824 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1825 dev_err(dev, "Too much slave registered\n");
1826 return -EBUSY;
1827 }
1828
1829 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1830 if (ret)
1831 return ret;
1832
1833 ret = pm_runtime_resume_and_get(dev);
1834 if (ret < 0)
1835 return ret;
1836
1837 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1838 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1839
1840 switch (id) {
1841 case 0:
1842
1843 i2c_dev->slave[id] = slave;
1844 break;
1845
1846 case 1:
1847
1848 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1849 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1850 if (slave->flags & I2C_CLIENT_TEN) {
1851 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1852 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1853 } else {
1854 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1855 }
1856 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1857 i2c_dev->slave[id] = slave;
1858 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1859 break;
1860
1861 case 2:
1862
1863 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1864 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1865 if (slave->flags & I2C_CLIENT_TEN) {
1866 ret = -EOPNOTSUPP;
1867 goto pm_free;
1868 }
1869
1870 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1871 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1872 i2c_dev->slave[id] = slave;
1873 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1874 break;
1875
1876 default:
1877 dev_err(dev, "I2C slave id not supported\n");
1878 ret = -ENODEV;
1879 goto pm_free;
1880 }
1881
1882
1883 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1884
1885
1886 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1887 STM32F7_I2C_CR1_PE;
1888 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1889
1890 ret = 0;
1891pm_free:
1892 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1893 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1894
1895 pm_runtime_mark_last_busy(dev);
1896 pm_runtime_put_autosuspend(dev);
1897
1898 return ret;
1899}
1900
1901static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1902{
1903 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1904 void __iomem *base = i2c_dev->base;
1905 u32 mask;
1906 int id, ret;
1907
1908 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1909 if (ret)
1910 return ret;
1911
1912 WARN_ON(!i2c_dev->slave[id]);
1913
1914 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1915 if (ret < 0)
1916 return ret;
1917
1918 if (id == 1) {
1919 mask = STM32F7_I2C_OAR1_OA1EN;
1920 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1921 } else if (id == 2) {
1922 mask = STM32F7_I2C_OAR2_OA2EN;
1923 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1924 }
1925
1926 i2c_dev->slave[id] = NULL;
1927
1928 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1929 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1930 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1931 }
1932
1933 pm_runtime_mark_last_busy(i2c_dev->dev);
1934 pm_runtime_put_autosuspend(i2c_dev->dev);
1935
1936 return 0;
1937}
1938
1939static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1940 bool enable)
1941{
1942 int ret;
1943
1944 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
1945 IS_ERR_OR_NULL(i2c_dev->regmap))
1946
1947 return 0;
1948
1949 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1950 ret = regmap_update_bits(i2c_dev->regmap,
1951 i2c_dev->fmp_sreg,
1952 i2c_dev->fmp_mask,
1953 enable ? i2c_dev->fmp_mask : 0);
1954 else
1955 ret = regmap_write(i2c_dev->regmap,
1956 enable ? i2c_dev->fmp_sreg :
1957 i2c_dev->fmp_creg,
1958 i2c_dev->fmp_mask);
1959
1960 return ret;
1961}
1962
1963static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1964 struct stm32f7_i2c_dev *i2c_dev)
1965{
1966 struct device_node *np = pdev->dev.of_node;
1967 int ret;
1968
1969 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1970 if (IS_ERR(i2c_dev->regmap))
1971
1972 return 0;
1973
1974 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
1975 &i2c_dev->fmp_sreg);
1976 if (ret)
1977 return ret;
1978
1979 i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
1980 i2c_dev->setup.fmp_clr_offset;
1981
1982 return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
1983 &i2c_dev->fmp_mask);
1984}
1985
1986static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
1987{
1988 struct i2c_adapter *adap = &i2c_dev->adap;
1989 void __iomem *base = i2c_dev->base;
1990 struct i2c_client *client;
1991
1992 client = i2c_new_slave_host_notify_device(adap);
1993 if (IS_ERR(client))
1994 return PTR_ERR(client);
1995
1996 i2c_dev->host_notify_client = client;
1997
1998
1999 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
2000
2001 return 0;
2002}
2003
2004static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2005{
2006 void __iomem *base = i2c_dev->base;
2007
2008 if (i2c_dev->host_notify_client) {
2009
2010 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2011 STM32F7_I2C_CR1_SMBHEN);
2012 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
2013 }
2014}
2015
2016static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2017{
2018 struct stm32f7_i2c_alert *alert;
2019 struct i2c_adapter *adap = &i2c_dev->adap;
2020 struct device *dev = i2c_dev->dev;
2021 void __iomem *base = i2c_dev->base;
2022
2023 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
2024 if (!alert)
2025 return -ENOMEM;
2026
2027 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup);
2028 if (IS_ERR(alert->ara))
2029 return PTR_ERR(alert->ara);
2030
2031 i2c_dev->alert = alert;
2032
2033
2034 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
2035
2036 return 0;
2037}
2038
2039static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2040{
2041 struct stm32f7_i2c_alert *alert = i2c_dev->alert;
2042 void __iomem *base = i2c_dev->base;
2043
2044 if (alert) {
2045
2046 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2047 STM32F7_I2C_CR1_ALERTEN);
2048 i2c_unregister_device(alert->ara);
2049 }
2050}
2051
2052static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
2053{
2054 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2055
2056 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
2057 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
2058 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2059 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2060 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2061 I2C_FUNC_SMBUS_I2C_BLOCK;
2062
2063 if (i2c_dev->smbus_mode)
2064 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2065
2066 return func;
2067}
2068
2069static const struct i2c_algorithm stm32f7_i2c_algo = {
2070 .master_xfer = stm32f7_i2c_xfer,
2071 .smbus_xfer = stm32f7_i2c_smbus_xfer,
2072 .functionality = stm32f7_i2c_func,
2073 .reg_slave = stm32f7_i2c_reg_slave,
2074 .unreg_slave = stm32f7_i2c_unreg_slave,
2075};
2076
2077static int stm32f7_i2c_probe(struct platform_device *pdev)
2078{
2079 struct stm32f7_i2c_dev *i2c_dev;
2080 const struct stm32f7_i2c_setup *setup;
2081 struct resource *res;
2082 struct i2c_adapter *adap;
2083 struct reset_control *rst;
2084 dma_addr_t phy_addr;
2085 int irq_error, irq_event, ret;
2086
2087 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2088 if (!i2c_dev)
2089 return -ENOMEM;
2090
2091 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2092 if (IS_ERR(i2c_dev->base))
2093 return PTR_ERR(i2c_dev->base);
2094 phy_addr = (dma_addr_t)res->start;
2095
2096 irq_event = platform_get_irq(pdev, 0);
2097 if (irq_event <= 0)
2098 return irq_event ? : -ENOENT;
2099
2100 irq_error = platform_get_irq(pdev, 1);
2101 if (irq_error <= 0)
2102 return irq_error ? : -ENOENT;
2103
2104 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2105 "wakeup-source");
2106
2107 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
2108 if (IS_ERR(i2c_dev->clk))
2109 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2110 "Failed to get controller clock\n");
2111
2112 ret = clk_prepare_enable(i2c_dev->clk);
2113 if (ret) {
2114 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
2115 return ret;
2116 }
2117
2118 rst = devm_reset_control_get(&pdev->dev, NULL);
2119 if (IS_ERR(rst)) {
2120 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
2121 "Error: Missing reset ctrl\n");
2122 goto clk_free;
2123 }
2124 reset_control_assert(rst);
2125 udelay(2);
2126 reset_control_deassert(rst);
2127
2128 i2c_dev->dev = &pdev->dev;
2129
2130 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2131 stm32f7_i2c_isr_event,
2132 stm32f7_i2c_isr_event_thread,
2133 IRQF_ONESHOT,
2134 pdev->name, i2c_dev);
2135 if (ret) {
2136 dev_err(&pdev->dev, "Failed to request irq event %i\n",
2137 irq_event);
2138 goto clk_free;
2139 }
2140
2141 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
2142 pdev->name, i2c_dev);
2143 if (ret) {
2144 dev_err(&pdev->dev, "Failed to request irq error %i\n",
2145 irq_error);
2146 goto clk_free;
2147 }
2148
2149 setup = of_device_get_match_data(&pdev->dev);
2150 if (!setup) {
2151 dev_err(&pdev->dev, "Can't get device data\n");
2152 ret = -ENODEV;
2153 goto clk_free;
2154 }
2155 i2c_dev->setup = *setup;
2156
2157 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2158 if (ret)
2159 goto clk_free;
2160
2161
2162 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2163 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2164 if (ret)
2165 goto clk_free;
2166 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2167 if (ret)
2168 goto clk_free;
2169 }
2170
2171 adap = &i2c_dev->adap;
2172 i2c_set_adapdata(adap, i2c_dev);
2173 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2174 &res->start);
2175 adap->owner = THIS_MODULE;
2176 adap->timeout = 2 * HZ;
2177 adap->retries = 3;
2178 adap->algo = &stm32f7_i2c_algo;
2179 adap->dev.parent = &pdev->dev;
2180 adap->dev.of_node = pdev->dev.of_node;
2181
2182 init_completion(&i2c_dev->complete);
2183
2184
2185 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2186 STM32F7_I2C_TXDR,
2187 STM32F7_I2C_RXDR);
2188 if (IS_ERR(i2c_dev->dma)) {
2189 ret = PTR_ERR(i2c_dev->dma);
2190
2191 if (ret != -ENODEV)
2192 goto fmp_clear;
2193 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2194 i2c_dev->dma = NULL;
2195 }
2196
2197 if (i2c_dev->wakeup_src) {
2198 device_set_wakeup_capable(i2c_dev->dev, true);
2199
2200 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2201 if (ret) {
2202 dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2203 goto clr_wakeup_capable;
2204 }
2205 }
2206
2207 platform_set_drvdata(pdev, i2c_dev);
2208
2209 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2210 STM32F7_AUTOSUSPEND_DELAY);
2211 pm_runtime_use_autosuspend(i2c_dev->dev);
2212 pm_runtime_set_active(i2c_dev->dev);
2213 pm_runtime_enable(i2c_dev->dev);
2214
2215 pm_runtime_get_noresume(&pdev->dev);
2216
2217 stm32f7_i2c_hw_config(i2c_dev);
2218
2219 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2220
2221 ret = i2c_add_adapter(adap);
2222 if (ret)
2223 goto pm_disable;
2224
2225 if (i2c_dev->smbus_mode) {
2226 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2227 if (ret) {
2228 dev_err(i2c_dev->dev,
2229 "failed to enable SMBus Host-Notify protocol (%d)\n",
2230 ret);
2231 goto i2c_adapter_remove;
2232 }
2233 }
2234
2235 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) {
2236 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev);
2237 if (ret) {
2238 dev_err(i2c_dev->dev,
2239 "failed to enable SMBus alert protocol (%d)\n",
2240 ret);
2241 goto i2c_disable_smbus_host;
2242 }
2243 }
2244
2245 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2246
2247 pm_runtime_mark_last_busy(i2c_dev->dev);
2248 pm_runtime_put_autosuspend(i2c_dev->dev);
2249
2250 return 0;
2251
2252i2c_disable_smbus_host:
2253 stm32f7_i2c_disable_smbus_host(i2c_dev);
2254
2255i2c_adapter_remove:
2256 i2c_del_adapter(adap);
2257
2258pm_disable:
2259 pm_runtime_put_noidle(i2c_dev->dev);
2260 pm_runtime_disable(i2c_dev->dev);
2261 pm_runtime_set_suspended(i2c_dev->dev);
2262 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2263
2264 if (i2c_dev->wakeup_src)
2265 dev_pm_clear_wake_irq(i2c_dev->dev);
2266
2267clr_wakeup_capable:
2268 if (i2c_dev->wakeup_src)
2269 device_set_wakeup_capable(i2c_dev->dev, false);
2270
2271 if (i2c_dev->dma) {
2272 stm32_i2c_dma_free(i2c_dev->dma);
2273 i2c_dev->dma = NULL;
2274 }
2275
2276fmp_clear:
2277 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2278
2279clk_free:
2280 clk_disable_unprepare(i2c_dev->clk);
2281
2282 return ret;
2283}
2284
2285static int stm32f7_i2c_remove(struct platform_device *pdev)
2286{
2287 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2288
2289 stm32f7_i2c_disable_smbus_alert(i2c_dev);
2290 stm32f7_i2c_disable_smbus_host(i2c_dev);
2291
2292 i2c_del_adapter(&i2c_dev->adap);
2293 pm_runtime_get_sync(i2c_dev->dev);
2294
2295 if (i2c_dev->wakeup_src) {
2296 dev_pm_clear_wake_irq(i2c_dev->dev);
2297
2298
2299
2300
2301 device_init_wakeup(i2c_dev->dev, false);
2302 }
2303
2304 pm_runtime_put_noidle(i2c_dev->dev);
2305 pm_runtime_disable(i2c_dev->dev);
2306 pm_runtime_set_suspended(i2c_dev->dev);
2307 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2308
2309 if (i2c_dev->dma) {
2310 stm32_i2c_dma_free(i2c_dev->dma);
2311 i2c_dev->dma = NULL;
2312 }
2313
2314 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2315
2316 clk_disable_unprepare(i2c_dev->clk);
2317
2318 return 0;
2319}
2320
2321static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2322{
2323 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2324
2325 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2326 clk_disable_unprepare(i2c_dev->clk);
2327
2328 return 0;
2329}
2330
2331static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2332{
2333 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2334 int ret;
2335
2336 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2337 ret = clk_prepare_enable(i2c_dev->clk);
2338 if (ret) {
2339 dev_err(dev, "failed to prepare_enable clock\n");
2340 return ret;
2341 }
2342 }
2343
2344 return 0;
2345}
2346
2347static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2348{
2349 int ret;
2350 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2351
2352 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2353 if (ret < 0)
2354 return ret;
2355
2356 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2357 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2358 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2359 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2360 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2361 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2362
2363 pm_runtime_put_sync(i2c_dev->dev);
2364
2365 return ret;
2366}
2367
2368static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2369{
2370 u32 cr1;
2371 int ret;
2372 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2373
2374 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2375 if (ret < 0)
2376 return ret;
2377
2378 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2379 if (cr1 & STM32F7_I2C_CR1_PE)
2380 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2381 STM32F7_I2C_CR1_PE);
2382
2383 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2384 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2385 i2c_dev->base + STM32F7_I2C_CR1);
2386 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2387 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2388 STM32F7_I2C_CR1_PE);
2389 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2390 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2391 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2392 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2393
2394 pm_runtime_put_sync(i2c_dev->dev);
2395
2396 return ret;
2397}
2398
2399static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2400{
2401 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2402 int ret;
2403
2404 i2c_mark_adapter_suspended(&i2c_dev->adap);
2405
2406 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2407 ret = stm32f7_i2c_regs_backup(i2c_dev);
2408 if (ret < 0) {
2409 i2c_mark_adapter_resumed(&i2c_dev->adap);
2410 return ret;
2411 }
2412
2413 pinctrl_pm_select_sleep_state(dev);
2414 pm_runtime_force_suspend(dev);
2415 }
2416
2417 return 0;
2418}
2419
2420static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2421{
2422 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2423 int ret;
2424
2425 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2426 ret = pm_runtime_force_resume(dev);
2427 if (ret < 0)
2428 return ret;
2429 pinctrl_pm_select_default_state(dev);
2430
2431 ret = stm32f7_i2c_regs_restore(i2c_dev);
2432 if (ret < 0)
2433 return ret;
2434 }
2435
2436 i2c_mark_adapter_resumed(&i2c_dev->adap);
2437
2438 return 0;
2439}
2440
2441static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2442 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2443 stm32f7_i2c_runtime_resume, NULL)
2444 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2445};
2446
2447static const struct of_device_id stm32f7_i2c_match[] = {
2448 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2449 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2450 {},
2451};
2452MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2453
2454static struct platform_driver stm32f7_i2c_driver = {
2455 .driver = {
2456 .name = "stm32f7-i2c",
2457 .of_match_table = stm32f7_i2c_match,
2458 .pm = &stm32f7_i2c_pm_ops,
2459 },
2460 .probe = stm32f7_i2c_probe,
2461 .remove = stm32f7_i2c_remove,
2462};
2463
2464module_platform_driver(stm32f7_i2c_driver);
2465
2466MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2467MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2468MODULE_LICENSE("GPL v2");
2469