linux/drivers/iio/adc/ti_am335x_adc.c
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   1/*
   2 * TI ADC MFD driver
   3 *
   4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License as
   8 * published by the Free Software Foundation version 2.
   9 *
  10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11 * kind, whether express or implied; without even the implied warranty
  12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 */
  15
  16#include <linux/kernel.h>
  17#include <linux/err.h>
  18#include <linux/module.h>
  19#include <linux/slab.h>
  20#include <linux/interrupt.h>
  21#include <linux/platform_device.h>
  22#include <linux/io.h>
  23#include <linux/iio/iio.h>
  24#include <linux/of.h>
  25#include <linux/of_device.h>
  26#include <linux/iio/machine.h>
  27#include <linux/iio/driver.h>
  28
  29#include <linux/mfd/ti_am335x_tscadc.h>
  30#include <linux/iio/buffer.h>
  31#include <linux/iio/kfifo_buf.h>
  32
  33#include <linux/dmaengine.h>
  34#include <linux/dma-mapping.h>
  35
  36#define DMA_BUFFER_SIZE         SZ_2K
  37
  38struct tiadc_dma {
  39        struct dma_slave_config conf;
  40        struct dma_chan         *chan;
  41        dma_addr_t              addr;
  42        dma_cookie_t            cookie;
  43        u8                      *buf;
  44        int                     current_period;
  45        int                     period_size;
  46        u8                      fifo_thresh;
  47};
  48
  49struct tiadc_device {
  50        struct ti_tscadc_dev *mfd_tscadc;
  51        struct tiadc_dma dma;
  52        struct mutex fifo1_lock; /* to protect fifo access */
  53        int channels;
  54        int total_ch_enabled;
  55        u8 channel_line[8];
  56        u8 channel_step[8];
  57        int buffer_en_ch_steps;
  58        u16 data[8];
  59        u32 open_delay[8], sample_delay[8], step_avg[8];
  60};
  61
  62static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg)
  63{
  64        return readl(adc->mfd_tscadc->tscadc_base + reg);
  65}
  66
  67static void tiadc_writel(struct tiadc_device *adc, unsigned int reg,
  68                                        unsigned int val)
  69{
  70        writel(val, adc->mfd_tscadc->tscadc_base + reg);
  71}
  72
  73static u32 get_adc_step_mask(struct tiadc_device *adc_dev)
  74{
  75        u32 step_en;
  76
  77        step_en = ((1 << adc_dev->channels) - 1);
  78        step_en <<= TOTAL_STEPS - adc_dev->channels + 1;
  79        return step_en;
  80}
  81
  82static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev,
  83                struct iio_chan_spec const *chan)
  84{
  85        int i;
  86
  87        for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) {
  88                if (chan->channel == adc_dev->channel_line[i]) {
  89                        u32 step;
  90
  91                        step = adc_dev->channel_step[i];
  92                        /* +1 for the charger */
  93                        return 1 << (step + 1);
  94                }
  95        }
  96        WARN_ON(1);
  97        return 0;
  98}
  99
 100static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan)
 101{
 102        return 1 << adc_dev->channel_step[chan];
 103}
 104
 105static void tiadc_step_config(struct iio_dev *indio_dev)
 106{
 107        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 108        struct device *dev = adc_dev->mfd_tscadc->dev;
 109        unsigned int stepconfig;
 110        int i, steps = 0;
 111
 112        /*
 113         * There are 16 configurable steps and 8 analog input
 114         * lines available which are shared between Touchscreen and ADC.
 115         *
 116         * Steps forwards i.e. from 0 towards 16 are used by ADC
 117         * depending on number of input lines needed.
 118         * Channel would represent which analog input
 119         * needs to be given to ADC to digitalize data.
 120         */
 121
 122
 123        for (i = 0; i < adc_dev->channels; i++) {
 124                int chan;
 125
 126                chan = adc_dev->channel_line[i];
 127
 128                if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) {
 129                        dev_warn(dev, "chan %d step_avg truncating to %d\n",
 130                                 chan, STEPCONFIG_AVG_16);
 131                        adc_dev->step_avg[i] = STEPCONFIG_AVG_16;
 132                }
 133
 134                if (adc_dev->step_avg[i])
 135                        stepconfig =
 136                        STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) |
 137                        STEPCONFIG_FIFO1;
 138                else
 139                        stepconfig = STEPCONFIG_FIFO1;
 140
 141                if (iio_buffer_enabled(indio_dev))
 142                        stepconfig |= STEPCONFIG_MODE_SWCNT;
 143
 144                tiadc_writel(adc_dev, REG_STEPCONFIG(steps),
 145                                stepconfig | STEPCONFIG_INP(chan) |
 146                                STEPCONFIG_INM_ADCREFM |
 147                                STEPCONFIG_RFP_VREFP |
 148                                STEPCONFIG_RFM_VREFN);
 149
 150                if (adc_dev->open_delay[i] > STEPDELAY_OPEN_MASK) {
 151                        dev_warn(dev, "chan %d open delay truncating to 0x3FFFF\n",
 152                                 chan);
 153                        adc_dev->open_delay[i] = STEPDELAY_OPEN_MASK;
 154                }
 155
 156                if (adc_dev->sample_delay[i] > 0xFF) {
 157                        dev_warn(dev, "chan %d sample delay truncating to 0xFF\n",
 158                                 chan);
 159                        adc_dev->sample_delay[i] = 0xFF;
 160                }
 161
 162                tiadc_writel(adc_dev, REG_STEPDELAY(steps),
 163                                STEPDELAY_OPEN(adc_dev->open_delay[i]) |
 164                                STEPDELAY_SAMPLE(adc_dev->sample_delay[i]));
 165
 166                adc_dev->channel_step[i] = steps;
 167                steps++;
 168        }
 169}
 170
 171static irqreturn_t tiadc_irq_h(int irq, void *private)
 172{
 173        struct iio_dev *indio_dev = private;
 174        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 175        unsigned int status, config, adc_fsm;
 176        unsigned short count = 0;
 177
 178        status = tiadc_readl(adc_dev, REG_IRQSTATUS);
 179
 180        /*
 181         * ADC and touchscreen share the IRQ line.
 182         * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only
 183         */
 184        if (status & IRQENB_FIFO1OVRRUN) {
 185                /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */
 186                config = tiadc_readl(adc_dev, REG_CTRL);
 187                config &= ~(CNTRLREG_TSCSSENB);
 188                tiadc_writel(adc_dev, REG_CTRL, config);
 189                tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1OVRRUN
 190                                | IRQENB_FIFO1UNDRFLW | IRQENB_FIFO1THRES);
 191
 192                /* wait for idle state.
 193                 * ADC needs to finish the current conversion
 194                 * before disabling the module
 195                 */
 196                do {
 197                        adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM);
 198                } while (adc_fsm != 0x10 && count++ < 100);
 199
 200                tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_TSCSSENB));
 201                return IRQ_HANDLED;
 202        } else if (status & IRQENB_FIFO1THRES) {
 203                /* Disable irq and wake worker thread */
 204                tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES);
 205                return IRQ_WAKE_THREAD;
 206        }
 207
 208        return IRQ_NONE;
 209}
 210
 211static irqreturn_t tiadc_worker_h(int irq, void *private)
 212{
 213        struct iio_dev *indio_dev = private;
 214        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 215        int i, k, fifo1count, read;
 216        u16 *data = adc_dev->data;
 217
 218        fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 219        for (k = 0; k < fifo1count; k = k + i) {
 220                for (i = 0; i < (indio_dev->scan_bytes)/2; i++) {
 221                        read = tiadc_readl(adc_dev, REG_FIFO1);
 222                        data[i] = read & FIFOREAD_DATA_MASK;
 223                }
 224                iio_push_to_buffers(indio_dev, (u8 *) data);
 225        }
 226
 227        tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES);
 228        tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES);
 229
 230        return IRQ_HANDLED;
 231}
 232
 233static void tiadc_dma_rx_complete(void *param)
 234{
 235        struct iio_dev *indio_dev = param;
 236        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 237        struct tiadc_dma *dma = &adc_dev->dma;
 238        u8 *data;
 239        int i;
 240
 241        data = dma->buf + dma->current_period * dma->period_size;
 242        dma->current_period = 1 - dma->current_period; /* swap the buffer ID */
 243
 244        for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) {
 245                iio_push_to_buffers(indio_dev, data);
 246                data += indio_dev->scan_bytes;
 247        }
 248}
 249
 250static int tiadc_start_dma(struct iio_dev *indio_dev)
 251{
 252        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 253        struct tiadc_dma *dma = &adc_dev->dma;
 254        struct dma_async_tx_descriptor *desc;
 255
 256        dma->current_period = 0; /* We start to fill period 0 */
 257        /*
 258         * Make the fifo thresh as the multiple of total number of
 259         * channels enabled, so make sure that cyclic DMA period
 260         * length is also a multiple of total number of channels
 261         * enabled. This ensures that no invalid data is reported
 262         * to the stack via iio_push_to_buffers().
 263         */
 264        dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1,
 265                                     adc_dev->total_ch_enabled) - 1;
 266        /* Make sure that period length is multiple of fifo thresh level */
 267        dma->period_size = rounddown(DMA_BUFFER_SIZE / 2,
 268                                    (dma->fifo_thresh + 1) * sizeof(u16));
 269
 270        dma->conf.src_maxburst = dma->fifo_thresh + 1;
 271        dmaengine_slave_config(dma->chan, &dma->conf);
 272
 273        desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr,
 274                                         dma->period_size * 2,
 275                                         dma->period_size, DMA_DEV_TO_MEM,
 276                                         DMA_PREP_INTERRUPT);
 277        if (!desc)
 278                return -EBUSY;
 279
 280        desc->callback = tiadc_dma_rx_complete;
 281        desc->callback_param = indio_dev;
 282
 283        dma->cookie = dmaengine_submit(desc);
 284
 285        dma_async_issue_pending(dma->chan);
 286
 287        tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh);
 288        tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh);
 289        tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1);
 290
 291        return 0;
 292}
 293
 294static int tiadc_buffer_preenable(struct iio_dev *indio_dev)
 295{
 296        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 297        int i, fifo1count;
 298
 299        tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES |
 300                                IRQENB_FIFO1OVRRUN |
 301                                IRQENB_FIFO1UNDRFLW));
 302
 303        /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */
 304        fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 305        for (i = 0; i < fifo1count; i++)
 306                tiadc_readl(adc_dev, REG_FIFO1);
 307
 308        return 0;
 309}
 310
 311static int tiadc_buffer_postenable(struct iio_dev *indio_dev)
 312{
 313        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 314        struct tiadc_dma *dma = &adc_dev->dma;
 315        unsigned int irq_enable;
 316        unsigned int enb = 0;
 317        u8 bit;
 318
 319        tiadc_step_config(indio_dev);
 320        for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) {
 321                enb |= (get_adc_step_bit(adc_dev, bit) << 1);
 322                adc_dev->total_ch_enabled++;
 323        }
 324        adc_dev->buffer_en_ch_steps = enb;
 325
 326        if (dma->chan)
 327                tiadc_start_dma(indio_dev);
 328
 329        am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb);
 330
 331        tiadc_writel(adc_dev,  REG_IRQSTATUS, IRQENB_FIFO1THRES
 332                                | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW);
 333
 334        irq_enable = IRQENB_FIFO1OVRRUN;
 335        if (!dma->chan)
 336                irq_enable |= IRQENB_FIFO1THRES;
 337        tiadc_writel(adc_dev,  REG_IRQENABLE, irq_enable);
 338
 339        return 0;
 340}
 341
 342static int tiadc_buffer_predisable(struct iio_dev *indio_dev)
 343{
 344        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 345        struct tiadc_dma *dma = &adc_dev->dma;
 346        int fifo1count, i;
 347
 348        tiadc_writel(adc_dev, REG_IRQCLR, (IRQENB_FIFO1THRES |
 349                                IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW));
 350        am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps);
 351        adc_dev->buffer_en_ch_steps = 0;
 352        adc_dev->total_ch_enabled = 0;
 353        if (dma->chan) {
 354                tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2);
 355                dmaengine_terminate_async(dma->chan);
 356        }
 357
 358        /* Flush FIFO of leftover data in the time it takes to disable adc */
 359        fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 360        for (i = 0; i < fifo1count; i++)
 361                tiadc_readl(adc_dev, REG_FIFO1);
 362
 363        return 0;
 364}
 365
 366static int tiadc_buffer_postdisable(struct iio_dev *indio_dev)
 367{
 368        tiadc_step_config(indio_dev);
 369
 370        return 0;
 371}
 372
 373static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = {
 374        .preenable = &tiadc_buffer_preenable,
 375        .postenable = &tiadc_buffer_postenable,
 376        .predisable = &tiadc_buffer_predisable,
 377        .postdisable = &tiadc_buffer_postdisable,
 378};
 379
 380static int tiadc_iio_buffered_hardware_setup(struct device *dev,
 381        struct iio_dev *indio_dev,
 382        irqreturn_t (*pollfunc_bh)(int irq, void *p),
 383        irqreturn_t (*pollfunc_th)(int irq, void *p),
 384        int irq,
 385        unsigned long flags,
 386        const struct iio_buffer_setup_ops *setup_ops)
 387{
 388        int ret;
 389
 390        ret = devm_iio_kfifo_buffer_setup(dev, indio_dev,
 391                                          INDIO_BUFFER_SOFTWARE,
 392                                          setup_ops);
 393        if (ret)
 394                return ret;
 395
 396        return devm_request_threaded_irq(dev, irq, pollfunc_th, pollfunc_bh,
 397                                flags, indio_dev->name, indio_dev);
 398}
 399
 400static const char * const chan_name_ain[] = {
 401        "AIN0",
 402        "AIN1",
 403        "AIN2",
 404        "AIN3",
 405        "AIN4",
 406        "AIN5",
 407        "AIN6",
 408        "AIN7",
 409};
 410
 411static int tiadc_channel_init(struct device *dev, struct iio_dev *indio_dev,
 412                              int channels)
 413{
 414        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 415        struct iio_chan_spec *chan_array;
 416        struct iio_chan_spec *chan;
 417        int i;
 418
 419        indio_dev->num_channels = channels;
 420        chan_array = devm_kcalloc(dev, channels, sizeof(*chan_array),
 421                                  GFP_KERNEL);
 422        if (chan_array == NULL)
 423                return -ENOMEM;
 424
 425        chan = chan_array;
 426        for (i = 0; i < channels; i++, chan++) {
 427
 428                chan->type = IIO_VOLTAGE;
 429                chan->indexed = 1;
 430                chan->channel = adc_dev->channel_line[i];
 431                chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
 432                chan->datasheet_name = chan_name_ain[chan->channel];
 433                chan->scan_index = i;
 434                chan->scan_type.sign = 'u';
 435                chan->scan_type.realbits = 12;
 436                chan->scan_type.storagebits = 16;
 437        }
 438
 439        indio_dev->channels = chan_array;
 440
 441        return 0;
 442}
 443
 444static int tiadc_read_raw(struct iio_dev *indio_dev,
 445                struct iio_chan_spec const *chan,
 446                int *val, int *val2, long mask)
 447{
 448        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 449        int ret = IIO_VAL_INT;
 450        int i, map_val;
 451        unsigned int fifo1count, read, stepid;
 452        bool found = false;
 453        u32 step_en;
 454        unsigned long timeout;
 455
 456        if (iio_buffer_enabled(indio_dev))
 457                return -EBUSY;
 458
 459        step_en = get_adc_chan_step_mask(adc_dev, chan);
 460        if (!step_en)
 461                return -EINVAL;
 462
 463        mutex_lock(&adc_dev->fifo1_lock);
 464        fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 465        while (fifo1count--)
 466                tiadc_readl(adc_dev, REG_FIFO1);
 467
 468        am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en);
 469
 470        timeout = jiffies + msecs_to_jiffies
 471                                (IDLE_TIMEOUT * adc_dev->channels);
 472        /* Wait for Fifo threshold interrupt */
 473        while (1) {
 474                fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
 475                if (fifo1count)
 476                        break;
 477
 478                if (time_after(jiffies, timeout)) {
 479                        am335x_tsc_se_adc_done(adc_dev->mfd_tscadc);
 480                        ret = -EAGAIN;
 481                        goto err_unlock;
 482                }
 483        }
 484        map_val = adc_dev->channel_step[chan->scan_index];
 485
 486        /*
 487         * We check the complete FIFO. We programmed just one entry but in case
 488         * something went wrong we left empty handed (-EAGAIN previously) and
 489         * then the value apeared somehow in the FIFO we would have two entries.
 490         * Therefore we read every item and keep only the latest version of the
 491         * requested channel.
 492         */
 493        for (i = 0; i < fifo1count; i++) {
 494                read = tiadc_readl(adc_dev, REG_FIFO1);
 495                stepid = read & FIFOREAD_CHNLID_MASK;
 496                stepid = stepid >> 0x10;
 497
 498                if (stepid == map_val) {
 499                        read = read & FIFOREAD_DATA_MASK;
 500                        found = true;
 501                        *val = (u16) read;
 502                }
 503        }
 504        am335x_tsc_se_adc_done(adc_dev->mfd_tscadc);
 505
 506        if (!found)
 507                ret =  -EBUSY;
 508
 509err_unlock:
 510        mutex_unlock(&adc_dev->fifo1_lock);
 511        return ret;
 512}
 513
 514static const struct iio_info tiadc_info = {
 515        .read_raw = &tiadc_read_raw,
 516};
 517
 518static int tiadc_request_dma(struct platform_device *pdev,
 519                             struct tiadc_device *adc_dev)
 520{
 521        struct tiadc_dma        *dma = &adc_dev->dma;
 522        dma_cap_mask_t          mask;
 523
 524        /* Default slave configuration parameters */
 525        dma->conf.direction = DMA_DEV_TO_MEM;
 526        dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 527        dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1;
 528
 529        dma_cap_zero(mask);
 530        dma_cap_set(DMA_CYCLIC, mask);
 531
 532        /* Get a channel for RX */
 533        dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1");
 534        if (IS_ERR(dma->chan)) {
 535                int ret = PTR_ERR(dma->chan);
 536
 537                dma->chan = NULL;
 538                return ret;
 539        }
 540
 541        /* RX buffer */
 542        dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
 543                                      &dma->addr, GFP_KERNEL);
 544        if (!dma->buf)
 545                goto err;
 546
 547        return 0;
 548err:
 549        dma_release_channel(dma->chan);
 550        return -ENOMEM;
 551}
 552
 553static int tiadc_parse_dt(struct platform_device *pdev,
 554                          struct tiadc_device *adc_dev)
 555{
 556        struct device_node *node = pdev->dev.of_node;
 557        struct property *prop;
 558        const __be32 *cur;
 559        int channels = 0;
 560        u32 val;
 561
 562        of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
 563                adc_dev->channel_line[channels] = val;
 564
 565                /* Set Default values for optional DT parameters */
 566                adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY;
 567                adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY;
 568                adc_dev->step_avg[channels] = 16;
 569
 570                channels++;
 571        }
 572
 573        of_property_read_u32_array(node, "ti,chan-step-avg",
 574                                   adc_dev->step_avg, channels);
 575        of_property_read_u32_array(node, "ti,chan-step-opendelay",
 576                                   adc_dev->open_delay, channels);
 577        of_property_read_u32_array(node, "ti,chan-step-sampledelay",
 578                                   adc_dev->sample_delay, channels);
 579
 580        adc_dev->channels = channels;
 581        return 0;
 582}
 583
 584static int tiadc_probe(struct platform_device *pdev)
 585{
 586        struct iio_dev          *indio_dev;
 587        struct tiadc_device     *adc_dev;
 588        struct device_node      *node = pdev->dev.of_node;
 589        int                     err;
 590
 591        if (!node) {
 592                dev_err(&pdev->dev, "Could not find valid DT data.\n");
 593                return -EINVAL;
 594        }
 595
 596        indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
 597        if (indio_dev == NULL) {
 598                dev_err(&pdev->dev, "failed to allocate iio device\n");
 599                return -ENOMEM;
 600        }
 601        adc_dev = iio_priv(indio_dev);
 602
 603        adc_dev->mfd_tscadc = ti_tscadc_dev_get(pdev);
 604        tiadc_parse_dt(pdev, adc_dev);
 605
 606        indio_dev->name = dev_name(&pdev->dev);
 607        indio_dev->modes = INDIO_DIRECT_MODE;
 608        indio_dev->info = &tiadc_info;
 609
 610        tiadc_step_config(indio_dev);
 611        tiadc_writel(adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD);
 612        mutex_init(&adc_dev->fifo1_lock);
 613
 614        err = tiadc_channel_init(&pdev->dev, indio_dev, adc_dev->channels);
 615        if (err < 0)
 616                return err;
 617
 618        err = tiadc_iio_buffered_hardware_setup(&pdev->dev, indio_dev,
 619                &tiadc_worker_h,
 620                &tiadc_irq_h,
 621                adc_dev->mfd_tscadc->irq,
 622                IRQF_SHARED,
 623                &tiadc_buffer_setup_ops);
 624
 625        if (err)
 626                goto err_free_channels;
 627
 628        err = iio_device_register(indio_dev);
 629        if (err)
 630                goto err_buffer_unregister;
 631
 632        platform_set_drvdata(pdev, indio_dev);
 633
 634        err = tiadc_request_dma(pdev, adc_dev);
 635        if (err && err == -EPROBE_DEFER)
 636                goto err_dma;
 637
 638        return 0;
 639
 640err_dma:
 641        iio_device_unregister(indio_dev);
 642err_buffer_unregister:
 643err_free_channels:
 644        return err;
 645}
 646
 647static int tiadc_remove(struct platform_device *pdev)
 648{
 649        struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 650        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 651        struct tiadc_dma *dma = &adc_dev->dma;
 652        u32 step_en;
 653
 654        if (dma->chan) {
 655                dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE,
 656                                  dma->buf, dma->addr);
 657                dma_release_channel(dma->chan);
 658        }
 659        iio_device_unregister(indio_dev);
 660
 661        step_en = get_adc_step_mask(adc_dev);
 662        am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en);
 663
 664        return 0;
 665}
 666
 667static int __maybe_unused tiadc_suspend(struct device *dev)
 668{
 669        struct iio_dev *indio_dev = dev_get_drvdata(dev);
 670        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 671        unsigned int idle;
 672
 673        idle = tiadc_readl(adc_dev, REG_CTRL);
 674        idle &= ~(CNTRLREG_TSCSSENB);
 675        tiadc_writel(adc_dev, REG_CTRL, (idle |
 676                        CNTRLREG_POWERDOWN));
 677
 678        return 0;
 679}
 680
 681static int __maybe_unused tiadc_resume(struct device *dev)
 682{
 683        struct iio_dev *indio_dev = dev_get_drvdata(dev);
 684        struct tiadc_device *adc_dev = iio_priv(indio_dev);
 685        unsigned int restore;
 686
 687        /* Make sure ADC is powered up */
 688        restore = tiadc_readl(adc_dev, REG_CTRL);
 689        restore &= ~(CNTRLREG_POWERDOWN);
 690        tiadc_writel(adc_dev, REG_CTRL, restore);
 691
 692        tiadc_step_config(indio_dev);
 693        am335x_tsc_se_set_cache(adc_dev->mfd_tscadc,
 694                        adc_dev->buffer_en_ch_steps);
 695        return 0;
 696}
 697
 698static SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume);
 699
 700static const struct of_device_id ti_adc_dt_ids[] = {
 701        { .compatible = "ti,am3359-adc", },
 702        { }
 703};
 704MODULE_DEVICE_TABLE(of, ti_adc_dt_ids);
 705
 706static struct platform_driver tiadc_driver = {
 707        .driver = {
 708                .name   = "TI-am335x-adc",
 709                .pm     = &tiadc_pm_ops,
 710                .of_match_table = ti_adc_dt_ids,
 711        },
 712        .probe  = tiadc_probe,
 713        .remove = tiadc_remove,
 714};
 715module_platform_driver(tiadc_driver);
 716
 717MODULE_DESCRIPTION("TI ADC controller driver");
 718MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
 719MODULE_LICENSE("GPL");
 720