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48#include <linux/pci.h>
49#include <linux/netdevice.h>
50#include <linux/vmalloc.h>
51#include <linux/delay.h>
52#include <linux/xarray.h>
53#include <linux/module.h>
54#include <linux/printk.h>
55#include <linux/hrtimer.h>
56#include <linux/bitmap.h>
57#include <linux/numa.h>
58#include <rdma/rdma_vt.h>
59
60#include "hfi.h"
61#include "device.h"
62#include "common.h"
63#include "trace.h"
64#include "mad.h"
65#include "sdma.h"
66#include "debugfs.h"
67#include "verbs.h"
68#include "aspm.h"
69#include "affinity.h"
70#include "vnic.h"
71#include "exp_rcv.h"
72#include "netdev.h"
73
74#undef pr_fmt
75#define pr_fmt(fmt) DRIVER_NAME ": " fmt
76
77
78
79
80#define HFI1_MIN_USER_CTXT_BUFCNT 7
81
82#define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024)
83#define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024)
84
85#define NUM_IB_PORTS 1
86
87
88
89
90
91int num_user_contexts = -1;
92module_param_named(num_user_contexts, num_user_contexts, int, 0444);
93MODULE_PARM_DESC(
94 num_user_contexts, "Set max number of user contexts to use (default: -1 will use the real (non-HT) CPU count)");
95
96uint krcvqs[RXE_NUM_DATA_VL];
97int krcvqsset;
98module_param_array(krcvqs, uint, &krcvqsset, S_IRUGO);
99MODULE_PARM_DESC(krcvqs, "Array of the number of non-control kernel receive queues by VL");
100
101
102unsigned long n_krcvqs;
103
104static unsigned hfi1_rcvarr_split = 25;
105module_param_named(rcvarr_split, hfi1_rcvarr_split, uint, S_IRUGO);
106MODULE_PARM_DESC(rcvarr_split, "Percent of context's RcvArray entries used for Eager buffers");
107
108static uint eager_buffer_size = (8 << 20);
109module_param(eager_buffer_size, uint, S_IRUGO);
110MODULE_PARM_DESC(eager_buffer_size, "Size of the eager buffers, default: 8MB");
111
112static uint rcvhdrcnt = 2048;
113module_param_named(rcvhdrcnt, rcvhdrcnt, uint, S_IRUGO);
114MODULE_PARM_DESC(rcvhdrcnt, "Receive header queue count (default 2048)");
115
116static uint hfi1_hdrq_entsize = 32;
117module_param_named(hdrq_entsize, hfi1_hdrq_entsize, uint, 0444);
118MODULE_PARM_DESC(hdrq_entsize, "Size of header queue entries: 2 - 8B, 16 - 64B, 32 - 128B (default)");
119
120unsigned int user_credit_return_threshold = 33;
121module_param(user_credit_return_threshold, uint, S_IRUGO);
122MODULE_PARM_DESC(user_credit_return_threshold, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)");
123
124DEFINE_XARRAY_FLAGS(hfi1_dev_table, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
125
126static int hfi1_create_kctxt(struct hfi1_devdata *dd,
127 struct hfi1_pportdata *ppd)
128{
129 struct hfi1_ctxtdata *rcd;
130 int ret;
131
132
133 BUILD_BUG_ON(HFI1_CTRL_CTXT != 0);
134
135 ret = hfi1_create_ctxtdata(ppd, dd->node, &rcd);
136 if (ret < 0) {
137 dd_dev_err(dd, "Kernel receive context allocation failed\n");
138 return ret;
139 }
140
141
142
143
144
145
146 rcd->flags = HFI1_CAP_KGET(MULTI_PKT_EGR) |
147 HFI1_CAP_KGET(NODROP_RHQ_FULL) |
148 HFI1_CAP_KGET(NODROP_EGR_FULL) |
149 HFI1_CAP_KGET(DMA_RTAIL);
150
151
152 if (rcd->ctxt == HFI1_CTRL_CTXT)
153 rcd->flags |= HFI1_CAP_DMA_RTAIL;
154 rcd->fast_handler = get_dma_rtail_setting(rcd) ?
155 handle_receive_interrupt_dma_rtail :
156 handle_receive_interrupt_nodma_rtail;
157 rcd->slow_handler = handle_receive_interrupt;
158
159 hfi1_set_seq_cnt(rcd, 1);
160
161 rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node);
162 if (!rcd->sc) {
163 dd_dev_err(dd, "Kernel send context allocation failed\n");
164 return -ENOMEM;
165 }
166 hfi1_init_ctxt(rcd->sc);
167
168 return 0;
169}
170
171
172
173
174int hfi1_create_kctxts(struct hfi1_devdata *dd)
175{
176 u16 i;
177 int ret;
178
179 dd->rcd = kcalloc_node(dd->num_rcv_contexts, sizeof(*dd->rcd),
180 GFP_KERNEL, dd->node);
181 if (!dd->rcd)
182 return -ENOMEM;
183
184 for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) {
185 ret = hfi1_create_kctxt(dd, dd->pport);
186 if (ret)
187 goto bail;
188 }
189
190 return 0;
191bail:
192 for (i = 0; dd->rcd && i < dd->first_dyn_alloc_ctxt; ++i)
193 hfi1_free_ctxt(dd->rcd[i]);
194
195
196 kfree(dd->rcd);
197 dd->rcd = NULL;
198 return ret;
199}
200
201
202
203
204static void hfi1_rcd_init(struct hfi1_ctxtdata *rcd)
205{
206 kref_init(&rcd->kref);
207}
208
209
210
211
212
213
214static void hfi1_rcd_free(struct kref *kref)
215{
216 unsigned long flags;
217 struct hfi1_ctxtdata *rcd =
218 container_of(kref, struct hfi1_ctxtdata, kref);
219
220 spin_lock_irqsave(&rcd->dd->uctxt_lock, flags);
221 rcd->dd->rcd[rcd->ctxt] = NULL;
222 spin_unlock_irqrestore(&rcd->dd->uctxt_lock, flags);
223
224 hfi1_free_ctxtdata(rcd->dd, rcd);
225
226 kfree(rcd);
227}
228
229
230
231
232
233
234
235int hfi1_rcd_put(struct hfi1_ctxtdata *rcd)
236{
237 if (rcd)
238 return kref_put(&rcd->kref, hfi1_rcd_free);
239
240 return 0;
241}
242
243
244
245
246
247
248
249
250
251
252int hfi1_rcd_get(struct hfi1_ctxtdata *rcd)
253{
254 return kref_get_unless_zero(&rcd->kref);
255}
256
257
258
259
260
261
262
263
264
265
266
267static int allocate_rcd_index(struct hfi1_devdata *dd,
268 struct hfi1_ctxtdata *rcd, u16 *index)
269{
270 unsigned long flags;
271 u16 ctxt;
272
273 spin_lock_irqsave(&dd->uctxt_lock, flags);
274 for (ctxt = 0; ctxt < dd->num_rcv_contexts; ctxt++)
275 if (!dd->rcd[ctxt])
276 break;
277
278 if (ctxt < dd->num_rcv_contexts) {
279 rcd->ctxt = ctxt;
280 dd->rcd[ctxt] = rcd;
281 hfi1_rcd_init(rcd);
282 }
283 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
284
285 if (ctxt >= dd->num_rcv_contexts)
286 return -EBUSY;
287
288 *index = ctxt;
289
290 return 0;
291}
292
293
294
295
296
297
298
299
300
301
302
303
304
305struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
306 u16 ctxt)
307{
308 if (ctxt < dd->num_rcv_contexts)
309 return hfi1_rcd_get_by_index(dd, ctxt);
310
311 return NULL;
312}
313
314
315
316
317
318
319
320
321
322
323
324
325
326struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt)
327{
328 unsigned long flags;
329 struct hfi1_ctxtdata *rcd = NULL;
330
331 spin_lock_irqsave(&dd->uctxt_lock, flags);
332 if (dd->rcd[ctxt]) {
333 rcd = dd->rcd[ctxt];
334 if (!hfi1_rcd_get(rcd))
335 rcd = NULL;
336 }
337 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
338
339 return rcd;
340}
341
342
343
344
345
346int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
347 struct hfi1_ctxtdata **context)
348{
349 struct hfi1_devdata *dd = ppd->dd;
350 struct hfi1_ctxtdata *rcd;
351 unsigned kctxt_ngroups = 0;
352 u32 base;
353
354 if (dd->rcv_entries.nctxt_extra >
355 dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt)
356 kctxt_ngroups = (dd->rcv_entries.nctxt_extra -
357 (dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt));
358 rcd = kzalloc_node(sizeof(*rcd), GFP_KERNEL, numa);
359 if (rcd) {
360 u32 rcvtids, max_entries;
361 u16 ctxt;
362 int ret;
363
364 ret = allocate_rcd_index(dd, rcd, &ctxt);
365 if (ret) {
366 *context = NULL;
367 kfree(rcd);
368 return ret;
369 }
370
371 INIT_LIST_HEAD(&rcd->qp_wait_list);
372 hfi1_exp_tid_group_init(rcd);
373 rcd->ppd = ppd;
374 rcd->dd = dd;
375 rcd->numa_id = numa;
376 rcd->rcv_array_groups = dd->rcv_entries.ngroups;
377 rcd->rhf_rcv_function_map = normal_rhf_rcv_functions;
378 rcd->msix_intr = CCE_NUM_MSIX_VECTORS;
379
380 mutex_init(&rcd->exp_mutex);
381 spin_lock_init(&rcd->exp_lock);
382 INIT_LIST_HEAD(&rcd->flow_queue.queue_head);
383 INIT_LIST_HEAD(&rcd->rarr_queue.queue_head);
384
385 hfi1_cdbg(PROC, "setting up context %u\n", rcd->ctxt);
386
387
388
389
390
391
392
393
394 if (ctxt < dd->first_dyn_alloc_ctxt) {
395 if (ctxt < kctxt_ngroups) {
396 base = ctxt * (dd->rcv_entries.ngroups + 1);
397 rcd->rcv_array_groups++;
398 } else {
399 base = kctxt_ngroups +
400 (ctxt * dd->rcv_entries.ngroups);
401 }
402 } else {
403 u16 ct = ctxt - dd->first_dyn_alloc_ctxt;
404
405 base = ((dd->n_krcv_queues * dd->rcv_entries.ngroups) +
406 kctxt_ngroups);
407 if (ct < dd->rcv_entries.nctxt_extra) {
408 base += ct * (dd->rcv_entries.ngroups + 1);
409 rcd->rcv_array_groups++;
410 } else {
411 base += dd->rcv_entries.nctxt_extra +
412 (ct * dd->rcv_entries.ngroups);
413 }
414 }
415 rcd->eager_base = base * dd->rcv_entries.group_size;
416
417 rcd->rcvhdrq_cnt = rcvhdrcnt;
418 rcd->rcvhdrqentsize = hfi1_hdrq_entsize;
419 rcd->rhf_offset =
420 rcd->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
421
422
423
424
425
426
427
428
429
430
431
432 max_entries = rcd->rcv_array_groups *
433 dd->rcv_entries.group_size;
434 rcvtids = ((max_entries * hfi1_rcvarr_split) / 100);
435 rcd->egrbufs.count = round_down(rcvtids,
436 dd->rcv_entries.group_size);
437 if (rcd->egrbufs.count > MAX_EAGER_ENTRIES) {
438 dd_dev_err(dd, "ctxt%u: requested too many RcvArray entries.\n",
439 rcd->ctxt);
440 rcd->egrbufs.count = MAX_EAGER_ENTRIES;
441 }
442 hfi1_cdbg(PROC,
443 "ctxt%u: max Eager buffer RcvArray entries: %u\n",
444 rcd->ctxt, rcd->egrbufs.count);
445
446
447
448
449
450
451
452
453
454 rcd->egrbufs.buffers =
455 kcalloc_node(rcd->egrbufs.count,
456 sizeof(*rcd->egrbufs.buffers),
457 GFP_KERNEL, numa);
458 if (!rcd->egrbufs.buffers)
459 goto bail;
460 rcd->egrbufs.rcvtids =
461 kcalloc_node(rcd->egrbufs.count,
462 sizeof(*rcd->egrbufs.rcvtids),
463 GFP_KERNEL, numa);
464 if (!rcd->egrbufs.rcvtids)
465 goto bail;
466 rcd->egrbufs.size = eager_buffer_size;
467
468
469
470
471
472 if (rcd->egrbufs.size < hfi1_max_mtu) {
473 rcd->egrbufs.size = __roundup_pow_of_two(hfi1_max_mtu);
474 hfi1_cdbg(PROC,
475 "ctxt%u: eager bufs size too small. Adjusting to %u\n",
476 rcd->ctxt, rcd->egrbufs.size);
477 }
478 rcd->egrbufs.rcvtid_size = HFI1_MAX_EAGER_BUFFER_SIZE;
479
480
481 if (ctxt < dd->first_dyn_alloc_ctxt) {
482 rcd->opstats = kzalloc_node(sizeof(*rcd->opstats),
483 GFP_KERNEL, numa);
484 if (!rcd->opstats)
485 goto bail;
486
487
488 hfi1_kern_init_ctxt_generations(rcd);
489 }
490
491 *context = rcd;
492 return 0;
493 }
494
495bail:
496 *context = NULL;
497 hfi1_free_ctxt(rcd);
498 return -ENOMEM;
499}
500
501
502
503
504
505
506
507
508
509
510
511void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd)
512{
513 hfi1_rcd_put(rcd);
514}
515
516
517
518
519
520
521
522
523void set_link_ipg(struct hfi1_pportdata *ppd)
524{
525 struct hfi1_devdata *dd = ppd->dd;
526 struct cc_state *cc_state;
527 int i;
528 u16 cce, ccti_limit, max_ccti = 0;
529 u16 shift, mult;
530 u64 src;
531 u32 current_egress_rate;
532 u32 max_pkt_time;
533
534
535
536
537
538 cc_state = get_cc_state(ppd);
539
540 if (!cc_state)
541
542
543
544
545
546 return;
547
548 for (i = 0; i < OPA_MAX_SLS; i++) {
549 u16 ccti = ppd->cca_timer[i].ccti;
550
551 if (ccti > max_ccti)
552 max_ccti = ccti;
553 }
554
555 ccti_limit = cc_state->cct.ccti_limit;
556 if (max_ccti > ccti_limit)
557 max_ccti = ccti_limit;
558
559 cce = cc_state->cct.entries[max_ccti].entry;
560 shift = (cce & 0xc000) >> 14;
561 mult = (cce & 0x3fff);
562
563 current_egress_rate = active_egress_rate(ppd);
564
565 max_pkt_time = egress_cycles(ppd->ibmaxlen, current_egress_rate);
566
567 src = (max_pkt_time >> shift) * mult;
568
569 src &= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK;
570 src <<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT;
571
572 write_csr(dd, SEND_STATIC_RATE_CONTROL, src);
573}
574
575static enum hrtimer_restart cca_timer_fn(struct hrtimer *t)
576{
577 struct cca_timer *cca_timer;
578 struct hfi1_pportdata *ppd;
579 int sl;
580 u16 ccti_timer, ccti_min;
581 struct cc_state *cc_state;
582 unsigned long flags;
583 enum hrtimer_restart ret = HRTIMER_NORESTART;
584
585 cca_timer = container_of(t, struct cca_timer, hrtimer);
586 ppd = cca_timer->ppd;
587 sl = cca_timer->sl;
588
589 rcu_read_lock();
590
591 cc_state = get_cc_state(ppd);
592
593 if (!cc_state) {
594 rcu_read_unlock();
595 return HRTIMER_NORESTART;
596 }
597
598
599
600
601
602
603
604 ccti_min = cc_state->cong_setting.entries[sl].ccti_min;
605 ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer;
606
607 spin_lock_irqsave(&ppd->cca_timer_lock, flags);
608
609 if (cca_timer->ccti > ccti_min) {
610 cca_timer->ccti--;
611 set_link_ipg(ppd);
612 }
613
614 if (cca_timer->ccti > ccti_min) {
615 unsigned long nsec = 1024 * ccti_timer;
616
617 hrtimer_forward_now(t, ns_to_ktime(nsec));
618 ret = HRTIMER_RESTART;
619 }
620
621 spin_unlock_irqrestore(&ppd->cca_timer_lock, flags);
622 rcu_read_unlock();
623 return ret;
624}
625
626
627
628
629void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
630 struct hfi1_devdata *dd, u8 hw_pidx, u32 port)
631{
632 int i;
633 uint default_pkey_idx;
634 struct cc_state *cc_state;
635
636 ppd->dd = dd;
637 ppd->hw_pidx = hw_pidx;
638 ppd->port = port;
639 ppd->prev_link_width = LINK_WIDTH_DEFAULT;
640
641
642
643
644 for (i = 0; i < C_VL_COUNT + 1; i++) {
645 ppd->port_vl_xmit_wait_last[i] = 0;
646 ppd->vl_xmit_flit_cnt[i] = 0;
647 }
648
649 default_pkey_idx = 1;
650
651 ppd->pkeys[default_pkey_idx] = DEFAULT_P_KEY;
652 ppd->part_enforce |= HFI1_PART_ENFORCE_IN;
653
654 if (loopback) {
655 dd_dev_err(dd, "Faking data partition 0x8001 in idx %u\n",
656 !default_pkey_idx);
657 ppd->pkeys[!default_pkey_idx] = 0x8001;
658 }
659
660 INIT_WORK(&ppd->link_vc_work, handle_verify_cap);
661 INIT_WORK(&ppd->link_up_work, handle_link_up);
662 INIT_WORK(&ppd->link_down_work, handle_link_down);
663 INIT_WORK(&ppd->freeze_work, handle_freeze);
664 INIT_WORK(&ppd->link_downgrade_work, handle_link_downgrade);
665 INIT_WORK(&ppd->sma_message_work, handle_sma_message);
666 INIT_WORK(&ppd->link_bounce_work, handle_link_bounce);
667 INIT_DELAYED_WORK(&ppd->start_link_work, handle_start_link);
668 INIT_WORK(&ppd->linkstate_active_work, receive_interrupt_work);
669 INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event);
670
671 mutex_init(&ppd->hls_lock);
672 spin_lock_init(&ppd->qsfp_info.qsfp_lock);
673
674 ppd->qsfp_info.ppd = ppd;
675 ppd->sm_trap_qp = 0x0;
676 ppd->sa_qp = 0x1;
677
678 ppd->hfi1_wq = NULL;
679
680 spin_lock_init(&ppd->cca_timer_lock);
681
682 for (i = 0; i < OPA_MAX_SLS; i++) {
683 hrtimer_init(&ppd->cca_timer[i].hrtimer, CLOCK_MONOTONIC,
684 HRTIMER_MODE_REL);
685 ppd->cca_timer[i].ppd = ppd;
686 ppd->cca_timer[i].sl = i;
687 ppd->cca_timer[i].ccti = 0;
688 ppd->cca_timer[i].hrtimer.function = cca_timer_fn;
689 }
690
691 ppd->cc_max_table_entries = IB_CC_TABLE_CAP_DEFAULT;
692
693 spin_lock_init(&ppd->cc_state_lock);
694 spin_lock_init(&ppd->cc_log_lock);
695 cc_state = kzalloc(sizeof(*cc_state), GFP_KERNEL);
696 RCU_INIT_POINTER(ppd->cc_state, cc_state);
697 if (!cc_state)
698 goto bail;
699 return;
700
701bail:
702 dd_dev_err(dd, "Congestion Control Agent disabled for port %d\n", port);
703}
704
705
706
707
708
709static int loadtime_init(struct hfi1_devdata *dd)
710{
711 return 0;
712}
713
714
715
716
717
718
719
720
721
722static int init_after_reset(struct hfi1_devdata *dd)
723{
724 int i;
725 struct hfi1_ctxtdata *rcd;
726
727
728
729
730
731 for (i = 0; i < dd->num_rcv_contexts; i++) {
732 rcd = hfi1_rcd_get_by_index(dd, i);
733 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS |
734 HFI1_RCVCTRL_INTRAVAIL_DIS |
735 HFI1_RCVCTRL_TAILUPD_DIS, rcd);
736 hfi1_rcd_put(rcd);
737 }
738 pio_send_control(dd, PSC_GLOBAL_DISABLE);
739 for (i = 0; i < dd->num_send_contexts; i++)
740 sc_disable(dd->send_contexts[i].sc);
741
742 return 0;
743}
744
745static void enable_chip(struct hfi1_devdata *dd)
746{
747 struct hfi1_ctxtdata *rcd;
748 u32 rcvmask;
749 u16 i;
750
751
752 pio_send_control(dd, PSC_GLOBAL_ENABLE);
753
754
755
756
757
758 for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) {
759 rcd = hfi1_rcd_get_by_index(dd, i);
760 if (!rcd)
761 continue;
762 rcvmask = HFI1_RCVCTRL_CTXT_ENB | HFI1_RCVCTRL_INTRAVAIL_ENB;
763 rcvmask |= HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ?
764 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
765 if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR))
766 rcvmask |= HFI1_RCVCTRL_ONE_PKT_EGR_ENB;
767 if (HFI1_CAP_KGET_MASK(rcd->flags, NODROP_RHQ_FULL))
768 rcvmask |= HFI1_RCVCTRL_NO_RHQ_DROP_ENB;
769 if (HFI1_CAP_KGET_MASK(rcd->flags, NODROP_EGR_FULL))
770 rcvmask |= HFI1_RCVCTRL_NO_EGR_DROP_ENB;
771 if (HFI1_CAP_IS_KSET(TID_RDMA))
772 rcvmask |= HFI1_RCVCTRL_TIDFLOW_ENB;
773 hfi1_rcvctrl(dd, rcvmask, rcd);
774 sc_enable(rcd->sc);
775 hfi1_rcd_put(rcd);
776 }
777}
778
779
780
781
782
783static int create_workqueues(struct hfi1_devdata *dd)
784{
785 int pidx;
786 struct hfi1_pportdata *ppd;
787
788 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
789 ppd = dd->pport + pidx;
790 if (!ppd->hfi1_wq) {
791 ppd->hfi1_wq =
792 alloc_workqueue(
793 "hfi%d_%d",
794 WQ_SYSFS | WQ_HIGHPRI | WQ_CPU_INTENSIVE |
795 WQ_MEM_RECLAIM,
796 HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES,
797 dd->unit, pidx);
798 if (!ppd->hfi1_wq)
799 goto wq_error;
800 }
801 if (!ppd->link_wq) {
802
803
804
805
806 ppd->link_wq =
807 alloc_workqueue(
808 "hfi_link_%d_%d",
809 WQ_SYSFS | WQ_MEM_RECLAIM | WQ_UNBOUND,
810 1,
811 dd->unit, pidx);
812 if (!ppd->link_wq)
813 goto wq_error;
814 }
815 }
816 return 0;
817wq_error:
818 pr_err("alloc_workqueue failed for port %d\n", pidx + 1);
819 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
820 ppd = dd->pport + pidx;
821 if (ppd->hfi1_wq) {
822 destroy_workqueue(ppd->hfi1_wq);
823 ppd->hfi1_wq = NULL;
824 }
825 if (ppd->link_wq) {
826 destroy_workqueue(ppd->link_wq);
827 ppd->link_wq = NULL;
828 }
829 }
830 return -ENOMEM;
831}
832
833
834
835
836
837static void destroy_workqueues(struct hfi1_devdata *dd)
838{
839 int pidx;
840 struct hfi1_pportdata *ppd;
841
842 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
843 ppd = dd->pport + pidx;
844
845 if (ppd->hfi1_wq) {
846 destroy_workqueue(ppd->hfi1_wq);
847 ppd->hfi1_wq = NULL;
848 }
849 if (ppd->link_wq) {
850 destroy_workqueue(ppd->link_wq);
851 ppd->link_wq = NULL;
852 }
853 }
854}
855
856
857
858
859
860
861
862static void enable_general_intr(struct hfi1_devdata *dd)
863{
864 set_intr_bits(dd, CCE_ERR_INT, MISC_ERR_INT, true);
865 set_intr_bits(dd, PIO_ERR_INT, TXE_ERR_INT, true);
866 set_intr_bits(dd, IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END, true);
867 set_intr_bits(dd, PBC_INT, GPIO_ASSERT_INT, true);
868 set_intr_bits(dd, TCRIT_INT, TCRIT_INT, true);
869 set_intr_bits(dd, IS_DC_START, IS_DC_END, true);
870 set_intr_bits(dd, IS_SENDCREDIT_START, IS_SENDCREDIT_END, true);
871}
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888int hfi1_init(struct hfi1_devdata *dd, int reinit)
889{
890 int ret = 0, pidx, lastfail = 0;
891 unsigned long len;
892 u16 i;
893 struct hfi1_ctxtdata *rcd;
894 struct hfi1_pportdata *ppd;
895
896
897 dd->process_pio_send = hfi1_verbs_send_pio;
898 dd->process_dma_send = hfi1_verbs_send_dma;
899 dd->pio_inline_send = pio_copy;
900 dd->process_vnic_dma_send = hfi1_vnic_send_dma;
901
902 if (is_ax(dd)) {
903 atomic_set(&dd->drop_packet, DROP_PACKET_ON);
904 dd->do_drop = true;
905 } else {
906 atomic_set(&dd->drop_packet, DROP_PACKET_OFF);
907 dd->do_drop = false;
908 }
909
910
911 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
912 ppd = dd->pport + pidx;
913 ppd->linkup = 0;
914 }
915
916 if (reinit)
917 ret = init_after_reset(dd);
918 else
919 ret = loadtime_init(dd);
920 if (ret)
921 goto done;
922
923
924 dd->rcvhdrtail_dummy_kvaddr = dma_alloc_coherent(&dd->pcidev->dev,
925 sizeof(u64),
926 &dd->rcvhdrtail_dummy_dma,
927 GFP_KERNEL);
928
929 if (!dd->rcvhdrtail_dummy_kvaddr) {
930 dd_dev_err(dd, "cannot allocate dummy tail memory\n");
931 ret = -ENOMEM;
932 goto done;
933 }
934
935
936 for (i = 0; dd->rcd && i < dd->first_dyn_alloc_ctxt; ++i) {
937
938
939
940
941
942
943 rcd = hfi1_rcd_get_by_index(dd, i);
944 if (!rcd)
945 continue;
946
947 rcd->do_interrupt = &handle_receive_interrupt;
948
949 lastfail = hfi1_create_rcvhdrq(dd, rcd);
950 if (!lastfail)
951 lastfail = hfi1_setup_eagerbufs(rcd);
952 if (!lastfail)
953 lastfail = hfi1_kern_exp_rcv_init(rcd, reinit);
954 if (lastfail) {
955 dd_dev_err(dd,
956 "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
957 ret = lastfail;
958 }
959
960 hfi1_rcd_put(rcd);
961 }
962
963
964 len = PAGE_ALIGN(chip_rcv_contexts(dd) * HFI1_MAX_SHARED_CTXTS *
965 sizeof(*dd->events));
966 dd->events = vmalloc_user(len);
967 if (!dd->events)
968 dd_dev_err(dd, "Failed to allocate user events page\n");
969
970
971
972
973 dd->status = vmalloc_user(PAGE_SIZE);
974 if (!dd->status)
975 dd_dev_err(dd, "Failed to allocate dev status page\n");
976 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
977 ppd = dd->pport + pidx;
978 if (dd->status)
979
980 ppd->statusp = &dd->status->port;
981
982 set_mtu(ppd);
983 }
984
985
986 enable_chip(dd);
987
988done:
989
990
991
992
993 if (dd->status)
994 dd->status->dev |= HFI1_STATUS_CHIP_PRESENT |
995 HFI1_STATUS_INITTED;
996 if (!ret) {
997
998 enable_general_intr(dd);
999 init_qsfp_int(dd);
1000
1001
1002 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1003 ppd = dd->pport + pidx;
1004
1005
1006
1007
1008
1009 lastfail = bringup_serdes(ppd);
1010 if (lastfail)
1011 dd_dev_info(dd,
1012 "Failed to bring up port %u\n",
1013 ppd->port);
1014
1015
1016
1017
1018
1019 if (ppd->statusp)
1020 *ppd->statusp |= HFI1_STATUS_CHIP_PRESENT |
1021 HFI1_STATUS_INITTED;
1022 if (!ppd->link_speed_enabled)
1023 continue;
1024 }
1025 }
1026
1027
1028 return ret;
1029}
1030
1031struct hfi1_devdata *hfi1_lookup(int unit)
1032{
1033 return xa_load(&hfi1_dev_table, unit);
1034}
1035
1036
1037
1038
1039
1040static void stop_timers(struct hfi1_devdata *dd)
1041{
1042 struct hfi1_pportdata *ppd;
1043 int pidx;
1044
1045 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1046 ppd = dd->pport + pidx;
1047 if (ppd->led_override_timer.function) {
1048 del_timer_sync(&ppd->led_override_timer);
1049 atomic_set(&ppd->led_override_timer_active, 0);
1050 }
1051 }
1052}
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063static void shutdown_device(struct hfi1_devdata *dd)
1064{
1065 struct hfi1_pportdata *ppd;
1066 struct hfi1_ctxtdata *rcd;
1067 unsigned pidx;
1068 int i;
1069
1070 if (dd->flags & HFI1_SHUTDOWN)
1071 return;
1072 dd->flags |= HFI1_SHUTDOWN;
1073
1074 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1075 ppd = dd->pport + pidx;
1076
1077 ppd->linkup = 0;
1078 if (ppd->statusp)
1079 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
1080 HFI1_STATUS_IB_READY);
1081 }
1082 dd->flags &= ~HFI1_INITTED;
1083
1084
1085 set_intr_bits(dd, IS_FIRST_SOURCE, IS_LAST_SOURCE, false);
1086 msix_clean_up_interrupts(dd);
1087
1088 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1089 ppd = dd->pport + pidx;
1090 for (i = 0; i < dd->num_rcv_contexts; i++) {
1091 rcd = hfi1_rcd_get_by_index(dd, i);
1092 hfi1_rcvctrl(dd, HFI1_RCVCTRL_TAILUPD_DIS |
1093 HFI1_RCVCTRL_CTXT_DIS |
1094 HFI1_RCVCTRL_INTRAVAIL_DIS |
1095 HFI1_RCVCTRL_PKEY_DIS |
1096 HFI1_RCVCTRL_ONE_PKT_EGR_DIS, rcd);
1097 hfi1_rcd_put(rcd);
1098 }
1099
1100
1101
1102
1103 for (i = 0; i < dd->num_send_contexts; i++)
1104 sc_flush(dd->send_contexts[i].sc);
1105 }
1106
1107
1108
1109
1110
1111 udelay(20);
1112
1113 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1114 ppd = dd->pport + pidx;
1115
1116
1117 for (i = 0; i < dd->num_send_contexts; i++)
1118 sc_disable(dd->send_contexts[i].sc);
1119
1120 pio_send_control(dd, PSC_GLOBAL_DISABLE);
1121
1122 shutdown_led_override(ppd);
1123
1124
1125
1126
1127
1128 hfi1_quiet_serdes(ppd);
1129 if (ppd->hfi1_wq)
1130 flush_workqueue(ppd->hfi1_wq);
1131 if (ppd->link_wq)
1132 flush_workqueue(ppd->link_wq);
1133 }
1134 sdma_exit(dd);
1135}
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
1146{
1147 u32 e;
1148
1149 if (!rcd)
1150 return;
1151
1152 if (rcd->rcvhdrq) {
1153 dma_free_coherent(&dd->pcidev->dev, rcvhdrq_size(rcd),
1154 rcd->rcvhdrq, rcd->rcvhdrq_dma);
1155 rcd->rcvhdrq = NULL;
1156 if (hfi1_rcvhdrtail_kvaddr(rcd)) {
1157 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1158 (void *)hfi1_rcvhdrtail_kvaddr(rcd),
1159 rcd->rcvhdrqtailaddr_dma);
1160 rcd->rcvhdrtail_kvaddr = NULL;
1161 }
1162 }
1163
1164
1165 kfree(rcd->egrbufs.rcvtids);
1166 rcd->egrbufs.rcvtids = NULL;
1167
1168 for (e = 0; e < rcd->egrbufs.alloced; e++) {
1169 if (rcd->egrbufs.buffers[e].dma)
1170 dma_free_coherent(&dd->pcidev->dev,
1171 rcd->egrbufs.buffers[e].len,
1172 rcd->egrbufs.buffers[e].addr,
1173 rcd->egrbufs.buffers[e].dma);
1174 }
1175 kfree(rcd->egrbufs.buffers);
1176 rcd->egrbufs.alloced = 0;
1177 rcd->egrbufs.buffers = NULL;
1178
1179 sc_free(rcd->sc);
1180 rcd->sc = NULL;
1181
1182 vfree(rcd->subctxt_uregbase);
1183 vfree(rcd->subctxt_rcvegrbuf);
1184 vfree(rcd->subctxt_rcvhdr_base);
1185 kfree(rcd->opstats);
1186
1187 rcd->subctxt_uregbase = NULL;
1188 rcd->subctxt_rcvegrbuf = NULL;
1189 rcd->subctxt_rcvhdr_base = NULL;
1190 rcd->opstats = NULL;
1191}
1192
1193
1194
1195
1196
1197
1198static struct hfi1_asic_data *release_asic_data(struct hfi1_devdata *dd)
1199{
1200 struct hfi1_asic_data *ad;
1201 int other;
1202
1203 if (!dd->asic_data)
1204 return NULL;
1205 dd->asic_data->dds[dd->hfi1_id] = NULL;
1206 other = dd->hfi1_id ? 0 : 1;
1207 ad = dd->asic_data;
1208 dd->asic_data = NULL;
1209
1210 return ad->dds[other] ? NULL : ad;
1211}
1212
1213static void finalize_asic_data(struct hfi1_devdata *dd,
1214 struct hfi1_asic_data *ad)
1215{
1216 clean_up_i2c(dd, ad);
1217 kfree(ad);
1218}
1219
1220
1221
1222
1223
1224
1225
1226
1227void hfi1_free_devdata(struct hfi1_devdata *dd)
1228{
1229 struct hfi1_asic_data *ad;
1230 unsigned long flags;
1231
1232 xa_lock_irqsave(&hfi1_dev_table, flags);
1233 __xa_erase(&hfi1_dev_table, dd->unit);
1234 ad = release_asic_data(dd);
1235 xa_unlock_irqrestore(&hfi1_dev_table, flags);
1236
1237 finalize_asic_data(dd, ad);
1238 free_platform_config(dd);
1239 rcu_barrier();
1240 free_percpu(dd->int_counter);
1241 free_percpu(dd->rcv_limit);
1242 free_percpu(dd->send_schedule);
1243 free_percpu(dd->tx_opstats);
1244 dd->int_counter = NULL;
1245 dd->rcv_limit = NULL;
1246 dd->send_schedule = NULL;
1247 dd->tx_opstats = NULL;
1248 kfree(dd->comp_vect);
1249 dd->comp_vect = NULL;
1250 sdma_clean(dd, dd->num_sdma);
1251 rvt_dealloc_device(&dd->verbs_dev.rdi);
1252}
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263static struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev,
1264 size_t extra)
1265{
1266 struct hfi1_devdata *dd;
1267 int ret, nports;
1268
1269
1270 nports = extra / sizeof(struct hfi1_pportdata);
1271
1272 dd = (struct hfi1_devdata *)rvt_alloc_device(sizeof(*dd) + extra,
1273 nports);
1274 if (!dd)
1275 return ERR_PTR(-ENOMEM);
1276 dd->num_pports = nports;
1277 dd->pport = (struct hfi1_pportdata *)(dd + 1);
1278 dd->pcidev = pdev;
1279 pci_set_drvdata(pdev, dd);
1280
1281 ret = xa_alloc_irq(&hfi1_dev_table, &dd->unit, dd, xa_limit_32b,
1282 GFP_KERNEL);
1283 if (ret < 0) {
1284 dev_err(&pdev->dev,
1285 "Could not allocate unit ID: error %d\n", -ret);
1286 goto bail;
1287 }
1288 rvt_set_ibdev_name(&dd->verbs_dev.rdi, "%s_%d", class_name(), dd->unit);
1289
1290
1291
1292
1293 dd->node = pcibus_to_node(pdev->bus);
1294 if (dd->node == NUMA_NO_NODE) {
1295 dd_dev_err(dd, "Invalid PCI NUMA node. Performance may be affected\n");
1296 dd->node = 0;
1297 }
1298
1299
1300
1301
1302
1303 spin_lock_init(&dd->sc_lock);
1304 spin_lock_init(&dd->sendctrl_lock);
1305 spin_lock_init(&dd->rcvctrl_lock);
1306 spin_lock_init(&dd->uctxt_lock);
1307 spin_lock_init(&dd->hfi1_diag_trans_lock);
1308 spin_lock_init(&dd->sc_init_lock);
1309 spin_lock_init(&dd->dc8051_memlock);
1310 seqlock_init(&dd->sc2vl_lock);
1311 spin_lock_init(&dd->sde_map_lock);
1312 spin_lock_init(&dd->pio_map_lock);
1313 mutex_init(&dd->dc8051_lock);
1314 init_waitqueue_head(&dd->event_queue);
1315 spin_lock_init(&dd->irq_src_lock);
1316
1317 dd->int_counter = alloc_percpu(u64);
1318 if (!dd->int_counter) {
1319 ret = -ENOMEM;
1320 goto bail;
1321 }
1322
1323 dd->rcv_limit = alloc_percpu(u64);
1324 if (!dd->rcv_limit) {
1325 ret = -ENOMEM;
1326 goto bail;
1327 }
1328
1329 dd->send_schedule = alloc_percpu(u64);
1330 if (!dd->send_schedule) {
1331 ret = -ENOMEM;
1332 goto bail;
1333 }
1334
1335 dd->tx_opstats = alloc_percpu(struct hfi1_opcode_stats_perctx);
1336 if (!dd->tx_opstats) {
1337 ret = -ENOMEM;
1338 goto bail;
1339 }
1340
1341 dd->comp_vect = kzalloc(sizeof(*dd->comp_vect), GFP_KERNEL);
1342 if (!dd->comp_vect) {
1343 ret = -ENOMEM;
1344 goto bail;
1345 }
1346
1347 atomic_set(&dd->ipoib_rsm_usr_num, 0);
1348 return dd;
1349
1350bail:
1351 hfi1_free_devdata(dd);
1352 return ERR_PTR(ret);
1353}
1354
1355
1356
1357
1358
1359
1360void hfi1_disable_after_error(struct hfi1_devdata *dd)
1361{
1362 if (dd->flags & HFI1_INITTED) {
1363 u32 pidx;
1364
1365 dd->flags &= ~HFI1_INITTED;
1366 if (dd->pport)
1367 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1368 struct hfi1_pportdata *ppd;
1369
1370 ppd = dd->pport + pidx;
1371 if (dd->flags & HFI1_PRESENT)
1372 set_link_state(ppd, HLS_DN_DISABLE);
1373
1374 if (ppd->statusp)
1375 *ppd->statusp &= ~HFI1_STATUS_IB_READY;
1376 }
1377 }
1378
1379
1380
1381
1382
1383
1384 if (dd->status)
1385 dd->status->dev |= HFI1_STATUS_HWERROR;
1386}
1387
1388static void remove_one(struct pci_dev *);
1389static int init_one(struct pci_dev *, const struct pci_device_id *);
1390static void shutdown_one(struct pci_dev *);
1391
1392#define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: "
1393#define PFX DRIVER_NAME ": "
1394
1395const struct pci_device_id hfi1_pci_tbl[] = {
1396 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL0) },
1397 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL1) },
1398 { 0, }
1399};
1400
1401MODULE_DEVICE_TABLE(pci, hfi1_pci_tbl);
1402
1403static struct pci_driver hfi1_pci_driver = {
1404 .name = DRIVER_NAME,
1405 .probe = init_one,
1406 .remove = remove_one,
1407 .shutdown = shutdown_one,
1408 .id_table = hfi1_pci_tbl,
1409 .err_handler = &hfi1_pci_err_handler,
1410};
1411
1412static void __init compute_krcvqs(void)
1413{
1414 int i;
1415
1416 for (i = 0; i < krcvqsset; i++)
1417 n_krcvqs += krcvqs[i];
1418}
1419
1420
1421
1422
1423
1424static int __init hfi1_mod_init(void)
1425{
1426 int ret;
1427
1428 ret = dev_init();
1429 if (ret)
1430 goto bail;
1431
1432 ret = node_affinity_init();
1433 if (ret)
1434 goto bail;
1435
1436
1437 if (!valid_opa_max_mtu(hfi1_max_mtu)) {
1438 pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n",
1439 hfi1_max_mtu, HFI1_DEFAULT_MAX_MTU);
1440 hfi1_max_mtu = HFI1_DEFAULT_MAX_MTU;
1441 }
1442
1443 if (hfi1_cu > 128 || !is_power_of_2(hfi1_cu))
1444 hfi1_cu = 1;
1445
1446 if (user_credit_return_threshold > 100)
1447 user_credit_return_threshold = 100;
1448
1449 compute_krcvqs();
1450
1451
1452
1453
1454 if (rcv_intr_count > RCV_HDR_HEAD_COUNTER_MASK)
1455 rcv_intr_count = RCV_HDR_HEAD_COUNTER_MASK;
1456
1457 if (rcv_intr_count == 0 && rcv_intr_timeout == 0) {
1458 pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n");
1459 rcv_intr_count = 1;
1460 }
1461 if (rcv_intr_count > 1 && rcv_intr_timeout == 0) {
1462
1463
1464
1465
1466 pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n");
1467 rcv_intr_timeout = 1;
1468 }
1469 if (rcv_intr_dynamic && !(rcv_intr_count > 1 && rcv_intr_timeout > 0)) {
1470
1471
1472
1473
1474 pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n");
1475 rcv_intr_dynamic = 0;
1476 }
1477
1478
1479 link_crc_mask &= SUPPORTED_CRCS;
1480
1481 ret = opfn_init();
1482 if (ret < 0) {
1483 pr_err("Failed to allocate opfn_wq");
1484 goto bail_dev;
1485 }
1486
1487
1488
1489
1490
1491 hfi1_dbg_init();
1492 ret = pci_register_driver(&hfi1_pci_driver);
1493 if (ret < 0) {
1494 pr_err("Unable to register driver: error %d\n", -ret);
1495 goto bail_dev;
1496 }
1497 goto bail;
1498
1499bail_dev:
1500 hfi1_dbg_exit();
1501 dev_cleanup();
1502bail:
1503 return ret;
1504}
1505
1506module_init(hfi1_mod_init);
1507
1508
1509
1510
1511static void __exit hfi1_mod_cleanup(void)
1512{
1513 pci_unregister_driver(&hfi1_pci_driver);
1514 opfn_exit();
1515 node_affinity_destroy_all();
1516 hfi1_dbg_exit();
1517
1518 WARN_ON(!xa_empty(&hfi1_dev_table));
1519 dispose_firmware();
1520 dev_cleanup();
1521}
1522
1523module_exit(hfi1_mod_cleanup);
1524
1525
1526static void cleanup_device_data(struct hfi1_devdata *dd)
1527{
1528 int ctxt;
1529 int pidx;
1530
1531
1532 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1533 struct hfi1_pportdata *ppd = &dd->pport[pidx];
1534 struct cc_state *cc_state;
1535 int i;
1536
1537 if (ppd->statusp)
1538 *ppd->statusp &= ~HFI1_STATUS_CHIP_PRESENT;
1539
1540 for (i = 0; i < OPA_MAX_SLS; i++)
1541 hrtimer_cancel(&ppd->cca_timer[i].hrtimer);
1542
1543 spin_lock(&ppd->cc_state_lock);
1544 cc_state = get_cc_state_protected(ppd);
1545 RCU_INIT_POINTER(ppd->cc_state, NULL);
1546 spin_unlock(&ppd->cc_state_lock);
1547
1548 if (cc_state)
1549 kfree_rcu(cc_state, rcu);
1550 }
1551
1552 free_credit_return(dd);
1553
1554 if (dd->rcvhdrtail_dummy_kvaddr) {
1555 dma_free_coherent(&dd->pcidev->dev, sizeof(u64),
1556 (void *)dd->rcvhdrtail_dummy_kvaddr,
1557 dd->rcvhdrtail_dummy_dma);
1558 dd->rcvhdrtail_dummy_kvaddr = NULL;
1559 }
1560
1561
1562
1563
1564
1565 for (ctxt = 0; dd->rcd && ctxt < dd->num_rcv_contexts; ctxt++) {
1566 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
1567
1568 if (rcd) {
1569 hfi1_free_ctxt_rcv_groups(rcd);
1570 hfi1_free_ctxt(rcd);
1571 }
1572 }
1573
1574 kfree(dd->rcd);
1575 dd->rcd = NULL;
1576
1577 free_pio_map(dd);
1578
1579 for (ctxt = 0; ctxt < dd->num_send_contexts; ctxt++)
1580 sc_free(dd->send_contexts[ctxt].sc);
1581 dd->num_send_contexts = 0;
1582 kfree(dd->send_contexts);
1583 dd->send_contexts = NULL;
1584 kfree(dd->hw_to_sw);
1585 dd->hw_to_sw = NULL;
1586 kfree(dd->boardname);
1587 vfree(dd->events);
1588 vfree(dd->status);
1589}
1590
1591
1592
1593
1594
1595static void postinit_cleanup(struct hfi1_devdata *dd)
1596{
1597 hfi1_start_cleanup(dd);
1598 hfi1_comp_vectors_clean_up(dd);
1599 hfi1_dev_affinity_clean_up(dd);
1600
1601 hfi1_pcie_ddcleanup(dd);
1602 hfi1_pcie_cleanup(dd->pcidev);
1603
1604 cleanup_device_data(dd);
1605
1606 hfi1_free_devdata(dd);
1607}
1608
1609static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1610{
1611 int ret = 0, j, pidx, initfail;
1612 struct hfi1_devdata *dd;
1613 struct hfi1_pportdata *ppd;
1614
1615
1616 HFI1_CAP_LOCK();
1617
1618
1619 if (!(ent->device == PCI_DEVICE_ID_INTEL0 ||
1620 ent->device == PCI_DEVICE_ID_INTEL1)) {
1621 dev_err(&pdev->dev, "Failing on unknown Intel deviceid 0x%x\n",
1622 ent->device);
1623 ret = -ENODEV;
1624 goto bail;
1625 }
1626
1627
1628 dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS *
1629 sizeof(struct hfi1_pportdata));
1630 if (IS_ERR(dd)) {
1631 ret = PTR_ERR(dd);
1632 goto bail;
1633 }
1634
1635
1636 ret = hfi1_validate_rcvhdrcnt(dd, rcvhdrcnt);
1637 if (ret)
1638 goto bail;
1639
1640
1641 if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) {
1642 dd_dev_err(dd, "Invalid HdrQ Entry size %u\n",
1643 hfi1_hdrq_entsize);
1644 ret = -EINVAL;
1645 goto bail;
1646 }
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657 if (eager_buffer_size) {
1658 if (!is_power_of_2(eager_buffer_size))
1659 eager_buffer_size =
1660 roundup_pow_of_two(eager_buffer_size);
1661 eager_buffer_size =
1662 clamp_val(eager_buffer_size,
1663 MIN_EAGER_BUFFER * 8,
1664 MAX_EAGER_BUFFER_TOTAL);
1665 dd_dev_info(dd, "Eager buffer size %u\n",
1666 eager_buffer_size);
1667 } else {
1668 dd_dev_err(dd, "Invalid Eager buffer size of 0\n");
1669 ret = -EINVAL;
1670 goto bail;
1671 }
1672
1673
1674 hfi1_rcvarr_split = clamp_val(hfi1_rcvarr_split, 0, 100);
1675
1676 ret = hfi1_pcie_init(dd);
1677 if (ret)
1678 goto bail;
1679
1680
1681
1682
1683
1684 ret = hfi1_init_dd(dd);
1685 if (ret)
1686 goto clean_bail;
1687
1688 ret = create_workqueues(dd);
1689 if (ret)
1690 goto clean_bail;
1691
1692
1693 initfail = hfi1_init(dd, 0);
1694
1695 ret = hfi1_register_ib_device(dd);
1696
1697
1698
1699
1700
1701
1702
1703 if (!initfail && !ret) {
1704 dd->flags |= HFI1_INITTED;
1705
1706 hfi1_dbg_ibdev_init(&dd->verbs_dev);
1707 }
1708
1709 j = hfi1_device_create(dd);
1710 if (j)
1711 dd_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
1712
1713 if (initfail || ret) {
1714 msix_clean_up_interrupts(dd);
1715 stop_timers(dd);
1716 flush_workqueue(ib_wq);
1717 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1718 hfi1_quiet_serdes(dd->pport + pidx);
1719 ppd = dd->pport + pidx;
1720 if (ppd->hfi1_wq) {
1721 destroy_workqueue(ppd->hfi1_wq);
1722 ppd->hfi1_wq = NULL;
1723 }
1724 if (ppd->link_wq) {
1725 destroy_workqueue(ppd->link_wq);
1726 ppd->link_wq = NULL;
1727 }
1728 }
1729 if (!j)
1730 hfi1_device_remove(dd);
1731 if (!ret)
1732 hfi1_unregister_ib_device(dd);
1733 postinit_cleanup(dd);
1734 if (initfail)
1735 ret = initfail;
1736 goto bail;
1737 }
1738
1739 sdma_start(dd);
1740
1741 return 0;
1742
1743clean_bail:
1744 hfi1_pcie_cleanup(pdev);
1745bail:
1746 return ret;
1747}
1748
1749static void wait_for_clients(struct hfi1_devdata *dd)
1750{
1751
1752
1753
1754
1755 if (atomic_dec_and_test(&dd->user_refcount))
1756 complete(&dd->user_comp);
1757
1758 wait_for_completion(&dd->user_comp);
1759}
1760
1761static void remove_one(struct pci_dev *pdev)
1762{
1763 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
1764
1765
1766 hfi1_dbg_ibdev_exit(&dd->verbs_dev);
1767
1768
1769 hfi1_device_remove(dd);
1770
1771
1772 wait_for_clients(dd);
1773
1774
1775 hfi1_unregister_ib_device(dd);
1776
1777
1778 hfi1_free_rx(dd);
1779
1780
1781
1782
1783
1784 shutdown_device(dd);
1785 destroy_workqueues(dd);
1786
1787 stop_timers(dd);
1788
1789
1790 flush_workqueue(ib_wq);
1791
1792 postinit_cleanup(dd);
1793}
1794
1795static void shutdown_one(struct pci_dev *pdev)
1796{
1797 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
1798
1799 shutdown_device(dd);
1800}
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
1812{
1813 unsigned amt;
1814
1815 if (!rcd->rcvhdrq) {
1816 gfp_t gfp_flags;
1817
1818 amt = rcvhdrq_size(rcd);
1819
1820 if (rcd->ctxt < dd->first_dyn_alloc_ctxt || rcd->is_vnic)
1821 gfp_flags = GFP_KERNEL;
1822 else
1823 gfp_flags = GFP_USER;
1824 rcd->rcvhdrq = dma_alloc_coherent(&dd->pcidev->dev, amt,
1825 &rcd->rcvhdrq_dma,
1826 gfp_flags | __GFP_COMP);
1827
1828 if (!rcd->rcvhdrq) {
1829 dd_dev_err(dd,
1830 "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1831 amt, rcd->ctxt);
1832 goto bail;
1833 }
1834
1835 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ||
1836 HFI1_CAP_UGET_MASK(rcd->flags, DMA_RTAIL)) {
1837 rcd->rcvhdrtail_kvaddr = dma_alloc_coherent(&dd->pcidev->dev,
1838 PAGE_SIZE,
1839 &rcd->rcvhdrqtailaddr_dma,
1840 gfp_flags);
1841 if (!rcd->rcvhdrtail_kvaddr)
1842 goto bail_free;
1843 }
1844 }
1845
1846 set_hdrq_regs(rcd->dd, rcd->ctxt, rcd->rcvhdrqentsize,
1847 rcd->rcvhdrq_cnt);
1848
1849 return 0;
1850
1851bail_free:
1852 dd_dev_err(dd,
1853 "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1854 rcd->ctxt);
1855 dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
1856 rcd->rcvhdrq_dma);
1857 rcd->rcvhdrq = NULL;
1858bail:
1859 return -ENOMEM;
1860}
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd)
1873{
1874 struct hfi1_devdata *dd = rcd->dd;
1875 u32 max_entries, egrtop, alloced_bytes = 0;
1876 gfp_t gfp_flags;
1877 u16 order, idx = 0;
1878 int ret = 0;
1879 u16 round_mtu = roundup_pow_of_two(hfi1_max_mtu);
1880
1881
1882
1883
1884
1885
1886
1887 gfp_flags = __GFP_RECLAIM | __GFP_IO | __GFP_COMP;
1888
1889
1890
1891
1892
1893
1894
1895
1896 if (rcd->egrbufs.size < (round_mtu * dd->rcv_entries.group_size))
1897 rcd->egrbufs.size = round_mtu * dd->rcv_entries.group_size;
1898
1899
1900
1901
1902 if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR))
1903 rcd->egrbufs.rcvtid_size = round_mtu;
1904
1905
1906
1907
1908
1909 if (rcd->egrbufs.size <= (1 << 20))
1910 rcd->egrbufs.rcvtid_size = max((unsigned long)round_mtu,
1911 rounddown_pow_of_two(rcd->egrbufs.size / 8));
1912
1913 while (alloced_bytes < rcd->egrbufs.size &&
1914 rcd->egrbufs.alloced < rcd->egrbufs.count) {
1915 rcd->egrbufs.buffers[idx].addr =
1916 dma_alloc_coherent(&dd->pcidev->dev,
1917 rcd->egrbufs.rcvtid_size,
1918 &rcd->egrbufs.buffers[idx].dma,
1919 gfp_flags);
1920 if (rcd->egrbufs.buffers[idx].addr) {
1921 rcd->egrbufs.buffers[idx].len =
1922 rcd->egrbufs.rcvtid_size;
1923 rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].addr =
1924 rcd->egrbufs.buffers[idx].addr;
1925 rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].dma =
1926 rcd->egrbufs.buffers[idx].dma;
1927 rcd->egrbufs.alloced++;
1928 alloced_bytes += rcd->egrbufs.rcvtid_size;
1929 idx++;
1930 } else {
1931 u32 new_size, i, j;
1932 u64 offset = 0;
1933
1934
1935
1936
1937
1938
1939
1940 if (rcd->egrbufs.rcvtid_size == round_mtu ||
1941 !HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) {
1942 dd_dev_err(dd, "ctxt%u: Failed to allocate eager buffers\n",
1943 rcd->ctxt);
1944 ret = -ENOMEM;
1945 goto bail_rcvegrbuf_phys;
1946 }
1947
1948 new_size = rcd->egrbufs.rcvtid_size / 2;
1949
1950
1951
1952
1953
1954
1955 if (idx == 0) {
1956 rcd->egrbufs.rcvtid_size = new_size;
1957 continue;
1958 }
1959
1960
1961
1962
1963
1964 rcd->egrbufs.alloced = 0;
1965 for (i = 0, j = 0, offset = 0; j < idx; i++) {
1966 if (i >= rcd->egrbufs.count)
1967 break;
1968 rcd->egrbufs.rcvtids[i].dma =
1969 rcd->egrbufs.buffers[j].dma + offset;
1970 rcd->egrbufs.rcvtids[i].addr =
1971 rcd->egrbufs.buffers[j].addr + offset;
1972 rcd->egrbufs.alloced++;
1973 if ((rcd->egrbufs.buffers[j].dma + offset +
1974 new_size) ==
1975 (rcd->egrbufs.buffers[j].dma +
1976 rcd->egrbufs.buffers[j].len)) {
1977 j++;
1978 offset = 0;
1979 } else {
1980 offset += new_size;
1981 }
1982 }
1983 rcd->egrbufs.rcvtid_size = new_size;
1984 }
1985 }
1986 rcd->egrbufs.numbufs = idx;
1987 rcd->egrbufs.size = alloced_bytes;
1988
1989 hfi1_cdbg(PROC,
1990 "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %uKB\n",
1991 rcd->ctxt, rcd->egrbufs.alloced,
1992 rcd->egrbufs.rcvtid_size / 1024, rcd->egrbufs.size / 1024);
1993
1994
1995
1996
1997
1998
1999 rcd->egrbufs.threshold =
2000 rounddown_pow_of_two(rcd->egrbufs.alloced / 2);
2001
2002
2003
2004
2005
2006 max_entries = rcd->rcv_array_groups * dd->rcv_entries.group_size;
2007 egrtop = roundup(rcd->egrbufs.alloced, dd->rcv_entries.group_size);
2008 rcd->expected_count = max_entries - egrtop;
2009 if (rcd->expected_count > MAX_TID_PAIR_ENTRIES * 2)
2010 rcd->expected_count = MAX_TID_PAIR_ENTRIES * 2;
2011
2012 rcd->expected_base = rcd->eager_base + egrtop;
2013 hfi1_cdbg(PROC, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n",
2014 rcd->ctxt, rcd->egrbufs.alloced, rcd->expected_count,
2015 rcd->eager_base, rcd->expected_base);
2016
2017 if (!hfi1_rcvbuf_validate(rcd->egrbufs.rcvtid_size, PT_EAGER, &order)) {
2018 hfi1_cdbg(PROC,
2019 "ctxt%u: current Eager buffer size is invalid %u\n",
2020 rcd->ctxt, rcd->egrbufs.rcvtid_size);
2021 ret = -EINVAL;
2022 goto bail_rcvegrbuf_phys;
2023 }
2024
2025 for (idx = 0; idx < rcd->egrbufs.alloced; idx++) {
2026 hfi1_put_tid(dd, rcd->eager_base + idx, PT_EAGER,
2027 rcd->egrbufs.rcvtids[idx].dma, order);
2028 cond_resched();
2029 }
2030
2031 return 0;
2032
2033bail_rcvegrbuf_phys:
2034 for (idx = 0; idx < rcd->egrbufs.alloced &&
2035 rcd->egrbufs.buffers[idx].addr;
2036 idx++) {
2037 dma_free_coherent(&dd->pcidev->dev,
2038 rcd->egrbufs.buffers[idx].len,
2039 rcd->egrbufs.buffers[idx].addr,
2040 rcd->egrbufs.buffers[idx].dma);
2041 rcd->egrbufs.buffers[idx].addr = NULL;
2042 rcd->egrbufs.buffers[idx].dma = 0;
2043 rcd->egrbufs.buffers[idx].len = 0;
2044 }
2045
2046 return ret;
2047}
2048