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6
7#include <linux/debugfs.h>
8#include <linux/highmem.h>
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/errno.h>
12#include <linux/pci.h>
13#include <linux/dma-mapping.h>
14#include <linux/slab.h>
15#include <linux/bitmap.h>
16#include <linux/sched.h>
17#include <linux/sched/mm.h>
18#include <linux/sched/task.h>
19#include <linux/delay.h>
20#include <rdma/ib_user_verbs.h>
21#include <rdma/ib_addr.h>
22#include <rdma/ib_cache.h>
23#include <linux/mlx5/port.h>
24#include <linux/mlx5/vport.h>
25#include <linux/mlx5/fs.h>
26#include <linux/mlx5/eswitch.h>
27#include <linux/list.h>
28#include <rdma/ib_smi.h>
29#include <rdma/ib_umem.h>
30#include <rdma/lag.h>
31#include <linux/in.h>
32#include <linux/etherdevice.h>
33#include "mlx5_ib.h"
34#include "ib_rep.h"
35#include "cmd.h"
36#include "devx.h"
37#include "dm.h"
38#include "fs.h"
39#include "srq.h"
40#include "qp.h"
41#include "wr.h"
42#include "restrack.h"
43#include "counters.h"
44#include <linux/mlx5/accel.h>
45#include <rdma/uverbs_std_types.h>
46#include <rdma/uverbs_ioctl.h>
47#include <rdma/mlx5_user_ioctl_verbs.h>
48#include <rdma/mlx5_user_ioctl_cmds.h>
49#include <rdma/ib_umem_odp.h>
50
51#define UVERBS_MODULE_NAME mlx5_ib
52#include <rdma/uverbs_named_ioctl.h>
53
54MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
55MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
56MODULE_LICENSE("Dual BSD/GPL");
57
58struct mlx5_ib_event_work {
59 struct work_struct work;
60 union {
61 struct mlx5_ib_dev *dev;
62 struct mlx5_ib_multiport_info *mpi;
63 };
64 bool is_slave;
65 unsigned int event;
66 void *param;
67};
68
69enum {
70 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
71};
72
73static struct workqueue_struct *mlx5_ib_event_wq;
74static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
75static LIST_HEAD(mlx5_ib_dev_list);
76
77
78
79static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
80
81struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
82{
83 struct mlx5_ib_dev *dev;
84
85 mutex_lock(&mlx5_ib_multiport_mutex);
86 dev = mpi->ibdev;
87 mutex_unlock(&mlx5_ib_multiport_mutex);
88 return dev;
89}
90
91static enum rdma_link_layer
92mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
93{
94 switch (port_type_cap) {
95 case MLX5_CAP_PORT_TYPE_IB:
96 return IB_LINK_LAYER_INFINIBAND;
97 case MLX5_CAP_PORT_TYPE_ETH:
98 return IB_LINK_LAYER_ETHERNET;
99 default:
100 return IB_LINK_LAYER_UNSPECIFIED;
101 }
102}
103
104static enum rdma_link_layer
105mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num)
106{
107 struct mlx5_ib_dev *dev = to_mdev(device);
108 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
109
110 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
111}
112
113static int get_port_state(struct ib_device *ibdev,
114 u32 port_num,
115 enum ib_port_state *state)
116{
117 struct ib_port_attr attr;
118 int ret;
119
120 memset(&attr, 0, sizeof(attr));
121 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
122 if (!ret)
123 *state = attr.state;
124 return ret;
125}
126
127static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
128 struct net_device *ndev,
129 u32 *port_num)
130{
131 struct net_device *rep_ndev;
132 struct mlx5_ib_port *port;
133 int i;
134
135 for (i = 0; i < dev->num_ports; i++) {
136 port = &dev->port[i];
137 if (!port->rep)
138 continue;
139
140 read_lock(&port->roce.netdev_lock);
141 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw,
142 port->rep->vport);
143 if (rep_ndev == ndev) {
144 read_unlock(&port->roce.netdev_lock);
145 *port_num = i + 1;
146 return &port->roce;
147 }
148 read_unlock(&port->roce.netdev_lock);
149 }
150
151 return NULL;
152}
153
154static int mlx5_netdev_event(struct notifier_block *this,
155 unsigned long event, void *ptr)
156{
157 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
158 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
159 u32 port_num = roce->native_port_num;
160 struct mlx5_core_dev *mdev;
161 struct mlx5_ib_dev *ibdev;
162
163 ibdev = roce->dev;
164 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
165 if (!mdev)
166 return NOTIFY_DONE;
167
168 switch (event) {
169 case NETDEV_REGISTER:
170
171 if (ibdev->is_rep)
172 break;
173 write_lock(&roce->netdev_lock);
174 if (ndev->dev.parent == mdev->device)
175 roce->netdev = ndev;
176 write_unlock(&roce->netdev_lock);
177 break;
178
179 case NETDEV_UNREGISTER:
180
181 write_lock(&roce->netdev_lock);
182 if (roce->netdev == ndev)
183 roce->netdev = NULL;
184 write_unlock(&roce->netdev_lock);
185 break;
186
187 case NETDEV_CHANGE:
188 case NETDEV_UP:
189 case NETDEV_DOWN: {
190 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
191 struct net_device *upper = NULL;
192
193 if (lag_ndev) {
194 upper = netdev_master_upper_dev_get(lag_ndev);
195 dev_put(lag_ndev);
196 }
197
198 if (ibdev->is_rep)
199 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
200 if (!roce)
201 return NOTIFY_DONE;
202 if ((upper == ndev || (!upper && ndev == roce->netdev))
203 && ibdev->ib_active) {
204 struct ib_event ibev = { };
205 enum ib_port_state port_state;
206
207 if (get_port_state(&ibdev->ib_dev, port_num,
208 &port_state))
209 goto done;
210
211 if (roce->last_port_state == port_state)
212 goto done;
213
214 roce->last_port_state = port_state;
215 ibev.device = &ibdev->ib_dev;
216 if (port_state == IB_PORT_DOWN)
217 ibev.event = IB_EVENT_PORT_ERR;
218 else if (port_state == IB_PORT_ACTIVE)
219 ibev.event = IB_EVENT_PORT_ACTIVE;
220 else
221 goto done;
222
223 ibev.element.port_num = port_num;
224 ib_dispatch_event(&ibev);
225 }
226 break;
227 }
228
229 default:
230 break;
231 }
232done:
233 mlx5_ib_put_native_port_mdev(ibdev, port_num);
234 return NOTIFY_DONE;
235}
236
237static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
238 u32 port_num)
239{
240 struct mlx5_ib_dev *ibdev = to_mdev(device);
241 struct net_device *ndev;
242 struct mlx5_core_dev *mdev;
243
244 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
245 if (!mdev)
246 return NULL;
247
248 ndev = mlx5_lag_get_roce_netdev(mdev);
249 if (ndev)
250 goto out;
251
252
253
254 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
255 ndev = ibdev->port[port_num - 1].roce.netdev;
256 if (ndev)
257 dev_hold(ndev);
258 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
259
260out:
261 mlx5_ib_put_native_port_mdev(ibdev, port_num);
262 return ndev;
263}
264
265struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
266 u32 ib_port_num,
267 u32 *native_port_num)
268{
269 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
270 ib_port_num);
271 struct mlx5_core_dev *mdev = NULL;
272 struct mlx5_ib_multiport_info *mpi;
273 struct mlx5_ib_port *port;
274
275 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
276 ll != IB_LINK_LAYER_ETHERNET) {
277 if (native_port_num)
278 *native_port_num = ib_port_num;
279 return ibdev->mdev;
280 }
281
282 if (native_port_num)
283 *native_port_num = 1;
284
285 port = &ibdev->port[ib_port_num - 1];
286 spin_lock(&port->mp.mpi_lock);
287 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
288 if (mpi && !mpi->unaffiliate) {
289 mdev = mpi->mdev;
290
291
292
293 if (!mpi->is_master)
294 mpi->mdev_refcnt++;
295 }
296 spin_unlock(&port->mp.mpi_lock);
297
298 return mdev;
299}
300
301void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num)
302{
303 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
304 port_num);
305 struct mlx5_ib_multiport_info *mpi;
306 struct mlx5_ib_port *port;
307
308 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
309 return;
310
311 port = &ibdev->port[port_num - 1];
312
313 spin_lock(&port->mp.mpi_lock);
314 mpi = ibdev->port[port_num - 1].mp.mpi;
315 if (mpi->is_master)
316 goto out;
317
318 mpi->mdev_refcnt--;
319 if (mpi->unaffiliate)
320 complete(&mpi->unref_comp);
321out:
322 spin_unlock(&port->mp.mpi_lock);
323}
324
325static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
326 u16 *active_speed, u8 *active_width)
327{
328 switch (eth_proto_oper) {
329 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
331 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
332 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
333 *active_width = IB_WIDTH_1X;
334 *active_speed = IB_SPEED_SDR;
335 break;
336 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
343 *active_width = IB_WIDTH_1X;
344 *active_speed = IB_SPEED_QDR;
345 break;
346 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
349 *active_width = IB_WIDTH_1X;
350 *active_speed = IB_SPEED_EDR;
351 break;
352 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
356 *active_width = IB_WIDTH_4X;
357 *active_speed = IB_SPEED_QDR;
358 break;
359 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
362 *active_width = IB_WIDTH_1X;
363 *active_speed = IB_SPEED_HDR;
364 break;
365 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
366 *active_width = IB_WIDTH_4X;
367 *active_speed = IB_SPEED_FDR;
368 break;
369 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
373 *active_width = IB_WIDTH_4X;
374 *active_speed = IB_SPEED_EDR;
375 break;
376 default:
377 return -EINVAL;
378 }
379
380 return 0;
381}
382
383static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
384 u8 *active_width)
385{
386 switch (eth_proto_oper) {
387 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
388 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
389 *active_width = IB_WIDTH_1X;
390 *active_speed = IB_SPEED_SDR;
391 break;
392 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
393 *active_width = IB_WIDTH_1X;
394 *active_speed = IB_SPEED_DDR;
395 break;
396 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
397 *active_width = IB_WIDTH_1X;
398 *active_speed = IB_SPEED_QDR;
399 break;
400 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
401 *active_width = IB_WIDTH_4X;
402 *active_speed = IB_SPEED_QDR;
403 break;
404 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
405 *active_width = IB_WIDTH_1X;
406 *active_speed = IB_SPEED_EDR;
407 break;
408 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
409 *active_width = IB_WIDTH_2X;
410 *active_speed = IB_SPEED_EDR;
411 break;
412 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
413 *active_width = IB_WIDTH_1X;
414 *active_speed = IB_SPEED_HDR;
415 break;
416 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
417 *active_width = IB_WIDTH_4X;
418 *active_speed = IB_SPEED_EDR;
419 break;
420 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
421 *active_width = IB_WIDTH_2X;
422 *active_speed = IB_SPEED_HDR;
423 break;
424 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
425 *active_width = IB_WIDTH_1X;
426 *active_speed = IB_SPEED_NDR;
427 break;
428 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
429 *active_width = IB_WIDTH_4X;
430 *active_speed = IB_SPEED_HDR;
431 break;
432 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
433 *active_width = IB_WIDTH_2X;
434 *active_speed = IB_SPEED_NDR;
435 break;
436 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
437 *active_width = IB_WIDTH_4X;
438 *active_speed = IB_SPEED_NDR;
439 break;
440 default:
441 return -EINVAL;
442 }
443
444 return 0;
445}
446
447static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
448 u8 *active_width, bool ext)
449{
450 return ext ?
451 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
452 active_width) :
453 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
454 active_width);
455}
456
457static int mlx5_query_port_roce(struct ib_device *device, u32 port_num,
458 struct ib_port_attr *props)
459{
460 struct mlx5_ib_dev *dev = to_mdev(device);
461 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
462 struct mlx5_core_dev *mdev;
463 struct net_device *ndev, *upper;
464 enum ib_mtu ndev_ib_mtu;
465 bool put_mdev = true;
466 u32 eth_prot_oper;
467 u32 mdev_port_num;
468 bool ext;
469 int err;
470
471 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
472 if (!mdev) {
473
474
475
476 put_mdev = false;
477 mdev = dev->mdev;
478 mdev_port_num = 1;
479 port_num = 1;
480 }
481
482
483
484
485
486 if (dev->is_rep)
487 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
488 1);
489 else
490 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
491 mdev_port_num);
492 if (err)
493 goto out;
494 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
495 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
496
497 props->active_width = IB_WIDTH_4X;
498 props->active_speed = IB_SPEED_QDR;
499
500 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
501 &props->active_width, ext);
502
503 if (!dev->is_rep && dev->mdev->roce.roce_en) {
504 u16 qkey_viol_cntr;
505
506 props->port_cap_flags |= IB_PORT_CM_SUP;
507 props->ip_gids = true;
508 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
509 roce_address_table_size);
510 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
511 props->qkey_viol_cntr = qkey_viol_cntr;
512 }
513 props->max_mtu = IB_MTU_4096;
514 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
515 props->pkey_tbl_len = 1;
516 props->state = IB_PORT_DOWN;
517 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
518
519
520 if (!put_mdev)
521 goto out;
522
523 ndev = mlx5_ib_get_netdev(device, port_num);
524 if (!ndev)
525 goto out;
526
527 if (dev->lag_active) {
528 rcu_read_lock();
529 upper = netdev_master_upper_dev_get_rcu(ndev);
530 if (upper) {
531 dev_put(ndev);
532 ndev = upper;
533 dev_hold(ndev);
534 }
535 rcu_read_unlock();
536 }
537
538 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
539 props->state = IB_PORT_ACTIVE;
540 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
541 }
542
543 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
544
545 dev_put(ndev);
546
547 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
548out:
549 if (put_mdev)
550 mlx5_ib_put_native_port_mdev(dev, port_num);
551 return err;
552}
553
554static int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
555 unsigned int index, const union ib_gid *gid,
556 const struct ib_gid_attr *attr)
557{
558 enum ib_gid_type gid_type;
559 u16 vlan_id = 0xffff;
560 u8 roce_version = 0;
561 u8 roce_l3_type = 0;
562 u8 mac[ETH_ALEN];
563 int ret;
564
565 gid_type = attr->gid_type;
566 if (gid) {
567 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
568 if (ret)
569 return ret;
570 }
571
572 switch (gid_type) {
573 case IB_GID_TYPE_ROCE:
574 roce_version = MLX5_ROCE_VERSION_1;
575 break;
576 case IB_GID_TYPE_ROCE_UDP_ENCAP:
577 roce_version = MLX5_ROCE_VERSION_2;
578 if (gid && ipv6_addr_v4mapped((void *)gid))
579 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
580 else
581 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
582 break;
583
584 default:
585 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
586 }
587
588 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
589 roce_l3_type, gid->raw, mac,
590 vlan_id < VLAN_CFI_MASK, vlan_id,
591 port_num);
592}
593
594static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
595 __always_unused void **context)
596{
597 return set_roce_addr(to_mdev(attr->device), attr->port_num,
598 attr->index, &attr->gid, attr);
599}
600
601static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
602 __always_unused void **context)
603{
604 return set_roce_addr(to_mdev(attr->device), attr->port_num,
605 attr->index, NULL, attr);
606}
607
608__be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
609 const struct ib_gid_attr *attr)
610{
611 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
612 return 0;
613
614 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
615}
616
617static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
618{
619 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
620 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
621 return 0;
622}
623
624enum {
625 MLX5_VPORT_ACCESS_METHOD_MAD,
626 MLX5_VPORT_ACCESS_METHOD_HCA,
627 MLX5_VPORT_ACCESS_METHOD_NIC,
628};
629
630static int mlx5_get_vport_access_method(struct ib_device *ibdev)
631{
632 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
633 return MLX5_VPORT_ACCESS_METHOD_MAD;
634
635 if (mlx5_ib_port_link_layer(ibdev, 1) ==
636 IB_LINK_LAYER_ETHERNET)
637 return MLX5_VPORT_ACCESS_METHOD_NIC;
638
639 return MLX5_VPORT_ACCESS_METHOD_HCA;
640}
641
642static void get_atomic_caps(struct mlx5_ib_dev *dev,
643 u8 atomic_size_qp,
644 struct ib_device_attr *props)
645{
646 u8 tmp;
647 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
648 u8 atomic_req_8B_endianness_mode =
649 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
650
651
652
653
654 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
655 if (((atomic_operations & tmp) == tmp) &&
656 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
657 (atomic_req_8B_endianness_mode)) {
658 props->atomic_cap = IB_ATOMIC_HCA;
659 } else {
660 props->atomic_cap = IB_ATOMIC_NONE;
661 }
662}
663
664static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
665 struct ib_device_attr *props)
666{
667 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
668
669 get_atomic_caps(dev, atomic_size_qp, props);
670}
671
672static int mlx5_query_system_image_guid(struct ib_device *ibdev,
673 __be64 *sys_image_guid)
674{
675 struct mlx5_ib_dev *dev = to_mdev(ibdev);
676 struct mlx5_core_dev *mdev = dev->mdev;
677 u64 tmp;
678 int err;
679
680 switch (mlx5_get_vport_access_method(ibdev)) {
681 case MLX5_VPORT_ACCESS_METHOD_MAD:
682 return mlx5_query_mad_ifc_system_image_guid(ibdev,
683 sys_image_guid);
684
685 case MLX5_VPORT_ACCESS_METHOD_HCA:
686 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
687 break;
688
689 case MLX5_VPORT_ACCESS_METHOD_NIC:
690 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
691 break;
692
693 default:
694 return -EINVAL;
695 }
696
697 if (!err)
698 *sys_image_guid = cpu_to_be64(tmp);
699
700 return err;
701
702}
703
704static int mlx5_query_max_pkeys(struct ib_device *ibdev,
705 u16 *max_pkeys)
706{
707 struct mlx5_ib_dev *dev = to_mdev(ibdev);
708 struct mlx5_core_dev *mdev = dev->mdev;
709
710 switch (mlx5_get_vport_access_method(ibdev)) {
711 case MLX5_VPORT_ACCESS_METHOD_MAD:
712 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
713
714 case MLX5_VPORT_ACCESS_METHOD_HCA:
715 case MLX5_VPORT_ACCESS_METHOD_NIC:
716 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
717 pkey_table_size));
718 return 0;
719
720 default:
721 return -EINVAL;
722 }
723}
724
725static int mlx5_query_vendor_id(struct ib_device *ibdev,
726 u32 *vendor_id)
727{
728 struct mlx5_ib_dev *dev = to_mdev(ibdev);
729
730 switch (mlx5_get_vport_access_method(ibdev)) {
731 case MLX5_VPORT_ACCESS_METHOD_MAD:
732 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
733
734 case MLX5_VPORT_ACCESS_METHOD_HCA:
735 case MLX5_VPORT_ACCESS_METHOD_NIC:
736 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
737
738 default:
739 return -EINVAL;
740 }
741}
742
743static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
744 __be64 *node_guid)
745{
746 u64 tmp;
747 int err;
748
749 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
750 case MLX5_VPORT_ACCESS_METHOD_MAD:
751 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
752
753 case MLX5_VPORT_ACCESS_METHOD_HCA:
754 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
755 break;
756
757 case MLX5_VPORT_ACCESS_METHOD_NIC:
758 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
759 break;
760
761 default:
762 return -EINVAL;
763 }
764
765 if (!err)
766 *node_guid = cpu_to_be64(tmp);
767
768 return err;
769}
770
771struct mlx5_reg_node_desc {
772 u8 desc[IB_DEVICE_NODE_DESC_MAX];
773};
774
775static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
776{
777 struct mlx5_reg_node_desc in;
778
779 if (mlx5_use_mad_ifc(dev))
780 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
781
782 memset(&in, 0, sizeof(in));
783
784 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
785 sizeof(struct mlx5_reg_node_desc),
786 MLX5_REG_NODE_DESC, 0, 0);
787}
788
789static int mlx5_ib_query_device(struct ib_device *ibdev,
790 struct ib_device_attr *props,
791 struct ib_udata *uhw)
792{
793 size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
794 struct mlx5_ib_dev *dev = to_mdev(ibdev);
795 struct mlx5_core_dev *mdev = dev->mdev;
796 int err = -ENOMEM;
797 int max_sq_desc;
798 int max_rq_sg;
799 int max_sq_sg;
800 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
801 bool raw_support = !mlx5_core_mp_enabled(mdev);
802 struct mlx5_ib_query_device_resp resp = {};
803 size_t resp_len;
804 u64 max_tso;
805
806 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
807 if (uhw_outlen && uhw_outlen < resp_len)
808 return -EINVAL;
809
810 resp.response_length = resp_len;
811
812 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
813 return -EINVAL;
814
815 memset(props, 0, sizeof(*props));
816 err = mlx5_query_system_image_guid(ibdev,
817 &props->sys_image_guid);
818 if (err)
819 return err;
820
821 props->max_pkeys = dev->pkey_table_len;
822
823 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
824 if (err)
825 return err;
826
827 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
828 (fw_rev_min(dev->mdev) << 16) |
829 fw_rev_sub(dev->mdev);
830 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
831 IB_DEVICE_PORT_ACTIVE_EVENT |
832 IB_DEVICE_SYS_IMAGE_GUID |
833 IB_DEVICE_RC_RNR_NAK_GEN;
834
835 if (MLX5_CAP_GEN(mdev, pkv))
836 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
837 if (MLX5_CAP_GEN(mdev, qkv))
838 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
839 if (MLX5_CAP_GEN(mdev, apm))
840 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
841 if (MLX5_CAP_GEN(mdev, xrc))
842 props->device_cap_flags |= IB_DEVICE_XRC;
843 if (MLX5_CAP_GEN(mdev, imaicl)) {
844 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
845 IB_DEVICE_MEM_WINDOW_TYPE_2B;
846 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
847
848 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
849 }
850
851 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
852 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
853 if (MLX5_CAP_GEN(mdev, sho)) {
854 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
855
856 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
857 IB_PROT_T10DIF_TYPE_2 |
858 IB_PROT_T10DIF_TYPE_3;
859 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
860 IB_GUARD_T10DIF_CSUM;
861 }
862 if (MLX5_CAP_GEN(mdev, block_lb_mc))
863 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
864
865 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
866 if (MLX5_CAP_ETH(mdev, csum_cap)) {
867
868 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
869 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
870 }
871
872 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
873 props->raw_packet_caps |=
874 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
875
876 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
877 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
878 if (max_tso) {
879 resp.tso_caps.max_tso = 1 << max_tso;
880 resp.tso_caps.supported_qpts |=
881 1 << IB_QPT_RAW_PACKET;
882 resp.response_length += sizeof(resp.tso_caps);
883 }
884 }
885
886 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
887 resp.rss_caps.rx_hash_function =
888 MLX5_RX_HASH_FUNC_TOEPLITZ;
889 resp.rss_caps.rx_hash_fields_mask =
890 MLX5_RX_HASH_SRC_IPV4 |
891 MLX5_RX_HASH_DST_IPV4 |
892 MLX5_RX_HASH_SRC_IPV6 |
893 MLX5_RX_HASH_DST_IPV6 |
894 MLX5_RX_HASH_SRC_PORT_TCP |
895 MLX5_RX_HASH_DST_PORT_TCP |
896 MLX5_RX_HASH_SRC_PORT_UDP |
897 MLX5_RX_HASH_DST_PORT_UDP |
898 MLX5_RX_HASH_INNER;
899 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
900 MLX5_ACCEL_IPSEC_CAP_DEVICE)
901 resp.rss_caps.rx_hash_fields_mask |=
902 MLX5_RX_HASH_IPSEC_SPI;
903 resp.response_length += sizeof(resp.rss_caps);
904 }
905 } else {
906 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
907 resp.response_length += sizeof(resp.tso_caps);
908 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
909 resp.response_length += sizeof(resp.rss_caps);
910 }
911
912 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
913 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
914 props->device_cap_flags |= IB_DEVICE_UD_TSO;
915 }
916
917 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
918 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
919 raw_support)
920 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
921
922 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
923 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
924 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
925
926 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
927 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
928 raw_support) {
929
930 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
931 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
932 }
933
934 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
935 props->max_dm_size =
936 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
937 }
938
939 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
940 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
941
942 if (MLX5_CAP_GEN(mdev, end_pad))
943 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
944
945 props->vendor_part_id = mdev->pdev->device;
946 props->hw_ver = mdev->pdev->revision;
947
948 props->max_mr_size = ~0ull;
949 props->page_size_cap = ~(min_page_size - 1);
950 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
951 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
952 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
953 sizeof(struct mlx5_wqe_data_seg);
954 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
955 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
956 sizeof(struct mlx5_wqe_raddr_seg)) /
957 sizeof(struct mlx5_wqe_data_seg);
958 props->max_send_sge = max_sq_sg;
959 props->max_recv_sge = max_rq_sg;
960 props->max_sge_rd = MLX5_MAX_SGE_RD;
961 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
962 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
963 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
964 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
965 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
966 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
967 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
968 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
969 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
970 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
971 props->max_srq_sge = max_rq_sg - 1;
972 props->max_fast_reg_page_list_len =
973 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
974 props->max_pi_fast_reg_page_list_len =
975 props->max_fast_reg_page_list_len / 2;
976 props->max_sgl_rd =
977 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
978 get_atomic_caps_qp(dev, props);
979 props->masked_atomic_cap = IB_ATOMIC_NONE;
980 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
981 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
982 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
983 props->max_mcast_grp;
984 props->max_ah = INT_MAX;
985 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
986 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
987
988 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
989 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
990 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
991 props->odp_caps = dev->odp_caps;
992 if (!uhw) {
993
994
995
996 props->odp_caps.per_transport_caps.rc_odp_caps &=
997 ~(IB_ODP_SUPPORT_READ |
998 IB_ODP_SUPPORT_SRQ_RECV);
999 props->odp_caps.per_transport_caps.uc_odp_caps &=
1000 ~(IB_ODP_SUPPORT_READ |
1001 IB_ODP_SUPPORT_SRQ_RECV);
1002 props->odp_caps.per_transport_caps.ud_odp_caps &=
1003 ~(IB_ODP_SUPPORT_READ |
1004 IB_ODP_SUPPORT_SRQ_RECV);
1005 props->odp_caps.per_transport_caps.xrc_odp_caps &=
1006 ~(IB_ODP_SUPPORT_READ |
1007 IB_ODP_SUPPORT_SRQ_RECV);
1008 }
1009 }
1010
1011 if (MLX5_CAP_GEN(mdev, cd))
1012 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1013
1014 if (mlx5_core_is_vf(mdev))
1015 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1016
1017 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1018 IB_LINK_LAYER_ETHERNET && raw_support) {
1019 props->rss_caps.max_rwq_indirection_tables =
1020 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1021 props->rss_caps.max_rwq_indirection_table_size =
1022 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1023 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1024 props->max_wq_type_rq =
1025 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1026 }
1027
1028 if (MLX5_CAP_GEN(mdev, tag_matching)) {
1029 props->tm_caps.max_num_tags =
1030 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1031 props->tm_caps.max_ops =
1032 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1033 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1034 }
1035
1036 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1037 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1038 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1039 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1040 }
1041
1042 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1043 props->cq_caps.max_cq_moderation_count =
1044 MLX5_MAX_CQ_COUNT;
1045 props->cq_caps.max_cq_moderation_period =
1046 MLX5_MAX_CQ_PERIOD;
1047 }
1048
1049 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1050 resp.response_length += sizeof(resp.cqe_comp_caps);
1051
1052 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1053 resp.cqe_comp_caps.max_num =
1054 MLX5_CAP_GEN(dev->mdev,
1055 cqe_compression_max_num);
1056
1057 resp.cqe_comp_caps.supported_format =
1058 MLX5_IB_CQE_RES_FORMAT_HASH |
1059 MLX5_IB_CQE_RES_FORMAT_CSUM;
1060
1061 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1062 resp.cqe_comp_caps.supported_format |=
1063 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1064 }
1065 }
1066
1067 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1068 raw_support) {
1069 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1070 MLX5_CAP_GEN(mdev, qos)) {
1071 resp.packet_pacing_caps.qp_rate_limit_max =
1072 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1073 resp.packet_pacing_caps.qp_rate_limit_min =
1074 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1075 resp.packet_pacing_caps.supported_qpts |=
1076 1 << IB_QPT_RAW_PACKET;
1077 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1078 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1079 resp.packet_pacing_caps.cap_flags |=
1080 MLX5_IB_PP_SUPPORT_BURST;
1081 }
1082 resp.response_length += sizeof(resp.packet_pacing_caps);
1083 }
1084
1085 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1086 uhw_outlen) {
1087 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1088 resp.mlx5_ib_support_multi_pkt_send_wqes =
1089 MLX5_IB_ALLOW_MPW;
1090
1091 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1092 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1093 MLX5_IB_SUPPORT_EMPW;
1094
1095 resp.response_length +=
1096 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1097 }
1098
1099 if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1100 resp.response_length += sizeof(resp.flags);
1101
1102 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1103 resp.flags |=
1104 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1105
1106 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1107 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1108 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1109 resp.flags |=
1110 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1111
1112 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1113 }
1114
1115 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1116 resp.response_length += sizeof(resp.sw_parsing_caps);
1117 if (MLX5_CAP_ETH(mdev, swp)) {
1118 resp.sw_parsing_caps.sw_parsing_offloads |=
1119 MLX5_IB_SW_PARSING;
1120
1121 if (MLX5_CAP_ETH(mdev, swp_csum))
1122 resp.sw_parsing_caps.sw_parsing_offloads |=
1123 MLX5_IB_SW_PARSING_CSUM;
1124
1125 if (MLX5_CAP_ETH(mdev, swp_lso))
1126 resp.sw_parsing_caps.sw_parsing_offloads |=
1127 MLX5_IB_SW_PARSING_LSO;
1128
1129 if (resp.sw_parsing_caps.sw_parsing_offloads)
1130 resp.sw_parsing_caps.supported_qpts =
1131 BIT(IB_QPT_RAW_PACKET);
1132 }
1133 }
1134
1135 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1136 raw_support) {
1137 resp.response_length += sizeof(resp.striding_rq_caps);
1138 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1139 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1140 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1141 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1142 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1143 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1144 resp.striding_rq_caps
1145 .min_single_wqe_log_num_of_strides =
1146 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1147 else
1148 resp.striding_rq_caps
1149 .min_single_wqe_log_num_of_strides =
1150 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1151 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1152 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1153 resp.striding_rq_caps.supported_qpts =
1154 BIT(IB_QPT_RAW_PACKET);
1155 }
1156 }
1157
1158 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1159 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1160 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1161 resp.tunnel_offloads_caps |=
1162 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1163 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1164 resp.tunnel_offloads_caps |=
1165 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1166 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1167 resp.tunnel_offloads_caps |=
1168 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1169 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1170 resp.tunnel_offloads_caps |=
1171 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1172 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1173 resp.tunnel_offloads_caps |=
1174 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1175 }
1176
1177 if (uhw_outlen) {
1178 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1179
1180 if (err)
1181 return err;
1182 }
1183
1184 return 0;
1185}
1186
1187static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1188 u8 *ib_width)
1189{
1190 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1191
1192 if (active_width & MLX5_PTYS_WIDTH_1X)
1193 *ib_width = IB_WIDTH_1X;
1194 else if (active_width & MLX5_PTYS_WIDTH_2X)
1195 *ib_width = IB_WIDTH_2X;
1196 else if (active_width & MLX5_PTYS_WIDTH_4X)
1197 *ib_width = IB_WIDTH_4X;
1198 else if (active_width & MLX5_PTYS_WIDTH_8X)
1199 *ib_width = IB_WIDTH_8X;
1200 else if (active_width & MLX5_PTYS_WIDTH_12X)
1201 *ib_width = IB_WIDTH_12X;
1202 else {
1203 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1204 active_width);
1205 *ib_width = IB_WIDTH_4X;
1206 }
1207
1208 return;
1209}
1210
1211static int mlx5_mtu_to_ib_mtu(int mtu)
1212{
1213 switch (mtu) {
1214 case 256: return 1;
1215 case 512: return 2;
1216 case 1024: return 3;
1217 case 2048: return 4;
1218 case 4096: return 5;
1219 default:
1220 pr_warn("invalid mtu\n");
1221 return -1;
1222 }
1223}
1224
1225enum ib_max_vl_num {
1226 __IB_MAX_VL_0 = 1,
1227 __IB_MAX_VL_0_1 = 2,
1228 __IB_MAX_VL_0_3 = 3,
1229 __IB_MAX_VL_0_7 = 4,
1230 __IB_MAX_VL_0_14 = 5,
1231};
1232
1233enum mlx5_vl_hw_cap {
1234 MLX5_VL_HW_0 = 1,
1235 MLX5_VL_HW_0_1 = 2,
1236 MLX5_VL_HW_0_2 = 3,
1237 MLX5_VL_HW_0_3 = 4,
1238 MLX5_VL_HW_0_4 = 5,
1239 MLX5_VL_HW_0_5 = 6,
1240 MLX5_VL_HW_0_6 = 7,
1241 MLX5_VL_HW_0_7 = 8,
1242 MLX5_VL_HW_0_14 = 15
1243};
1244
1245static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1246 u8 *max_vl_num)
1247{
1248 switch (vl_hw_cap) {
1249 case MLX5_VL_HW_0:
1250 *max_vl_num = __IB_MAX_VL_0;
1251 break;
1252 case MLX5_VL_HW_0_1:
1253 *max_vl_num = __IB_MAX_VL_0_1;
1254 break;
1255 case MLX5_VL_HW_0_3:
1256 *max_vl_num = __IB_MAX_VL_0_3;
1257 break;
1258 case MLX5_VL_HW_0_7:
1259 *max_vl_num = __IB_MAX_VL_0_7;
1260 break;
1261 case MLX5_VL_HW_0_14:
1262 *max_vl_num = __IB_MAX_VL_0_14;
1263 break;
1264
1265 default:
1266 return -EINVAL;
1267 }
1268
1269 return 0;
1270}
1271
1272static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port,
1273 struct ib_port_attr *props)
1274{
1275 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1276 struct mlx5_core_dev *mdev = dev->mdev;
1277 struct mlx5_hca_vport_context *rep;
1278 u16 max_mtu;
1279 u16 oper_mtu;
1280 int err;
1281 u16 ib_link_width_oper;
1282 u8 vl_hw_cap;
1283
1284 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1285 if (!rep) {
1286 err = -ENOMEM;
1287 goto out;
1288 }
1289
1290
1291
1292 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1293 if (err)
1294 goto out;
1295
1296 props->lid = rep->lid;
1297 props->lmc = rep->lmc;
1298 props->sm_lid = rep->sm_lid;
1299 props->sm_sl = rep->sm_sl;
1300 props->state = rep->vport_state;
1301 props->phys_state = rep->port_physical_state;
1302 props->port_cap_flags = rep->cap_mask1;
1303 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1304 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1305 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1306 props->bad_pkey_cntr = rep->pkey_violation_counter;
1307 props->qkey_viol_cntr = rep->qkey_violation_counter;
1308 props->subnet_timeout = rep->subnet_timeout;
1309 props->init_type_reply = rep->init_type_reply;
1310
1311 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1312 props->port_cap_flags2 = rep->cap_mask2;
1313
1314 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1315 &props->active_speed, port);
1316 if (err)
1317 goto out;
1318
1319 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1320
1321 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1322
1323 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1324
1325 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1326
1327 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1328
1329 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1330 if (err)
1331 goto out;
1332
1333 err = translate_max_vl_num(ibdev, vl_hw_cap,
1334 &props->max_vl_num);
1335out:
1336 kfree(rep);
1337 return err;
1338}
1339
1340int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1341 struct ib_port_attr *props)
1342{
1343 unsigned int count;
1344 int ret;
1345
1346 switch (mlx5_get_vport_access_method(ibdev)) {
1347 case MLX5_VPORT_ACCESS_METHOD_MAD:
1348 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1349 break;
1350
1351 case MLX5_VPORT_ACCESS_METHOD_HCA:
1352 ret = mlx5_query_hca_port(ibdev, port, props);
1353 break;
1354
1355 case MLX5_VPORT_ACCESS_METHOD_NIC:
1356 ret = mlx5_query_port_roce(ibdev, port, props);
1357 break;
1358
1359 default:
1360 ret = -EINVAL;
1361 }
1362
1363 if (!ret && props) {
1364 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1365 struct mlx5_core_dev *mdev;
1366 bool put_mdev = true;
1367
1368 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1369 if (!mdev) {
1370
1371
1372
1373 mdev = dev->mdev;
1374 port = 1;
1375 put_mdev = false;
1376 }
1377 count = mlx5_core_reserved_gids_count(mdev);
1378 if (put_mdev)
1379 mlx5_ib_put_native_port_mdev(dev, port);
1380 props->gid_tbl_len -= count;
1381 }
1382 return ret;
1383}
1384
1385static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port,
1386 struct ib_port_attr *props)
1387{
1388 return mlx5_query_port_roce(ibdev, port, props);
1389}
1390
1391static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1392 u16 *pkey)
1393{
1394
1395
1396
1397 *pkey = 0xffff;
1398 return 0;
1399}
1400
1401static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
1402 union ib_gid *gid)
1403{
1404 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1405 struct mlx5_core_dev *mdev = dev->mdev;
1406
1407 switch (mlx5_get_vport_access_method(ibdev)) {
1408 case MLX5_VPORT_ACCESS_METHOD_MAD:
1409 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1410
1411 case MLX5_VPORT_ACCESS_METHOD_HCA:
1412 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1413
1414 default:
1415 return -EINVAL;
1416 }
1417
1418}
1419
1420static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port,
1421 u16 index, u16 *pkey)
1422{
1423 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1424 struct mlx5_core_dev *mdev;
1425 bool put_mdev = true;
1426 u32 mdev_port_num;
1427 int err;
1428
1429 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1430 if (!mdev) {
1431
1432
1433
1434 put_mdev = false;
1435 mdev = dev->mdev;
1436 mdev_port_num = 1;
1437 }
1438
1439 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1440 index, pkey);
1441 if (put_mdev)
1442 mlx5_ib_put_native_port_mdev(dev, port);
1443
1444 return err;
1445}
1446
1447static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1448 u16 *pkey)
1449{
1450 switch (mlx5_get_vport_access_method(ibdev)) {
1451 case MLX5_VPORT_ACCESS_METHOD_MAD:
1452 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1453
1454 case MLX5_VPORT_ACCESS_METHOD_HCA:
1455 case MLX5_VPORT_ACCESS_METHOD_NIC:
1456 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1457 default:
1458 return -EINVAL;
1459 }
1460}
1461
1462static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1463 struct ib_device_modify *props)
1464{
1465 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1466 struct mlx5_reg_node_desc in;
1467 struct mlx5_reg_node_desc out;
1468 int err;
1469
1470 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1471 return -EOPNOTSUPP;
1472
1473 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1474 return 0;
1475
1476
1477
1478
1479
1480 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1481 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1482 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1483 if (err)
1484 return err;
1485
1486 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1487
1488 return err;
1489}
1490
1491static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask,
1492 u32 value)
1493{
1494 struct mlx5_hca_vport_context ctx = {};
1495 struct mlx5_core_dev *mdev;
1496 u32 mdev_port_num;
1497 int err;
1498
1499 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1500 if (!mdev)
1501 return -ENODEV;
1502
1503 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1504 if (err)
1505 goto out;
1506
1507 if (~ctx.cap_mask1_perm & mask) {
1508 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1509 mask, ctx.cap_mask1_perm);
1510 err = -EINVAL;
1511 goto out;
1512 }
1513
1514 ctx.cap_mask1 = value;
1515 ctx.cap_mask1_perm = mask;
1516 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1517 0, &ctx);
1518
1519out:
1520 mlx5_ib_put_native_port_mdev(dev, port_num);
1521
1522 return err;
1523}
1524
1525static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask,
1526 struct ib_port_modify *props)
1527{
1528 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1529 struct ib_port_attr attr;
1530 u32 tmp;
1531 int err;
1532 u32 change_mask;
1533 u32 value;
1534 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1535 IB_LINK_LAYER_INFINIBAND);
1536
1537
1538
1539
1540 if (!is_ib)
1541 return 0;
1542
1543 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1544 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1545 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1546 return set_port_caps_atomic(dev, port, change_mask, value);
1547 }
1548
1549 mutex_lock(&dev->cap_mask_mutex);
1550
1551 err = ib_query_port(ibdev, port, &attr);
1552 if (err)
1553 goto out;
1554
1555 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1556 ~props->clr_port_cap_mask;
1557
1558 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1559
1560out:
1561 mutex_unlock(&dev->cap_mask_mutex);
1562 return err;
1563}
1564
1565static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1566{
1567 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1568 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1569}
1570
1571static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1572{
1573
1574 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1575 return MLX5_MIN_DYN_BFREGS;
1576
1577 return MLX5_MAX_DYN_BFREGS;
1578}
1579
1580static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1581 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1582 struct mlx5_bfreg_info *bfregi)
1583{
1584 int uars_per_sys_page;
1585 int bfregs_per_sys_page;
1586 int ref_bfregs = req->total_num_bfregs;
1587
1588 if (req->total_num_bfregs == 0)
1589 return -EINVAL;
1590
1591 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1592 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1593
1594 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1595 return -ENOMEM;
1596
1597 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1598 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1599
1600 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1601 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1602 return -EINVAL;
1603
1604 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1605 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1606 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1607 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1608
1609 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1610 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1611 lib_uar_4k ? "yes" : "no", ref_bfregs,
1612 req->total_num_bfregs, bfregi->total_num_bfregs,
1613 bfregi->num_sys_pages);
1614
1615 return 0;
1616}
1617
1618static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1619{
1620 struct mlx5_bfreg_info *bfregi;
1621 int err;
1622 int i;
1623
1624 bfregi = &context->bfregi;
1625 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1626 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1627 if (err)
1628 goto error;
1629
1630 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1631 }
1632
1633 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1634 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1635
1636 return 0;
1637
1638error:
1639 for (--i; i >= 0; i--)
1640 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1641 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1642
1643 return err;
1644}
1645
1646static void deallocate_uars(struct mlx5_ib_dev *dev,
1647 struct mlx5_ib_ucontext *context)
1648{
1649 struct mlx5_bfreg_info *bfregi;
1650 int i;
1651
1652 bfregi = &context->bfregi;
1653 for (i = 0; i < bfregi->num_sys_pages; i++)
1654 if (i < bfregi->num_static_sys_pages ||
1655 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1656 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1657}
1658
1659int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1660{
1661 int err = 0;
1662
1663 mutex_lock(&dev->lb.mutex);
1664 if (td)
1665 dev->lb.user_td++;
1666 if (qp)
1667 dev->lb.qps++;
1668
1669 if (dev->lb.user_td == 2 ||
1670 dev->lb.qps == 1) {
1671 if (!dev->lb.enabled) {
1672 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1673 dev->lb.enabled = true;
1674 }
1675 }
1676
1677 mutex_unlock(&dev->lb.mutex);
1678
1679 return err;
1680}
1681
1682void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1683{
1684 mutex_lock(&dev->lb.mutex);
1685 if (td)
1686 dev->lb.user_td--;
1687 if (qp)
1688 dev->lb.qps--;
1689
1690 if (dev->lb.user_td == 1 &&
1691 dev->lb.qps == 0) {
1692 if (dev->lb.enabled) {
1693 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1694 dev->lb.enabled = false;
1695 }
1696 }
1697
1698 mutex_unlock(&dev->lb.mutex);
1699}
1700
1701static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1702 u16 uid)
1703{
1704 int err;
1705
1706 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1707 return 0;
1708
1709 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1710 if (err)
1711 return err;
1712
1713 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1714 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1715 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1716 return err;
1717
1718 return mlx5_ib_enable_lb(dev, true, false);
1719}
1720
1721static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1722 u16 uid)
1723{
1724 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1725 return;
1726
1727 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1728
1729 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1730 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1731 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1732 return;
1733
1734 mlx5_ib_disable_lb(dev, true, false);
1735}
1736
1737static int set_ucontext_resp(struct ib_ucontext *uctx,
1738 struct mlx5_ib_alloc_ucontext_resp *resp)
1739{
1740 struct ib_device *ibdev = uctx->device;
1741 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1742 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1743 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1744 int err;
1745
1746 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1747 err = mlx5_cmd_dump_fill_mkey(dev->mdev,
1748 &resp->dump_fill_mkey);
1749 if (err)
1750 return err;
1751 resp->comp_mask |=
1752 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1753 }
1754
1755 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1756 if (dev->wc_support)
1757 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1758 log_bf_reg_size);
1759 resp->cache_line_size = cache_line_size();
1760 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1761 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1762 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1763 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1764 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1765 resp->cqe_version = context->cqe_version;
1766 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1767 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1768 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1769 MLX5_CAP_GEN(dev->mdev,
1770 num_of_uars_per_page) : 1;
1771
1772 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1773 MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1774 if (mlx5_get_flow_namespace(dev->mdev,
1775 MLX5_FLOW_NAMESPACE_EGRESS))
1776 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1777 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1778 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1779 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1780 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1781 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1782 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1783 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1784 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1785
1786 }
1787
1788 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
1789 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
1790 resp->num_ports = dev->num_ports;
1791 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1792 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1793
1794 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1795 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1796 resp->eth_min_inline++;
1797 }
1798
1799 if (dev->mdev->clock_info)
1800 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1801
1802
1803
1804
1805
1806
1807
1808 if (PAGE_SIZE <= 4096) {
1809 resp->comp_mask |=
1810 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1811 resp->hca_core_clock_offset =
1812 offsetof(struct mlx5_init_seg,
1813 internal_timer_h) % PAGE_SIZE;
1814 }
1815
1816 if (MLX5_CAP_GEN(dev->mdev, ece_support))
1817 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
1818
1819 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) &&
1820 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) &&
1821 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format)))
1822 resp->comp_mask |=
1823 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
1824
1825 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1826
1827 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
1828 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
1829
1830 return 0;
1831}
1832
1833static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1834 struct ib_udata *udata)
1835{
1836 struct ib_device *ibdev = uctx->device;
1837 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1838 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1839 struct mlx5_ib_alloc_ucontext_resp resp = {};
1840 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1841 struct mlx5_bfreg_info *bfregi;
1842 int ver;
1843 int err;
1844 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1845 max_cqe_version);
1846 bool lib_uar_4k;
1847 bool lib_uar_dyn;
1848
1849 if (!dev->ib_active)
1850 return -EAGAIN;
1851
1852 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1853 ver = 0;
1854 else if (udata->inlen >= min_req_v2)
1855 ver = 2;
1856 else
1857 return -EINVAL;
1858
1859 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1860 if (err)
1861 return err;
1862
1863 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1864 return -EOPNOTSUPP;
1865
1866 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1867 return -EOPNOTSUPP;
1868
1869 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1870 MLX5_NON_FP_BFREGS_PER_UAR);
1871 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1872 return -EINVAL;
1873
1874 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1875 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1876 bfregi = &context->bfregi;
1877
1878 if (lib_uar_dyn) {
1879 bfregi->lib_uar_dyn = lib_uar_dyn;
1880 goto uar_done;
1881 }
1882
1883
1884 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1885 if (err)
1886 goto out_ctx;
1887
1888 mutex_init(&bfregi->lock);
1889 bfregi->lib_uar_4k = lib_uar_4k;
1890 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1891 GFP_KERNEL);
1892 if (!bfregi->count) {
1893 err = -ENOMEM;
1894 goto out_ctx;
1895 }
1896
1897 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1898 sizeof(*bfregi->sys_pages),
1899 GFP_KERNEL);
1900 if (!bfregi->sys_pages) {
1901 err = -ENOMEM;
1902 goto out_count;
1903 }
1904
1905 err = allocate_uars(dev, context);
1906 if (err)
1907 goto out_sys_pages;
1908
1909uar_done:
1910 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1911 err = mlx5_ib_devx_create(dev, true);
1912 if (err < 0)
1913 goto out_uars;
1914 context->devx_uid = err;
1915 }
1916
1917 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1918 context->devx_uid);
1919 if (err)
1920 goto out_devx;
1921
1922 INIT_LIST_HEAD(&context->db_page_list);
1923 mutex_init(&context->db_page_mutex);
1924
1925 context->cqe_version = min_t(__u8,
1926 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1927 req.max_cqe_version);
1928
1929 err = set_ucontext_resp(uctx, &resp);
1930 if (err)
1931 goto out_mdev;
1932
1933 resp.response_length = min(udata->outlen, sizeof(resp));
1934 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1935 if (err)
1936 goto out_mdev;
1937
1938 bfregi->ver = ver;
1939 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1940 context->lib_caps = req.lib_caps;
1941 print_lib_caps(dev, context->lib_caps);
1942
1943 if (mlx5_ib_lag_should_assign_affinity(dev)) {
1944 u32 port = mlx5_core_native_port_num(dev->mdev) - 1;
1945
1946 atomic_set(&context->tx_port_affinity,
1947 atomic_add_return(
1948 1, &dev->port[port].roce.tx_port_affinity));
1949 }
1950
1951 return 0;
1952
1953out_mdev:
1954 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1955out_devx:
1956 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1957 mlx5_ib_devx_destroy(dev, context->devx_uid);
1958
1959out_uars:
1960 deallocate_uars(dev, context);
1961
1962out_sys_pages:
1963 kfree(bfregi->sys_pages);
1964
1965out_count:
1966 kfree(bfregi->count);
1967
1968out_ctx:
1969 return err;
1970}
1971
1972static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
1973 struct uverbs_attr_bundle *attrs)
1974{
1975 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
1976 int ret;
1977
1978 ret = set_ucontext_resp(ibcontext, &uctx_resp);
1979 if (ret)
1980 return ret;
1981
1982 uctx_resp.response_length =
1983 min_t(size_t,
1984 uverbs_attr_get_len(attrs,
1985 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
1986 sizeof(uctx_resp));
1987
1988 ret = uverbs_copy_to_struct_or_zero(attrs,
1989 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
1990 &uctx_resp,
1991 sizeof(uctx_resp));
1992 return ret;
1993}
1994
1995static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1996{
1997 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1998 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1999 struct mlx5_bfreg_info *bfregi;
2000
2001 bfregi = &context->bfregi;
2002 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2003
2004 if (context->devx_uid)
2005 mlx5_ib_devx_destroy(dev, context->devx_uid);
2006
2007 deallocate_uars(dev, context);
2008 kfree(bfregi->sys_pages);
2009 kfree(bfregi->count);
2010}
2011
2012static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2013 int uar_idx)
2014{
2015 int fw_uars_per_page;
2016
2017 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2018
2019 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2020}
2021
2022static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2023 int uar_idx)
2024{
2025 unsigned int fw_uars_per_page;
2026
2027 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2028 MLX5_UARS_IN_PAGE : 1;
2029
2030 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2031}
2032
2033static int get_command(unsigned long offset)
2034{
2035 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2036}
2037
2038static int get_arg(unsigned long offset)
2039{
2040 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2041}
2042
2043static int get_index(unsigned long offset)
2044{
2045 return get_arg(offset);
2046}
2047
2048
2049static int get_extended_index(unsigned long offset)
2050{
2051 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2052}
2053
2054
2055static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2056{
2057}
2058
2059static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2060{
2061 switch (cmd) {
2062 case MLX5_IB_MMAP_WC_PAGE:
2063 return "WC";
2064 case MLX5_IB_MMAP_REGULAR_PAGE:
2065 return "best effort WC";
2066 case MLX5_IB_MMAP_NC_PAGE:
2067 return "NC";
2068 case MLX5_IB_MMAP_DEVICE_MEM:
2069 return "Device Memory";
2070 default:
2071 return NULL;
2072 }
2073}
2074
2075static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2076 struct vm_area_struct *vma,
2077 struct mlx5_ib_ucontext *context)
2078{
2079 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2080 !(vma->vm_flags & VM_SHARED))
2081 return -EINVAL;
2082
2083 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2084 return -EOPNOTSUPP;
2085
2086 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2087 return -EPERM;
2088 vma->vm_flags &= ~VM_MAYWRITE;
2089
2090 if (!dev->mdev->clock_info)
2091 return -EOPNOTSUPP;
2092
2093 return vm_insert_page(vma, vma->vm_start,
2094 virt_to_page(dev->mdev->clock_info));
2095}
2096
2097static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2098{
2099 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2100 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2101 struct mlx5_var_table *var_table = &dev->var_table;
2102
2103 switch (mentry->mmap_flag) {
2104 case MLX5_IB_MMAP_TYPE_MEMIC:
2105 case MLX5_IB_MMAP_TYPE_MEMIC_OP:
2106 mlx5_ib_dm_mmap_free(dev, mentry);
2107 break;
2108 case MLX5_IB_MMAP_TYPE_VAR:
2109 mutex_lock(&var_table->bitmap_lock);
2110 clear_bit(mentry->page_idx, var_table->bitmap);
2111 mutex_unlock(&var_table->bitmap_lock);
2112 kfree(mentry);
2113 break;
2114 case MLX5_IB_MMAP_TYPE_UAR_WC:
2115 case MLX5_IB_MMAP_TYPE_UAR_NC:
2116 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx);
2117 kfree(mentry);
2118 break;
2119 default:
2120 WARN_ON(true);
2121 }
2122}
2123
2124static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2125 struct vm_area_struct *vma,
2126 struct mlx5_ib_ucontext *context)
2127{
2128 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2129 int err;
2130 unsigned long idx;
2131 phys_addr_t pfn;
2132 pgprot_t prot;
2133 u32 bfreg_dyn_idx = 0;
2134 u32 uar_index;
2135 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2136 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2137 bfregi->num_static_sys_pages;
2138
2139 if (bfregi->lib_uar_dyn)
2140 return -EINVAL;
2141
2142 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2143 return -EINVAL;
2144
2145 if (dyn_uar)
2146 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2147 else
2148 idx = get_index(vma->vm_pgoff);
2149
2150 if (idx >= max_valid_idx) {
2151 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2152 idx, max_valid_idx);
2153 return -EINVAL;
2154 }
2155
2156 switch (cmd) {
2157 case MLX5_IB_MMAP_WC_PAGE:
2158 case MLX5_IB_MMAP_ALLOC_WC:
2159 case MLX5_IB_MMAP_REGULAR_PAGE:
2160
2161 prot = pgprot_writecombine(vma->vm_page_prot);
2162 break;
2163 case MLX5_IB_MMAP_NC_PAGE:
2164 prot = pgprot_noncached(vma->vm_page_prot);
2165 break;
2166 default:
2167 return -EINVAL;
2168 }
2169
2170 if (dyn_uar) {
2171 int uars_per_page;
2172
2173 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2174 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2175 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2176 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2177 bfreg_dyn_idx, bfregi->total_num_bfregs);
2178 return -EINVAL;
2179 }
2180
2181 mutex_lock(&bfregi->lock);
2182
2183
2184
2185 if (bfregi->count[bfreg_dyn_idx]) {
2186 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2187 mutex_unlock(&bfregi->lock);
2188 return -EINVAL;
2189 }
2190
2191 bfregi->count[bfreg_dyn_idx]++;
2192 mutex_unlock(&bfregi->lock);
2193
2194 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2195 if (err) {
2196 mlx5_ib_warn(dev, "UAR alloc failed\n");
2197 goto free_bfreg;
2198 }
2199 } else {
2200 uar_index = bfregi->sys_pages[idx];
2201 }
2202
2203 pfn = uar_index2pfn(dev, uar_index);
2204 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2205
2206 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2207 prot, NULL);
2208 if (err) {
2209 mlx5_ib_err(dev,
2210 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2211 err, mmap_cmd2str(cmd));
2212 goto err;
2213 }
2214
2215 if (dyn_uar)
2216 bfregi->sys_pages[idx] = uar_index;
2217 return 0;
2218
2219err:
2220 if (!dyn_uar)
2221 return err;
2222
2223 mlx5_cmd_free_uar(dev->mdev, idx);
2224
2225free_bfreg:
2226 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2227
2228 return err;
2229}
2230
2231static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2232{
2233 unsigned long idx;
2234 u8 command;
2235
2236 command = get_command(vma->vm_pgoff);
2237 idx = get_extended_index(vma->vm_pgoff);
2238
2239 return (command << 16 | idx);
2240}
2241
2242static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2243 struct vm_area_struct *vma,
2244 struct ib_ucontext *ucontext)
2245{
2246 struct mlx5_user_mmap_entry *mentry;
2247 struct rdma_user_mmap_entry *entry;
2248 unsigned long pgoff;
2249 pgprot_t prot;
2250 phys_addr_t pfn;
2251 int ret;
2252
2253 pgoff = mlx5_vma_to_pgoff(vma);
2254 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2255 if (!entry)
2256 return -EINVAL;
2257
2258 mentry = to_mmmap(entry);
2259 pfn = (mentry->address >> PAGE_SHIFT);
2260 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2261 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2262 prot = pgprot_noncached(vma->vm_page_prot);
2263 else
2264 prot = pgprot_writecombine(vma->vm_page_prot);
2265 ret = rdma_user_mmap_io(ucontext, vma, pfn,
2266 entry->npages * PAGE_SIZE,
2267 prot,
2268 entry);
2269 rdma_user_mmap_entry_put(&mentry->rdma_entry);
2270 return ret;
2271}
2272
2273static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2274{
2275 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2276 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2277
2278 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2279 (index & 0xFF)) << PAGE_SHIFT;
2280}
2281
2282static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2283{
2284 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2285 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2286 unsigned long command;
2287 phys_addr_t pfn;
2288
2289 command = get_command(vma->vm_pgoff);
2290 switch (command) {
2291 case MLX5_IB_MMAP_WC_PAGE:
2292 case MLX5_IB_MMAP_ALLOC_WC:
2293 if (!dev->wc_support)
2294 return -EPERM;
2295 fallthrough;
2296 case MLX5_IB_MMAP_NC_PAGE:
2297 case MLX5_IB_MMAP_REGULAR_PAGE:
2298 return uar_mmap(dev, command, vma, context);
2299
2300 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2301 return -ENOSYS;
2302
2303 case MLX5_IB_MMAP_CORE_CLOCK:
2304 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2305 return -EINVAL;
2306
2307 if (vma->vm_flags & VM_WRITE)
2308 return -EPERM;
2309 vma->vm_flags &= ~VM_MAYWRITE;
2310
2311
2312 if (PAGE_SIZE > 4096)
2313 return -EOPNOTSUPP;
2314
2315 pfn = (dev->mdev->iseg_base +
2316 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2317 PAGE_SHIFT;
2318 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2319 PAGE_SIZE,
2320 pgprot_noncached(vma->vm_page_prot),
2321 NULL);
2322 case MLX5_IB_MMAP_CLOCK_INFO:
2323 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2324
2325 default:
2326 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2327 }
2328
2329 return 0;
2330}
2331
2332static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2333{
2334 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2335 struct ib_device *ibdev = ibpd->device;
2336 struct mlx5_ib_alloc_pd_resp resp;
2337 int err;
2338 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2339 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2340 u16 uid = 0;
2341 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2342 udata, struct mlx5_ib_ucontext, ibucontext);
2343
2344 uid = context ? context->devx_uid : 0;
2345 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2346 MLX5_SET(alloc_pd_in, in, uid, uid);
2347 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2348 if (err)
2349 return err;
2350
2351 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2352 pd->uid = uid;
2353 if (udata) {
2354 resp.pdn = pd->pdn;
2355 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2356 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2357 return -EFAULT;
2358 }
2359 }
2360
2361 return 0;
2362}
2363
2364static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2365{
2366 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2367 struct mlx5_ib_pd *mpd = to_mpd(pd);
2368
2369 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2370}
2371
2372static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2373{
2374 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2375 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2376 int err;
2377 u16 uid;
2378
2379 uid = ibqp->pd ?
2380 to_mpd(ibqp->pd)->uid : 0;
2381
2382 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2383 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2384 return -EOPNOTSUPP;
2385 }
2386
2387 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2388 if (err)
2389 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2390 ibqp->qp_num, gid->raw);
2391
2392 return err;
2393}
2394
2395static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2396{
2397 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2398 int err;
2399 u16 uid;
2400
2401 uid = ibqp->pd ?
2402 to_mpd(ibqp->pd)->uid : 0;
2403 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2404 if (err)
2405 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2406 ibqp->qp_num, gid->raw);
2407
2408 return err;
2409}
2410
2411static int init_node_data(struct mlx5_ib_dev *dev)
2412{
2413 int err;
2414
2415 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2416 if (err)
2417 return err;
2418
2419 dev->mdev->rev_id = dev->mdev->pdev->revision;
2420
2421 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2422}
2423
2424static ssize_t fw_pages_show(struct device *device,
2425 struct device_attribute *attr, char *buf)
2426{
2427 struct mlx5_ib_dev *dev =
2428 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2429
2430 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
2431}
2432static DEVICE_ATTR_RO(fw_pages);
2433
2434static ssize_t reg_pages_show(struct device *device,
2435 struct device_attribute *attr, char *buf)
2436{
2437 struct mlx5_ib_dev *dev =
2438 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2439
2440 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2441}
2442static DEVICE_ATTR_RO(reg_pages);
2443
2444static ssize_t hca_type_show(struct device *device,
2445 struct device_attribute *attr, char *buf)
2446{
2447 struct mlx5_ib_dev *dev =
2448 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2449
2450 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
2451}
2452static DEVICE_ATTR_RO(hca_type);
2453
2454static ssize_t hw_rev_show(struct device *device,
2455 struct device_attribute *attr, char *buf)
2456{
2457 struct mlx5_ib_dev *dev =
2458 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2459
2460 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
2461}
2462static DEVICE_ATTR_RO(hw_rev);
2463
2464static ssize_t board_id_show(struct device *device,
2465 struct device_attribute *attr, char *buf)
2466{
2467 struct mlx5_ib_dev *dev =
2468 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2469
2470 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2471 dev->mdev->board_id);
2472}
2473static DEVICE_ATTR_RO(board_id);
2474
2475static struct attribute *mlx5_class_attributes[] = {
2476 &dev_attr_hw_rev.attr,
2477 &dev_attr_hca_type.attr,
2478 &dev_attr_board_id.attr,
2479 &dev_attr_fw_pages.attr,
2480 &dev_attr_reg_pages.attr,
2481 NULL,
2482};
2483
2484static const struct attribute_group mlx5_attr_group = {
2485 .attrs = mlx5_class_attributes,
2486};
2487
2488static void pkey_change_handler(struct work_struct *work)
2489{
2490 struct mlx5_ib_port_resources *ports =
2491 container_of(work, struct mlx5_ib_port_resources,
2492 pkey_change_work);
2493
2494 mlx5_ib_gsi_pkey_change(ports->gsi);
2495}
2496
2497static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2498{
2499 struct mlx5_ib_qp *mqp;
2500 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2501 struct mlx5_core_cq *mcq;
2502 struct list_head cq_armed_list;
2503 unsigned long flags_qp;
2504 unsigned long flags_cq;
2505 unsigned long flags;
2506
2507 INIT_LIST_HEAD(&cq_armed_list);
2508
2509
2510 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2511 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2512 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2513 if (mqp->sq.tail != mqp->sq.head) {
2514 send_mcq = to_mcq(mqp->ibqp.send_cq);
2515 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2516 if (send_mcq->mcq.comp &&
2517 mqp->ibqp.send_cq->comp_handler) {
2518 if (!send_mcq->mcq.reset_notify_added) {
2519 send_mcq->mcq.reset_notify_added = 1;
2520 list_add_tail(&send_mcq->mcq.reset_notify,
2521 &cq_armed_list);
2522 }
2523 }
2524 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2525 }
2526 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2527 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2528
2529 if (!mqp->ibqp.srq) {
2530 if (mqp->rq.tail != mqp->rq.head) {
2531 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2532 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2533 if (recv_mcq->mcq.comp &&
2534 mqp->ibqp.recv_cq->comp_handler) {
2535 if (!recv_mcq->mcq.reset_notify_added) {
2536 recv_mcq->mcq.reset_notify_added = 1;
2537 list_add_tail(&recv_mcq->mcq.reset_notify,
2538 &cq_armed_list);
2539 }
2540 }
2541 spin_unlock_irqrestore(&recv_mcq->lock,
2542 flags_cq);
2543 }
2544 }
2545 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2546 }
2547
2548
2549
2550 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2551 mcq->comp(mcq, NULL);
2552 }
2553 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2554}
2555
2556static void delay_drop_handler(struct work_struct *work)
2557{
2558 int err;
2559 struct mlx5_ib_delay_drop *delay_drop =
2560 container_of(work, struct mlx5_ib_delay_drop,
2561 delay_drop_work);
2562
2563 atomic_inc(&delay_drop->events_cnt);
2564
2565 mutex_lock(&delay_drop->lock);
2566 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
2567 if (err) {
2568 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2569 delay_drop->timeout);
2570 delay_drop->activate = false;
2571 }
2572 mutex_unlock(&delay_drop->lock);
2573}
2574
2575static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2576 struct ib_event *ibev)
2577{
2578 u32 port = (eqe->data.port.port >> 4) & 0xf;
2579
2580 switch (eqe->sub_type) {
2581 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
2582 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2583 IB_LINK_LAYER_ETHERNET)
2584 schedule_work(&ibdev->delay_drop.delay_drop_work);
2585 break;
2586 default:
2587 return;
2588 }
2589}
2590
2591static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2592 struct ib_event *ibev)
2593{
2594 u32 port = (eqe->data.port.port >> 4) & 0xf;
2595
2596 ibev->element.port_num = port;
2597
2598 switch (eqe->sub_type) {
2599 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2600 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2601 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2602
2603
2604
2605 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2606 IB_LINK_LAYER_ETHERNET)
2607 return -EINVAL;
2608
2609 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2610 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2611 break;
2612
2613 case MLX5_PORT_CHANGE_SUBTYPE_LID:
2614 ibev->event = IB_EVENT_LID_CHANGE;
2615 break;
2616
2617 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2618 ibev->event = IB_EVENT_PKEY_CHANGE;
2619 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2620 break;
2621
2622 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2623 ibev->event = IB_EVENT_GID_CHANGE;
2624 break;
2625
2626 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2627 ibev->event = IB_EVENT_CLIENT_REREGISTER;
2628 break;
2629 default:
2630 return -EINVAL;
2631 }
2632
2633 return 0;
2634}
2635
2636static void mlx5_ib_handle_event(struct work_struct *_work)
2637{
2638 struct mlx5_ib_event_work *work =
2639 container_of(_work, struct mlx5_ib_event_work, work);
2640 struct mlx5_ib_dev *ibdev;
2641 struct ib_event ibev;
2642 bool fatal = false;
2643
2644 if (work->is_slave) {
2645 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
2646 if (!ibdev)
2647 goto out;
2648 } else {
2649 ibdev = work->dev;
2650 }
2651
2652 switch (work->event) {
2653 case MLX5_DEV_EVENT_SYS_ERROR:
2654 ibev.event = IB_EVENT_DEVICE_FATAL;
2655 mlx5_ib_handle_internal_error(ibdev);
2656 ibev.element.port_num = (u8)(unsigned long)work->param;
2657 fatal = true;
2658 break;
2659 case MLX5_EVENT_TYPE_PORT_CHANGE:
2660 if (handle_port_change(ibdev, work->param, &ibev))
2661 goto out;
2662 break;
2663 case MLX5_EVENT_TYPE_GENERAL_EVENT:
2664 handle_general_event(ibdev, work->param, &ibev);
2665 fallthrough;
2666 default:
2667 goto out;
2668 }
2669
2670 ibev.device = &ibdev->ib_dev;
2671
2672 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2673 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
2674 goto out;
2675 }
2676
2677 if (ibdev->ib_active)
2678 ib_dispatch_event(&ibev);
2679
2680 if (fatal)
2681 ibdev->ib_active = false;
2682out:
2683 kfree(work);
2684}
2685
2686static int mlx5_ib_event(struct notifier_block *nb,
2687 unsigned long event, void *param)
2688{
2689 struct mlx5_ib_event_work *work;
2690
2691 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2692 if (!work)
2693 return NOTIFY_DONE;
2694
2695 INIT_WORK(&work->work, mlx5_ib_handle_event);
2696 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2697 work->is_slave = false;
2698 work->param = param;
2699 work->event = event;
2700
2701 queue_work(mlx5_ib_event_wq, &work->work);
2702
2703 return NOTIFY_OK;
2704}
2705
2706static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2707 unsigned long event, void *param)
2708{
2709 struct mlx5_ib_event_work *work;
2710
2711 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2712 if (!work)
2713 return NOTIFY_DONE;
2714
2715 INIT_WORK(&work->work, mlx5_ib_handle_event);
2716 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2717 work->is_slave = true;
2718 work->param = param;
2719 work->event = event;
2720 queue_work(mlx5_ib_event_wq, &work->work);
2721
2722 return NOTIFY_OK;
2723}
2724
2725static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2726{
2727 struct mlx5_hca_vport_context vport_ctx;
2728 int err;
2729 int port;
2730
2731 for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) {
2732 dev->port_caps[port - 1].has_smi = false;
2733 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2734 MLX5_CAP_PORT_TYPE_IB) {
2735 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2736 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2737 port, 0,
2738 &vport_ctx);
2739 if (err) {
2740 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2741 port, err);
2742 return err;
2743 }
2744 dev->port_caps[port - 1].has_smi =
2745 vport_ctx.has_smi;
2746 } else {
2747 dev->port_caps[port - 1].has_smi = true;
2748 }
2749 }
2750 }
2751 return 0;
2752}
2753
2754static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2755{
2756 unsigned int port;
2757
2758 rdma_for_each_port (&dev->ib_dev, port)
2759 mlx5_query_ext_port_caps(dev, port);
2760}
2761
2762static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2763{
2764 switch (umr_fence_cap) {
2765 case MLX5_CAP_UMR_FENCE_NONE:
2766 return MLX5_FENCE_MODE_NONE;
2767 case MLX5_CAP_UMR_FENCE_SMALL:
2768 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2769 default:
2770 return MLX5_FENCE_MODE_STRONG_ORDERING;
2771 }
2772}
2773
2774static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
2775{
2776 struct mlx5_ib_resources *devr = &dev->devr;
2777 struct ib_srq_init_attr attr;
2778 struct ib_device *ibdev;
2779 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2780 int port;
2781 int ret = 0;
2782
2783 ibdev = &dev->ib_dev;
2784
2785 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2786 return -EOPNOTSUPP;
2787
2788 mutex_init(&devr->mutex);
2789
2790 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
2791 if (!devr->p0)
2792 return -ENOMEM;
2793
2794 devr->p0->device = ibdev;
2795 devr->p0->uobject = NULL;
2796 atomic_set(&devr->p0->usecnt, 0);
2797
2798 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
2799 if (ret)
2800 goto error0;
2801
2802 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
2803 if (!devr->c0) {
2804 ret = -ENOMEM;
2805 goto error1;
2806 }
2807
2808 devr->c0->device = &dev->ib_dev;
2809 atomic_set(&devr->c0->usecnt, 0);
2810
2811 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
2812 if (ret)
2813 goto err_create_cq;
2814
2815 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
2816 if (ret)
2817 goto error2;
2818
2819 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
2820 if (ret)
2821 goto error3;
2822
2823 memset(&attr, 0, sizeof(attr));
2824 attr.attr.max_sge = 1;
2825 attr.attr.max_wr = 1;
2826 attr.srq_type = IB_SRQT_XRC;
2827 attr.ext.cq = devr->c0;
2828
2829 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
2830 if (!devr->s0) {
2831 ret = -ENOMEM;
2832 goto error4;
2833 }
2834
2835 devr->s0->device = &dev->ib_dev;
2836 devr->s0->pd = devr->p0;
2837 devr->s0->srq_type = IB_SRQT_XRC;
2838 devr->s0->ext.cq = devr->c0;
2839 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
2840 if (ret)
2841 goto err_create;
2842
2843 atomic_inc(&devr->s0->ext.cq->usecnt);
2844 atomic_inc(&devr->p0->usecnt);
2845 atomic_set(&devr->s0->usecnt, 0);
2846
2847 memset(&attr, 0, sizeof(attr));
2848 attr.attr.max_sge = 1;
2849 attr.attr.max_wr = 1;
2850 attr.srq_type = IB_SRQT_BASIC;
2851 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
2852 if (!devr->s1) {
2853 ret = -ENOMEM;
2854 goto error5;
2855 }
2856
2857 devr->s1->device = &dev->ib_dev;
2858 devr->s1->pd = devr->p0;
2859 devr->s1->srq_type = IB_SRQT_BASIC;
2860 devr->s1->ext.cq = devr->c0;
2861
2862 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
2863 if (ret)
2864 goto error6;
2865
2866 atomic_inc(&devr->p0->usecnt);
2867 atomic_set(&devr->s1->usecnt, 0);
2868
2869 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2870 INIT_WORK(&devr->ports[port].pkey_change_work,
2871 pkey_change_handler);
2872
2873 return 0;
2874
2875error6:
2876 kfree(devr->s1);
2877error5:
2878 mlx5_ib_destroy_srq(devr->s0, NULL);
2879err_create:
2880 kfree(devr->s0);
2881error4:
2882 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2883error3:
2884 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2885error2:
2886 mlx5_ib_destroy_cq(devr->c0, NULL);
2887err_create_cq:
2888 kfree(devr->c0);
2889error1:
2890 mlx5_ib_dealloc_pd(devr->p0, NULL);
2891error0:
2892 kfree(devr->p0);
2893 return ret;
2894}
2895
2896static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
2897{
2898 struct mlx5_ib_resources *devr = &dev->devr;
2899 int port;
2900
2901 mlx5_ib_destroy_srq(devr->s1, NULL);
2902 kfree(devr->s1);
2903 mlx5_ib_destroy_srq(devr->s0, NULL);
2904 kfree(devr->s0);
2905 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2906 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2907 mlx5_ib_destroy_cq(devr->c0, NULL);
2908 kfree(devr->c0);
2909 mlx5_ib_dealloc_pd(devr->p0, NULL);
2910 kfree(devr->p0);
2911
2912
2913 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2914 cancel_work_sync(&devr->ports[port].pkey_change_work);
2915}
2916
2917static u32 get_core_cap_flags(struct ib_device *ibdev,
2918 struct mlx5_hca_vport_context *rep)
2919{
2920 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2921 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2922 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2923 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2924 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
2925 u32 ret = 0;
2926
2927 if (rep->grh_required)
2928 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
2929
2930 if (ll == IB_LINK_LAYER_INFINIBAND)
2931 return ret | RDMA_CORE_PORT_IBA_IB;
2932
2933 if (raw_support)
2934 ret |= RDMA_CORE_PORT_RAW_PACKET;
2935
2936 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2937 return ret;
2938
2939 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2940 return ret;
2941
2942 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2943 ret |= RDMA_CORE_PORT_IBA_ROCE;
2944
2945 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2946 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2947
2948 return ret;
2949}
2950
2951static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num,
2952 struct ib_port_immutable *immutable)
2953{
2954 struct ib_port_attr attr;
2955 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2956 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
2957 struct mlx5_hca_vport_context rep = {0};
2958 int err;
2959
2960 err = ib_query_port(ibdev, port_num, &attr);
2961 if (err)
2962 return err;
2963
2964 if (ll == IB_LINK_LAYER_INFINIBAND) {
2965 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
2966 &rep);
2967 if (err)
2968 return err;
2969 }
2970
2971 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2972 immutable->gid_tbl_len = attr.gid_tbl_len;
2973 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
2974 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2975
2976 return 0;
2977}
2978
2979static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num,
2980 struct ib_port_immutable *immutable)
2981{
2982 struct ib_port_attr attr;
2983 int err;
2984
2985 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
2986
2987 err = ib_query_port(ibdev, port_num, &attr);
2988 if (err)
2989 return err;
2990
2991 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2992 immutable->gid_tbl_len = attr.gid_tbl_len;
2993 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
2994
2995 return 0;
2996}
2997
2998static void get_dev_fw_str(struct ib_device *ibdev, char *str)
2999{
3000 struct mlx5_ib_dev *dev =
3001 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3002 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3003 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3004 fw_rev_sub(dev->mdev));
3005}
3006
3007static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3008{
3009 struct mlx5_core_dev *mdev = dev->mdev;
3010 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3011 MLX5_FLOW_NAMESPACE_LAG);
3012 struct mlx5_flow_table *ft;
3013 int err;
3014
3015 if (!ns || !mlx5_lag_is_roce(mdev))
3016 return 0;
3017
3018 err = mlx5_cmd_create_vport_lag(mdev);
3019 if (err)
3020 return err;
3021
3022 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3023 if (IS_ERR(ft)) {
3024 err = PTR_ERR(ft);
3025 goto err_destroy_vport_lag;
3026 }
3027
3028 dev->flow_db->lag_demux_ft = ft;
3029 dev->lag_active = true;
3030 return 0;
3031
3032err_destroy_vport_lag:
3033 mlx5_cmd_destroy_vport_lag(mdev);
3034 return err;
3035}
3036
3037static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3038{
3039 struct mlx5_core_dev *mdev = dev->mdev;
3040
3041 if (dev->lag_active) {
3042 dev->lag_active = false;
3043
3044 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3045 dev->flow_db->lag_demux_ft = NULL;
3046
3047 mlx5_cmd_destroy_vport_lag(mdev);
3048 }
3049}
3050
3051static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3052{
3053 int err;
3054
3055 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
3056 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
3057 if (err) {
3058 dev->port[port_num].roce.nb.notifier_call = NULL;
3059 return err;
3060 }
3061
3062 return 0;
3063}
3064
3065static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3066{
3067 if (dev->port[port_num].roce.nb.notifier_call) {
3068 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
3069 dev->port[port_num].roce.nb.notifier_call = NULL;
3070 }
3071}
3072
3073static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3074{
3075 int err;
3076
3077 err = mlx5_nic_vport_enable_roce(dev->mdev);
3078 if (err)
3079 return err;
3080
3081 err = mlx5_eth_lag_init(dev);
3082 if (err)
3083 goto err_disable_roce;
3084
3085 return 0;
3086
3087err_disable_roce:
3088 mlx5_nic_vport_disable_roce(dev->mdev);
3089
3090 return err;
3091}
3092
3093static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3094{
3095 mlx5_eth_lag_cleanup(dev);
3096 mlx5_nic_vport_disable_roce(dev->mdev);
3097}
3098
3099static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num,
3100 enum rdma_netdev_t type,
3101 struct rdma_netdev_alloc_params *params)
3102{
3103 if (type != RDMA_NETDEV_IPOIB)
3104 return -EOPNOTSUPP;
3105
3106 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3107}
3108
3109static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3110 size_t count, loff_t *pos)
3111{
3112 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3113 char lbuf[20];
3114 int len;
3115
3116 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3117 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3118}
3119
3120static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3121 size_t count, loff_t *pos)
3122{
3123 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3124 u32 timeout;
3125 u32 var;
3126
3127 if (kstrtouint_from_user(buf, count, 0, &var))
3128 return -EFAULT;
3129
3130 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3131 1000);
3132 if (timeout != var)
3133 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3134 timeout);
3135
3136 delay_drop->timeout = timeout;
3137
3138 return count;
3139}
3140
3141static const struct file_operations fops_delay_drop_timeout = {
3142 .owner = THIS_MODULE,
3143 .open = simple_open,
3144 .write = delay_drop_timeout_write,
3145 .read = delay_drop_timeout_read,
3146};
3147
3148static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3149 struct mlx5_ib_multiport_info *mpi)
3150{
3151 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3152 struct mlx5_ib_port *port = &ibdev->port[port_num];
3153 int comps;
3154 int err;
3155 int i;
3156
3157 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3158
3159 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3160
3161 spin_lock(&port->mp.mpi_lock);
3162 if (!mpi->ibdev) {
3163 spin_unlock(&port->mp.mpi_lock);
3164 return;
3165 }
3166
3167 mpi->ibdev = NULL;
3168
3169 spin_unlock(&port->mp.mpi_lock);
3170 if (mpi->mdev_events.notifier_call)
3171 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3172 mpi->mdev_events.notifier_call = NULL;
3173 mlx5_remove_netdev_notifier(ibdev, port_num);
3174 spin_lock(&port->mp.mpi_lock);
3175
3176 comps = mpi->mdev_refcnt;
3177 if (comps) {
3178 mpi->unaffiliate = true;
3179 init_completion(&mpi->unref_comp);
3180 spin_unlock(&port->mp.mpi_lock);
3181
3182 for (i = 0; i < comps; i++)
3183 wait_for_completion(&mpi->unref_comp);
3184
3185 spin_lock(&port->mp.mpi_lock);
3186 mpi->unaffiliate = false;
3187 }
3188
3189 port->mp.mpi = NULL;
3190
3191 spin_unlock(&port->mp.mpi_lock);
3192
3193 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3194
3195 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1);
3196
3197
3198
3199 if (err)
3200 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3201 port_num + 1);
3202
3203 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
3204}
3205
3206static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3207 struct mlx5_ib_multiport_info *mpi)
3208{
3209 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3210 int err;
3211
3212 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3213
3214 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3215 if (ibdev->port[port_num].mp.mpi) {
3216 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n",
3217 port_num + 1);
3218 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3219 return false;
3220 }
3221
3222 ibdev->port[port_num].mp.mpi = mpi;
3223 mpi->ibdev = ibdev;
3224 mpi->mdev_events.notifier_call = NULL;
3225 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3226
3227 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3228 if (err)
3229 goto unbind;
3230
3231 err = mlx5_add_netdev_notifier(ibdev, port_num);
3232 if (err) {
3233 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
3234 port_num + 1);
3235 goto unbind;
3236 }
3237
3238 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3239 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3240
3241 mlx5_ib_init_cong_debugfs(ibdev, port_num);
3242
3243 return true;
3244
3245unbind:
3246 mlx5_ib_unbind_slave_port(ibdev, mpi);
3247 return false;
3248}
3249
3250static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3251{
3252 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3253 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3254 port_num + 1);
3255 struct mlx5_ib_multiport_info *mpi;
3256 int err;
3257 u32 i;
3258
3259 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3260 return 0;
3261
3262 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3263 &dev->sys_image_guid);
3264 if (err)
3265 return err;
3266
3267 err = mlx5_nic_vport_enable_roce(dev->mdev);
3268 if (err)
3269 return err;
3270
3271 mutex_lock(&mlx5_ib_multiport_mutex);
3272 for (i = 0; i < dev->num_ports; i++) {
3273 bool bound = false;
3274
3275
3276 if (i == port_num) {
3277 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3278 if (!mpi) {
3279 mutex_unlock(&mlx5_ib_multiport_mutex);
3280 mlx5_nic_vport_disable_roce(dev->mdev);
3281 return -ENOMEM;
3282 }
3283
3284 mpi->is_master = true;
3285 mpi->mdev = dev->mdev;
3286 mpi->sys_image_guid = dev->sys_image_guid;
3287 dev->port[i].mp.mpi = mpi;
3288 mpi->ibdev = dev;
3289 mpi = NULL;
3290 continue;
3291 }
3292
3293 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3294 list) {
3295 if (dev->sys_image_guid == mpi->sys_image_guid &&
3296 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
3297 bound = mlx5_ib_bind_slave_port(dev, mpi);
3298 }
3299
3300 if (bound) {
3301 dev_dbg(mpi->mdev->device,
3302 "removing port from unaffiliated list.\n");
3303 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3304 list_del(&mpi->list);
3305 break;
3306 }
3307 }
3308 if (!bound)
3309 mlx5_ib_dbg(dev, "no free port found for port %d\n",
3310 i + 1);
3311 }
3312
3313 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3314 mutex_unlock(&mlx5_ib_multiport_mutex);
3315 return err;
3316}
3317
3318static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3319{
3320 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3321 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3322 port_num + 1);
3323 u32 i;
3324
3325 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3326 return;
3327
3328 mutex_lock(&mlx5_ib_multiport_mutex);
3329 for (i = 0; i < dev->num_ports; i++) {
3330 if (dev->port[i].mp.mpi) {
3331
3332 if (i == port_num) {
3333 kfree(dev->port[i].mp.mpi);
3334 dev->port[i].mp.mpi = NULL;
3335 } else {
3336 mlx5_ib_dbg(dev, "unbinding port_num: %u\n",
3337 i + 1);
3338 list_add_tail(&dev->port[i].mp.mpi->list,
3339 &mlx5_ib_unaffiliated_port_list);
3340 mlx5_ib_unbind_slave_port(dev,
3341 dev->port[i].mp.mpi);
3342 }
3343 }
3344 }
3345
3346 mlx5_ib_dbg(dev, "removing from devlist\n");
3347 list_del(&dev->ib_dev_list);
3348 mutex_unlock(&mlx5_ib_multiport_mutex);
3349
3350 mlx5_nic_vport_disable_roce(dev->mdev);
3351}
3352
3353static int mmap_obj_cleanup(struct ib_uobject *uobject,
3354 enum rdma_remove_reason why,
3355 struct uverbs_attr_bundle *attrs)
3356{
3357 struct mlx5_user_mmap_entry *obj = uobject->object;
3358
3359 rdma_user_mmap_entry_remove(&obj->rdma_entry);
3360 return 0;
3361}
3362
3363static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3364 struct mlx5_user_mmap_entry *entry,
3365 size_t length)
3366{
3367 return rdma_user_mmap_entry_insert_range(
3368 &c->ibucontext, &entry->rdma_entry, length,
3369 (MLX5_IB_MMAP_OFFSET_START << 16),
3370 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3371}
3372
3373static struct mlx5_user_mmap_entry *
3374alloc_var_entry(struct mlx5_ib_ucontext *c)
3375{
3376 struct mlx5_user_mmap_entry *entry;
3377 struct mlx5_var_table *var_table;
3378 u32 page_idx;
3379 int err;
3380
3381 var_table = &to_mdev(c->ibucontext.device)->var_table;
3382 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3383 if (!entry)
3384 return ERR_PTR(-ENOMEM);
3385
3386 mutex_lock(&var_table->bitmap_lock);
3387 page_idx = find_first_zero_bit(var_table->bitmap,
3388 var_table->num_var_hw_entries);
3389 if (page_idx >= var_table->num_var_hw_entries) {
3390 err = -ENOSPC;
3391 mutex_unlock(&var_table->bitmap_lock);
3392 goto end;
3393 }
3394
3395 set_bit(page_idx, var_table->bitmap);
3396 mutex_unlock(&var_table->bitmap_lock);
3397
3398 entry->address = var_table->hw_start_addr +
3399 (page_idx * var_table->stride_size);
3400 entry->page_idx = page_idx;
3401 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3402
3403 err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3404 var_table->stride_size);
3405 if (err)
3406 goto err_insert;
3407
3408 return entry;
3409
3410err_insert:
3411 mutex_lock(&var_table->bitmap_lock);
3412 clear_bit(page_idx, var_table->bitmap);
3413 mutex_unlock(&var_table->bitmap_lock);
3414end:
3415 kfree(entry);
3416 return ERR_PTR(err);
3417}
3418
3419static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3420 struct uverbs_attr_bundle *attrs)
3421{
3422 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3423 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3424 struct mlx5_ib_ucontext *c;
3425 struct mlx5_user_mmap_entry *entry;
3426 u64 mmap_offset;
3427 u32 length;
3428 int err;
3429
3430 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3431 if (IS_ERR(c))
3432 return PTR_ERR(c);
3433
3434 entry = alloc_var_entry(c);
3435 if (IS_ERR(entry))
3436 return PTR_ERR(entry);
3437
3438 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3439 length = entry->rdma_entry.npages * PAGE_SIZE;
3440 uobj->object = entry;
3441 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3442
3443 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3444 &mmap_offset, sizeof(mmap_offset));
3445 if (err)
3446 return err;
3447
3448 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3449 &entry->page_idx, sizeof(entry->page_idx));
3450 if (err)
3451 return err;
3452
3453 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3454 &length, sizeof(length));
3455 return err;
3456}
3457
3458DECLARE_UVERBS_NAMED_METHOD(
3459 MLX5_IB_METHOD_VAR_OBJ_ALLOC,
3460 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
3461 MLX5_IB_OBJECT_VAR,
3462 UVERBS_ACCESS_NEW,
3463 UA_MANDATORY),
3464 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3465 UVERBS_ATTR_TYPE(u32),
3466 UA_MANDATORY),
3467 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3468 UVERBS_ATTR_TYPE(u32),
3469 UA_MANDATORY),
3470 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3471 UVERBS_ATTR_TYPE(u64),
3472 UA_MANDATORY));
3473
3474DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3475 MLX5_IB_METHOD_VAR_OBJ_DESTROY,
3476 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
3477 MLX5_IB_OBJECT_VAR,
3478 UVERBS_ACCESS_DESTROY,
3479 UA_MANDATORY));
3480
3481DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
3482 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3483 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
3484 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
3485
3486static bool var_is_supported(struct ib_device *device)
3487{
3488 struct mlx5_ib_dev *dev = to_mdev(device);
3489
3490 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3491 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
3492}
3493
3494static struct mlx5_user_mmap_entry *
3495alloc_uar_entry(struct mlx5_ib_ucontext *c,
3496 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
3497{
3498 struct mlx5_user_mmap_entry *entry;
3499 struct mlx5_ib_dev *dev;
3500 u32 uar_index;
3501 int err;
3502
3503 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3504 if (!entry)
3505 return ERR_PTR(-ENOMEM);
3506
3507 dev = to_mdev(c->ibucontext.device);
3508 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
3509 if (err)
3510 goto end;
3511
3512 entry->page_idx = uar_index;
3513 entry->address = uar_index2paddress(dev, uar_index);
3514 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3515 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
3516 else
3517 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
3518
3519 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
3520 if (err)
3521 goto err_insert;
3522
3523 return entry;
3524
3525err_insert:
3526 mlx5_cmd_free_uar(dev->mdev, uar_index);
3527end:
3528 kfree(entry);
3529 return ERR_PTR(err);
3530}
3531
3532static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3533 struct uverbs_attr_bundle *attrs)
3534{
3535 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3536 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3537 enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3538 struct mlx5_ib_ucontext *c;
3539 struct mlx5_user_mmap_entry *entry;
3540 u64 mmap_offset;
3541 u32 length;
3542 int err;
3543
3544 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3545 if (IS_ERR(c))
3546 return PTR_ERR(c);
3547
3548 err = uverbs_get_const(&alloc_type, attrs,
3549 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3550 if (err)
3551 return err;
3552
3553 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3554 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3555 return -EOPNOTSUPP;
3556
3557 if (!to_mdev(c->ibucontext.device)->wc_support &&
3558 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3559 return -EOPNOTSUPP;
3560
3561 entry = alloc_uar_entry(c, alloc_type);
3562 if (IS_ERR(entry))
3563 return PTR_ERR(entry);
3564
3565 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3566 length = entry->rdma_entry.npages * PAGE_SIZE;
3567 uobj->object = entry;
3568 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3569
3570 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3571 &mmap_offset, sizeof(mmap_offset));
3572 if (err)
3573 return err;
3574
3575 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3576 &entry->page_idx, sizeof(entry->page_idx));
3577 if (err)
3578 return err;
3579
3580 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3581 &length, sizeof(length));
3582 return err;
3583}
3584
3585DECLARE_UVERBS_NAMED_METHOD(
3586 MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3587 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3588 MLX5_IB_OBJECT_UAR,
3589 UVERBS_ACCESS_NEW,
3590 UA_MANDATORY),
3591 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3592 enum mlx5_ib_uapi_uar_alloc_type,
3593 UA_MANDATORY),
3594 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3595 UVERBS_ATTR_TYPE(u32),
3596 UA_MANDATORY),
3597 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3598 UVERBS_ATTR_TYPE(u32),
3599 UA_MANDATORY),
3600 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3601 UVERBS_ATTR_TYPE(u64),
3602 UA_MANDATORY));
3603
3604DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3605 MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3606 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3607 MLX5_IB_OBJECT_UAR,
3608 UVERBS_ACCESS_DESTROY,
3609 UA_MANDATORY));
3610
3611DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3612 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3613 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3614 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3615
3616ADD_UVERBS_ATTRIBUTES_SIMPLE(
3617 mlx5_ib_flow_action,
3618 UVERBS_OBJECT_FLOW_ACTION,
3619 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
3620 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3621 enum mlx5_ib_uapi_flow_action_flags));
3622
3623ADD_UVERBS_ATTRIBUTES_SIMPLE(
3624 mlx5_ib_query_context,
3625 UVERBS_OBJECT_DEVICE,
3626 UVERBS_METHOD_QUERY_CONTEXT,
3627 UVERBS_ATTR_PTR_OUT(
3628 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
3629 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
3630 dump_fill_mkey),
3631 UA_MANDATORY));
3632
3633static const struct uapi_definition mlx5_ib_defs[] = {
3634 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
3635 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
3636 UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
3637 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
3638 UAPI_DEF_CHAIN(mlx5_ib_dm_defs),
3639
3640 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
3641 &mlx5_ib_flow_action),
3642 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
3643 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
3644 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
3645 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
3646 {}
3647};
3648
3649static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
3650{
3651 mlx5_ib_cleanup_multiport_master(dev);
3652 WARN_ON(!xa_empty(&dev->odp_mkeys));
3653 mutex_destroy(&dev->cap_mask_mutex);
3654 WARN_ON(!xa_empty(&dev->sig_mrs));
3655 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
3656}
3657
3658static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
3659{
3660 struct mlx5_core_dev *mdev = dev->mdev;
3661 int err;
3662 int i;
3663
3664 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3665 dev->ib_dev.local_dma_lkey = 0 ;
3666 dev->ib_dev.phys_port_cnt = dev->num_ports;
3667 dev->ib_dev.dev.parent = mdev->device;
3668 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
3669
3670 for (i = 0; i < dev->num_ports; i++) {
3671 spin_lock_init(&dev->port[i].mp.mpi_lock);
3672 rwlock_init(&dev->port[i].roce.netdev_lock);
3673 dev->port[i].roce.dev = dev;
3674 dev->port[i].roce.native_port_num = i + 1;
3675 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
3676 }
3677
3678 err = mlx5_ib_init_multiport_master(dev);
3679 if (err)
3680 return err;
3681
3682 err = set_has_smi_cap(dev);
3683 if (err)
3684 goto err_mp;
3685
3686 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len);
3687 if (err)
3688 goto err_mp;
3689
3690 if (mlx5_use_mad_ifc(dev))
3691 get_ext_port_caps(dev);
3692
3693 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
3694
3695 mutex_init(&dev->cap_mask_mutex);
3696 INIT_LIST_HEAD(&dev->qp_list);
3697 spin_lock_init(&dev->reset_flow_resource_lock);
3698 xa_init(&dev->odp_mkeys);
3699 xa_init(&dev->sig_mrs);
3700 atomic_set(&dev->mkey_var, 0);
3701
3702 spin_lock_init(&dev->dm.lock);
3703 dev->dm.dev = mdev;
3704 return 0;
3705
3706err_mp:
3707 mlx5_ib_cleanup_multiport_master(dev);
3708 return err;
3709}
3710
3711static int mlx5_ib_enable_driver(struct ib_device *dev)
3712{
3713 struct mlx5_ib_dev *mdev = to_mdev(dev);
3714 int ret;
3715
3716 ret = mlx5_ib_test_wc(mdev);
3717 mlx5_ib_dbg(mdev, "Write-Combining %s",
3718 mdev->wc_support ? "supported" : "not supported");
3719
3720 return ret;
3721}
3722
3723static const struct ib_device_ops mlx5_ib_dev_ops = {
3724 .owner = THIS_MODULE,
3725 .driver_id = RDMA_DRIVER_MLX5,
3726 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
3727
3728 .add_gid = mlx5_ib_add_gid,
3729 .alloc_mr = mlx5_ib_alloc_mr,
3730 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
3731 .alloc_pd = mlx5_ib_alloc_pd,
3732 .alloc_ucontext = mlx5_ib_alloc_ucontext,
3733 .attach_mcast = mlx5_ib_mcg_attach,
3734 .check_mr_status = mlx5_ib_check_mr_status,
3735 .create_ah = mlx5_ib_create_ah,
3736 .create_cq = mlx5_ib_create_cq,
3737 .create_qp = mlx5_ib_create_qp,
3738 .create_srq = mlx5_ib_create_srq,
3739 .create_user_ah = mlx5_ib_create_ah,
3740 .dealloc_pd = mlx5_ib_dealloc_pd,
3741 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
3742 .del_gid = mlx5_ib_del_gid,
3743 .dereg_mr = mlx5_ib_dereg_mr,
3744 .destroy_ah = mlx5_ib_destroy_ah,
3745 .destroy_cq = mlx5_ib_destroy_cq,
3746 .destroy_qp = mlx5_ib_destroy_qp,
3747 .destroy_srq = mlx5_ib_destroy_srq,
3748 .detach_mcast = mlx5_ib_mcg_detach,
3749 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
3750 .drain_rq = mlx5_ib_drain_rq,
3751 .drain_sq = mlx5_ib_drain_sq,
3752 .device_group = &mlx5_attr_group,
3753 .enable_driver = mlx5_ib_enable_driver,
3754 .get_dev_fw_str = get_dev_fw_str,
3755 .get_dma_mr = mlx5_ib_get_dma_mr,
3756 .get_link_layer = mlx5_ib_port_link_layer,
3757 .map_mr_sg = mlx5_ib_map_mr_sg,
3758 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
3759 .mmap = mlx5_ib_mmap,
3760 .mmap_free = mlx5_ib_mmap_free,
3761 .modify_cq = mlx5_ib_modify_cq,
3762 .modify_device = mlx5_ib_modify_device,
3763 .modify_port = mlx5_ib_modify_port,
3764 .modify_qp = mlx5_ib_modify_qp,
3765 .modify_srq = mlx5_ib_modify_srq,
3766 .poll_cq = mlx5_ib_poll_cq,
3767 .post_recv = mlx5_ib_post_recv_nodrain,
3768 .post_send = mlx5_ib_post_send_nodrain,
3769 .post_srq_recv = mlx5_ib_post_srq_recv,
3770 .process_mad = mlx5_ib_process_mad,
3771 .query_ah = mlx5_ib_query_ah,
3772 .query_device = mlx5_ib_query_device,
3773 .query_gid = mlx5_ib_query_gid,
3774 .query_pkey = mlx5_ib_query_pkey,
3775 .query_qp = mlx5_ib_query_qp,
3776 .query_srq = mlx5_ib_query_srq,
3777 .query_ucontext = mlx5_ib_query_ucontext,
3778 .reg_user_mr = mlx5_ib_reg_user_mr,
3779 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf,
3780 .req_notify_cq = mlx5_ib_arm_cq,
3781 .rereg_user_mr = mlx5_ib_rereg_user_mr,
3782 .resize_cq = mlx5_ib_resize_cq,
3783
3784 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
3785 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
3786 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
3787 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
3788 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
3789 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
3790};
3791
3792static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
3793 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
3794};
3795
3796static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
3797 .get_vf_config = mlx5_ib_get_vf_config,
3798 .get_vf_guid = mlx5_ib_get_vf_guid,
3799 .get_vf_stats = mlx5_ib_get_vf_stats,
3800 .set_vf_guid = mlx5_ib_set_vf_guid,
3801 .set_vf_link_state = mlx5_ib_set_vf_link_state,
3802};
3803
3804static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
3805 .alloc_mw = mlx5_ib_alloc_mw,
3806 .dealloc_mw = mlx5_ib_dealloc_mw,
3807
3808 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
3809};
3810
3811static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
3812 .alloc_xrcd = mlx5_ib_alloc_xrcd,
3813 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
3814
3815 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
3816};
3817
3818static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
3819{
3820 struct mlx5_core_dev *mdev = dev->mdev;
3821 struct mlx5_var_table *var_table = &dev->var_table;
3822 u8 log_doorbell_bar_size;
3823 u8 log_doorbell_stride;
3824 u64 bar_size;
3825
3826 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3827 log_doorbell_bar_size);
3828 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3829 log_doorbell_stride);
3830 var_table->hw_start_addr = dev->mdev->bar_addr +
3831 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
3832 doorbell_bar_offset);
3833 bar_size = (1ULL << log_doorbell_bar_size) * 4096;
3834 var_table->stride_size = 1ULL << log_doorbell_stride;
3835 var_table->num_var_hw_entries = div_u64(bar_size,
3836 var_table->stride_size);
3837 mutex_init(&var_table->bitmap_lock);
3838 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
3839 GFP_KERNEL);
3840 return (var_table->bitmap) ? 0 : -ENOMEM;
3841}
3842
3843static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
3844{
3845 bitmap_free(dev->var_table.bitmap);
3846}
3847
3848static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
3849{
3850 struct mlx5_core_dev *mdev = dev->mdev;
3851 int err;
3852
3853 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
3854 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
3855 ib_set_device_ops(&dev->ib_dev,
3856 &mlx5_ib_dev_ipoib_enhanced_ops);
3857
3858 if (mlx5_core_is_pf(mdev))
3859 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
3860
3861 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3862
3863 if (MLX5_CAP_GEN(mdev, imaicl))
3864 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
3865
3866 if (MLX5_CAP_GEN(mdev, xrc))
3867 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
3868
3869 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
3870 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3871 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
3872 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
3873
3874 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
3875
3876 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
3877 dev->ib_dev.driver_def = mlx5_ib_defs;
3878
3879 err = init_node_data(dev);
3880 if (err)
3881 return err;
3882
3883 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
3884 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
3885 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
3886 mutex_init(&dev->lb.mutex);
3887
3888 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3889 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
3890 err = mlx5_ib_init_var_table(dev);
3891 if (err)
3892 return err;
3893 }
3894
3895 dev->ib_dev.use_cq_dim = true;
3896
3897 return 0;
3898}
3899
3900static const struct ib_device_ops mlx5_ib_dev_port_ops = {
3901 .get_port_immutable = mlx5_port_immutable,
3902 .query_port = mlx5_ib_query_port,
3903};
3904
3905static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
3906{
3907 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
3908 return 0;
3909}
3910
3911static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
3912 .get_port_immutable = mlx5_port_rep_immutable,
3913 .query_port = mlx5_ib_rep_query_port,
3914 .query_pkey = mlx5_ib_rep_query_pkey,
3915};
3916
3917static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
3918{
3919 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
3920 return 0;
3921}
3922
3923static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
3924 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
3925 .create_wq = mlx5_ib_create_wq,
3926 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
3927 .destroy_wq = mlx5_ib_destroy_wq,
3928 .get_netdev = mlx5_ib_get_netdev,
3929 .modify_wq = mlx5_ib_modify_wq,
3930
3931 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
3932 ib_rwq_ind_tbl),
3933};
3934
3935static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
3936{
3937 struct mlx5_core_dev *mdev = dev->mdev;
3938 enum rdma_link_layer ll;
3939 int port_type_cap;
3940 u32 port_num = 0;
3941 int err;
3942
3943 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3944 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3945
3946 if (ll == IB_LINK_LAYER_ETHERNET) {
3947 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
3948
3949 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3950
3951
3952 err = mlx5_add_netdev_notifier(dev, port_num);
3953 if (err || dev->is_rep || !mlx5_is_roce_init_enabled(mdev))
3954
3955
3956
3957
3958
3959 return err;
3960
3961 err = mlx5_enable_eth(dev);
3962 if (err)
3963 goto cleanup;
3964 }
3965
3966 return 0;
3967cleanup:
3968 mlx5_remove_netdev_notifier(dev, port_num);
3969 return err;
3970}
3971
3972static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
3973{
3974 struct mlx5_core_dev *mdev = dev->mdev;
3975 enum rdma_link_layer ll;
3976 int port_type_cap;
3977 u32 port_num;
3978
3979 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3980 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3981
3982 if (ll == IB_LINK_LAYER_ETHERNET) {
3983 if (!dev->is_rep)
3984 mlx5_disable_eth(dev);
3985
3986 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3987 mlx5_remove_netdev_notifier(dev, port_num);
3988 }
3989}
3990
3991static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
3992{
3993 mlx5_ib_init_cong_debugfs(dev,
3994 mlx5_core_native_port_num(dev->mdev) - 1);
3995 return 0;
3996}
3997
3998static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
3999{
4000 mlx5_ib_cleanup_cong_debugfs(dev,
4001 mlx5_core_native_port_num(dev->mdev) - 1);
4002}
4003
4004static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4005{
4006 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4007 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
4008}
4009
4010static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4011{
4012 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4013}
4014
4015static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4016{
4017 int err;
4018
4019 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4020 if (err)
4021 return err;
4022
4023 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4024 if (err)
4025 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4026
4027 return err;
4028}
4029
4030static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4031{
4032 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4033 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4034}
4035
4036static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4037{
4038 const char *name;
4039
4040 if (!mlx5_lag_is_roce(dev->mdev))
4041 name = "mlx5_%d";
4042 else
4043 name = "mlx5_bond_%d";
4044 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
4045}
4046
4047static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4048{
4049 int err;
4050
4051 err = mlx5_mr_cache_cleanup(dev);
4052 if (err)
4053 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4054
4055 if (dev->umrc.qp)
4056 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4057 if (dev->umrc.cq)
4058 ib_free_cq(dev->umrc.cq);
4059 if (dev->umrc.pd)
4060 ib_dealloc_pd(dev->umrc.pd);
4061}
4062
4063static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4064{
4065 ib_unregister_device(&dev->ib_dev);
4066}
4067
4068enum {
4069 MAX_UMR_WR = 128,
4070};
4071
4072static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4073{
4074 struct ib_qp_init_attr *init_attr = NULL;
4075 struct ib_qp_attr *attr = NULL;
4076 struct ib_pd *pd;
4077 struct ib_cq *cq;
4078 struct ib_qp *qp;
4079 int ret;
4080
4081 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4082 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4083 if (!attr || !init_attr) {
4084 ret = -ENOMEM;
4085 goto error_0;
4086 }
4087
4088 pd = ib_alloc_pd(&dev->ib_dev, 0);
4089 if (IS_ERR(pd)) {
4090 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4091 ret = PTR_ERR(pd);
4092 goto error_0;
4093 }
4094
4095 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4096 if (IS_ERR(cq)) {
4097 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4098 ret = PTR_ERR(cq);
4099 goto error_2;
4100 }
4101
4102 init_attr->send_cq = cq;
4103 init_attr->recv_cq = cq;
4104 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4105 init_attr->cap.max_send_wr = MAX_UMR_WR;
4106 init_attr->cap.max_send_sge = 1;
4107 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4108 init_attr->port_num = 1;
4109 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4110 if (IS_ERR(qp)) {
4111 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4112 ret = PTR_ERR(qp);
4113 goto error_3;
4114 }
4115 qp->device = &dev->ib_dev;
4116 qp->real_qp = qp;
4117 qp->uobject = NULL;
4118 qp->qp_type = MLX5_IB_QPT_REG_UMR;
4119 qp->send_cq = init_attr->send_cq;
4120 qp->recv_cq = init_attr->recv_cq;
4121
4122 attr->qp_state = IB_QPS_INIT;
4123 attr->port_num = 1;
4124 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4125 IB_QP_PORT, NULL);
4126 if (ret) {
4127 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4128 goto error_4;
4129 }
4130
4131 memset(attr, 0, sizeof(*attr));
4132 attr->qp_state = IB_QPS_RTR;
4133 attr->path_mtu = IB_MTU_256;
4134
4135 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4136 if (ret) {
4137 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4138 goto error_4;
4139 }
4140
4141 memset(attr, 0, sizeof(*attr));
4142 attr->qp_state = IB_QPS_RTS;
4143 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4144 if (ret) {
4145 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4146 goto error_4;
4147 }
4148
4149 dev->umrc.qp = qp;
4150 dev->umrc.cq = cq;
4151 dev->umrc.pd = pd;
4152
4153 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4154 ret = mlx5_mr_cache_init(dev);
4155 if (ret) {
4156 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4157 goto error_4;
4158 }
4159
4160 kfree(attr);
4161 kfree(init_attr);
4162
4163 return 0;
4164
4165error_4:
4166 mlx5_ib_destroy_qp(qp, NULL);
4167 dev->umrc.qp = NULL;
4168
4169error_3:
4170 ib_free_cq(cq);
4171 dev->umrc.cq = NULL;
4172
4173error_2:
4174 ib_dealloc_pd(pd);
4175 dev->umrc.pd = NULL;
4176
4177error_0:
4178 kfree(attr);
4179 kfree(init_attr);
4180 return ret;
4181}
4182
4183static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4184{
4185 struct dentry *root;
4186
4187 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4188 return 0;
4189
4190 mutex_init(&dev->delay_drop.lock);
4191 dev->delay_drop.dev = dev;
4192 dev->delay_drop.activate = false;
4193 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4194 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4195 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4196 atomic_set(&dev->delay_drop.events_cnt, 0);
4197
4198 if (!mlx5_debugfs_root)
4199 return 0;
4200
4201 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root);
4202 dev->delay_drop.dir_debugfs = root;
4203
4204 debugfs_create_atomic_t("num_timeout_events", 0400, root,
4205 &dev->delay_drop.events_cnt);
4206 debugfs_create_atomic_t("num_rqs", 0400, root,
4207 &dev->delay_drop.rqs_cnt);
4208 debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4209 &fops_delay_drop_timeout);
4210 return 0;
4211}
4212
4213static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4214{
4215 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4216 return;
4217
4218 cancel_work_sync(&dev->delay_drop.delay_drop_work);
4219 if (!dev->delay_drop.dir_debugfs)
4220 return;
4221
4222 debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4223 dev->delay_drop.dir_debugfs = NULL;
4224}
4225
4226static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4227{
4228 dev->mdev_events.notifier_call = mlx5_ib_event;
4229 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4230 return 0;
4231}
4232
4233static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4234{
4235 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4236}
4237
4238void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4239 const struct mlx5_ib_profile *profile,
4240 int stage)
4241{
4242 dev->ib_active = false;
4243
4244
4245 while (stage) {
4246 stage--;
4247 if (profile->stage[stage].cleanup)
4248 profile->stage[stage].cleanup(dev);
4249 }
4250
4251 kfree(dev->port);
4252 ib_dealloc_device(&dev->ib_dev);
4253}
4254
4255int __mlx5_ib_add(struct mlx5_ib_dev *dev,
4256 const struct mlx5_ib_profile *profile)
4257{
4258 int err;
4259 int i;
4260
4261 dev->profile = profile;
4262
4263 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4264 if (profile->stage[i].init) {
4265 err = profile->stage[i].init(dev);
4266 if (err)
4267 goto err_out;
4268 }
4269 }
4270
4271 dev->ib_active = true;
4272 return 0;
4273
4274err_out:
4275
4276 while (i) {
4277 i--;
4278 if (profile->stage[i].cleanup)
4279 profile->stage[i].cleanup(dev);
4280 }
4281 return -ENOMEM;
4282}
4283
4284static const struct mlx5_ib_profile pf_profile = {
4285 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4286 mlx5_ib_stage_init_init,
4287 mlx5_ib_stage_init_cleanup),
4288 STAGE_CREATE(MLX5_IB_STAGE_FS,
4289 mlx5_ib_fs_init,
4290 mlx5_ib_fs_cleanup),
4291 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4292 mlx5_ib_stage_caps_init,
4293 mlx5_ib_stage_caps_cleanup),
4294 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4295 mlx5_ib_stage_non_default_cb,
4296 NULL),
4297 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4298 mlx5_ib_roce_init,
4299 mlx5_ib_roce_cleanup),
4300 STAGE_CREATE(MLX5_IB_STAGE_QP,
4301 mlx5_init_qp_table,
4302 mlx5_cleanup_qp_table),
4303 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4304 mlx5_init_srq_table,
4305 mlx5_cleanup_srq_table),
4306 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4307 mlx5_ib_dev_res_init,
4308 mlx5_ib_dev_res_cleanup),
4309 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4310 mlx5_ib_stage_dev_notifier_init,
4311 mlx5_ib_stage_dev_notifier_cleanup),
4312 STAGE_CREATE(MLX5_IB_STAGE_ODP,
4313 mlx5_ib_odp_init_one,
4314 mlx5_ib_odp_cleanup_one),
4315 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4316 mlx5_ib_counters_init,
4317 mlx5_ib_counters_cleanup),
4318 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4319 mlx5_ib_stage_cong_debugfs_init,
4320 mlx5_ib_stage_cong_debugfs_cleanup),
4321 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4322 mlx5_ib_stage_uar_init,
4323 mlx5_ib_stage_uar_cleanup),
4324 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4325 mlx5_ib_stage_bfrag_init,
4326 mlx5_ib_stage_bfrag_cleanup),
4327 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4328 NULL,
4329 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4330 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4331 mlx5_ib_devx_init,
4332 mlx5_ib_devx_cleanup),
4333 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4334 mlx5_ib_stage_ib_reg_init,
4335 mlx5_ib_stage_ib_reg_cleanup),
4336 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4337 mlx5_ib_stage_post_ib_reg_umr_init,
4338 NULL),
4339 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4340 mlx5_ib_stage_delay_drop_init,
4341 mlx5_ib_stage_delay_drop_cleanup),
4342 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4343 mlx5_ib_restrack_init,
4344 NULL),
4345};
4346
4347const struct mlx5_ib_profile raw_eth_profile = {
4348 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4349 mlx5_ib_stage_init_init,
4350 mlx5_ib_stage_init_cleanup),
4351 STAGE_CREATE(MLX5_IB_STAGE_FS,
4352 mlx5_ib_fs_init,
4353 mlx5_ib_fs_cleanup),
4354 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4355 mlx5_ib_stage_caps_init,
4356 mlx5_ib_stage_caps_cleanup),
4357 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4358 mlx5_ib_stage_raw_eth_non_default_cb,
4359 NULL),
4360 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4361 mlx5_ib_roce_init,
4362 mlx5_ib_roce_cleanup),
4363 STAGE_CREATE(MLX5_IB_STAGE_QP,
4364 mlx5_init_qp_table,
4365 mlx5_cleanup_qp_table),
4366 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4367 mlx5_init_srq_table,
4368 mlx5_cleanup_srq_table),
4369 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4370 mlx5_ib_dev_res_init,
4371 mlx5_ib_dev_res_cleanup),
4372 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4373 mlx5_ib_stage_dev_notifier_init,
4374 mlx5_ib_stage_dev_notifier_cleanup),
4375 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4376 mlx5_ib_counters_init,
4377 mlx5_ib_counters_cleanup),
4378 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4379 mlx5_ib_stage_cong_debugfs_init,
4380 mlx5_ib_stage_cong_debugfs_cleanup),
4381 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4382 mlx5_ib_stage_uar_init,
4383 mlx5_ib_stage_uar_cleanup),
4384 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4385 mlx5_ib_stage_bfrag_init,
4386 mlx5_ib_stage_bfrag_cleanup),
4387 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4388 NULL,
4389 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4390 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4391 mlx5_ib_devx_init,
4392 mlx5_ib_devx_cleanup),
4393 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4394 mlx5_ib_stage_ib_reg_init,
4395 mlx5_ib_stage_ib_reg_cleanup),
4396 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4397 mlx5_ib_stage_post_ib_reg_umr_init,
4398 NULL),
4399 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4400 mlx5_ib_restrack_init,
4401 NULL),
4402};
4403
4404static int mlx5r_mp_probe(struct auxiliary_device *adev,
4405 const struct auxiliary_device_id *id)
4406{
4407 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4408 struct mlx5_core_dev *mdev = idev->mdev;
4409 struct mlx5_ib_multiport_info *mpi;
4410 struct mlx5_ib_dev *dev;
4411 bool bound = false;
4412 int err;
4413
4414 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4415 if (!mpi)
4416 return -ENOMEM;
4417
4418 mpi->mdev = mdev;
4419 err = mlx5_query_nic_vport_system_image_guid(mdev,
4420 &mpi->sys_image_guid);
4421 if (err) {
4422 kfree(mpi);
4423 return err;
4424 }
4425
4426 mutex_lock(&mlx5_ib_multiport_mutex);
4427 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4428 if (dev->sys_image_guid == mpi->sys_image_guid)
4429 bound = mlx5_ib_bind_slave_port(dev, mpi);
4430
4431 if (bound) {
4432 rdma_roce_rescan_device(&dev->ib_dev);
4433 mpi->ibdev->ib_active = true;
4434 break;
4435 }
4436 }
4437
4438 if (!bound) {
4439 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4440 dev_dbg(mdev->device,
4441 "no suitable IB device found to bind to, added to unaffiliated list.\n");
4442 }
4443 mutex_unlock(&mlx5_ib_multiport_mutex);
4444
4445 dev_set_drvdata(&adev->dev, mpi);
4446 return 0;
4447}
4448
4449static void mlx5r_mp_remove(struct auxiliary_device *adev)
4450{
4451 struct mlx5_ib_multiport_info *mpi;
4452
4453 mpi = dev_get_drvdata(&adev->dev);
4454 mutex_lock(&mlx5_ib_multiport_mutex);
4455 if (mpi->ibdev)
4456 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
4457 else
4458 list_del(&mpi->list);
4459 mutex_unlock(&mlx5_ib_multiport_mutex);
4460 kfree(mpi);
4461}
4462
4463static int mlx5r_probe(struct auxiliary_device *adev,
4464 const struct auxiliary_device_id *id)
4465{
4466 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4467 struct mlx5_core_dev *mdev = idev->mdev;
4468 const struct mlx5_ib_profile *profile;
4469 int port_type_cap, num_ports, ret;
4470 enum rdma_link_layer ll;
4471 struct mlx5_ib_dev *dev;
4472
4473 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4474 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4475
4476 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4477 MLX5_CAP_GEN(mdev, num_vhca_ports));
4478 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
4479 if (!dev)
4480 return -ENOMEM;
4481 dev->port = kcalloc(num_ports, sizeof(*dev->port),
4482 GFP_KERNEL);
4483 if (!dev->port) {
4484 ib_dealloc_device(&dev->ib_dev);
4485 return -ENOMEM;
4486 }
4487
4488 dev->mdev = mdev;
4489 dev->num_ports = num_ports;
4490
4491 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_init_enabled(mdev))
4492 profile = &raw_eth_profile;
4493 else
4494 profile = &pf_profile;
4495
4496 ret = __mlx5_ib_add(dev, profile);
4497 if (ret) {
4498 kfree(dev->port);
4499 ib_dealloc_device(&dev->ib_dev);
4500 return ret;
4501 }
4502
4503 dev_set_drvdata(&adev->dev, dev);
4504 return 0;
4505}
4506
4507static void mlx5r_remove(struct auxiliary_device *adev)
4508{
4509 struct mlx5_ib_dev *dev;
4510
4511 dev = dev_get_drvdata(&adev->dev);
4512 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
4513}
4514
4515static const struct auxiliary_device_id mlx5r_mp_id_table[] = {
4516 { .name = MLX5_ADEV_NAME ".multiport", },
4517 {},
4518};
4519
4520static const struct auxiliary_device_id mlx5r_id_table[] = {
4521 { .name = MLX5_ADEV_NAME ".rdma", },
4522 {},
4523};
4524
4525MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table);
4526MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table);
4527
4528static struct auxiliary_driver mlx5r_mp_driver = {
4529 .name = "multiport",
4530 .probe = mlx5r_mp_probe,
4531 .remove = mlx5r_mp_remove,
4532 .id_table = mlx5r_mp_id_table,
4533};
4534
4535static struct auxiliary_driver mlx5r_driver = {
4536 .name = "rdma",
4537 .probe = mlx5r_probe,
4538 .remove = mlx5r_remove,
4539 .id_table = mlx5r_id_table,
4540};
4541
4542static int __init mlx5_ib_init(void)
4543{
4544 int ret;
4545
4546 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
4547 if (!xlt_emergency_page)
4548 return -ENOMEM;
4549
4550 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
4551 if (!mlx5_ib_event_wq) {
4552 free_page((unsigned long)xlt_emergency_page);
4553 return -ENOMEM;
4554 }
4555
4556 mlx5_ib_odp_init();
4557 ret = mlx5r_rep_init();
4558 if (ret)
4559 goto rep_err;
4560 ret = auxiliary_driver_register(&mlx5r_mp_driver);
4561 if (ret)
4562 goto mp_err;
4563 ret = auxiliary_driver_register(&mlx5r_driver);
4564 if (ret)
4565 goto drv_err;
4566 return 0;
4567
4568drv_err:
4569 auxiliary_driver_unregister(&mlx5r_mp_driver);
4570mp_err:
4571 mlx5r_rep_cleanup();
4572rep_err:
4573 destroy_workqueue(mlx5_ib_event_wq);
4574 free_page((unsigned long)xlt_emergency_page);
4575 return ret;
4576}
4577
4578static void __exit mlx5_ib_cleanup(void)
4579{
4580 auxiliary_driver_unregister(&mlx5r_driver);
4581 auxiliary_driver_unregister(&mlx5r_mp_driver);
4582 mlx5r_rep_cleanup();
4583
4584 destroy_workqueue(mlx5_ib_event_wq);
4585 free_page((unsigned long)xlt_emergency_page);
4586}
4587
4588module_init(mlx5_ib_init);
4589module_exit(mlx5_ib_cleanup);
4590
