LXR linux/drivers/irqchip/irq-bcm2835.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2010 Broadcom
   4 * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
   5 *
   6 * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
   7 *
   8 * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
   9 * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
  10 * to look in the bank 1 status register for more information.
  11 *
  12 * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
  13 * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
  14 * status register, but bank 0 bit 8 is _not_ set.
  15 *
  16 * Quirk 2: You can't mask the register 1/2 pending interrupts
  17 *
  18 * In a proper cascaded interrupt controller, the interrupt lines with
  19 * cascaded interrupt controllers on them are just normal interrupt lines.
  20 * You can mask the interrupts and get on with things. With this controller
  21 * you can't do that.
  22 *
  23 * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
  24 *
  25 * Those interrupts that have shortcuts can only be masked/unmasked in
  26 * their respective banks' enable/disable registers. Doing so in the bank 0
  27 * enable/disable registers has no effect.
  28 *
  29 * The FIQ control register:
  30 *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
  31 *  Bit    7: Enable FIQ generation
  32 *  Bits  8+: Unused
  33 *
  34 * An interrupt must be disabled before configuring it for FIQ generation
  35 * otherwise both handlers will fire at the same time!
  36 */
  37
  38#include <linux/io.h>
  39#include <linux/slab.h>
  40#include <linux/of_address.h>
  41#include <linux/of_irq.h>
  42#include <linux/irqchip.h>
  43#include <linux/irqdomain.h>
  44
  45#include <asm/exception.h>
  46
  47/* Put the bank and irq (32 bits) into the hwirq */
  48#define MAKE_HWIRQ(b, n)        ((b << 5) | (n))
  49#define HWIRQ_BANK(i)           (i >> 5)
  50#define HWIRQ_BIT(i)            BIT(i & 0x1f)
  51
  52#define NR_IRQS_BANK0           8
  53#define BANK0_HWIRQ_MASK        0xff
  54/* Shortcuts can't be disabled so any unknown new ones need to be masked */
  55#define SHORTCUT1_MASK          0x00007c00
  56#define SHORTCUT2_MASK          0x001f8000
  57#define SHORTCUT_SHIFT          10
  58#define BANK1_HWIRQ             BIT(8)
  59#define BANK2_HWIRQ             BIT(9)
  60#define BANK0_VALID_MASK        (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
  61                                        | SHORTCUT1_MASK | SHORTCUT2_MASK)
  62
  63#define REG_FIQ_CONTROL         0x0c
  64#define FIQ_CONTROL_ENABLE      BIT(7)
  65
  66#define NR_BANKS                3
  67#define IRQS_PER_BANK           32
  68
  69static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
  70static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
  71static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
  72static const int bank_irqs[] __initconst = { 8, 32, 32 };
  73
  74static const int shortcuts[] = {
  75        7, 9, 10, 18, 19,               /* Bank 1 */
  76        21, 22, 23, 24, 25, 30          /* Bank 2 */
  77};
  78
  79struct armctrl_ic {
  80        void __iomem *base;
  81        void __iomem *pending[NR_BANKS];
  82        void __iomem *enable[NR_BANKS];
  83        void __iomem *disable[NR_BANKS];
  84        struct irq_domain *domain;
  85};
  86
  87static struct armctrl_ic intc __read_mostly;
  88static void __exception_irq_entry bcm2835_handle_irq(
  89        struct pt_regs *regs);
  90static void bcm2836_chained_handle_irq(struct irq_desc *desc);
  91
  92static void armctrl_mask_irq(struct irq_data *d)
  93{
  94        writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
  95}
  96
  97static void armctrl_unmask_irq(struct irq_data *d)
  98{
  99        writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
 100}
 101
 102static struct irq_chip armctrl_chip = {
 103        .name = "ARMCTRL-level",
 104        .irq_mask = armctrl_mask_irq,
 105        .irq_unmask = armctrl_unmask_irq
 106};
 107
 108static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
 109        const u32 *intspec, unsigned int intsize,
 110        unsigned long *out_hwirq, unsigned int *out_type)
 111{
 112        if (WARN_ON(intsize != 2))
 113                return -EINVAL;
 114
 115        if (WARN_ON(intspec[0] >= NR_BANKS))
 116                return -EINVAL;
 117
 118        if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
 119                return -EINVAL;
 120
 121        if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
 122                return -EINVAL;
 123
 124        *out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
 125        *out_type = IRQ_TYPE_NONE;
 126        return 0;
 127}
 128
 129static const struct irq_domain_ops armctrl_ops = {
 130        .xlate = armctrl_xlate
 131};
 132
 133static int __init armctrl_of_init(struct device_node *node,
 134                                  struct device_node *parent,
 135                                  bool is_2836)
 136{
 137        void __iomem *base;
 138        int irq, b, i;
 139        u32 reg;
 140
 141        base = of_iomap(node, 0);
 142        if (!base)
 143                panic("%pOF: unable to map IC registers\n", node);
 144
 145        intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
 146                        &armctrl_ops, NULL);
 147        if (!intc.domain)
 148                panic("%pOF: unable to create IRQ domain\n", node);
 149
 150        for (b = 0; b < NR_BANKS; b++) {
 151                intc.pending[b] = base + reg_pending[b];
 152                intc.enable[b] = base + reg_enable[b];
 153                intc.disable[b] = base + reg_disable[b];
 154
 155                for (i = 0; i < bank_irqs[b]; i++) {
 156                        irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
 157                        BUG_ON(irq <= 0);
 158                        irq_set_chip_and_handler(irq, &armctrl_chip,
 159                                handle_level_irq);
 160                        irq_set_probe(irq);
 161                }
 162
 163                reg = readl_relaxed(intc.enable[b]);
 164                if (reg) {
 165                        writel_relaxed(reg, intc.disable[b]);
 166                        pr_err(FW_BUG "Bootloader left irq enabled: "
 167                               "bank %d irq %*pbl\n", b, IRQS_PER_BANK, &reg);
 168                }
 169        }
 170
 171        reg = readl_relaxed(base + REG_FIQ_CONTROL);
 172        if (reg & FIQ_CONTROL_ENABLE) {
 173                writel_relaxed(0, base + REG_FIQ_CONTROL);
 174                pr_err(FW_BUG "Bootloader left fiq enabled\n");
 175        }
 176
 177        if (is_2836) {
 178                int parent_irq = irq_of_parse_and_map(node, 0);
 179
 180                if (!parent_irq) {
 181                        panic("%pOF: unable to get parent interrupt.\n",
 182                              node);
 183                }
 184                irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
 185        } else {
 186                set_handle_irq(bcm2835_handle_irq);
 187        }
 188
 189        return 0;
 190}
 191
 192static int __init bcm2835_armctrl_of_init(struct device_node *node,
 193                                          struct device_node *parent)
 194{
 195        return armctrl_of_init(node, parent, false);
 196}
 197
 198static int __init bcm2836_armctrl_of_init(struct device_node *node,
 199                                          struct device_node *parent)
 200{
 201        return armctrl_of_init(node, parent, true);
 202}
 203
 204
 205/*
 206 * Handle each interrupt across the entire interrupt controller.  This reads the
 207 * status register before handling each interrupt, which is necessary given that
 208 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
 209 */
 210
 211static u32 armctrl_translate_bank(int bank)
 212{
 213        u32 stat = readl_relaxed(intc.pending[bank]);
 214
 215        return MAKE_HWIRQ(bank, ffs(stat) - 1);
 216}
 217
 218static u32 armctrl_translate_shortcut(int bank, u32 stat)
 219{
 220        return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
 221}
 222
 223static u32 get_next_armctrl_hwirq(void)
 224{
 225        u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
 226
 227        if (stat == 0)
 228                return ~0;
 229        else if (stat & BANK0_HWIRQ_MASK)
 230                return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
 231        else if (stat & SHORTCUT1_MASK)
 232                return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
 233        else if (stat & SHORTCUT2_MASK)
 234                return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
 235        else if (stat & BANK1_HWIRQ)
 236                return armctrl_translate_bank(1);
 237        else if (stat & BANK2_HWIRQ)
 238                return armctrl_translate_bank(2);
 239        else
 240                BUG();
 241}
 242
 243static void __exception_irq_entry bcm2835_handle_irq(
 244        struct pt_regs *regs)
 245{
 246        u32 hwirq;
 247
 248        while ((hwirq = get_next_armctrl_hwirq()) != ~0)
 249                handle_domain_irq(intc.domain, hwirq, regs);
 250}
 251
 252static void bcm2836_chained_handle_irq(struct irq_desc *desc)
 253{
 254        u32 hwirq;
 255
 256        while ((hwirq = get_next_armctrl_hwirq()) != ~0)
 257                generic_handle_domain_irq(intc.domain, hwirq);
 258}
 259
 260IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
 261                bcm2835_armctrl_of_init);
 262IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
 263                bcm2836_armctrl_of_init);
 264