linux/drivers/net/ethernet/3com/3c59x.c
<<
>>
Prefs
   1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
   2/*
   3        Written 1996-1999 by Donald Becker.
   4
   5        This software may be used and distributed according to the terms
   6        of the GNU General Public License, incorporated herein by reference.
   7
   8        This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
   9        Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
  10        and the EtherLink XL 3c900 and 3c905 cards.
  11
  12        Problem reports and questions should be directed to
  13        vortex@scyld.com
  14
  15        The author may be reached as becker@scyld.com, or C/O
  16        Scyld Computing Corporation
  17        410 Severn Ave., Suite 210
  18        Annapolis MD 21403
  19
  20*/
  21
  22/*
  23 * FIXME: This driver _could_ support MTU changing, but doesn't.  See Don's hamachi.c implementation
  24 * as well as other drivers
  25 *
  26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
  27 * due to dead code elimination.  There will be some performance benefits from this due to
  28 * elimination of all the tests and reduced cache footprint.
  29 */
  30
  31
  32#define DRV_NAME        "3c59x"
  33
  34
  35
  36/* A few values that may be tweaked. */
  37/* Keep the ring sizes a power of two for efficiency. */
  38#define TX_RING_SIZE    16
  39#define RX_RING_SIZE    32
  40#define PKT_BUF_SZ              1536                    /* Size of each temporary Rx buffer.*/
  41
  42/* "Knobs" that adjust features and parameters. */
  43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  44   Setting to > 1512 effectively disables this feature. */
  45#ifndef __arm__
  46static int rx_copybreak = 200;
  47#else
  48/* ARM systems perform better by disregarding the bus-master
  49   transfer capability of these cards. -- rmk */
  50static int rx_copybreak = 1513;
  51#endif
  52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
  53static const int mtu = 1500;
  54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  55static int max_interrupt_work = 32;
  56/* Tx timeout interval (millisecs) */
  57static int watchdog = 5000;
  58
  59/* Allow aggregation of Tx interrupts.  Saves CPU load at the cost
  60 * of possible Tx stalls if the system is blocking interrupts
  61 * somewhere else.  Undefine this to disable.
  62 */
  63#define tx_interrupt_mitigation 1
  64
  65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
  66#define vortex_debug debug
  67#ifdef VORTEX_DEBUG
  68static int vortex_debug = VORTEX_DEBUG;
  69#else
  70static int vortex_debug = 1;
  71#endif
  72
  73#include <linux/module.h>
  74#include <linux/kernel.h>
  75#include <linux/string.h>
  76#include <linux/timer.h>
  77#include <linux/errno.h>
  78#include <linux/in.h>
  79#include <linux/ioport.h>
  80#include <linux/interrupt.h>
  81#include <linux/pci.h>
  82#include <linux/mii.h>
  83#include <linux/init.h>
  84#include <linux/netdevice.h>
  85#include <linux/etherdevice.h>
  86#include <linux/skbuff.h>
  87#include <linux/ethtool.h>
  88#include <linux/highmem.h>
  89#include <linux/eisa.h>
  90#include <linux/bitops.h>
  91#include <linux/jiffies.h>
  92#include <linux/gfp.h>
  93#include <asm/irq.h>                    /* For nr_irqs only. */
  94#include <asm/io.h>
  95#include <linux/uaccess.h>
  96
  97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
  98   This is only in the support-all-kernels source code. */
  99
 100#define RUN_AT(x) (jiffies + (x))
 101
 102#include <linux/delay.h>
 103
 104
 105static const char version[] =
 106        DRV_NAME ": Donald Becker and others.\n";
 107
 108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
 110MODULE_LICENSE("GPL");
 111
 112
 113/* Operational parameter that usually are not changed. */
 114
 115/* The Vortex size is twice that of the original EtherLinkIII series: the
 116   runtime register window, window 1, is now always mapped in.
 117   The Boomerang size is twice as large as the Vortex -- it has additional
 118   bus master control registers. */
 119#define VORTEX_TOTAL_SIZE 0x20
 120#define BOOMERANG_TOTAL_SIZE 0x40
 121
 122/* Set iff a MII transceiver on any interface requires mdio preamble.
 123   This only set with the original DP83840 on older 3c905 boards, so the extra
 124   code size of a per-interface flag is not worthwhile. */
 125static char mii_preamble_required;
 126
 127#define PFX DRV_NAME ": "
 128
 129
 130
 131/*
 132                                Theory of Operation
 133
 134I. Board Compatibility
 135
 136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
 137XL, 3Com's PCI to 10/100baseT adapters.  It also works with the 10Mbs
 138versions of the FastEtherLink cards.  The supported product IDs are
 139  3c590, 3c592, 3c595, 3c597, 3c900, 3c905
 140
 141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
 142with the kernel source or available from
 143    cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
 144
 145II. Board-specific settings
 146
 147PCI bus devices are configured by the system at boot time, so no jumpers
 148need to be set on the board.  The system BIOS should be set to assign the
 149PCI INTA signal to an otherwise unused system IRQ line.
 150
 151The EEPROM settings for media type and forced-full-duplex are observed.
 152The EEPROM media type should be left at the default "autoselect" unless using
 15310base2 or AUI connections which cannot be reliably detected.
 154
 155III. Driver operation
 156
 157The 3c59x series use an interface that's very similar to the previous 3c5x9
 158series.  The primary interface is two programmed-I/O FIFOs, with an
 159alternate single-contiguous-region bus-master transfer (see next).
 160
 161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
 162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
 163DEC Tulip and Intel Speedo3.  The first chip version retains a compatible
 164programmed-I/O interface that has been removed in 'B' and subsequent board
 165revisions.
 166
 167One extension that is advertised in a very large font is that the adapters
 168are capable of being bus masters.  On the Vortex chip this capability was
 169only for a single contiguous region making it far less useful than the full
 170bus master capability.  There is a significant performance impact of taking
 171an extra interrupt or polling for the completion of each transfer, as well
 172as difficulty sharing the single transfer engine between the transmit and
 173receive threads.  Using DMA transfers is a win only with large blocks or
 174with the flawed versions of the Intel Orion motherboard PCI controller.
 175
 176The Boomerang chip's full-bus-master interface is useful, and has the
 177currently-unused advantages over other similar chips that queued transmit
 178packets may be reordered and receive buffer groups are associated with a
 179single frame.
 180
 181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
 182Rather than a fixed intermediate receive buffer, this scheme allocates
 183full-sized skbuffs as receive buffers.  The value RX_COPYBREAK is used as
 184the copying breakpoint: it is chosen to trade-off the memory wasted by
 185passing the full-sized skbuff to the queue layer for all frames vs. the
 186copying cost of copying a frame to a correctly-sized skbuff.
 187
 188IIIC. Synchronization
 189The driver runs as two independent, single-threaded flows of control.  One
 190is the send-packet routine, which enforces single-threaded use by the
 191dev->tbusy flag.  The other thread is the interrupt handler, which is single
 192threaded by the hardware and other software.
 193
 194IV. Notes
 195
 196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
 1973c590, 3c595, and 3c900 boards.
 198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
 199the EISA version is called "Demon".  According to Terry these names come
 200from rides at the local amusement park.
 201
 202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
 203This driver only supports ethernet packets because of the skbuff allocation
 204limit of 4K.
 205*/
 206
 207/* This table drives the PCI probe routines.  It's mostly boilerplate in all
 208   of the drivers, and will likely be provided by some future kernel.
 209*/
 210enum pci_flags_bit {
 211        PCI_USES_MASTER=4,
 212};
 213
 214enum {  IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
 215        EEPROM_8BIT=0x10,       /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
 216        HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
 217        INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
 218        EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
 219        EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
 220
 221enum vortex_chips {
 222        CH_3C590 = 0,
 223        CH_3C592,
 224        CH_3C597,
 225        CH_3C595_1,
 226        CH_3C595_2,
 227
 228        CH_3C595_3,
 229        CH_3C900_1,
 230        CH_3C900_2,
 231        CH_3C900_3,
 232        CH_3C900_4,
 233
 234        CH_3C900_5,
 235        CH_3C900B_FL,
 236        CH_3C905_1,
 237        CH_3C905_2,
 238        CH_3C905B_TX,
 239        CH_3C905B_1,
 240
 241        CH_3C905B_2,
 242        CH_3C905B_FX,
 243        CH_3C905C,
 244        CH_3C9202,
 245        CH_3C980,
 246        CH_3C9805,
 247
 248        CH_3CSOHO100_TX,
 249        CH_3C555,
 250        CH_3C556,
 251        CH_3C556B,
 252        CH_3C575,
 253
 254        CH_3C575_1,
 255        CH_3CCFE575,
 256        CH_3CCFE575CT,
 257        CH_3CCFE656,
 258        CH_3CCFEM656,
 259
 260        CH_3CCFEM656_1,
 261        CH_3C450,
 262        CH_3C920,
 263        CH_3C982A,
 264        CH_3C982B,
 265
 266        CH_905BT4,
 267        CH_920B_EMB_WNM,
 268};
 269
 270
 271/* note: this array directly indexed by above enums, and MUST
 272 * be kept in sync with both the enums above, and the PCI device
 273 * table below
 274 */
 275static struct vortex_chip_info {
 276        const char *name;
 277        int flags;
 278        int drv_flags;
 279        int io_size;
 280} vortex_info_tbl[] = {
 281        {"3c590 Vortex 10Mbps",
 282         PCI_USES_MASTER, IS_VORTEX, 32, },
 283        {"3c592 EISA 10Mbps Demon/Vortex",                                      /* AKPM: from Don's 3c59x_cb.c 0.49H */
 284         PCI_USES_MASTER, IS_VORTEX, 32, },
 285        {"3c597 EISA Fast Demon/Vortex",                                        /* AKPM: from Don's 3c59x_cb.c 0.49H */
 286         PCI_USES_MASTER, IS_VORTEX, 32, },
 287        {"3c595 Vortex 100baseTx",
 288         PCI_USES_MASTER, IS_VORTEX, 32, },
 289        {"3c595 Vortex 100baseT4",
 290         PCI_USES_MASTER, IS_VORTEX, 32, },
 291
 292        {"3c595 Vortex 100base-MII",
 293         PCI_USES_MASTER, IS_VORTEX, 32, },
 294        {"3c900 Boomerang 10baseT",
 295         PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
 296        {"3c900 Boomerang 10Mbps Combo",
 297         PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
 298        {"3c900 Cyclone 10Mbps TPO",                                            /* AKPM: from Don's 0.99M */
 299         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
 300        {"3c900 Cyclone 10Mbps Combo",
 301         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
 302
 303        {"3c900 Cyclone 10Mbps TPC",                                            /* AKPM: from Don's 0.99M */
 304         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
 305        {"3c900B-FL Cyclone 10base-FL",
 306         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
 307        {"3c905 Boomerang 100baseTx",
 308         PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
 309        {"3c905 Boomerang 100baseT4",
 310         PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
 311        {"3C905B-TX Fast Etherlink XL PCI",
 312         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
 313        {"3c905B Cyclone 100baseTx",
 314         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
 315
 316        {"3c905B Cyclone 10/100/BNC",
 317         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
 318        {"3c905B-FX Cyclone 100baseFx",
 319         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
 320        {"3c905C Tornado",
 321        PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
 322        {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
 323         PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
 324        {"3c980 Cyclone",
 325         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
 326
 327        {"3c980C Python-T",
 328         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
 329        {"3cSOHO100-TX Hurricane",
 330         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
 331        {"3c555 Laptop Hurricane",
 332         PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
 333        {"3c556 Laptop Tornado",
 334         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
 335                                                                        HAS_HWCKSM, 128, },
 336        {"3c556B Laptop Hurricane",
 337         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
 338                                        WNO_XCVR_PWR|HAS_HWCKSM, 128, },
 339
 340        {"3c575 [Megahertz] 10/100 LAN  CardBus",
 341        PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
 342        {"3c575 Boomerang CardBus",
 343         PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
 344        {"3CCFE575BT Cyclone CardBus",
 345         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
 346                                                                        INVERT_LED_PWR|HAS_HWCKSM, 128, },
 347        {"3CCFE575CT Tornado CardBus",
 348         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
 349                                                                        MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
 350        {"3CCFE656 Cyclone CardBus",
 351         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
 352                                                                        INVERT_LED_PWR|HAS_HWCKSM, 128, },
 353
 354        {"3CCFEM656B Cyclone+Winmodem CardBus",
 355         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
 356                                                                        INVERT_LED_PWR|HAS_HWCKSM, 128, },
 357        {"3CXFEM656C Tornado+Winmodem CardBus",                 /* From pcmcia-cs-3.1.5 */
 358         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
 359                                                                        MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
 360        {"3c450 HomePNA Tornado",                                               /* AKPM: from Don's 0.99Q */
 361         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
 362        {"3c920 Tornado",
 363         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
 364        {"3c982 Hydra Dual Port A",
 365         PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
 366
 367        {"3c982 Hydra Dual Port B",
 368         PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
 369        {"3c905B-T4",
 370         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
 371        {"3c920B-EMB-WNM Tornado",
 372         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
 373
 374        {NULL,}, /* NULL terminated list. */
 375};
 376
 377
 378static const struct pci_device_id vortex_pci_tbl[] = {
 379        { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
 380        { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
 381        { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
 382        { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
 383        { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
 384
 385        { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
 386        { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
 387        { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
 388        { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
 389        { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
 390
 391        { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
 392        { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
 393        { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
 394        { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
 395        { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
 396        { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
 397
 398        { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
 399        { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
 400        { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
 401        { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
 402        { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
 403        { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
 404
 405        { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
 406        { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
 407        { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
 408        { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
 409        { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
 410
 411        { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
 412        { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
 413        { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
 414        { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
 415        { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
 416
 417        { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
 418        { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
 419        { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
 420        { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
 421        { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
 422
 423        { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
 424        { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
 425
 426        {0,}                                            /* 0 terminated list. */
 427};
 428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
 429
 430
 431/* Operational definitions.
 432   These are not used by other compilation units and thus are not
 433   exported in a ".h" file.
 434
 435   First the windows.  There are eight register windows, with the command
 436   and status registers available in each.
 437   */
 438#define EL3_CMD 0x0e
 439#define EL3_STATUS 0x0e
 440
 441/* The top five bits written to EL3_CMD are a command, the lower
 442   11 bits are the parameter, if applicable.
 443   Note that 11 parameters bits was fine for ethernet, but the new chip
 444   can handle FDDI length frames (~4500 octets) and now parameters count
 445   32-bit 'Dwords' rather than octets. */
 446
 447enum vortex_cmd {
 448        TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
 449        RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
 450        UpStall = 6<<11, UpUnstall = (6<<11)+1,
 451        DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
 452        RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
 453        FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
 454        SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
 455        SetTxThreshold = 18<<11, SetTxStart = 19<<11,
 456        StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
 457        StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
 458
 459/* The SetRxFilter command accepts the following classes: */
 460enum RxFilter {
 461        RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
 462
 463/* Bits in the general status register. */
 464enum vortex_status {
 465        IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
 466        TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
 467        IntReq = 0x0040, StatsFull = 0x0080,
 468        DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
 469        DMAInProgress = 1<<11,                  /* DMA controller is still busy.*/
 470        CmdInProgress = 1<<12,                  /* EL3_CMD is still busy.*/
 471};
 472
 473/* Register window 1 offsets, the window used in normal operation.
 474   On the Vortex this window is always mapped at offsets 0x10-0x1f. */
 475enum Window1 {
 476        TX_FIFO = 0x10,  RX_FIFO = 0x10,  RxErrors = 0x14,
 477        RxStatus = 0x18,  Timer=0x1A, TxStatus = 0x1B,
 478        TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
 479};
 480enum Window0 {
 481        Wn0EepromCmd = 10,              /* Window 0: EEPROM command register. */
 482        Wn0EepromData = 12,             /* Window 0: EEPROM results register. */
 483        IntrStatus=0x0E,                /* Valid in all windows. */
 484};
 485enum Win0_EEPROM_bits {
 486        EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
 487        EEPROM_EWENB = 0x30,            /* Enable erasing/writing for 10 msec. */
 488        EEPROM_EWDIS = 0x00,            /* Disable EWENB before 10 msec timeout. */
 489};
 490/* EEPROM locations. */
 491enum eeprom_offset {
 492        PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
 493        EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
 494        NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
 495        DriverTune=13, Checksum=15};
 496
 497enum Window2 {                  /* Window 2. */
 498        Wn2_ResetOptions=12,
 499};
 500enum Window3 {                  /* Window 3: MAC/config bits. */
 501        Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
 502};
 503
 504#define BFEXT(value, offset, bitcount)  \
 505    ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
 506
 507#define BFINS(lhs, rhs, offset, bitcount)                                       \
 508        (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) |   \
 509        (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
 510
 511#define RAM_SIZE(v)             BFEXT(v, 0, 3)
 512#define RAM_WIDTH(v)    BFEXT(v, 3, 1)
 513#define RAM_SPEED(v)    BFEXT(v, 4, 2)
 514#define ROM_SIZE(v)             BFEXT(v, 6, 2)
 515#define RAM_SPLIT(v)    BFEXT(v, 16, 2)
 516#define XCVR(v)                 BFEXT(v, 20, 4)
 517#define AUTOSELECT(v)   BFEXT(v, 24, 1)
 518
 519enum Window4 {          /* Window 4: Xcvr/media bits. */
 520        Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
 521};
 522enum Win4_Media_bits {
 523        Media_SQE = 0x0008,             /* Enable SQE error counting for AUI. */
 524        Media_10TP = 0x00C0,    /* Enable link beat and jabber for 10baseT. */
 525        Media_Lnk = 0x0080,             /* Enable just link beat for 100TX/100FX. */
 526        Media_LnkBeat = 0x0800,
 527};
 528enum Window7 {                                  /* Window 7: Bus Master control. */
 529        Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
 530        Wn7_MasterStatus = 12,
 531};
 532/* Boomerang bus master control registers. */
 533enum MasterCtrl {
 534        PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
 535        TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
 536};
 537
 538/* The Rx and Tx descriptor lists.
 539   Caution Alpha hackers: these types are 32 bits!  Note also the 8 byte
 540   alignment contraint on tx_ring[] and rx_ring[]. */
 541#define LAST_FRAG       0x80000000                      /* Last Addr/Len pair in descriptor. */
 542#define DN_COMPLETE     0x00010000                      /* This packet has been downloaded */
 543struct boom_rx_desc {
 544        __le32 next;                                    /* Last entry points to 0.   */
 545        __le32 status;
 546        __le32 addr;                                    /* Up to 63 addr/len pairs possible. */
 547        __le32 length;                                  /* Set LAST_FRAG to indicate last pair. */
 548};
 549/* Values for the Rx status entry. */
 550enum rx_desc_status {
 551        RxDComplete=0x00008000, RxDError=0x4000,
 552        /* See boomerang_rx() for actual error bits */
 553        IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
 554        IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
 555};
 556
 557#ifdef MAX_SKB_FRAGS
 558#define DO_ZEROCOPY 1
 559#else
 560#define DO_ZEROCOPY 0
 561#endif
 562
 563struct boom_tx_desc {
 564        __le32 next;                                    /* Last entry points to 0.   */
 565        __le32 status;                                  /* bits 0:12 length, others see below.  */
 566#if DO_ZEROCOPY
 567        struct {
 568                __le32 addr;
 569                __le32 length;
 570        } frag[1+MAX_SKB_FRAGS];
 571#else
 572                __le32 addr;
 573                __le32 length;
 574#endif
 575};
 576
 577/* Values for the Tx status entry. */
 578enum tx_desc_status {
 579        CRCDisable=0x2000, TxDComplete=0x8000,
 580        AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
 581        TxIntrUploaded=0x80000000,              /* IRQ when in FIFO, but maybe not sent. */
 582};
 583
 584/* Chip features we care about in vp->capabilities, read from the EEPROM. */
 585enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
 586
 587struct vortex_extra_stats {
 588        unsigned long tx_deferred;
 589        unsigned long tx_max_collisions;
 590        unsigned long tx_multiple_collisions;
 591        unsigned long tx_single_collisions;
 592        unsigned long rx_bad_ssd;
 593};
 594
 595struct vortex_private {
 596        /* The Rx and Tx rings should be quad-word-aligned. */
 597        struct boom_rx_desc* rx_ring;
 598        struct boom_tx_desc* tx_ring;
 599        dma_addr_t rx_ring_dma;
 600        dma_addr_t tx_ring_dma;
 601        /* The addresses of transmit- and receive-in-place skbuffs. */
 602        struct sk_buff* rx_skbuff[RX_RING_SIZE];
 603        struct sk_buff* tx_skbuff[TX_RING_SIZE];
 604        unsigned int cur_rx, cur_tx;            /* The next free ring entry */
 605        unsigned int dirty_tx;  /* The ring entries to be free()ed. */
 606        struct vortex_extra_stats xstats;       /* NIC-specific extra stats */
 607        struct sk_buff *tx_skb;                         /* Packet being eaten by bus master ctrl.  */
 608        dma_addr_t tx_skb_dma;                          /* Allocated DMA address for bus master ctrl DMA.   */
 609
 610        /* PCI configuration space information. */
 611        struct device *gendev;
 612        void __iomem *ioaddr;                   /* IO address space */
 613        void __iomem *cb_fn_base;               /* CardBus function status addr space. */
 614
 615        /* Some values here only for performance evaluation and path-coverage */
 616        int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
 617        int card_idx;
 618
 619        /* The remainder are related to chip state, mostly media selection. */
 620        struct timer_list timer;                        /* Media selection timer. */
 621        int options;                                            /* User-settable misc. driver options. */
 622        unsigned int media_override:4,          /* Passed-in media type. */
 623                default_media:4,                                /* Read from the EEPROM/Wn3_Config. */
 624                full_duplex:1, autoselect:1,
 625                bus_master:1,                                   /* Vortex can only do a fragment bus-m. */
 626                full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang  */
 627                flow_ctrl:1,                                    /* Use 802.3x flow control (PAUSE only) */
 628                partner_flow_ctrl:1,                    /* Partner supports flow control */
 629                has_nway:1,
 630                enable_wol:1,                                   /* Wake-on-LAN is enabled */
 631                pm_state_valid:1,                               /* pci_dev->saved_config_space has sane contents */
 632                open:1,
 633                medialock:1,
 634                large_frames:1,                 /* accept large frames */
 635                handling_irq:1;                 /* private in_irq indicator */
 636        /* {get|set}_wol operations are already serialized by rtnl.
 637         * no additional locking is required for the enable_wol and acpi_set_WOL()
 638         */
 639        int drv_flags;
 640        u16 status_enable;
 641        u16 intr_enable;
 642        u16 available_media;                            /* From Wn3_Options. */
 643        u16 capabilities, info1, info2;         /* Various, from EEPROM. */
 644        u16 advertising;                                        /* NWay media advertisement */
 645        unsigned char phys[2];                          /* MII device addresses. */
 646        u16 deferred;                                           /* Resend these interrupts when we
 647                                                                                 * bale from the ISR */
 648        u16 io_size;                                            /* Size of PCI region (for release_region) */
 649
 650        /* Serialises access to hardware other than MII and variables below.
 651         * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
 652        spinlock_t lock;
 653
 654        spinlock_t mii_lock;            /* Serialises access to MII */
 655        struct mii_if_info mii;         /* MII lib hooks/info */
 656        spinlock_t window_lock;         /* Serialises access to windowed regs */
 657        int window;                     /* Register window */
 658};
 659
 660static void window_set(struct vortex_private *vp, int window)
 661{
 662        if (window != vp->window) {
 663                iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
 664                vp->window = window;
 665        }
 666}
 667
 668#define DEFINE_WINDOW_IO(size)                                          \
 669static u ## size                                                        \
 670window_read ## size(struct vortex_private *vp, int window, int addr)    \
 671{                                                                       \
 672        unsigned long flags;                                            \
 673        u ## size ret;                                                  \
 674        spin_lock_irqsave(&vp->window_lock, flags);                     \
 675        window_set(vp, window);                                         \
 676        ret = ioread ## size(vp->ioaddr + addr);                        \
 677        spin_unlock_irqrestore(&vp->window_lock, flags);                \
 678        return ret;                                                     \
 679}                                                                       \
 680static void                                                             \
 681window_write ## size(struct vortex_private *vp, u ## size value,        \
 682                     int window, int addr)                              \
 683{                                                                       \
 684        unsigned long flags;                                            \
 685        spin_lock_irqsave(&vp->window_lock, flags);                     \
 686        window_set(vp, window);                                         \
 687        iowrite ## size(value, vp->ioaddr + addr);                      \
 688        spin_unlock_irqrestore(&vp->window_lock, flags);                \
 689}
 690DEFINE_WINDOW_IO(8)
 691DEFINE_WINDOW_IO(16)
 692DEFINE_WINDOW_IO(32)
 693
 694#ifdef CONFIG_PCI
 695#define DEVICE_PCI(dev) ((dev_is_pci(dev)) ? to_pci_dev((dev)) : NULL)
 696#else
 697#define DEVICE_PCI(dev) NULL
 698#endif
 699
 700#define VORTEX_PCI(vp)                                                  \
 701        ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
 702
 703#ifdef CONFIG_EISA
 704#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
 705#else
 706#define DEVICE_EISA(dev) NULL
 707#endif
 708
 709#define VORTEX_EISA(vp)                                                 \
 710        ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
 711
 712/* The action to take with a media selection timer tick.
 713   Note that we deviate from the 3Com order by checking 10base2 before AUI.
 714 */
 715enum xcvr_types {
 716        XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
 717        XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
 718};
 719
 720static const struct media_table {
 721        char *name;
 722        unsigned int media_bits:16,             /* Bits to set in Wn4_Media register. */
 723                mask:8,                                         /* The transceiver-present bit in Wn3_Config.*/
 724                next:8;                                         /* The media type to try next. */
 725        int wait;                                               /* Time before we check media status. */
 726} media_tbl[] = {
 727  {     "10baseT",   Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
 728  { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
 729  { "undefined", 0,                     0x80, XCVR_10baseT, 10000},
 730  { "10base2",   0,                     0x10, XCVR_AUI,         (1*HZ)/10},
 731  { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
 732  { "100baseFX", Media_Lnk, 0x04, XCVR_MII,             (14*HZ)/10},
 733  { "MII",               0,                     0x41, XCVR_10baseT, 3*HZ },
 734  { "undefined", 0,                     0x01, XCVR_10baseT, 10000},
 735  { "Autonegotiate", 0,         0x41, XCVR_10baseT, 3*HZ},
 736  { "MII-External",      0,             0x41, XCVR_10baseT, 3*HZ },
 737  { "Default",   0,                     0xFF, XCVR_10baseT, 10000},
 738};
 739
 740static struct {
 741        const char str[ETH_GSTRING_LEN];
 742} ethtool_stats_keys[] = {
 743        { "tx_deferred" },
 744        { "tx_max_collisions" },
 745        { "tx_multiple_collisions" },
 746        { "tx_single_collisions" },
 747        { "rx_bad_ssd" },
 748};
 749
 750/* number of ETHTOOL_GSTATS u64's */
 751#define VORTEX_NUM_STATS    5
 752
 753static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
 754                                   int chip_idx, int card_idx);
 755static int vortex_up(struct net_device *dev);
 756static void vortex_down(struct net_device *dev, int final);
 757static int vortex_open(struct net_device *dev);
 758static void mdio_sync(struct vortex_private *vp, int bits);
 759static int mdio_read(struct net_device *dev, int phy_id, int location);
 760static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
 761static void vortex_timer(struct timer_list *t);
 762static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
 763                                     struct net_device *dev);
 764static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
 765                                        struct net_device *dev);
 766static int vortex_rx(struct net_device *dev);
 767static int boomerang_rx(struct net_device *dev);
 768static irqreturn_t vortex_boomerang_interrupt(int irq, void *dev_id);
 769static irqreturn_t _vortex_interrupt(int irq, struct net_device *dev);
 770static irqreturn_t _boomerang_interrupt(int irq, struct net_device *dev);
 771static int vortex_close(struct net_device *dev);
 772static void dump_tx_ring(struct net_device *dev);
 773static void update_stats(void __iomem *ioaddr, struct net_device *dev);
 774static struct net_device_stats *vortex_get_stats(struct net_device *dev);
 775static void set_rx_mode(struct net_device *dev);
 776#ifdef CONFIG_PCI
 777static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 778#endif
 779static void vortex_tx_timeout(struct net_device *dev, unsigned int txqueue);
 780static void acpi_set_WOL(struct net_device *dev);
 781static const struct ethtool_ops vortex_ethtool_ops;
 782static void set_8021q_mode(struct net_device *dev, int enable);
 783
 784/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
 785/* Option count limit only -- unlimited interfaces are supported. */
 786#define MAX_UNITS 8
 787static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
 788static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
 789static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
 790static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
 791static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
 792static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
 793static int global_options = -1;
 794static int global_full_duplex = -1;
 795static int global_enable_wol = -1;
 796static int global_use_mmio = -1;
 797
 798/* Variables to work-around the Compaq PCI BIOS32 problem. */
 799static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
 800static struct net_device *compaq_net_device;
 801
 802static int vortex_cards_found;
 803
 804module_param(debug, int, 0);
 805module_param(global_options, int, 0);
 806module_param_array(options, int, NULL, 0);
 807module_param(global_full_duplex, int, 0);
 808module_param_array(full_duplex, int, NULL, 0);
 809module_param_array(hw_checksums, int, NULL, 0);
 810module_param_array(flow_ctrl, int, NULL, 0);
 811module_param(global_enable_wol, int, 0);
 812module_param_array(enable_wol, int, NULL, 0);
 813module_param(rx_copybreak, int, 0);
 814module_param(max_interrupt_work, int, 0);
 815module_param_hw(compaq_ioaddr, int, ioport, 0);
 816module_param_hw(compaq_irq, int, irq, 0);
 817module_param(compaq_device_id, int, 0);
 818module_param(watchdog, int, 0);
 819module_param(global_use_mmio, int, 0);
 820module_param_array(use_mmio, int, NULL, 0);
 821MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
 822MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
 823MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
 824MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
 825MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
 826MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
 827MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
 828MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
 829MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
 830MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
 831MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
 832MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
 833MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
 834MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
 835MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
 836MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
 837MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
 838
 839#ifdef CONFIG_NET_POLL_CONTROLLER
 840static void poll_vortex(struct net_device *dev)
 841{
 842        vortex_boomerang_interrupt(dev->irq, dev);
 843}
 844#endif
 845
 846#ifdef CONFIG_PM
 847
 848static int vortex_suspend(struct device *dev)
 849{
 850        struct net_device *ndev = dev_get_drvdata(dev);
 851
 852        if (!ndev || !netif_running(ndev))
 853                return 0;
 854
 855        netif_device_detach(ndev);
 856        vortex_down(ndev, 1);
 857
 858        return 0;
 859}
 860
 861static int vortex_resume(struct device *dev)
 862{
 863        struct net_device *ndev = dev_get_drvdata(dev);
 864        int err;
 865
 866        if (!ndev || !netif_running(ndev))
 867                return 0;
 868
 869        err = vortex_up(ndev);
 870        if (err)
 871                return err;
 872
 873        netif_device_attach(ndev);
 874
 875        return 0;
 876}
 877
 878static const struct dev_pm_ops vortex_pm_ops = {
 879        .suspend = vortex_suspend,
 880        .resume = vortex_resume,
 881        .freeze = vortex_suspend,
 882        .thaw = vortex_resume,
 883        .poweroff = vortex_suspend,
 884        .restore = vortex_resume,
 885};
 886
 887#define VORTEX_PM_OPS (&vortex_pm_ops)
 888
 889#else /* !CONFIG_PM */
 890
 891#define VORTEX_PM_OPS NULL
 892
 893#endif /* !CONFIG_PM */
 894
 895#ifdef CONFIG_EISA
 896static const struct eisa_device_id vortex_eisa_ids[] = {
 897        { "TCM5920", CH_3C592 },
 898        { "TCM5970", CH_3C597 },
 899        { "" }
 900};
 901MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
 902
 903static int vortex_eisa_probe(struct device *device)
 904{
 905        void __iomem *ioaddr;
 906        struct eisa_device *edev;
 907
 908        edev = to_eisa_device(device);
 909
 910        if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
 911                return -EBUSY;
 912
 913        ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
 914
 915        if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
 916                                          edev->id.driver_data, vortex_cards_found)) {
 917                release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
 918                return -ENODEV;
 919        }
 920
 921        vortex_cards_found++;
 922
 923        return 0;
 924}
 925
 926static int vortex_eisa_remove(struct device *device)
 927{
 928        struct eisa_device *edev;
 929        struct net_device *dev;
 930        struct vortex_private *vp;
 931        void __iomem *ioaddr;
 932
 933        edev = to_eisa_device(device);
 934        dev = eisa_get_drvdata(edev);
 935
 936        if (!dev) {
 937                pr_err("vortex_eisa_remove called for Compaq device!\n");
 938                BUG();
 939        }
 940
 941        vp = netdev_priv(dev);
 942        ioaddr = vp->ioaddr;
 943
 944        unregister_netdev(dev);
 945        iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
 946        release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
 947
 948        free_netdev(dev);
 949        return 0;
 950}
 951
 952static struct eisa_driver vortex_eisa_driver = {
 953        .id_table = vortex_eisa_ids,
 954        .driver   = {
 955                .name    = "3c59x",
 956                .probe   = vortex_eisa_probe,
 957                .remove  = vortex_eisa_remove
 958        }
 959};
 960
 961#endif /* CONFIG_EISA */
 962
 963/* returns count found (>= 0), or negative on error */
 964static int __init vortex_eisa_init(void)
 965{
 966        int eisa_found = 0;
 967        int orig_cards_found = vortex_cards_found;
 968
 969#ifdef CONFIG_EISA
 970        int err;
 971
 972        err = eisa_driver_register (&vortex_eisa_driver);
 973        if (!err) {
 974                /*
 975                 * Because of the way EISA bus is probed, we cannot assume
 976                 * any device have been found when we exit from
 977                 * eisa_driver_register (the bus root driver may not be
 978                 * initialized yet). So we blindly assume something was
 979                 * found, and let the sysfs magic happened...
 980                 */
 981                eisa_found = 1;
 982        }
 983#endif
 984
 985        /* Special code to work-around the Compaq PCI BIOS32 problem. */
 986        if (compaq_ioaddr) {
 987                vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
 988                              compaq_irq, compaq_device_id, vortex_cards_found++);
 989        }
 990
 991        return vortex_cards_found - orig_cards_found + eisa_found;
 992}
 993
 994/* returns count (>= 0), or negative on error */
 995static int vortex_init_one(struct pci_dev *pdev,
 996                           const struct pci_device_id *ent)
 997{
 998        int rc, unit, pci_bar;
 999        struct vortex_chip_info *vci;
1000        void __iomem *ioaddr;
1001
1002        /* wake up and enable device */
1003        rc = pci_enable_device(pdev);
1004        if (rc < 0)
1005                goto out;
1006
1007        rc = pci_request_regions(pdev, DRV_NAME);
1008        if (rc < 0)
1009                goto out_disable;
1010
1011        unit = vortex_cards_found;
1012
1013        if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1014                /* Determine the default if the user didn't override us */
1015                vci = &vortex_info_tbl[ent->driver_data];
1016                pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1017        } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1018                pci_bar = use_mmio[unit] ? 1 : 0;
1019        else
1020                pci_bar = global_use_mmio ? 1 : 0;
1021
1022        ioaddr = pci_iomap(pdev, pci_bar, 0);
1023        if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1024                ioaddr = pci_iomap(pdev, 0, 0);
1025        if (!ioaddr) {
1026                rc = -ENOMEM;
1027                goto out_release;
1028        }
1029
1030        rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1031                           ent->driver_data, unit);
1032        if (rc < 0)
1033                goto out_iounmap;
1034
1035        vortex_cards_found++;
1036        goto out;
1037
1038out_iounmap:
1039        pci_iounmap(pdev, ioaddr);
1040out_release:
1041        pci_release_regions(pdev);
1042out_disable:
1043        pci_disable_device(pdev);
1044out:
1045        return rc;
1046}
1047
1048static const struct net_device_ops boomrang_netdev_ops = {
1049        .ndo_open               = vortex_open,
1050        .ndo_stop               = vortex_close,
1051        .ndo_start_xmit         = boomerang_start_xmit,
1052        .ndo_tx_timeout         = vortex_tx_timeout,
1053        .ndo_get_stats          = vortex_get_stats,
1054#ifdef CONFIG_PCI
1055        .ndo_do_ioctl           = vortex_ioctl,
1056#endif
1057        .ndo_set_rx_mode        = set_rx_mode,
1058        .ndo_set_mac_address    = eth_mac_addr,
1059        .ndo_validate_addr      = eth_validate_addr,
1060#ifdef CONFIG_NET_POLL_CONTROLLER
1061        .ndo_poll_controller    = poll_vortex,
1062#endif
1063};
1064
1065static const struct net_device_ops vortex_netdev_ops = {
1066        .ndo_open               = vortex_open,
1067        .ndo_stop               = vortex_close,
1068        .ndo_start_xmit         = vortex_start_xmit,
1069        .ndo_tx_timeout         = vortex_tx_timeout,
1070        .ndo_get_stats          = vortex_get_stats,
1071#ifdef CONFIG_PCI
1072        .ndo_do_ioctl           = vortex_ioctl,
1073#endif
1074        .ndo_set_rx_mode        = set_rx_mode,
1075        .ndo_set_mac_address    = eth_mac_addr,
1076        .ndo_validate_addr      = eth_validate_addr,
1077#ifdef CONFIG_NET_POLL_CONTROLLER
1078        .ndo_poll_controller    = poll_vortex,
1079#endif
1080};
1081
1082/*
1083 * Start up the PCI/EISA device which is described by *gendev.
1084 * Return 0 on success.
1085 *
1086 * NOTE: pdev can be NULL, for the case of a Compaq device
1087 */
1088static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1089                         int chip_idx, int card_idx)
1090{
1091        struct vortex_private *vp;
1092        int option;
1093        unsigned int eeprom[0x40], checksum = 0;                /* EEPROM contents */
1094        int i, step;
1095        struct net_device *dev;
1096        static int printed_version;
1097        int retval, print_info;
1098        struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1099        const char *print_name = "3c59x";
1100        struct pci_dev *pdev = NULL;
1101        struct eisa_device *edev = NULL;
1102
1103        if (!printed_version) {
1104                pr_info("%s", version);
1105                printed_version = 1;
1106        }
1107
1108        if (gendev) {
1109                if ((pdev = DEVICE_PCI(gendev))) {
1110                        print_name = pci_name(pdev);
1111                }
1112
1113                if ((edev = DEVICE_EISA(gendev))) {
1114                        print_name = dev_name(&edev->dev);
1115                }
1116        }
1117
1118        dev = alloc_etherdev(sizeof(*vp));
1119        retval = -ENOMEM;
1120        if (!dev)
1121                goto out;
1122
1123        SET_NETDEV_DEV(dev, gendev);
1124        vp = netdev_priv(dev);
1125
1126        option = global_options;
1127
1128        /* The lower four bits are the media type. */
1129        if (dev->mem_start) {
1130                /*
1131                 * The 'options' param is passed in as the third arg to the
1132                 * LILO 'ether=' argument for non-modular use
1133                 */
1134                option = dev->mem_start;
1135        }
1136        else if (card_idx < MAX_UNITS) {
1137                if (options[card_idx] >= 0)
1138                        option = options[card_idx];
1139        }
1140
1141        if (option > 0) {
1142                if (option & 0x8000)
1143                        vortex_debug = 7;
1144                if (option & 0x4000)
1145                        vortex_debug = 2;
1146                if (option & 0x0400)
1147                        vp->enable_wol = 1;
1148        }
1149
1150        print_info = (vortex_debug > 1);
1151        if (print_info)
1152                pr_info("See Documentation/networking/device_drivers/ethernet/3com/vortex.rst\n");
1153
1154        pr_info("%s: 3Com %s %s at %p.\n",
1155               print_name,
1156               pdev ? "PCI" : "EISA",
1157               vci->name,
1158               ioaddr);
1159
1160        dev->base_addr = (unsigned long)ioaddr;
1161        dev->irq = irq;
1162        dev->mtu = mtu;
1163        vp->ioaddr = ioaddr;
1164        vp->large_frames = mtu > 1500;
1165        vp->drv_flags = vci->drv_flags;
1166        vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1167        vp->io_size = vci->io_size;
1168        vp->card_idx = card_idx;
1169        vp->window = -1;
1170
1171        /* module list only for Compaq device */
1172        if (gendev == NULL) {
1173                compaq_net_device = dev;
1174        }
1175
1176        /* PCI-only startup logic */
1177        if (pdev) {
1178                /* enable bus-mastering if necessary */
1179                if (vci->flags & PCI_USES_MASTER)
1180                        pci_set_master(pdev);
1181
1182                if (vci->drv_flags & IS_VORTEX) {
1183                        u8 pci_latency;
1184                        u8 new_latency = 248;
1185
1186                        /* Check the PCI latency value.  On the 3c590 series the latency timer
1187                           must be set to the maximum value to avoid data corruption that occurs
1188                           when the timer expires during a transfer.  This bug exists the Vortex
1189                           chip only. */
1190                        pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1191                        if (pci_latency < new_latency) {
1192                                pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1193                                        print_name, pci_latency, new_latency);
1194                                pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1195                        }
1196                }
1197        }
1198
1199        spin_lock_init(&vp->lock);
1200        spin_lock_init(&vp->mii_lock);
1201        spin_lock_init(&vp->window_lock);
1202        vp->gendev = gendev;
1203        vp->mii.dev = dev;
1204        vp->mii.mdio_read = mdio_read;
1205        vp->mii.mdio_write = mdio_write;
1206        vp->mii.phy_id_mask = 0x1f;
1207        vp->mii.reg_num_mask = 0x1f;
1208
1209        /* Makes sure rings are at least 16 byte aligned. */
1210        vp->rx_ring = dma_alloc_coherent(gendev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1211                                           + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1212                                           &vp->rx_ring_dma, GFP_KERNEL);
1213        retval = -ENOMEM;
1214        if (!vp->rx_ring)
1215                goto free_device;
1216
1217        vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1218        vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1219
1220        /* if we are a PCI driver, we store info in pdev->driver_data
1221         * instead of a module list */
1222        if (pdev)
1223                pci_set_drvdata(pdev, dev);
1224        if (edev)
1225                eisa_set_drvdata(edev, dev);
1226
1227        vp->media_override = 7;
1228        if (option >= 0) {
1229                vp->media_override = ((option & 7) == 2)  ?  0  :  option & 15;
1230                if (vp->media_override != 7)
1231                        vp->medialock = 1;
1232                vp->full_duplex = (option & 0x200) ? 1 : 0;
1233                vp->bus_master = (option & 16) ? 1 : 0;
1234        }
1235
1236        if (global_full_duplex > 0)
1237                vp->full_duplex = 1;
1238        if (global_enable_wol > 0)
1239                vp->enable_wol = 1;
1240
1241        if (card_idx < MAX_UNITS) {
1242                if (full_duplex[card_idx] > 0)
1243                        vp->full_duplex = 1;
1244                if (flow_ctrl[card_idx] > 0)
1245                        vp->flow_ctrl = 1;
1246                if (enable_wol[card_idx] > 0)
1247                        vp->enable_wol = 1;
1248        }
1249
1250        vp->mii.force_media = vp->full_duplex;
1251        vp->options = option;
1252        /* Read the station address from the EEPROM. */
1253        {
1254                int base;
1255
1256                if (vci->drv_flags & EEPROM_8BIT)
1257                        base = 0x230;
1258                else if (vci->drv_flags & EEPROM_OFFSET)
1259                        base = EEPROM_Read + 0x30;
1260                else
1261                        base = EEPROM_Read;
1262
1263                for (i = 0; i < 0x40; i++) {
1264                        int timer;
1265                        window_write16(vp, base + i, 0, Wn0EepromCmd);
1266                        /* Pause for at least 162 us. for the read to take place. */
1267                        for (timer = 10; timer >= 0; timer--) {
1268                                udelay(162);
1269                                if ((window_read16(vp, 0, Wn0EepromCmd) &
1270                                     0x8000) == 0)
1271                                        break;
1272                        }
1273                        eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1274                }
1275        }
1276        for (i = 0; i < 0x18; i++)
1277                checksum ^= eeprom[i];
1278        checksum = (checksum ^ (checksum >> 8)) & 0xff;
1279        if (checksum != 0x00) {         /* Grrr, needless incompatible change 3Com. */
1280                while (i < 0x21)
1281                        checksum ^= eeprom[i++];
1282                checksum = (checksum ^ (checksum >> 8)) & 0xff;
1283        }
1284        if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1285                pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1286        for (i = 0; i < 3; i++)
1287                ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1288        if (print_info)
1289                pr_cont(" %pM", dev->dev_addr);
1290        /* Unfortunately an all zero eeprom passes the checksum and this
1291           gets found in the wild in failure cases. Crypto is hard 8) */
1292        if (!is_valid_ether_addr(dev->dev_addr)) {
1293                retval = -EINVAL;
1294                pr_err("*** EEPROM MAC address is invalid.\n");
1295                goto free_ring; /* With every pack */
1296        }
1297        for (i = 0; i < 6; i++)
1298                window_write8(vp, dev->dev_addr[i], 2, i);
1299
1300        if (print_info)
1301                pr_cont(", IRQ %d\n", dev->irq);
1302        /* Tell them about an invalid IRQ. */
1303        if (dev->irq <= 0 || dev->irq >= nr_irqs)
1304                pr_warn(" *** Warning: IRQ %d is unlikely to work! ***\n",
1305                        dev->irq);
1306
1307        step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1308        if (print_info) {
1309                pr_info("  product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1310                        eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1311                        step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1312        }
1313
1314
1315        if (pdev && vci->drv_flags & HAS_CB_FNS) {
1316                unsigned short n;
1317
1318                vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1319                if (!vp->cb_fn_base) {
1320                        retval = -ENOMEM;
1321                        goto free_ring;
1322                }
1323
1324                if (print_info) {
1325                        pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1326                                print_name,
1327                                (unsigned long long)pci_resource_start(pdev, 2),
1328                                vp->cb_fn_base);
1329                }
1330
1331                n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1332                if (vp->drv_flags & INVERT_LED_PWR)
1333                        n |= 0x10;
1334                if (vp->drv_flags & INVERT_MII_PWR)
1335                        n |= 0x4000;
1336                window_write16(vp, n, 2, Wn2_ResetOptions);
1337                if (vp->drv_flags & WNO_XCVR_PWR) {
1338                        window_write16(vp, 0x0800, 0, 0);
1339                }
1340        }
1341
1342        /* Extract our information from the EEPROM data. */
1343        vp->info1 = eeprom[13];
1344        vp->info2 = eeprom[15];
1345        vp->capabilities = eeprom[16];
1346
1347        if (vp->info1 & 0x8000) {
1348                vp->full_duplex = 1;
1349                if (print_info)
1350                        pr_info("Full duplex capable\n");
1351        }
1352
1353        {
1354                static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1355                unsigned int config;
1356                vp->available_media = window_read16(vp, 3, Wn3_Options);
1357                if ((vp->available_media & 0xff) == 0)          /* Broken 3c916 */
1358                        vp->available_media = 0x40;
1359                config = window_read32(vp, 3, Wn3_Config);
1360                if (print_info) {
1361                        pr_debug("  Internal config register is %4.4x, transceivers %#x.\n",
1362                                config, window_read16(vp, 3, Wn3_Options));
1363                        pr_info("  %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1364                                   8 << RAM_SIZE(config),
1365                                   RAM_WIDTH(config) ? "word" : "byte",
1366                                   ram_split[RAM_SPLIT(config)],
1367                                   AUTOSELECT(config) ? "autoselect/" : "",
1368                                   XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1369                                   media_tbl[XCVR(config)].name);
1370                }
1371                vp->default_media = XCVR(config);
1372                if (vp->default_media == XCVR_NWAY)
1373                        vp->has_nway = 1;
1374                vp->autoselect = AUTOSELECT(config);
1375        }
1376
1377        if (vp->media_override != 7) {
1378                pr_info("%s:  Media override to transceiver type %d (%s).\n",
1379                                print_name, vp->media_override,
1380                                media_tbl[vp->media_override].name);
1381                dev->if_port = vp->media_override;
1382        } else
1383                dev->if_port = vp->default_media;
1384
1385        if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1386                dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1387                int phy, phy_idx = 0;
1388                mii_preamble_required++;
1389                if (vp->drv_flags & EXTRA_PREAMBLE)
1390                        mii_preamble_required++;
1391                mdio_sync(vp, 32);
1392                mdio_read(dev, 24, MII_BMSR);
1393                for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1394                        int mii_status, phyx;
1395
1396                        /*
1397                         * For the 3c905CX we look at index 24 first, because it bogusly
1398                         * reports an external PHY at all indices
1399                         */
1400                        if (phy == 0)
1401                                phyx = 24;
1402                        else if (phy <= 24)
1403                                phyx = phy - 1;
1404                        else
1405                                phyx = phy;
1406                        mii_status = mdio_read(dev, phyx, MII_BMSR);
1407                        if (mii_status  &&  mii_status != 0xffff) {
1408                                vp->phys[phy_idx++] = phyx;
1409                                if (print_info) {
1410                                        pr_info("  MII transceiver found at address %d, status %4x.\n",
1411                                                phyx, mii_status);
1412                                }
1413                                if ((mii_status & 0x0040) == 0)
1414                                        mii_preamble_required++;
1415                        }
1416                }
1417                mii_preamble_required--;
1418                if (phy_idx == 0) {
1419                        pr_warn("  ***WARNING*** No MII transceivers found!\n");
1420                        vp->phys[0] = 24;
1421                } else {
1422                        vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1423                        if (vp->full_duplex) {
1424                                /* Only advertise the FD media types. */
1425                                vp->advertising &= ~0x02A0;
1426                                mdio_write(dev, vp->phys[0], 4, vp->advertising);
1427                        }
1428                }
1429                vp->mii.phy_id = vp->phys[0];
1430        }
1431
1432        if (vp->capabilities & CapBusMaster) {
1433                vp->full_bus_master_tx = 1;
1434                if (print_info) {
1435                        pr_info("  Enabling bus-master transmits and %s receives.\n",
1436                        (vp->info2 & 1) ? "early" : "whole-frame" );
1437                }
1438                vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1439                vp->bus_master = 0;             /* AKPM: vortex only */
1440        }
1441
1442        /* The 3c59x-specific entries in the device structure. */
1443        if (vp->full_bus_master_tx) {
1444                dev->netdev_ops = &boomrang_netdev_ops;
1445                /* Actually, it still should work with iommu. */
1446                if (card_idx < MAX_UNITS &&
1447                    ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1448                                hw_checksums[card_idx] == 1)) {
1449                        dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1450                }
1451        } else
1452                dev->netdev_ops =  &vortex_netdev_ops;
1453
1454        if (print_info) {
1455                pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1456                                print_name,
1457                                (dev->features & NETIF_F_SG) ? "en":"dis",
1458                                (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1459        }
1460
1461        dev->ethtool_ops = &vortex_ethtool_ops;
1462        dev->watchdog_timeo = (watchdog * HZ) / 1000;
1463
1464        if (pdev) {
1465                vp->pm_state_valid = 1;
1466                pci_save_state(pdev);
1467                acpi_set_WOL(dev);
1468        }
1469        retval = register_netdev(dev);
1470        if (retval == 0)
1471                return 0;
1472
1473free_ring:
1474        dma_free_coherent(&pdev->dev,
1475                sizeof(struct boom_rx_desc) * RX_RING_SIZE +
1476                sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1477                vp->rx_ring, vp->rx_ring_dma);
1478free_device:
1479        free_netdev(dev);
1480        pr_err(PFX "vortex_probe1 fails.  Returns %d\n", retval);
1481out:
1482        return retval;
1483}
1484
1485static void
1486issue_and_wait(struct net_device *dev, int cmd)
1487{
1488        struct vortex_private *vp = netdev_priv(dev);
1489        void __iomem *ioaddr = vp->ioaddr;
1490        int i;
1491
1492        iowrite16(cmd, ioaddr + EL3_CMD);
1493        for (i = 0; i < 2000; i++) {
1494                if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1495                        return;
1496        }
1497
1498        /* OK, that didn't work.  Do it the slow way.  One second */
1499        for (i = 0; i < 100000; i++) {
1500                if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1501                        if (vortex_debug > 1)
1502                                pr_info("%s: command 0x%04x took %d usecs\n",
1503                                           dev->name, cmd, i * 10);
1504                        return;
1505                }
1506                udelay(10);
1507        }
1508        pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1509                           dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1510}
1511
1512static void
1513vortex_set_duplex(struct net_device *dev)
1514{
1515        struct vortex_private *vp = netdev_priv(dev);
1516
1517        pr_info("%s:  setting %s-duplex.\n",
1518                dev->name, (vp->full_duplex) ? "full" : "half");
1519
1520        /* Set the full-duplex bit. */
1521        window_write16(vp,
1522                       ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1523                       (vp->large_frames ? 0x40 : 0) |
1524                       ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1525                        0x100 : 0),
1526                       3, Wn3_MAC_Ctrl);
1527}
1528
1529static void vortex_check_media(struct net_device *dev, unsigned int init)
1530{
1531        struct vortex_private *vp = netdev_priv(dev);
1532        unsigned int ok_to_print = 0;
1533
1534        if (vortex_debug > 3)
1535                ok_to_print = 1;
1536
1537        if (mii_check_media(&vp->mii, ok_to_print, init)) {
1538                vp->full_duplex = vp->mii.full_duplex;
1539                vortex_set_duplex(dev);
1540        } else if (init) {
1541                vortex_set_duplex(dev);
1542        }
1543}
1544
1545static int
1546vortex_up(struct net_device *dev)
1547{
1548        struct vortex_private *vp = netdev_priv(dev);
1549        void __iomem *ioaddr = vp->ioaddr;
1550        unsigned int config;
1551        int i, mii_reg5, err = 0;
1552
1553        if (VORTEX_PCI(vp)) {
1554                pci_set_power_state(VORTEX_PCI(vp), PCI_D0);    /* Go active */
1555                if (vp->pm_state_valid)
1556                        pci_restore_state(VORTEX_PCI(vp));
1557                err = pci_enable_device(VORTEX_PCI(vp));
1558                if (err) {
1559                        pr_warn("%s: Could not enable device\n", dev->name);
1560                        goto err_out;
1561                }
1562        }
1563
1564        /* Before initializing select the active media port. */
1565        config = window_read32(vp, 3, Wn3_Config);
1566
1567        if (vp->media_override != 7) {
1568                pr_info("%s: Media override to transceiver %d (%s).\n",
1569                           dev->name, vp->media_override,
1570                           media_tbl[vp->media_override].name);
1571                dev->if_port = vp->media_override;
1572        } else if (vp->autoselect) {
1573                if (vp->has_nway) {
1574                        if (vortex_debug > 1)
1575                                pr_info("%s: using NWAY device table, not %d\n",
1576                                                                dev->name, dev->if_port);
1577                        dev->if_port = XCVR_NWAY;
1578                } else {
1579                        /* Find first available media type, starting with 100baseTx. */
1580                        dev->if_port = XCVR_100baseTx;
1581                        while (! (vp->available_media & media_tbl[dev->if_port].mask))
1582                                dev->if_port = media_tbl[dev->if_port].next;
1583                        if (vortex_debug > 1)
1584                                pr_info("%s: first available media type: %s\n",
1585                                        dev->name, media_tbl[dev->if_port].name);
1586                }
1587        } else {
1588                dev->if_port = vp->default_media;
1589                if (vortex_debug > 1)
1590                        pr_info("%s: using default media %s\n",
1591                                dev->name, media_tbl[dev->if_port].name);
1592        }
1593
1594        timer_setup(&vp->timer, vortex_timer, 0);
1595        mod_timer(&vp->timer, RUN_AT(media_tbl[dev->if_port].wait));
1596
1597        if (vortex_debug > 1)
1598                pr_debug("%s: Initial media type %s.\n",
1599                           dev->name, media_tbl[dev->if_port].name);
1600
1601        vp->full_duplex = vp->mii.force_media;
1602        config = BFINS(config, dev->if_port, 20, 4);
1603        if (vortex_debug > 6)
1604                pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1605        window_write32(vp, config, 3, Wn3_Config);
1606
1607        if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1608                mdio_read(dev, vp->phys[0], MII_BMSR);
1609                mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1610                vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1611                vp->mii.full_duplex = vp->full_duplex;
1612
1613                vortex_check_media(dev, 1);
1614        }
1615        else
1616                vortex_set_duplex(dev);
1617
1618        issue_and_wait(dev, TxReset);
1619        /*
1620         * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1621         */
1622        issue_and_wait(dev, RxReset|0x04);
1623
1624
1625        iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1626
1627        if (vortex_debug > 1) {
1628                pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1629                           dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1630        }
1631
1632        /* Set the station address and mask in window 2 each time opened. */
1633        for (i = 0; i < 6; i++)
1634                window_write8(vp, dev->dev_addr[i], 2, i);
1635        for (; i < 12; i+=2)
1636                window_write16(vp, 0, 2, i);
1637
1638        if (vp->cb_fn_base) {
1639                unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1640                if (vp->drv_flags & INVERT_LED_PWR)
1641                        n |= 0x10;
1642                if (vp->drv_flags & INVERT_MII_PWR)
1643                        n |= 0x4000;
1644                window_write16(vp, n, 2, Wn2_ResetOptions);
1645        }
1646
1647        if (dev->if_port == XCVR_10base2)
1648                /* Start the thinnet transceiver. We should really wait 50ms...*/
1649                iowrite16(StartCoax, ioaddr + EL3_CMD);
1650        if (dev->if_port != XCVR_NWAY) {
1651                window_write16(vp,
1652                               (window_read16(vp, 4, Wn4_Media) &
1653                                ~(Media_10TP|Media_SQE)) |
1654                               media_tbl[dev->if_port].media_bits,
1655                               4, Wn4_Media);
1656        }
1657
1658        /* Switch to the stats window, and clear all stats by reading. */
1659        iowrite16(StatsDisable, ioaddr + EL3_CMD);
1660        for (i = 0; i < 10; i++)
1661                window_read8(vp, 6, i);
1662        window_read16(vp, 6, 10);
1663        window_read16(vp, 6, 12);
1664        /* New: On the Vortex we must also clear the BadSSD counter. */
1665        window_read8(vp, 4, 12);
1666        /* ..and on the Boomerang we enable the extra statistics bits. */
1667        window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1668
1669        if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1670                vp->cur_rx = 0;
1671                /* Initialize the RxEarly register as recommended. */
1672                iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1673                iowrite32(0x0020, ioaddr + PktStatus);
1674                iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1675        }
1676        if (vp->full_bus_master_tx) {           /* Boomerang bus master Tx. */
1677                vp->cur_tx = vp->dirty_tx = 0;
1678                if (vp->drv_flags & IS_BOOMERANG)
1679                        iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1680                /* Clear the Rx, Tx rings. */
1681                for (i = 0; i < RX_RING_SIZE; i++)      /* AKPM: this is done in vortex_open, too */
1682                        vp->rx_ring[i].status = 0;
1683                for (i = 0; i < TX_RING_SIZE; i++)
1684                        vp->tx_skbuff[i] = NULL;
1685                iowrite32(0, ioaddr + DownListPtr);
1686        }
1687        /* Set receiver mode: presumably accept b-case and phys addr only. */
1688        set_rx_mode(dev);
1689        /* enable 802.1q tagged frames */
1690        set_8021q_mode(dev, 1);
1691        iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1692
1693        iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1694        iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1695        /* Allow status bits to be seen. */
1696        vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1697                (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1698                (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1699                (vp->bus_master ? DMADone : 0);
1700        vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1701                (vp->full_bus_master_rx ? 0 : RxComplete) |
1702                StatsFull | HostError | TxComplete | IntReq
1703                | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1704        iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1705        /* Ack all pending events, and set active indicator mask. */
1706        iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1707                 ioaddr + EL3_CMD);
1708        iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1709        if (vp->cb_fn_base)                     /* The PCMCIA people are idiots.  */
1710                iowrite32(0x8000, vp->cb_fn_base + 4);
1711        netif_start_queue (dev);
1712        netdev_reset_queue(dev);
1713err_out:
1714        return err;
1715}
1716
1717static int
1718vortex_open(struct net_device *dev)
1719{
1720        struct vortex_private *vp = netdev_priv(dev);
1721        int i;
1722        int retval;
1723        dma_addr_t dma;
1724
1725        /* Use the now-standard shared IRQ implementation. */
1726        if ((retval = request_irq(dev->irq, vortex_boomerang_interrupt, IRQF_SHARED, dev->name, dev))) {
1727                pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1728                goto err;
1729        }
1730
1731        if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1732                if (vortex_debug > 2)
1733                        pr_debug("%s:  Filling in the Rx ring.\n", dev->name);
1734                for (i = 0; i < RX_RING_SIZE; i++) {
1735                        struct sk_buff *skb;
1736                        vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1737                        vp->rx_ring[i].status = 0;      /* Clear complete bit. */
1738                        vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1739
1740                        skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1741                                                 GFP_KERNEL);
1742                        vp->rx_skbuff[i] = skb;
1743                        if (skb == NULL)
1744                                break;                  /* Bad news!  */
1745
1746                        skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1747                        dma = dma_map_single(vp->gendev, skb->data,
1748                                             PKT_BUF_SZ, DMA_FROM_DEVICE);
1749                        if (dma_mapping_error(vp->gendev, dma))
1750                                break;
1751                        vp->rx_ring[i].addr = cpu_to_le32(dma);
1752                }
1753                if (i != RX_RING_SIZE) {
1754                        pr_emerg("%s: no memory for rx ring\n", dev->name);
1755                        retval = -ENOMEM;
1756                        goto err_free_skb;
1757                }
1758                /* Wrap the ring. */
1759                vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1760        }
1761
1762        retval = vortex_up(dev);
1763        if (!retval)
1764                goto out;
1765
1766err_free_skb:
1767        for (i = 0; i < RX_RING_SIZE; i++) {
1768                if (vp->rx_skbuff[i]) {
1769                        dev_kfree_skb(vp->rx_skbuff[i]);
1770                        vp->rx_skbuff[i] = NULL;
1771                }
1772        }
1773        free_irq(dev->irq, dev);
1774err:
1775        if (vortex_debug > 1)
1776                pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1777out:
1778        return retval;
1779}
1780
1781static void
1782vortex_timer(struct timer_list *t)
1783{
1784        struct vortex_private *vp = from_timer(vp, t, timer);
1785        struct net_device *dev = vp->mii.dev;
1786        void __iomem *ioaddr = vp->ioaddr;
1787        int next_tick = 60*HZ;
1788        int ok = 0;
1789        int media_status;
1790
1791        if (vortex_debug > 2) {
1792                pr_debug("%s: Media selection timer tick happened, %s.\n",
1793                           dev->name, media_tbl[dev->if_port].name);
1794                pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1795        }
1796
1797        media_status = window_read16(vp, 4, Wn4_Media);
1798        switch (dev->if_port) {
1799        case XCVR_10baseT:  case XCVR_100baseTx:  case XCVR_100baseFx:
1800                if (media_status & Media_LnkBeat) {
1801                        netif_carrier_on(dev);
1802                        ok = 1;
1803                        if (vortex_debug > 1)
1804                                pr_debug("%s: Media %s has link beat, %x.\n",
1805                                           dev->name, media_tbl[dev->if_port].name, media_status);
1806                } else {
1807                        netif_carrier_off(dev);
1808                        if (vortex_debug > 1) {
1809                                pr_debug("%s: Media %s has no link beat, %x.\n",
1810                                           dev->name, media_tbl[dev->if_port].name, media_status);
1811                        }
1812                }
1813                break;
1814        case XCVR_MII: case XCVR_NWAY:
1815                {
1816                        ok = 1;
1817                        vortex_check_media(dev, 0);
1818                }
1819                break;
1820          default:                                      /* Other media types handled by Tx timeouts. */
1821                if (vortex_debug > 1)
1822                  pr_debug("%s: Media %s has no indication, %x.\n",
1823                                 dev->name, media_tbl[dev->if_port].name, media_status);
1824                ok = 1;
1825        }
1826
1827        if (dev->flags & IFF_SLAVE || !netif_carrier_ok(dev))
1828                next_tick = 5*HZ;
1829
1830        if (vp->medialock)
1831                goto leave_media_alone;
1832
1833        if (!ok) {
1834                unsigned int config;
1835
1836                spin_lock_irq(&vp->lock);
1837
1838                do {
1839                        dev->if_port = media_tbl[dev->if_port].next;
1840                } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1841                if (dev->if_port == XCVR_Default) { /* Go back to default. */
1842                  dev->if_port = vp->default_media;
1843                  if (vortex_debug > 1)
1844                        pr_debug("%s: Media selection failing, using default %s port.\n",
1845                                   dev->name, media_tbl[dev->if_port].name);
1846                } else {
1847                        if (vortex_debug > 1)
1848                                pr_debug("%s: Media selection failed, now trying %s port.\n",
1849                                           dev->name, media_tbl[dev->if_port].name);
1850                        next_tick = media_tbl[dev->if_port].wait;
1851                }
1852                window_write16(vp,
1853                               (media_status & ~(Media_10TP|Media_SQE)) |
1854                               media_tbl[dev->if_port].media_bits,
1855                               4, Wn4_Media);
1856
1857                config = window_read32(vp, 3, Wn3_Config);
1858                config = BFINS(config, dev->if_port, 20, 4);
1859                window_write32(vp, config, 3, Wn3_Config);
1860
1861                iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1862                         ioaddr + EL3_CMD);
1863                if (vortex_debug > 1)
1864                        pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1865                /* AKPM: FIXME: Should reset Rx & Tx here.  P60 of 3c90xc.pdf */
1866
1867                spin_unlock_irq(&vp->lock);
1868        }
1869
1870leave_media_alone:
1871        if (vortex_debug > 2)
1872          pr_debug("%s: Media selection timer finished, %s.\n",
1873                         dev->name, media_tbl[dev->if_port].name);
1874
1875        mod_timer(&vp->timer, RUN_AT(next_tick));
1876        if (vp->deferred)
1877                iowrite16(FakeIntr, ioaddr + EL3_CMD);
1878}
1879
1880static void vortex_tx_timeout(struct net_device *dev, unsigned int txqueue)
1881{
1882        struct vortex_private *vp = netdev_priv(dev);
1883        void __iomem *ioaddr = vp->ioaddr;
1884
1885        pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1886                   dev->name, ioread8(ioaddr + TxStatus),
1887                   ioread16(ioaddr + EL3_STATUS));
1888        pr_err("  diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1889                        window_read16(vp, 4, Wn4_NetDiag),
1890                        window_read16(vp, 4, Wn4_Media),
1891                        ioread32(ioaddr + PktStatus),
1892                        window_read16(vp, 4, Wn4_FIFODiag));
1893        /* Slight code bloat to be user friendly. */
1894        if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1895                pr_err("%s: Transmitter encountered 16 collisions --"
1896                           " network cable problem?\n", dev->name);
1897        if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1898                pr_err("%s: Interrupt posted but not delivered --"
1899                           " IRQ blocked by another device?\n", dev->name);
1900                /* Bad idea here.. but we might as well handle a few events. */
1901                vortex_boomerang_interrupt(dev->irq, dev);
1902        }
1903
1904        if (vortex_debug > 0)
1905                dump_tx_ring(dev);
1906
1907        issue_and_wait(dev, TxReset);
1908
1909        dev->stats.tx_errors++;
1910        if (vp->full_bus_master_tx) {
1911                pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1912                if (vp->cur_tx - vp->dirty_tx > 0  &&  ioread32(ioaddr + DownListPtr) == 0)
1913                        iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1914                                 ioaddr + DownListPtr);
1915                if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE) {
1916                        netif_wake_queue (dev);
1917                        netdev_reset_queue (dev);
1918                }
1919                if (vp->drv_flags & IS_BOOMERANG)
1920                        iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1921                iowrite16(DownUnstall, ioaddr + EL3_CMD);
1922        } else {
1923                dev->stats.tx_dropped++;
1924                netif_wake_queue(dev);
1925                netdev_reset_queue(dev);
1926        }
1927        /* Issue Tx Enable */
1928        iowrite16(TxEnable, ioaddr + EL3_CMD);
1929        netif_trans_update(dev); /* prevent tx timeout */
1930}
1931
1932/*
1933 * Handle uncommon interrupt sources.  This is a separate routine to minimize
1934 * the cache impact.
1935 */
1936static void
1937vortex_error(struct net_device *dev, int status)
1938{
1939        struct vortex_private *vp = netdev_priv(dev);
1940        void __iomem *ioaddr = vp->ioaddr;
1941        int do_tx_reset = 0, reset_mask = 0;
1942        unsigned char tx_status = 0;
1943
1944        if (vortex_debug > 2) {
1945                pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1946        }
1947
1948        if (status & TxComplete) {                      /* Really "TxError" for us. */
1949                tx_status = ioread8(ioaddr + TxStatus);
1950                /* Presumably a tx-timeout. We must merely re-enable. */
1951                if (vortex_debug > 2 ||
1952                    (tx_status != 0x88 && vortex_debug > 0)) {
1953                        pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1954                                   dev->name, tx_status);
1955                        if (tx_status == 0x82) {
1956                                pr_err("Probably a duplex mismatch.  See "
1957                                                "Documentation/networking/device_drivers/ethernet/3com/vortex.rst\n");
1958                        }
1959                        dump_tx_ring(dev);
1960                }
1961                if (tx_status & 0x14)  dev->stats.tx_fifo_errors++;
1962                if (tx_status & 0x38)  dev->stats.tx_aborted_errors++;
1963                if (tx_status & 0x08)  vp->xstats.tx_max_collisions++;
1964                iowrite8(0, ioaddr + TxStatus);
1965                if (tx_status & 0x30) {                 /* txJabber or txUnderrun */
1966                        do_tx_reset = 1;
1967                } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET))  {      /* maxCollisions */
1968                        do_tx_reset = 1;
1969                        reset_mask = 0x0108;            /* Reset interface logic, but not download logic */
1970                } else {                                /* Merely re-enable the transmitter. */
1971                        iowrite16(TxEnable, ioaddr + EL3_CMD);
1972                }
1973        }
1974
1975        if (status & RxEarly)                           /* Rx early is unused. */
1976                iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1977
1978        if (status & StatsFull) {                       /* Empty statistics. */
1979                static int DoneDidThat;
1980                if (vortex_debug > 4)
1981                        pr_debug("%s: Updating stats.\n", dev->name);
1982                update_stats(ioaddr, dev);
1983                /* HACK: Disable statistics as an interrupt source. */
1984                /* This occurs when we have the wrong media type! */
1985                if (DoneDidThat == 0  &&
1986                        ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1987                        pr_warn("%s: Updating statistics failed, disabling stats as an interrupt source\n",
1988                                dev->name);
1989                        iowrite16(SetIntrEnb |
1990                                  (window_read16(vp, 5, 10) & ~StatsFull),
1991                                  ioaddr + EL3_CMD);
1992                        vp->intr_enable &= ~StatsFull;
1993                        DoneDidThat++;
1994                }
1995        }
1996        if (status & IntReq) {          /* Restore all interrupt sources.  */
1997                iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1998                iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1999        }
2000        if (status & HostError) {
2001                u16 fifo_diag;
2002                fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2003                pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2004                           dev->name, fifo_diag);
2005                /* Adapter failure requires Tx/Rx reset and reinit. */
2006                if (vp->full_bus_master_tx) {
2007                        int bus_status = ioread32(ioaddr + PktStatus);
2008                        /* 0x80000000 PCI master abort. */
2009                        /* 0x40000000 PCI target abort. */
2010                        if (vortex_debug)
2011                                pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2012
2013                        /* In this case, blow the card away */
2014                        /* Must not enter D3 or we can't legally issue the reset! */
2015                        vortex_down(dev, 0);
2016                        issue_and_wait(dev, TotalReset | 0xff);
2017                        vortex_up(dev);         /* AKPM: bug.  vortex_up() assumes that the rx ring is full. It may not be. */
2018                } else if (fifo_diag & 0x0400)
2019                        do_tx_reset = 1;
2020                if (fifo_diag & 0x3000) {
2021                        /* Reset Rx fifo and upload logic */
2022                        issue_and_wait(dev, RxReset|0x07);
2023                        /* Set the Rx filter to the current state. */
2024                        set_rx_mode(dev);
2025                        /* enable 802.1q VLAN tagged frames */
2026                        set_8021q_mode(dev, 1);
2027                        iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2028                        iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2029                }
2030        }
2031
2032        if (do_tx_reset) {
2033                issue_and_wait(dev, TxReset|reset_mask);
2034                iowrite16(TxEnable, ioaddr + EL3_CMD);
2035                if (!vp->full_bus_master_tx)
2036                        netif_wake_queue(dev);
2037        }
2038}
2039
2040static netdev_tx_t
2041vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2042{
2043        struct vortex_private *vp = netdev_priv(dev);
2044        void __iomem *ioaddr = vp->ioaddr;
2045        int skblen = skb->len;
2046
2047        /* Put out the doubleword header... */
2048        iowrite32(skb->len, ioaddr + TX_FIFO);
2049        if (vp->bus_master) {
2050                /* Set the bus-master controller to transfer the packet. */
2051                int len = (skb->len + 3) & ~3;
2052                vp->tx_skb_dma = dma_map_single(vp->gendev, skb->data, len,
2053                                                DMA_TO_DEVICE);
2054                if (dma_mapping_error(vp->gendev, vp->tx_skb_dma)) {
2055                        dev_kfree_skb_any(skb);
2056                        dev->stats.tx_dropped++;
2057                        return NETDEV_TX_OK;
2058                }
2059
2060                spin_lock_irq(&vp->window_lock);
2061                window_set(vp, 7);
2062                iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2063                iowrite16(len, ioaddr + Wn7_MasterLen);
2064                spin_unlock_irq(&vp->window_lock);
2065                vp->tx_skb = skb;
2066                skb_tx_timestamp(skb);
2067                iowrite16(StartDMADown, ioaddr + EL3_CMD);
2068                /* netif_wake_queue() will be called at the DMADone interrupt. */
2069        } else {
2070                /* ... and the packet rounded to a doubleword. */
2071                skb_tx_timestamp(skb);
2072                iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2073                dev_consume_skb_any (skb);
2074                if (ioread16(ioaddr + TxFree) > 1536) {
2075                        netif_start_queue (dev);        /* AKPM: redundant? */
2076                } else {
2077                        /* Interrupt us when the FIFO has room for max-sized packet. */
2078                        netif_stop_queue(dev);
2079                        iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2080                }
2081        }
2082
2083        netdev_sent_queue(dev, skblen);
2084
2085        /* Clear the Tx status stack. */
2086        {
2087                int tx_status;
2088                int i = 32;
2089
2090                while (--i > 0  &&      (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2091                        if (tx_status & 0x3C) {         /* A Tx-disabling error occurred.  */
2092                                if (vortex_debug > 2)
2093                                  pr_debug("%s: Tx error, status %2.2x.\n",
2094                                                 dev->name, tx_status);
2095                                if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2096                                if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2097                                if (tx_status & 0x30) {
2098                                        issue_and_wait(dev, TxReset);
2099                                }
2100                                iowrite16(TxEnable, ioaddr + EL3_CMD);
2101                        }
2102                        iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2103                }
2104        }
2105        return NETDEV_TX_OK;
2106}
2107
2108static netdev_tx_t
2109boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2110{
2111        struct vortex_private *vp = netdev_priv(dev);
2112        void __iomem *ioaddr = vp->ioaddr;
2113        /* Calculate the next Tx descriptor entry. */
2114        int entry = vp->cur_tx % TX_RING_SIZE;
2115        int skblen = skb->len;
2116        struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2117        unsigned long flags;
2118        dma_addr_t dma_addr;
2119
2120        if (vortex_debug > 6) {
2121                pr_debug("boomerang_start_xmit()\n");
2122                pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2123                           dev->name, vp->cur_tx);
2124        }
2125
2126        /*
2127         * We can't allow a recursion from our interrupt handler back into the
2128         * tx routine, as they take the same spin lock, and that causes
2129         * deadlock.  Just return NETDEV_TX_BUSY and let the stack try again in
2130         * a bit
2131         */
2132        if (vp->handling_irq)
2133                return NETDEV_TX_BUSY;
2134
2135        if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2136                if (vortex_debug > 0)
2137                        pr_warn("%s: BUG! Tx Ring full, refusing to send buffer\n",
2138                                dev->name);
2139                netif_stop_queue(dev);
2140                return NETDEV_TX_BUSY;
2141        }
2142
2143        vp->tx_skbuff[entry] = skb;
2144
2145        vp->tx_ring[entry].next = 0;
2146#if DO_ZEROCOPY
2147        if (skb->ip_summed != CHECKSUM_PARTIAL)
2148                        vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2149        else
2150                        vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2151
2152        if (!skb_shinfo(skb)->nr_frags) {
2153                dma_addr = dma_map_single(vp->gendev, skb->data, skb->len,
2154                                          DMA_TO_DEVICE);
2155                if (dma_mapping_error(vp->gendev, dma_addr))
2156                        goto out_dma_err;
2157
2158                vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2159                vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2160        } else {
2161                int i;
2162
2163                dma_addr = dma_map_single(vp->gendev, skb->data,
2164                                          skb_headlen(skb), DMA_TO_DEVICE);
2165                if (dma_mapping_error(vp->gendev, dma_addr))
2166                        goto out_dma_err;
2167
2168                vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2169                vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2170
2171                for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2172                        skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2173
2174                        dma_addr = skb_frag_dma_map(vp->gendev, frag,
2175                                                    0,
2176                                                    skb_frag_size(frag),
2177                                                    DMA_TO_DEVICE);
2178                        if (dma_mapping_error(vp->gendev, dma_addr)) {
2179                                for(i = i-1; i >= 0; i--)
2180                                        dma_unmap_page(vp->gendev,
2181                                                       le32_to_cpu(vp->tx_ring[entry].frag[i+1].addr),
2182                                                       le32_to_cpu(vp->tx_ring[entry].frag[i+1].length),
2183                                                       DMA_TO_DEVICE);
2184
2185                                dma_unmap_single(vp->gendev,
2186                                                 le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
2187                                                 le32_to_cpu(vp->tx_ring[entry].frag[0].length),
2188                                                 DMA_TO_DEVICE);
2189
2190                                goto out_dma_err;
2191                        }
2192
2193                        vp->tx_ring[entry].frag[i+1].addr =
2194                                                cpu_to_le32(dma_addr);
2195
2196                        if (i == skb_shinfo(skb)->nr_frags-1)
2197                                        vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG);
2198                        else
2199                                        vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag));
2200                }
2201        }
2202#else
2203        dma_addr = dma_map_single(vp->gendev, skb->data, skb->len, DMA_TO_DEVICE);
2204        if (dma_mapping_error(vp->gendev, dma_addr))
2205                goto out_dma_err;
2206        vp->tx_ring[entry].addr = cpu_to_le32(dma_addr);
2207        vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2208        vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2209#endif
2210
2211        spin_lock_irqsave(&vp->lock, flags);
2212        /* Wait for the stall to complete. */
2213        issue_and_wait(dev, DownStall);
2214        prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2215        if (ioread32(ioaddr + DownListPtr) == 0) {
2216                iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2217                vp->queued_packet++;
2218        }
2219
2220        vp->cur_tx++;
2221        netdev_sent_queue(dev, skblen);
2222
2223        if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2224                netif_stop_queue (dev);
2225        } else {                                        /* Clear previous interrupt enable. */
2226#if defined(tx_interrupt_mitigation)
2227                /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2228                 * were selected, this would corrupt DN_COMPLETE. No?
2229                 */
2230                prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2231#endif
2232        }
2233        skb_tx_timestamp(skb);
2234        iowrite16(DownUnstall, ioaddr + EL3_CMD);
2235        spin_unlock_irqrestore(&vp->lock, flags);
2236out:
2237        return NETDEV_TX_OK;
2238out_dma_err:
2239        dev_err(vp->gendev, "Error mapping dma buffer\n");
2240        goto out;
2241}
2242
2243/* The interrupt handler does all of the Rx thread work and cleans up
2244   after the Tx thread. */
2245
2246/*
2247 * This is the ISR for the vortex series chips.
2248 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2249 */
2250
2251static irqreturn_t
2252_vortex_interrupt(int irq, struct net_device *dev)
2253{
2254        struct vortex_private *vp = netdev_priv(dev);
2255        void __iomem *ioaddr;
2256        int status;
2257        int work_done = max_interrupt_work;
2258        int handled = 0;
2259        unsigned int bytes_compl = 0, pkts_compl = 0;
2260
2261        ioaddr = vp->ioaddr;
2262
2263        status = ioread16(ioaddr + EL3_STATUS);
2264
2265        if (vortex_debug > 6)
2266                pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2267
2268        if ((status & IntLatch) == 0)
2269                goto handler_exit;              /* No interrupt: shared IRQs cause this */
2270        handled = 1;
2271
2272        if (status & IntReq) {
2273                status |= vp->deferred;
2274                vp->deferred = 0;
2275        }
2276
2277        if (status == 0xffff)           /* h/w no longer present (hotplug)? */
2278                goto handler_exit;
2279
2280        if (vortex_debug > 4)
2281                pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2282                           dev->name, status, ioread8(ioaddr + Timer));
2283
2284        spin_lock(&vp->window_lock);
2285        window_set(vp, 7);
2286
2287        do {
2288                if (vortex_debug > 5)
2289                                pr_debug("%s: In interrupt loop, status %4.4x.\n",
2290                                           dev->name, status);
2291                if (status & RxComplete)
2292                        vortex_rx(dev);
2293
2294                if (status & TxAvailable) {
2295                        if (vortex_debug > 5)
2296                                pr_debug("      TX room bit was handled.\n");
2297                        /* There's room in the FIFO for a full-sized packet. */
2298                        iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2299                        netif_wake_queue (dev);
2300                }
2301
2302                if (status & DMADone) {
2303                        if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2304                                iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2305                                dma_unmap_single(vp->gendev, vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, DMA_TO_DEVICE);
2306                                pkts_compl++;
2307                                bytes_compl += vp->tx_skb->len;
2308                                dev_consume_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2309                                if (ioread16(ioaddr + TxFree) > 1536) {
2310                                        /*
2311                                         * AKPM: FIXME: I don't think we need this.  If the queue was stopped due to
2312                                         * insufficient FIFO room, the TxAvailable test will succeed and call
2313                                         * netif_wake_queue()
2314                                         */
2315                                        netif_wake_queue(dev);
2316                                } else { /* Interrupt when FIFO has room for max-sized packet. */
2317                                        iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2318                                        netif_stop_queue(dev);
2319                                }
2320                        }
2321                }
2322                /* Check for all uncommon interrupts at once. */
2323                if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2324                        if (status == 0xffff)
2325                                break;
2326                        if (status & RxEarly)
2327                                vortex_rx(dev);
2328                        spin_unlock(&vp->window_lock);
2329                        vortex_error(dev, status);
2330                        spin_lock(&vp->window_lock);
2331                        window_set(vp, 7);
2332                }
2333
2334                if (--work_done < 0) {
2335                        pr_warn("%s: Too much work in interrupt, status %4.4x\n",
2336                                dev->name, status);
2337                        /* Disable all pending interrupts. */
2338                        do {
2339                                vp->deferred |= status;
2340                                iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2341                                         ioaddr + EL3_CMD);
2342                                iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2343                        } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2344                        /* The timer will reenable interrupts. */
2345                        mod_timer(&vp->timer, jiffies + 1*HZ);
2346                        break;
2347                }
2348                /* Acknowledge the IRQ. */
2349                iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2350        } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2351
2352        netdev_completed_queue(dev, pkts_compl, bytes_compl);
2353        spin_unlock(&vp->window_lock);
2354
2355        if (vortex_debug > 4)
2356                pr_debug("%s: exiting interrupt, status %4.4x.\n",
2357                           dev->name, status);
2358handler_exit:
2359        return IRQ_RETVAL(handled);
2360}
2361
2362/*
2363 * This is the ISR for the boomerang series chips.
2364 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2365 */
2366
2367static irqreturn_t
2368_boomerang_interrupt(int irq, struct net_device *dev)
2369{
2370        struct vortex_private *vp = netdev_priv(dev);
2371        void __iomem *ioaddr;
2372        int status;
2373        int work_done = max_interrupt_work;
2374        int handled = 0;
2375        unsigned int bytes_compl = 0, pkts_compl = 0;
2376
2377        ioaddr = vp->ioaddr;
2378
2379        vp->handling_irq = 1;
2380
2381        status = ioread16(ioaddr + EL3_STATUS);
2382
2383        if (vortex_debug > 6)
2384                pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2385
2386        if ((status & IntLatch) == 0)
2387                goto handler_exit;              /* No interrupt: shared IRQs can cause this */
2388        handled = 1;
2389
2390        if (status == 0xffff) {         /* h/w no longer present (hotplug)? */
2391                if (vortex_debug > 1)
2392                        pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2393                goto handler_exit;
2394        }
2395
2396        if (status & IntReq) {
2397                status |= vp->deferred;
2398                vp->deferred = 0;
2399        }
2400
2401        if (vortex_debug > 4)
2402                pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2403                           dev->name, status, ioread8(ioaddr + Timer));
2404        do {
2405                if (vortex_debug > 5)
2406                                pr_debug("%s: In interrupt loop, status %4.4x.\n",
2407                                           dev->name, status);
2408                if (status & UpComplete) {
2409                        iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2410                        if (vortex_debug > 5)
2411                                pr_debug("boomerang_interrupt->boomerang_rx\n");
2412                        boomerang_rx(dev);
2413                }
2414
2415                if (status & DownComplete) {
2416                        unsigned int dirty_tx = vp->dirty_tx;
2417
2418                        iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2419                        while (vp->cur_tx - dirty_tx > 0) {
2420                                int entry = dirty_tx % TX_RING_SIZE;
2421#if 1   /* AKPM: the latter is faster, but cyclone-only */
2422                                if (ioread32(ioaddr + DownListPtr) ==
2423                                        vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2424                                        break;                  /* It still hasn't been processed. */
2425#else
2426                                if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2427                                        break;                  /* It still hasn't been processed. */
2428#endif
2429
2430                                if (vp->tx_skbuff[entry]) {
2431                                        struct sk_buff *skb = vp->tx_skbuff[entry];
2432#if DO_ZEROCOPY
2433                                        int i;
2434                                        dma_unmap_single(vp->gendev,
2435                                                        le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
2436                                                        le32_to_cpu(vp->tx_ring[entry].frag[0].length)&0xFFF,
2437                                                        DMA_TO_DEVICE);
2438
2439                                        for (i=1; i<=skb_shinfo(skb)->nr_frags; i++)
2440                                                        dma_unmap_page(vp->gendev,
2441                                                                                         le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2442                                                                                         le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2443                                                                                         DMA_TO_DEVICE);
2444#else
2445                                        dma_unmap_single(vp->gendev,
2446                                                le32_to_cpu(vp->tx_ring[entry].addr), skb->len, DMA_TO_DEVICE);
2447#endif
2448                                        pkts_compl++;
2449                                        bytes_compl += skb->len;
2450                                        dev_consume_skb_irq(skb);
2451                                        vp->tx_skbuff[entry] = NULL;
2452                                } else {
2453                                        pr_debug("boomerang_interrupt: no skb!\n");
2454                                }
2455                                /* dev->stats.tx_packets++;  Counted below. */
2456                                dirty_tx++;
2457                        }
2458                        vp->dirty_tx = dirty_tx;
2459                        if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2460                                if (vortex_debug > 6)
2461                                        pr_debug("boomerang_interrupt: wake queue\n");
2462                                netif_wake_queue (dev);
2463                        }
2464                }
2465
2466                /* Check for all uncommon interrupts at once. */
2467                if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2468                        vortex_error(dev, status);
2469
2470                if (--work_done < 0) {
2471                        pr_warn("%s: Too much work in interrupt, status %4.4x\n",
2472                                dev->name, status);
2473                        /* Disable all pending interrupts. */
2474                        do {
2475                                vp->deferred |= status;
2476                                iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2477                                         ioaddr + EL3_CMD);
2478                                iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2479                        } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2480                        /* The timer will reenable interrupts. */
2481                        mod_timer(&vp->timer, jiffies + 1*HZ);
2482                        break;
2483                }
2484                /* Acknowledge the IRQ. */
2485                iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2486                if (vp->cb_fn_base)                     /* The PCMCIA people are idiots.  */
2487                        iowrite32(0x8000, vp->cb_fn_base + 4);
2488
2489        } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2490        netdev_completed_queue(dev, pkts_compl, bytes_compl);
2491
2492        if (vortex_debug > 4)
2493                pr_debug("%s: exiting interrupt, status %4.4x.\n",
2494                           dev->name, status);
2495handler_exit:
2496        vp->handling_irq = 0;
2497        return IRQ_RETVAL(handled);
2498}
2499
2500static irqreturn_t
2501vortex_boomerang_interrupt(int irq, void *dev_id)
2502{
2503        struct net_device *dev = dev_id;
2504        struct vortex_private *vp = netdev_priv(dev);
2505        unsigned long flags;
2506        irqreturn_t ret;
2507
2508        spin_lock_irqsave(&vp->lock, flags);
2509
2510        if (vp->full_bus_master_rx)
2511                ret = _boomerang_interrupt(dev->irq, dev);
2512        else
2513                ret = _vortex_interrupt(dev->irq, dev);
2514
2515        spin_unlock_irqrestore(&vp->lock, flags);
2516
2517        return ret;
2518}
2519
2520static int vortex_rx(struct net_device *dev)
2521{
2522        struct vortex_private *vp = netdev_priv(dev);
2523        void __iomem *ioaddr = vp->ioaddr;
2524        int i;
2525        short rx_status;
2526
2527        if (vortex_debug > 5)
2528                pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2529                           ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2530        while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2531                if (rx_status & 0x4000) { /* Error, update stats. */
2532                        unsigned char rx_error = ioread8(ioaddr + RxErrors);
2533                        if (vortex_debug > 2)
2534                                pr_debug(" Rx error: status %2.2x.\n", rx_error);
2535                        dev->stats.rx_errors++;
2536                        if (rx_error & 0x01)  dev->stats.rx_over_errors++;
2537                        if (rx_error & 0x02)  dev->stats.rx_length_errors++;
2538                        if (rx_error & 0x04)  dev->stats.rx_frame_errors++;
2539                        if (rx_error & 0x08)  dev->stats.rx_crc_errors++;
2540                        if (rx_error & 0x10)  dev->stats.rx_length_errors++;
2541                } else {
2542                        /* The packet length: up to 4.5K!. */
2543                        int pkt_len = rx_status & 0x1fff;
2544                        struct sk_buff *skb;
2545
2546                        skb = netdev_alloc_skb(dev, pkt_len + 5);
2547                        if (vortex_debug > 4)
2548                                pr_debug("Receiving packet size %d status %4.4x.\n",
2549                                           pkt_len, rx_status);
2550                        if (skb != NULL) {
2551                                skb_reserve(skb, 2);    /* Align IP on 16 byte boundaries */
2552                                /* 'skb_put()' points to the start of sk_buff data area. */
2553                                if (vp->bus_master &&
2554                                        ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2555                                        dma_addr_t dma = dma_map_single(vp->gendev, skb_put(skb, pkt_len),
2556                                                                           pkt_len, DMA_FROM_DEVICE);
2557                                        iowrite32(dma, ioaddr + Wn7_MasterAddr);
2558                                        iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2559                                        iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2560                                        while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2561                                                ;
2562                                        dma_unmap_single(vp->gendev, dma, pkt_len, DMA_FROM_DEVICE);
2563                                } else {
2564                                        ioread32_rep(ioaddr + RX_FIFO,
2565                                                     skb_put(skb, pkt_len),
2566                                                     (pkt_len + 3) >> 2);
2567                                }
2568                                iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2569                                skb->protocol = eth_type_trans(skb, dev);
2570                                netif_rx(skb);
2571                                dev->stats.rx_packets++;
2572                                /* Wait a limited time to go to next packet. */
2573                                for (i = 200; i >= 0; i--)
2574                                        if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2575                                                break;
2576                                continue;
2577                        } else if (vortex_debug > 0)
2578                                pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2579                                        dev->name, pkt_len);
2580                        dev->stats.rx_dropped++;
2581                }
2582                issue_and_wait(dev, RxDiscard);
2583        }
2584
2585        return 0;
2586}
2587
2588static int
2589boomerang_rx(struct net_device *dev)
2590{
2591        struct vortex_private *vp = netdev_priv(dev);
2592        int entry = vp->cur_rx % RX_RING_SIZE;
2593        void __iomem *ioaddr = vp->ioaddr;
2594        int rx_status;
2595        int rx_work_limit = RX_RING_SIZE;
2596
2597        if (vortex_debug > 5)
2598                pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2599
2600        while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2601                if (--rx_work_limit < 0)
2602                        break;
2603                if (rx_status & RxDError) { /* Error, update stats. */
2604                        unsigned char rx_error = rx_status >> 16;
2605                        if (vortex_debug > 2)
2606                                pr_debug(" Rx error: status %2.2x.\n", rx_error);
2607                        dev->stats.rx_errors++;
2608                        if (rx_error & 0x01)  dev->stats.rx_over_errors++;
2609                        if (rx_error & 0x02)  dev->stats.rx_length_errors++;
2610                        if (rx_error & 0x04)  dev->stats.rx_frame_errors++;
2611                        if (rx_error & 0x08)  dev->stats.rx_crc_errors++;
2612                        if (rx_error & 0x10)  dev->stats.rx_length_errors++;
2613                } else {
2614                        /* The packet length: up to 4.5K!. */
2615                        int pkt_len = rx_status & 0x1fff;
2616                        struct sk_buff *skb, *newskb;
2617                        dma_addr_t newdma;
2618                        dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2619
2620                        if (vortex_debug > 4)
2621                                pr_debug("Receiving packet size %d status %4.4x.\n",
2622                                           pkt_len, rx_status);
2623
2624                        /* Check if the packet is long enough to just accept without
2625                           copying to a properly sized skbuff. */
2626                        if (pkt_len < rx_copybreak &&
2627                            (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
2628                                skb_reserve(skb, 2);    /* Align IP on 16 byte boundaries */
2629                                dma_sync_single_for_cpu(vp->gendev, dma, PKT_BUF_SZ, DMA_FROM_DEVICE);
2630                                /* 'skb_put()' points to the start of sk_buff data area. */
2631                                skb_put_data(skb, vp->rx_skbuff[entry]->data,
2632                                             pkt_len);
2633                                dma_sync_single_for_device(vp->gendev, dma, PKT_BUF_SZ, DMA_FROM_DEVICE);
2634                                vp->rx_copy++;
2635                        } else {
2636                                /* Pre-allocate the replacement skb.  If it or its
2637                                 * mapping fails then recycle the buffer thats already
2638                                 * in place
2639                                 */
2640                                newskb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2641                                if (!newskb) {
2642                                        dev->stats.rx_dropped++;
2643                                        goto clear_complete;
2644                                }
2645                                newdma = dma_map_single(vp->gendev, newskb->data,
2646                                                        PKT_BUF_SZ, DMA_FROM_DEVICE);
2647                                if (dma_mapping_error(vp->gendev, newdma)) {
2648                                        dev->stats.rx_dropped++;
2649                                        consume_skb(newskb);
2650                                        goto clear_complete;
2651                                }
2652
2653                                /* Pass up the skbuff already on the Rx ring. */
2654                                skb = vp->rx_skbuff[entry];
2655                                vp->rx_skbuff[entry] = newskb;
2656                                vp->rx_ring[entry].addr = cpu_to_le32(newdma);
2657                                skb_put(skb, pkt_len);
2658                                dma_unmap_single(vp->gendev, dma, PKT_BUF_SZ, DMA_FROM_DEVICE);
2659                                vp->rx_nocopy++;
2660                        }
2661                        skb->protocol = eth_type_trans(skb, dev);
2662                        {                                       /* Use hardware checksum info. */
2663                                int csum_bits = rx_status & 0xee000000;
2664                                if (csum_bits &&
2665                                        (csum_bits == (IPChksumValid | TCPChksumValid) ||
2666                                         csum_bits == (IPChksumValid | UDPChksumValid))) {
2667                                        skb->ip_summed = CHECKSUM_UNNECESSARY;
2668                                        vp->rx_csumhits++;
2669                                }
2670                        }
2671                        netif_rx(skb);
2672                        dev->stats.rx_packets++;
2673                }
2674
2675clear_complete:
2676                vp->rx_ring[entry].status = 0;  /* Clear complete bit. */
2677                iowrite16(UpUnstall, ioaddr + EL3_CMD);
2678                entry = (++vp->cur_rx) % RX_RING_SIZE;
2679        }
2680        return 0;
2681}
2682
2683static void
2684vortex_down(struct net_device *dev, int final_down)
2685{
2686        struct vortex_private *vp = netdev_priv(dev);
2687        void __iomem *ioaddr = vp->ioaddr;
2688
2689        netdev_reset_queue(dev);
2690        netif_stop_queue(dev);
2691
2692        del_timer_sync(&vp->timer);
2693
2694        /* Turn off statistics ASAP.  We update dev->stats below. */
2695        iowrite16(StatsDisable, ioaddr + EL3_CMD);
2696
2697        /* Disable the receiver and transmitter. */
2698        iowrite16(RxDisable, ioaddr + EL3_CMD);
2699        iowrite16(TxDisable, ioaddr + EL3_CMD);
2700
2701        /* Disable receiving 802.1q tagged frames */
2702        set_8021q_mode(dev, 0);
2703
2704        if (dev->if_port == XCVR_10base2)
2705                /* Turn off thinnet power.  Green! */
2706                iowrite16(StopCoax, ioaddr + EL3_CMD);
2707
2708        iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2709
2710        update_stats(ioaddr, dev);
2711        if (vp->full_bus_master_rx)
2712                iowrite32(0, ioaddr + UpListPtr);
2713        if (vp->full_bus_master_tx)
2714                iowrite32(0, ioaddr + DownListPtr);
2715
2716        if (final_down && VORTEX_PCI(vp)) {
2717                vp->pm_state_valid = 1;
2718                pci_save_state(VORTEX_PCI(vp));
2719                acpi_set_WOL(dev);
2720        }
2721}
2722
2723static int
2724vortex_close(struct net_device *dev)
2725{
2726        struct vortex_private *vp = netdev_priv(dev);
2727        void __iomem *ioaddr = vp->ioaddr;
2728        int i;
2729
2730        if (netif_device_present(dev))
2731                vortex_down(dev, 1);
2732
2733        if (vortex_debug > 1) {
2734                pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2735                           dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2736                pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2737                           " tx_queued %d Rx pre-checksummed %d.\n",
2738                           dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2739        }
2740
2741#if DO_ZEROCOPY
2742        if (vp->rx_csumhits &&
2743            (vp->drv_flags & HAS_HWCKSM) == 0 &&
2744            (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2745                pr_warn("%s supports hardware checksums, and we're not using them!\n",
2746                        dev->name);
2747        }
2748#endif
2749
2750        free_irq(dev->irq, dev);
2751
2752        if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2753                for (i = 0; i < RX_RING_SIZE; i++)
2754                        if (vp->rx_skbuff[i]) {
2755                                dma_unmap_single(vp->gendev, le32_to_cpu(vp->rx_ring[i].addr),
2756                                                                        PKT_BUF_SZ, DMA_FROM_DEVICE);
2757                                dev_kfree_skb(vp->rx_skbuff[i]);
2758                                vp->rx_skbuff[i] = NULL;
2759                        }
2760        }
2761        if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2762                for (i = 0; i < TX_RING_SIZE; i++) {
2763                        if (vp->tx_skbuff[i]) {
2764                                struct sk_buff *skb = vp->tx_skbuff[i];
2765#if DO_ZEROCOPY
2766                                int k;
2767
2768                                for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2769                                                dma_unmap_single(vp->gendev,
2770                                                                                 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2771                                                                                 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2772                                                                                 DMA_TO_DEVICE);
2773#else
2774                                dma_unmap_single(vp->gendev, le32_to_cpu(vp->tx_ring[i].addr), skb->len, DMA_TO_DEVICE);
2775#endif
2776                                dev_kfree_skb(skb);
2777                                vp->tx_skbuff[i] = NULL;
2778                        }
2779                }
2780        }
2781
2782        return 0;
2783}
2784
2785static void
2786dump_tx_ring(struct net_device *dev)
2787{
2788        if (vortex_debug > 0) {
2789        struct vortex_private *vp = netdev_priv(dev);
2790                void __iomem *ioaddr = vp->ioaddr;
2791
2792                if (vp->full_bus_master_tx) {
2793                        int i;
2794                        int stalled = ioread32(ioaddr + PktStatus) & 0x04;      /* Possible racy. But it's only debug stuff */
2795
2796                        pr_err("  Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2797                                        vp->full_bus_master_tx,
2798                                        vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2799                                        vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2800                        pr_err("  Transmit list %8.8x vs. %p.\n",
2801                                   ioread32(ioaddr + DownListPtr),
2802                                   &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2803                        issue_and_wait(dev, DownStall);
2804                        for (i = 0; i < TX_RING_SIZE; i++) {
2805                                unsigned int length;
2806
2807#if DO_ZEROCOPY
2808                                length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2809#else
2810                                length = le32_to_cpu(vp->tx_ring[i].length);
2811#endif
2812                                pr_err("  %d: @%p  length %8.8x status %8.8x\n",
2813                                           i, &vp->tx_ring[i], length,
2814                                           le32_to_cpu(vp->tx_ring[i].status));
2815                        }
2816                        if (!stalled)
2817                                iowrite16(DownUnstall, ioaddr + EL3_CMD);
2818                }
2819        }
2820}
2821
2822static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2823{
2824        struct vortex_private *vp = netdev_priv(dev);
2825        void __iomem *ioaddr = vp->ioaddr;
2826        unsigned long flags;
2827
2828        if (netif_device_present(dev)) {        /* AKPM: Used to be netif_running */
2829                spin_lock_irqsave (&vp->lock, flags);
2830                update_stats(ioaddr, dev);
2831                spin_unlock_irqrestore (&vp->lock, flags);
2832        }
2833        return &dev->stats;
2834}
2835
2836/*  Update statistics.
2837        Unlike with the EL3 we need not worry about interrupts changing
2838        the window setting from underneath us, but we must still guard
2839        against a race condition with a StatsUpdate interrupt updating the
2840        table.  This is done by checking that the ASM (!) code generated uses
2841        atomic updates with '+='.
2842        */
2843static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2844{
2845        struct vortex_private *vp = netdev_priv(dev);
2846
2847        /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2848        /* Switch to the stats window, and read everything. */
2849        dev->stats.tx_carrier_errors            += window_read8(vp, 6, 0);
2850        dev->stats.tx_heartbeat_errors          += window_read8(vp, 6, 1);
2851        dev->stats.tx_window_errors             += window_read8(vp, 6, 4);
2852        dev->stats.rx_fifo_errors               += window_read8(vp, 6, 5);
2853        dev->stats.tx_packets                   += window_read8(vp, 6, 6);
2854        dev->stats.tx_packets                   += (window_read8(vp, 6, 9) &
2855                                                    0x30) << 4;
2856        /* Rx packets   */                      window_read8(vp, 6, 7);   /* Must read to clear */
2857        /* Don't bother with register 9, an extension of registers 6&7.
2858           If we do use the 6&7 values the atomic update assumption above
2859           is invalid. */
2860        dev->stats.rx_bytes                     += window_read16(vp, 6, 10);
2861        dev->stats.tx_bytes                     += window_read16(vp, 6, 12);
2862        /* Extra stats for get_ethtool_stats() */
2863        vp->xstats.tx_multiple_collisions       += window_read8(vp, 6, 2);
2864        vp->xstats.tx_single_collisions         += window_read8(vp, 6, 3);
2865        vp->xstats.tx_deferred                  += window_read8(vp, 6, 8);
2866        vp->xstats.rx_bad_ssd                   += window_read8(vp, 4, 12);
2867
2868        dev->stats.collisions = vp->xstats.tx_multiple_collisions
2869                + vp->xstats.tx_single_collisions
2870                + vp->xstats.tx_max_collisions;
2871
2872        {
2873                u8 up = window_read8(vp, 4, 13);
2874                dev->stats.rx_bytes += (up & 0x0f) << 16;
2875                dev->stats.tx_bytes += (up & 0xf0) << 12;
2876        }
2877}
2878
2879static int vortex_nway_reset(struct net_device *dev)
2880{
2881        struct vortex_private *vp = netdev_priv(dev);
2882
2883        return mii_nway_restart(&vp->mii);
2884}
2885
2886static int vortex_get_link_ksettings(struct net_device *dev,
2887                                     struct ethtool_link_ksettings *cmd)
2888{
2889        struct vortex_private *vp = netdev_priv(dev);
2890
2891        mii_ethtool_get_link_ksettings(&vp->mii, cmd);
2892
2893        return 0;
2894}
2895
2896static int vortex_set_link_ksettings(struct net_device *dev,
2897                                     const struct ethtool_link_ksettings *cmd)
2898{
2899        struct vortex_private *vp = netdev_priv(dev);
2900
2901        return mii_ethtool_set_link_ksettings(&vp->mii, cmd);
2902}
2903
2904static u32 vortex_get_msglevel(struct net_device *dev)
2905{
2906        return vortex_debug;
2907}
2908
2909static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2910{
2911        vortex_debug = dbg;
2912}
2913
2914static int vortex_get_sset_count(struct net_device *dev, int sset)
2915{
2916        switch (sset) {
2917        case ETH_SS_STATS:
2918                return VORTEX_NUM_STATS;
2919        default:
2920                return -EOPNOTSUPP;
2921        }
2922}
2923
2924static void vortex_get_ethtool_stats(struct net_device *dev,
2925        struct ethtool_stats *stats, u64 *data)
2926{
2927        struct vortex_private *vp = netdev_priv(dev);
2928        void __iomem *ioaddr = vp->ioaddr;
2929        unsigned long flags;
2930
2931        spin_lock_irqsave(&vp->lock, flags);
2932        update_stats(ioaddr, dev);
2933        spin_unlock_irqrestore(&vp->lock, flags);
2934
2935        data[0] = vp->xstats.tx_deferred;
2936        data[1] = vp->xstats.tx_max_collisions;
2937        data[2] = vp->xstats.tx_multiple_collisions;
2938        data[3] = vp->xstats.tx_single_collisions;
2939        data[4] = vp->xstats.rx_bad_ssd;
2940}
2941
2942
2943static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2944{
2945        switch (stringset) {
2946        case ETH_SS_STATS:
2947                memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2948                break;
2949        default:
2950                WARN_ON(1);
2951                break;
2952        }
2953}
2954
2955static void vortex_get_drvinfo(struct net_device *dev,
2956                                        struct ethtool_drvinfo *info)
2957{
2958        struct vortex_private *vp = netdev_priv(dev);
2959
2960        strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2961        if (VORTEX_PCI(vp)) {
2962                strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)),
2963                        sizeof(info->bus_info));
2964        } else {
2965                if (VORTEX_EISA(vp))
2966                        strlcpy(info->bus_info, dev_name(vp->gendev),
2967                                sizeof(info->bus_info));
2968                else
2969                        snprintf(info->bus_info, sizeof(info->bus_info),
2970                                "EISA 0x%lx %d", dev->base_addr, dev->irq);
2971        }
2972}
2973
2974static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2975{
2976        struct vortex_private *vp = netdev_priv(dev);
2977
2978        if (!VORTEX_PCI(vp))
2979                return;
2980
2981        wol->supported = WAKE_MAGIC;
2982
2983        wol->wolopts = 0;
2984        if (vp->enable_wol)
2985                wol->wolopts |= WAKE_MAGIC;
2986}
2987
2988static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2989{
2990        struct vortex_private *vp = netdev_priv(dev);
2991
2992        if (!VORTEX_PCI(vp))
2993                return -EOPNOTSUPP;
2994
2995        if (wol->wolopts & ~WAKE_MAGIC)
2996                return -EINVAL;
2997
2998        if (wol->wolopts & WAKE_MAGIC)
2999                vp->enable_wol = 1;
3000        else
3001                vp->enable_wol = 0;
3002        acpi_set_WOL(dev);
3003
3004        return 0;
3005}
3006
3007static const struct ethtool_ops vortex_ethtool_ops = {
3008        .get_drvinfo            = vortex_get_drvinfo,
3009        .get_strings            = vortex_get_strings,
3010        .get_msglevel           = vortex_get_msglevel,
3011        .set_msglevel           = vortex_set_msglevel,
3012        .get_ethtool_stats      = vortex_get_ethtool_stats,
3013        .get_sset_count         = vortex_get_sset_count,
3014        .get_link               = ethtool_op_get_link,
3015        .nway_reset             = vortex_nway_reset,
3016        .get_wol                = vortex_get_wol,
3017        .set_wol                = vortex_set_wol,
3018        .get_ts_info            = ethtool_op_get_ts_info,
3019        .get_link_ksettings     = vortex_get_link_ksettings,
3020        .set_link_ksettings     = vortex_set_link_ksettings,
3021};
3022
3023#ifdef CONFIG_PCI
3024/*
3025 *      Must power the device up to do MDIO operations
3026 */
3027static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3028{
3029        int err;
3030        struct vortex_private *vp = netdev_priv(dev);
3031        pci_power_t state = 0;
3032
3033        if(VORTEX_PCI(vp))
3034                state = VORTEX_PCI(vp)->current_state;
3035
3036        /* The kernel core really should have pci_get_power_state() */
3037
3038        if(state != 0)
3039                pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3040        err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3041        if(state != 0)
3042                pci_set_power_state(VORTEX_PCI(vp), state);
3043
3044        return err;
3045}
3046#endif
3047
3048
3049/* Pre-Cyclone chips have no documented multicast filter, so the only
3050   multicast setting is to receive all multicast frames.  At least
3051   the chip has a very clean way to set the mode, unlike many others. */
3052static void set_rx_mode(struct net_device *dev)
3053{
3054        struct vortex_private *vp = netdev_priv(dev);
3055        void __iomem *ioaddr = vp->ioaddr;
3056        int new_mode;
3057
3058        if (dev->flags & IFF_PROMISC) {
3059                if (vortex_debug > 3)
3060                        pr_notice("%s: Setting promiscuous mode.\n", dev->name);
3061                new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3062        } else  if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
3063                new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3064        } else
3065                new_mode = SetRxFilter | RxStation | RxBroadcast;
3066
3067        iowrite16(new_mode, ioaddr + EL3_CMD);
3068}
3069
3070#if IS_ENABLED(CONFIG_VLAN_8021Q)
3071/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3072   Note that this must be done after each RxReset due to some backwards
3073   compatibility logic in the Cyclone and Tornado ASICs */
3074
3075/* The Ethernet Type used for 802.1q tagged frames */
3076#define VLAN_ETHER_TYPE 0x8100
3077
3078static void set_8021q_mode(struct net_device *dev, int enable)
3079{
3080        struct vortex_private *vp = netdev_priv(dev);
3081        int mac_ctrl;
3082
3083        if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3084                /* cyclone and tornado chipsets can recognize 802.1q
3085                 * tagged frames and treat them correctly */
3086
3087                int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3088                if (enable)
3089                        max_pkt_size += 4;      /* 802.1Q VLAN tag */
3090
3091                window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3092
3093                /* set VlanEtherType to let the hardware checksumming
3094                   treat tagged frames correctly */
3095                window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3096        } else {
3097                /* on older cards we have to enable large frames */
3098
3099                vp->large_frames = dev->mtu > 1500 || enable;
3100
3101                mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3102                if (vp->large_frames)
3103                        mac_ctrl |= 0x40;
3104                else
3105                        mac_ctrl &= ~0x40;
3106                window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3107        }
3108}
3109#else
3110
3111static void set_8021q_mode(struct net_device *dev, int enable)
3112{
3113}
3114
3115
3116#endif
3117
3118/* MII transceiver control section.
3119   Read and write the MII registers using software-generated serial
3120   MDIO protocol.  See the MII specifications or DP83840A data sheet
3121   for details. */
3122
3123/* The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
3124   met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3125   "overclocking" issues. */
3126static void mdio_delay(struct vortex_private *vp)
3127{
3128        window_read32(vp, 4, Wn4_PhysicalMgmt);
3129}
3130
3131#define MDIO_SHIFT_CLK  0x01
3132#define MDIO_DIR_WRITE  0x04
3133#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3134#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3135#define MDIO_DATA_READ  0x02
3136#define MDIO_ENB_IN             0x00
3137
3138/* Generate the preamble required for initial synchronization and
3139   a few older transceivers. */
3140static void mdio_sync(struct vortex_private *vp, int bits)
3141{
3142        /* Establish sync by sending at least 32 logic ones. */
3143        while (-- bits >= 0) {
3144                window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3145                mdio_delay(vp);
3146                window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3147                               4, Wn4_PhysicalMgmt);
3148                mdio_delay(vp);
3149        }
3150}
3151
3152static int mdio_read(struct net_device *dev, int phy_id, int location)
3153{
3154        int i;
3155        struct vortex_private *vp = netdev_priv(dev);
3156        int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3157        unsigned int retval = 0;
3158
3159        spin_lock_bh(&vp->mii_lock);
3160
3161        if (mii_preamble_required)
3162                mdio_sync(vp, 32);
3163
3164        /* Shift the read command bits out. */
3165        for (i = 14; i >= 0; i--) {
3166                int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3167                window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3168                mdio_delay(vp);
3169                window_write16(vp, dataval | MDIO_SHIFT_CLK,
3170                               4, Wn4_PhysicalMgmt);
3171                mdio_delay(vp);
3172        }
3173        /* Read the two transition, 16 data, and wire-idle bits. */
3174        for (i = 19; i > 0; i--) {
3175                window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3176                mdio_delay(vp);
3177                retval = (retval << 1) |
3178                        ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3179                          MDIO_DATA_READ) ? 1 : 0);
3180                window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3181                               4, Wn4_PhysicalMgmt);
3182                mdio_delay(vp);
3183        }
3184
3185        spin_unlock_bh(&vp->mii_lock);
3186
3187        return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3188}
3189
3190static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3191{
3192        struct vortex_private *vp = netdev_priv(dev);
3193        int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3194        int i;
3195
3196        spin_lock_bh(&vp->mii_lock);
3197
3198        if (mii_preamble_required)
3199                mdio_sync(vp, 32);
3200
3201        /* Shift the command bits out. */
3202        for (i = 31; i >= 0; i--) {
3203                int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3204                window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3205                mdio_delay(vp);
3206                window_write16(vp, dataval | MDIO_SHIFT_CLK,
3207                               4, Wn4_PhysicalMgmt);
3208                mdio_delay(vp);
3209        }
3210        /* Leave the interface idle. */
3211        for (i = 1; i >= 0; i--) {
3212                window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3213                mdio_delay(vp);
3214                window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3215                               4, Wn4_PhysicalMgmt);
3216                mdio_delay(vp);
3217        }
3218
3219        spin_unlock_bh(&vp->mii_lock);
3220}
3221
3222/* ACPI: Advanced Configuration and Power Interface. */
3223/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3224static void acpi_set_WOL(struct net_device *dev)
3225{
3226        struct vortex_private *vp = netdev_priv(dev);
3227        void __iomem *ioaddr = vp->ioaddr;
3228
3229        device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3230
3231        if (vp->enable_wol) {
3232                /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3233                window_write16(vp, 2, 7, 0x0c);
3234                /* The RxFilter must accept the WOL frames. */
3235                iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3236                iowrite16(RxEnable, ioaddr + EL3_CMD);
3237
3238                if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3239                        pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3240
3241                        vp->enable_wol = 0;
3242                        return;
3243                }
3244
3245                if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3246                        return;
3247
3248                /* Change the power state to D3; RxEnable doesn't take effect. */
3249                pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3250        }
3251}
3252
3253
3254static void vortex_remove_one(struct pci_dev *pdev)
3255{
3256        struct net_device *dev = pci_get_drvdata(pdev);
3257        struct vortex_private *vp;
3258
3259        if (!dev) {
3260                pr_err("vortex_remove_one called for Compaq device!\n");
3261                BUG();
3262        }
3263
3264        vp = netdev_priv(dev);
3265
3266        if (vp->cb_fn_base)
3267                pci_iounmap(pdev, vp->cb_fn_base);
3268
3269        unregister_netdev(dev);
3270
3271        pci_set_power_state(pdev, PCI_D0);      /* Go active */
3272        if (vp->pm_state_valid)
3273                pci_restore_state(pdev);
3274        pci_disable_device(pdev);
3275
3276        /* Should really use issue_and_wait() here */
3277        iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3278             vp->ioaddr + EL3_CMD);
3279
3280        pci_iounmap(pdev, vp->ioaddr);
3281
3282        dma_free_coherent(&pdev->dev,
3283                        sizeof(struct boom_rx_desc) * RX_RING_SIZE +
3284                        sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3285                        vp->rx_ring, vp->rx_ring_dma);
3286
3287        pci_release_regions(pdev);
3288
3289        free_netdev(dev);
3290}
3291
3292
3293static struct pci_driver vortex_driver = {
3294        .name           = "3c59x",
3295        .probe          = vortex_init_one,
3296        .remove         = vortex_remove_one,
3297        .id_table       = vortex_pci_tbl,
3298        .driver.pm      = VORTEX_PM_OPS,
3299};
3300
3301
3302static int vortex_have_pci;
3303static int vortex_have_eisa;
3304
3305
3306static int __init vortex_init(void)
3307{
3308        int pci_rc, eisa_rc;
3309
3310        pci_rc = pci_register_driver(&vortex_driver);
3311        eisa_rc = vortex_eisa_init();
3312
3313        if (pci_rc == 0)
3314                vortex_have_pci = 1;
3315        if (eisa_rc > 0)
3316                vortex_have_eisa = 1;
3317
3318        return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3319}
3320
3321
3322static void __exit vortex_eisa_cleanup(void)
3323{
3324        void __iomem *ioaddr;
3325
3326#ifdef CONFIG_EISA
3327        /* Take care of the EISA devices */
3328        eisa_driver_unregister(&vortex_eisa_driver);
3329#endif
3330
3331        if (compaq_net_device) {
3332                ioaddr = ioport_map(compaq_net_device->base_addr,
3333                                    VORTEX_TOTAL_SIZE);
3334
3335                unregister_netdev(compaq_net_device);
3336                iowrite16(TotalReset, ioaddr + EL3_CMD);
3337                release_region(compaq_net_device->base_addr,
3338                               VORTEX_TOTAL_SIZE);
3339
3340                free_netdev(compaq_net_device);
3341        }
3342}
3343
3344
3345static void __exit vortex_cleanup(void)
3346{
3347        if (vortex_have_pci)
3348                pci_unregister_driver(&vortex_driver);
3349        if (vortex_have_eisa)
3350                vortex_eisa_cleanup();
3351}
3352
3353
3354module_init(vortex_init);
3355module_exit(vortex_cleanup);
3356