LXR linux/drivers/net/ethernet/chelsio/cxgb4/t4

   1/*
   2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3 *
   4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5 *
   6 * This software is available to you under a choice of one of two
   7 * licenses.  You may choose to be licensed under the terms of the GNU
   8 * General Public License (GPL) Version 2, available from the file
   9 * COPYING in the main directory of this source tree, or the
  10 * OpenIB.org BSD license below:
  11 *
  12 *     Redistribution and use in source and binary forms, with or
  13 *     without modification, are permitted provided that the following
  14 *     conditions are met:
  15 *
  16 *      - Redistributions of source code must retain the above
  17 *        copyright notice, this list of conditions and the following
  18 *        disclaimer.
  19 *
  20 *      - Redistributions in binary form must reproduce the above
  21 *        copyright notice, this list of conditions and the following
  22 *        disclaimer in the documentation and/or other materials
  23 *        provided with the distribution.
  24 *
  25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32 * SOFTWARE.
  33 */
  34
  35#include <linux/delay.h>
  36#include "cxgb4.h"
  37#include "t4_regs.h"
  38#include "t4_values.h"
  39#include "t4fw_api.h"
  40#include "t4fw_version.h"
  41
  42/**
  43 *      t4_wait_op_done_val - wait until an operation is completed
  44 *      @adapter: the adapter performing the operation
  45 *      @reg: the register to check for completion
  46 *      @mask: a single-bit field within @reg that indicates completion
  47 *      @polarity: the value of the field when the operation is completed
  48 *      @attempts: number of check iterations
  49 *      @delay: delay in usecs between iterations
  50 *      @valp: where to store the value of the register at completion time
  51 *
  52 *      Wait until an operation is completed by checking a bit in a register
  53 *      up to @attempts times.  If @valp is not NULL the value of the register
  54 *      at the time it indicated completion is stored there.  Returns 0 if the
  55 *      operation completes and -EAGAIN otherwise.
  56 */
  57static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                               int polarity, int attempts, int delay, u32 *valp)
  59{
  60        while (1) {
  61                u32 val = t4_read_reg(adapter, reg);
  62
  63                if (!!(val & mask) == polarity) {
  64                        if (valp)
  65                                *valp = val;
  66                        return 0;
  67                }
  68                if (--attempts == 0)
  69                        return -EAGAIN;
  70                if (delay)
  71                        udelay(delay);
  72        }
  73}
  74
  75static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                  int polarity, int attempts, int delay)
  77{
  78        return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                   delay, NULL);
  80}
  81
  82/**
  83 *      t4_set_reg_field - set a register field to a value
  84 *      @adapter: the adapter to program
  85 *      @addr: the register address
  86 *      @mask: specifies the portion of the register to modify
  87 *      @val: the new value for the register field
  88 *
  89 *      Sets a register field specified by the supplied mask to the
  90 *      given value.
  91 */
  92void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                      u32 val)
  94{
  95        u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97        t4_write_reg(adapter, addr, v | val);
  98        (void) t4_read_reg(adapter, addr);      /* flush */
  99}
 100
 101/**
 102 *      t4_read_indirect - read indirectly addressed registers
 103 *      @adap: the adapter
 104 *      @addr_reg: register holding the indirect address
 105 *      @data_reg: register holding the value of the indirect register
 106 *      @vals: where the read register values are stored
 107 *      @nregs: how many indirect registers to read
 108 *      @start_idx: index of first indirect register to read
 109 *
 110 *      Reads registers that are accessed indirectly through an address/data
 111 *      register pair.
 112 */
 113void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                             unsigned int data_reg, u32 *vals,
 115                             unsigned int nregs, unsigned int start_idx)
 116{
 117        while (nregs--) {
 118                t4_write_reg(adap, addr_reg, start_idx);
 119                *vals++ = t4_read_reg(adap, data_reg);
 120                start_idx++;
 121        }
 122}
 123
 124/**
 125 *      t4_write_indirect - write indirectly addressed registers
 126 *      @adap: the adapter
 127 *      @addr_reg: register holding the indirect addresses
 128 *      @data_reg: register holding the value for the indirect registers
 129 *      @vals: values to write
 130 *      @nregs: how many indirect registers to write
 131 *      @start_idx: address of first indirect register to write
 132 *
 133 *      Writes a sequential block of registers that are accessed indirectly
 134 *      through an address/data register pair.
 135 */
 136void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                       unsigned int data_reg, const u32 *vals,
 138                       unsigned int nregs, unsigned int start_idx)
 139{
 140        while (nregs--) {
 141                t4_write_reg(adap, addr_reg, start_idx++);
 142                t4_write_reg(adap, data_reg, *vals++);
 143        }
 144}
 145
 146/*
 147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148 * mechanism.  This guarantees that we get the real value even if we're
 149 * operating within a Virtual Machine and the Hypervisor is trapping our
 150 * Configuration Space accesses.
 151 */
 152void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153{
 154        u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156        if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                req |= ENABLE_F;
 158        else
 159                req |= T6_ENABLE_F;
 160
 161        if (is_t4(adap->params.chip))
 162                req |= LOCALCFG_F;
 163
 164        t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165        *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167        /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168         * Configuration Space read.  (None of the other fields matter when
 169         * ENABLE is 0 so a simple register write is easier than a
 170         * read-modify-write via t4_set_reg_field().)
 171         */
 172        t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173}
 174
 175/*
 176 * t4_report_fw_error - report firmware error
 177 * @adap: the adapter
 178 *
 179 * The adapter firmware can indicate error conditions to the host.
 180 * If the firmware has indicated an error, print out the reason for
 181 * the firmware error.
 182 */
 183static void t4_report_fw_error(struct adapter *adap)
 184{
 185        static const char *const reason[] = {
 186                "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                "Reserved",                     /* reserved */
 194        };
 195        u32 pcie_fw;
 196
 197        pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198        if (pcie_fw & PCIE_FW_ERR_F) {
 199                dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                        reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201                adap->flags &= ~CXGB4_FW_OK;
 202        }
 203}
 204
 205/*
 206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 207 */
 208static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 209                         u32 mbox_addr)
 210{
 211        for ( ; nflit; nflit--, mbox_addr += 8)
 212                *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 213}
 214
 215/*
 216 * Handle a FW assertion reported in a mailbox.
 217 */
 218static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 219{
 220        struct fw_debug_cmd asrt;
 221
 222        get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 223        dev_alert(adap->pdev_dev,
 224                  "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 225                  asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 226                  be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 227}
 228
 229/**
 230 *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 231 *      @adapter: the adapter
 232 *      @cmd: the Firmware Mailbox Command or Reply
 233 *      @size: command length in bytes
 234 *      @access: the time (ms) needed to access the Firmware Mailbox
 235 *      @execute: the time (ms) the command spent being executed
 236 */
 237static void t4_record_mbox(struct adapter *adapter,
 238                           const __be64 *cmd, unsigned int size,
 239                           int access, int execute)
 240{
 241        struct mbox_cmd_log *log = adapter->mbox_log;
 242        struct mbox_cmd *entry;
 243        int i;
 244
 245        entry = mbox_cmd_log_entry(log, log->cursor++);
 246        if (log->cursor == log->size)
 247                log->cursor = 0;
 248
 249        for (i = 0; i < size / 8; i++)
 250                entry->cmd[i] = be64_to_cpu(cmd[i]);
 251        while (i < MBOX_LEN / 8)
 252                entry->cmd[i++] = 0;
 253        entry->timestamp = jiffies;
 254        entry->seqno = log->seqno++;
 255        entry->access = access;
 256        entry->execute = execute;
 257}
 258
 259/**
 260 *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 261 *      @adap: the adapter
 262 *      @mbox: index of the mailbox to use
 263 *      @cmd: the command to write
 264 *      @size: command length in bytes
 265 *      @rpl: where to optionally store the reply
 266 *      @sleep_ok: if true we may sleep while awaiting command completion
 267 *      @timeout: time to wait for command to finish before timing out
 268 *
 269 *      Sends the given command to FW through the selected mailbox and waits
 270 *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 271 *      store the FW's reply to the command.  The command and its optional
 272 *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 273 *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 274 *      the response.  If sleeping is allowed we use progressive backoff
 275 *      otherwise we spin.
 276 *
 277 *      The return value is 0 on success or a negative errno on failure.  A
 278 *      failure can happen either because we are not able to execute the
 279 *      command or FW executes it but signals an error.  In the latter case
 280 *      the return value is the error code indicated by FW (negated).
 281 */
 282int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 283                            int size, void *rpl, bool sleep_ok, int timeout)
 284{
 285        static const int delay[] = {
 286                1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 287        };
 288
 289        struct mbox_list entry;
 290        u16 access = 0;
 291        u16 execute = 0;
 292        u32 v;
 293        u64 res;
 294        int i, ms, delay_idx, ret;
 295        const __be64 *p = cmd;
 296        u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 297        u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 298        __be64 cmd_rpl[MBOX_LEN / 8];
 299        u32 pcie_fw;
 300
 301        if ((size & 15) || size > MBOX_LEN)
 302                return -EINVAL;
 303
 304        /*
 305         * If the device is off-line, as in EEH, commands will time out.
 306         * Fail them early so we don't waste time waiting.
 307         */
 308        if (adap->pdev->error_state != pci_channel_io_normal)
 309                return -EIO;
 310
 311        /* If we have a negative timeout, that implies that we can't sleep. */
 312        if (timeout < 0) {
 313                sleep_ok = false;
 314                timeout = -timeout;
 315        }
 316
 317        /* Queue ourselves onto the mailbox access list.  When our entry is at
 318         * the front of the list, we have rights to access the mailbox.  So we
 319         * wait [for a while] till we're at the front [or bail out with an
 320         * EBUSY] ...
 321         */
 322        spin_lock_bh(&adap->mbox_lock);
 323        list_add_tail(&entry.list, &adap->mlist.list);
 324        spin_unlock_bh(&adap->mbox_lock);
 325
 326        delay_idx = 0;
 327        ms = delay[0];
 328
 329        for (i = 0; ; i += ms) {
 330                /* If we've waited too long, return a busy indication.  This
 331                 * really ought to be based on our initial position in the
 332                 * mailbox access list but this is a start.  We very rarely
 333                 * contend on access to the mailbox ...
 334                 */
 335                pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 336                if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
 337                        spin_lock_bh(&adap->mbox_lock);
 338                        list_del(&entry.list);
 339                        spin_unlock_bh(&adap->mbox_lock);
 340                        ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
 341                        t4_record_mbox(adap, cmd, size, access, ret);
 342                        return ret;
 343                }
 344
 345                /* If we're at the head, break out and start the mailbox
 346                 * protocol.
 347                 */
 348                if (list_first_entry(&adap->mlist.list, struct mbox_list,
 349                                     list) == &entry)
 350                        break;
 351
 352                /* Delay for a bit before checking again ... */
 353                if (sleep_ok) {
 354                        ms = delay[delay_idx];  /* last element may repeat */
 355                        if (delay_idx < ARRAY_SIZE(delay) - 1)
 356                                delay_idx++;
 357                        msleep(ms);
 358                } else {
 359                        mdelay(ms);
 360                }
 361        }
 362
 363        /* Loop trying to get ownership of the mailbox.  Return an error
 364         * if we can't gain ownership.
 365         */
 366        v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 367        for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 368                v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 369        if (v != MBOX_OWNER_DRV) {
 370                spin_lock_bh(&adap->mbox_lock);
 371                list_del(&entry.list);
 372                spin_unlock_bh(&adap->mbox_lock);
 373                ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 374                t4_record_mbox(adap, cmd, size, access, ret);
 375                return ret;
 376        }
 377
 378        /* Copy in the new mailbox command and send it on its way ... */
 379        t4_record_mbox(adap, cmd, size, access, 0);
 380        for (i = 0; i < size; i += 8)
 381                t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 382
 383        t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 384        t4_read_reg(adap, ctl_reg);          /* flush write */
 385
 386        delay_idx = 0;
 387        ms = delay[0];
 388
 389        for (i = 0;
 390             !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 391             i < timeout;
 392             i += ms) {
 393                if (sleep_ok) {
 394                        ms = delay[delay_idx];  /* last element may repeat */
 395                        if (delay_idx < ARRAY_SIZE(delay) - 1)
 396                                delay_idx++;
 397                        msleep(ms);
 398                } else
 399                        mdelay(ms);
 400
 401                v = t4_read_reg(adap, ctl_reg);
 402                if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 403                        if (!(v & MBMSGVALID_F)) {
 404                                t4_write_reg(adap, ctl_reg, 0);
 405                                continue;
 406                        }
 407
 408                        get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 409                        res = be64_to_cpu(cmd_rpl[0]);
 410
 411                        if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 412                                fw_asrt(adap, data_reg);
 413                                res = FW_CMD_RETVAL_V(EIO);
 414                        } else if (rpl) {
 415                                memcpy(rpl, cmd_rpl, size);
 416                        }
 417
 418                        t4_write_reg(adap, ctl_reg, 0);
 419
 420                        execute = i + ms;
 421                        t4_record_mbox(adap, cmd_rpl,
 422                                       MBOX_LEN, access, execute);
 423                        spin_lock_bh(&adap->mbox_lock);
 424                        list_del(&entry.list);
 425                        spin_unlock_bh(&adap->mbox_lock);
 426                        return -FW_CMD_RETVAL_G((int)res);
 427                }
 428        }
 429
 430        ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 431        t4_record_mbox(adap, cmd, size, access, ret);
 432        dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 433                *(const u8 *)cmd, mbox);
 434        t4_report_fw_error(adap);
 435        spin_lock_bh(&adap->mbox_lock);
 436        list_del(&entry.list);
 437        spin_unlock_bh(&adap->mbox_lock);
 438        t4_fatal_err(adap);
 439        return ret;
 440}
 441
 442int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 443                    void *rpl, bool sleep_ok)
 444{
 445        return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 446                                       FW_CMD_MAX_TIMEOUT);
 447}
 448
 449static int t4_edc_err_read(struct adapter *adap, int idx)
 450{
 451        u32 edc_ecc_err_addr_reg;
 452        u32 rdata_reg;
 453
 454        if (is_t4(adap->params.chip)) {
 455                CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 456                return 0;
 457        }
 458        if (idx != 0 && idx != 1) {
 459                CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 460                return 0;
 461        }
 462
 463        edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 464        rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 465
 466        CH_WARN(adap,
 467                "edc%d err addr 0x%x: 0x%x.\n",
 468                idx, edc_ecc_err_addr_reg,
 469                t4_read_reg(adap, edc_ecc_err_addr_reg));
 470        CH_WARN(adap,
 471                "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 472                rdata_reg,
 473                (unsigned long long)t4_read_reg64(adap, rdata_reg),
 474                (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 475                (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 476                (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 477                (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 478                (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 479                (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 480                (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 481                (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 482
 483        return 0;
 484}
 485
 486/**
 487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
 488 * @adap: the adapter
 489 * @win: PCI-E Memory Window to use
 490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
 491 * @mem_off: memory relative offset with respect to @mtype.
 492 * @mem_base: configured memory base address.
 493 * @mem_aperture: configured memory window aperture.
 494 *
 495 * Get the configured memory window's relative offset, base, and size.
 496 */
 497int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
 498                      u32 *mem_base, u32 *mem_aperture)
 499{
 500        u32 edc_size, mc_size, mem_reg;
 501
 502        /* Offset into the region of memory which is being accessed
 503         * MEM_EDC0 = 0
 504         * MEM_EDC1 = 1
 505         * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 506         * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 507         * MEM_HMA  = 4
 508         */
 509        edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 510        if (mtype == MEM_HMA) {
 511                *mem_off = 2 * (edc_size * 1024 * 1024);
 512        } else if (mtype != MEM_MC1) {
 513                *mem_off = (mtype * (edc_size * 1024 * 1024));
 514        } else {
 515                mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 516                                                      MA_EXT_MEMORY0_BAR_A));
 517                *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 518        }
 519
 520        /* Each PCI-E Memory Window is programmed with a window size -- or
 521         * "aperture" -- which controls the granularity of its mapping onto
 522         * adapter memory.  We need to grab that aperture in order to know
 523         * how to use the specified window.  The window is also programmed
 524         * with the base address of the Memory Window in BAR0's address
 525         * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 526         * the address is relative to BAR0.
 527         */
 528        mem_reg = t4_read_reg(adap,
 529                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 530                                                  win));
 531        /* a dead adapter will return 0xffffffff for PIO reads */
 532        if (mem_reg == 0xffffffff)
 533                return -ENXIO;
 534
 535        *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 536        *mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 537        if (is_t4(adap->params.chip))
 538                *mem_base -= adap->t4_bar0;
 539
 540        return 0;
 541}
 542
 543/**
 544 * t4_memory_update_win - Move memory window to specified address.
 545 * @adap: the adapter
 546 * @win: PCI-E Memory Window to use
 547 * @addr: location to move.
 548 *
 549 * Move memory window to specified address.
 550 */
 551void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
 552{
 553        t4_write_reg(adap,
 554                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 555                     addr);
 556        /* Read it back to ensure that changes propagate before we
 557         * attempt to use the new value.
 558         */
 559        t4_read_reg(adap,
 560                    PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 561}
 562
 563/**
 564 * t4_memory_rw_residual - Read/Write residual data.
 565 * @adap: the adapter
 566 * @off: relative offset within residual to start read/write.
 567 * @addr: address within indicated memory type.
 568 * @buf: host memory buffer
 569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 570 *
 571 * Read/Write residual data less than 32-bits.
 572 */
 573void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
 574                           int dir)
 575{
 576        union {
 577                u32 word;
 578                char byte[4];
 579        } last;
 580        unsigned char *bp;
 581        int i;
 582
 583        if (dir == T4_MEMORY_READ) {
 584                last.word = le32_to_cpu((__force __le32)
 585                                        t4_read_reg(adap, addr));
 586                for (bp = (unsigned char *)buf, i = off; i < 4; i++)
 587                        bp[i] = last.byte[i];
 588        } else {
 589                last.word = *buf;
 590                for (i = off; i < 4; i++)
 591                        last.byte[i] = 0;
 592                t4_write_reg(adap, addr,
 593                             (__force u32)cpu_to_le32(last.word));
 594        }
 595}
 596
 597/**
 598 *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 599 *      @adap: the adapter
 600 *      @win: PCI-E Memory Window to use
 601 *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 602 *      @addr: address within indicated memory type
 603 *      @len: amount of memory to transfer
 604 *      @hbuf: host memory buffer
 605 *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 606 *
 607 *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 608 *      firmware memory address and host buffer must be aligned on 32-bit
 609 *      boundaries; the length may be arbitrary.  The memory is transferred as
 610 *      a raw byte sequence from/to the firmware's memory.  If this memory
 611 *      contains data structures which contain multi-byte integers, it's the
 612 *      caller's responsibility to perform appropriate byte order conversions.
 613 */
 614int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 615                 u32 len, void *hbuf, int dir)
 616{
 617        u32 pos, offset, resid, memoffset;
 618        u32 win_pf, mem_aperture, mem_base;
 619        u32 *buf;
 620        int ret;
 621
 622        /* Argument sanity checks ...
 623         */
 624        if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 625                return -EINVAL;
 626        buf = (u32 *)hbuf;
 627
 628        /* It's convenient to be able to handle lengths which aren't a
 629         * multiple of 32-bits because we often end up transferring files to
 630         * the firmware.  So we'll handle that by normalizing the length here
 631         * and then handling any residual transfer at the end.
 632         */
 633        resid = len & 0x3;
 634        len -= resid;
 635
 636        ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
 637                                &mem_aperture);
 638        if (ret)
 639                return ret;
 640
 641        /* Determine the PCIE_MEM_ACCESS_OFFSET */
 642        addr = addr + memoffset;
 643
 644        win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 645
 646        /* Calculate our initial PCI-E Memory Window Position and Offset into
 647         * that Window.
 648         */
 649        pos = addr & ~(mem_aperture - 1);
 650        offset = addr - pos;
 651
 652        /* Set up initial PCI-E Memory Window to cover the start of our
 653         * transfer.
 654         */
 655        t4_memory_update_win(adap, win, pos | win_pf);
 656
 657        /* Transfer data to/from the adapter as long as there's an integral
 658         * number of 32-bit transfers to complete.
 659         *
 660         * A note on Endianness issues:
 661         *
 662         * The "register" reads and writes below from/to the PCI-E Memory
 663         * Window invoke the standard adapter Big-Endian to PCI-E Link
 664         * Little-Endian "swizzel."  As a result, if we have the following
 665         * data in adapter memory:
 666         *
 667         *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 668         *     Address:      i+0  i+1  i+2  i+3
 669         *
 670         * Then a read of the adapter memory via the PCI-E Memory Window
 671         * will yield:
 672         *
 673         *     x = readl(i)
 674         *         31                  0
 675         *         [ b3 | b2 | b1 | b0 ]
 676         *
 677         * If this value is stored into local memory on a Little-Endian system
 678         * it will show up correctly in local memory as:
 679         *
 680         *     ( ..., b0, b1, b2, b3, ... )
 681         *
 682         * But on a Big-Endian system, the store will show up in memory
 683         * incorrectly swizzled as:
 684         *
 685         *     ( ..., b3, b2, b1, b0, ... )
 686         *
 687         * So we need to account for this in the reads and writes to the
 688         * PCI-E Memory Window below by undoing the register read/write
 689         * swizzels.
 690         */
 691        while (len > 0) {
 692                if (dir == T4_MEMORY_READ)
 693                        *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 694                                                mem_base + offset));
 695                else
 696                        t4_write_reg(adap, mem_base + offset,
 697                                     (__force u32)cpu_to_le32(*buf++));
 698                offset += sizeof(__be32);
 699                len -= sizeof(__be32);
 700
 701                /* If we've reached the end of our current window aperture,
 702                 * move the PCI-E Memory Window on to the next.  Note that
 703                 * doing this here after "len" may be 0 allows us to set up
 704                 * the PCI-E Memory Window for a possible final residual
 705                 * transfer below ...
 706                 */
 707                if (offset == mem_aperture) {
 708                        pos += mem_aperture;
 709                        offset = 0;
 710                        t4_memory_update_win(adap, win, pos | win_pf);
 711                }
 712        }
 713
 714        /* If the original transfer had a length which wasn't a multiple of
 715         * 32-bits, now's where we need to finish off the transfer of the
 716         * residual amount.  The PCI-E Memory Window has already been moved
 717         * above (if necessary) to cover this final transfer.
 718         */
 719        if (resid)
 720                t4_memory_rw_residual(adap, resid, mem_base + offset,
 721                                      (u8 *)buf, dir);
 722
 723        return 0;
 724}
 725
 726/* Return the specified PCI-E Configuration Space register from our Physical
 727 * Function.  We try first via a Firmware LDST Command since we prefer to let
 728 * the firmware own all of these registers, but if that fails we go for it
 729 * directly ourselves.
 730 */
 731u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 732{
 733        u32 val, ldst_addrspace;
 734
 735        /* If fw_attach != 0, construct and send the Firmware LDST Command to
 736         * retrieve the specified PCI-E Configuration Space register.
 737         */
 738        struct fw_ldst_cmd ldst_cmd;
 739        int ret;
 740
 741        memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 742        ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 743        ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 744                                               FW_CMD_REQUEST_F |
 745                                               FW_CMD_READ_F |
 746                                               ldst_addrspace);
 747        ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 748        ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 749        ldst_cmd.u.pcie.ctrl_to_fn =
 750                (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 751        ldst_cmd.u.pcie.r = reg;
 752
 753        /* If the LDST Command succeeds, return the result, otherwise
 754         * fall through to reading it directly ourselves ...
 755         */
 756        ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 757                         &ldst_cmd);
 758        if (ret == 0)
 759                val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 760        else
 761                /* Read the desired Configuration Space register via the PCI-E
 762                 * Backdoor mechanism.
 763                 */
 764                t4_hw_pci_read_cfg4(adap, reg, &val);
 765        return val;
 766}
 767
 768/* Get the window based on base passed to it.
 769 * Window aperture is currently unhandled, but there is no use case for it
 770 * right now
 771 */
 772static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 773                         u32 memwin_base)
 774{
 775        u32 ret;
 776
 777        if (is_t4(adap->params.chip)) {
 778                u32 bar0;
 779
 780                /* Truncation intentional: we only read the bottom 32-bits of
 781                 * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 782                 * mechanism to read BAR0 instead of using
 783                 * pci_resource_start() because we could be operating from
 784                 * within a Virtual Machine which is trapping our accesses to
 785                 * our Configuration Space and we need to set up the PCI-E
 786                 * Memory Window decoders with the actual addresses which will
 787                 * be coming across the PCI-E link.
 788                 */
 789                bar0 = t4_read_pcie_cfg4(adap, pci_base);
 790                bar0 &= pci_mask;
 791                adap->t4_bar0 = bar0;
 792
 793                ret = bar0 + memwin_base;
 794        } else {
 795                /* For T5, only relative offset inside the PCIe BAR is passed */
 796                ret = memwin_base;
 797        }
 798        return ret;
 799}
 800
 801/* Get the default utility window (win0) used by everyone */
 802u32 t4_get_util_window(struct adapter *adap)
 803{
 804        return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 805                             PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 806}
 807
 808/* Set up memory window for accessing adapter memory ranges.  (Read
 809 * back MA register to ensure that changes propagate before we attempt
 810 * to use the new values.)
 811 */
 812void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 813{
 814        t4_write_reg(adap,
 815                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 816                     memwin_base | BIR_V(0) |
 817                     WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 818        t4_read_reg(adap,
 819                    PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 820}
 821
 822/**
 823 *      t4_get_regs_len - return the size of the chips register set
 824 *      @adapter: the adapter
 825 *
 826 *      Returns the size of the chip's BAR0 register space.
 827 */
 828unsigned int t4_get_regs_len(struct adapter *adapter)
 829{
 830        unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 831
 832        switch (chip_version) {
 833        case CHELSIO_T4:
 834                return T4_REGMAP_SIZE;
 835
 836        case CHELSIO_T5:
 837        case CHELSIO_T6:
 838                return T5_REGMAP_SIZE;
 839        }
 840
 841        dev_err(adapter->pdev_dev,
 842                "Unsupported chip version %d\n", chip_version);
 843        return 0;
 844}
 845
 846/**
 847 *      t4_get_regs - read chip registers into provided buffer
 848 *      @adap: the adapter
 849 *      @buf: register buffer
 850 *      @buf_size: size (in bytes) of register buffer
 851 *
 852 *      If the provided register buffer isn't large enough for the chip's
 853 *      full register range, the register dump will be truncated to the
 854 *      register buffer's size.
 855 */
 856void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 857{
 858        static const unsigned int t4_reg_ranges[] = {
 859                0x1008, 0x1108,
 860                0x1180, 0x1184,
 861                0x1190, 0x1194,
 862                0x11a0, 0x11a4,
 863                0x11b0, 0x11b4,
 864                0x11fc, 0x123c,
 865                0x1300, 0x173c,
 866                0x1800, 0x18fc,
 867                0x3000, 0x30d8,
 868                0x30e0, 0x30e4,
 869                0x30ec, 0x5910,
 870                0x5920, 0x5924,
 871                0x5960, 0x5960,
 872                0x5968, 0x5968,
 873                0x5970, 0x5970,
 874                0x5978, 0x5978,
 875                0x5980, 0x5980,
 876                0x5988, 0x5988,
 877                0x5990, 0x5990,
 878                0x5998, 0x5998,
 879                0x59a0, 0x59d4,
 880                0x5a00, 0x5ae0,
 881                0x5ae8, 0x5ae8,
 882                0x5af0, 0x5af0,
 883                0x5af8, 0x5af8,
 884                0x6000, 0x6098,
 885                0x6100, 0x6150,
 886                0x6200, 0x6208,
 887                0x6240, 0x6248,
 888                0x6280, 0x62b0,
 889                0x62c0, 0x6338,
 890                0x6370, 0x638c,
 891                0x6400, 0x643c,
 892                0x6500, 0x6524,
 893                0x6a00, 0x6a04,
 894                0x6a14, 0x6a38,
 895                0x6a60, 0x6a70,
 896                0x6a78, 0x6a78,
 897                0x6b00, 0x6b0c,
 898                0x6b1c, 0x6b84,
 899                0x6bf0, 0x6bf8,
 900                0x6c00, 0x6c0c,
 901                0x6c1c, 0x6c84,
 902                0x6cf0, 0x6cf8,
 903                0x6d00, 0x6d0c,
 904                0x6d1c, 0x6d84,
 905                0x6df0, 0x6df8,
 906                0x6e00, 0x6e0c,
 907                0x6e1c, 0x6e84,
 908                0x6ef0, 0x6ef8,
 909                0x6f00, 0x6f0c,
 910                0x6f1c, 0x6f84,
 911                0x6ff0, 0x6ff8,
 912                0x7000, 0x700c,
 913                0x701c, 0x7084,
 914                0x70f0, 0x70f8,
 915                0x7100, 0x710c,
 916                0x711c, 0x7184,
 917                0x71f0, 0x71f8,
 918                0x7200, 0x720c,
 919                0x721c, 0x7284,
 920                0x72f0, 0x72f8,
 921                0x7300, 0x730c,
 922                0x731c, 0x7384,
 923                0x73f0, 0x73f8,
 924                0x7400, 0x7450,
 925                0x7500, 0x7530,
 926                0x7600, 0x760c,
 927                0x7614, 0x761c,
 928                0x7680, 0x76cc,
 929                0x7700, 0x7798,
 930                0x77c0, 0x77fc,
 931                0x7900, 0x79fc,
 932                0x7b00, 0x7b58,
 933                0x7b60, 0x7b84,
 934                0x7b8c, 0x7c38,
 935                0x7d00, 0x7d38,
 936                0x7d40, 0x7d80,
 937                0x7d8c, 0x7ddc,
 938                0x7de4, 0x7e04,
 939                0x7e10, 0x7e1c,
 940                0x7e24, 0x7e38,
 941                0x7e40, 0x7e44,
 942                0x7e4c, 0x7e78,
 943                0x7e80, 0x7ea4,
 944                0x7eac, 0x7edc,
 945                0x7ee8, 0x7efc,
 946                0x8dc0, 0x8e04,
 947                0x8e10, 0x8e1c,
 948                0x8e30, 0x8e78,
 949                0x8ea0, 0x8eb8,
 950                0x8ec0, 0x8f6c,
 951                0x8fc0, 0x9008,
 952                0x9010, 0x9058,
 953                0x9060, 0x9060,
 954                0x9068, 0x9074,
 955                0x90fc, 0x90fc,
 956                0x9400, 0x9408,
 957                0x9410, 0x9458,
 958                0x9600, 0x9600,
 959                0x9608, 0x9638,
 960                0x9640, 0x96bc,
 961                0x9800, 0x9808,
 962                0x9820, 0x983c,
 963                0x9850, 0x9864,
 964                0x9c00, 0x9c6c,
 965                0x9c80, 0x9cec,
 966                0x9d00, 0x9d6c,
 967                0x9d80, 0x9dec,
 968                0x9e00, 0x9e6c,
 969                0x9e80, 0x9eec,
 970                0x9f00, 0x9f6c,
 971                0x9f80, 0x9fec,
 972                0xd004, 0xd004,
 973                0xd010, 0xd03c,
 974                0xdfc0, 0xdfe0,
 975                0xe000, 0xea7c,
 976                0xf000, 0x11110,
 977                0x11118, 0x11190,
 978                0x19040, 0x1906c,
 979                0x19078, 0x19080,
 980                0x1908c, 0x190e4,
 981                0x190f0, 0x190f8,
 982                0x19100, 0x19110,
 983                0x19120, 0x19124,
 984                0x19150, 0x19194,
 985                0x1919c, 0x191b0,
 986                0x191d0, 0x191e8,
 987                0x19238, 0x1924c,
 988                0x193f8, 0x1943c,
 989                0x1944c, 0x19474,
 990                0x19490, 0x194e0,
 991                0x194f0, 0x194f8,
 992                0x19800, 0x19c08,
 993                0x19c10, 0x19c90,
 994                0x19ca0, 0x19ce4,
 995                0x19cf0, 0x19d40,
 996                0x19d50, 0x19d94,
 997                0x19da0, 0x19de8,
 998                0x19df0, 0x19e40,
 999                0x19e50, 0x19e90,
1000                0x19ea0, 0x19f4c,

1001                0x1a000, 0x1a004,
1002                0x1a010, 0x1a06c,
1003                0x1a0b0, 0x1a0e4,
1004                0x1a0ec, 0x1a0f4,
1005                0x1a100, 0x1a108,
1006                0x1a114, 0x1a120,
1007                0x1a128, 0x1a130,
1008                0x1a138, 0x1a138,
1009                0x1a190, 0x1a1c4,
1010                0x1a1fc, 0x1a1fc,
1011                0x1e040, 0x1e04c,
1012                0x1e284, 0x1e28c,
1013                0x1e2c0, 0x1e2c0,
1014                0x1e2e0, 0x1e2e0,
1015                0x1e300, 0x1e384,
1016                0x1e3c0, 0x1e3c8,
1017                0x1e440, 0x1e44c,
1018                0x1e684, 0x1e68c,
1019                0x1e6c0, 0x1e6c0,
1020                0x1e6e0, 0x1e6e0,
1021                0x1e700, 0x1e784,
1022                0x1e7c0, 0x1e7c8,
1023                0x1e840, 0x1e84c,
1024                0x1ea84, 0x1ea8c,
1025                0x1eac0, 0x1eac0,
1026                0x1eae0, 0x1eae0,
1027                0x1eb00, 0x1eb84,
1028                0x1ebc0, 0x1ebc8,
1029                0x1ec40, 0x1ec4c,
1030                0x1ee84, 0x1ee8c,
1031                0x1eec0, 0x1eec0,
1032                0x1eee0, 0x1eee0,
1033                0x1ef00, 0x1ef84,
1034                0x1efc0, 0x1efc8,
1035                0x1f040, 0x1f04c,
1036                0x1f284, 0x1f28c,
1037                0x1f2c0, 0x1f2c0,
1038                0x1f2e0, 0x1f2e0,
1039                0x1f300, 0x1f384,
1040                0x1f3c0, 0x1f3c8,
1041                0x1f440, 0x1f44c,
1042                0x1f684, 0x1f68c,
1043                0x1f6c0, 0x1f6c0,
1044                0x1f6e0, 0x1f6e0,
1045                0x1f700, 0x1f784,
1046                0x1f7c0, 0x1f7c8,
1047                0x1f840, 0x1f84c,
1048                0x1fa84, 0x1fa8c,
1049                0x1fac0, 0x1fac0,
1050                0x1fae0, 0x1fae0,
1051                0x1fb00, 0x1fb84,
1052                0x1fbc0, 0x1fbc8,
1053                0x1fc40, 0x1fc4c,
1054                0x1fe84, 0x1fe8c,
1055                0x1fec0, 0x1fec0,
1056                0x1fee0, 0x1fee0,
1057                0x1ff00, 0x1ff84,
1058                0x1ffc0, 0x1ffc8,
1059                0x20000, 0x2002c,
1060                0x20100, 0x2013c,
1061                0x20190, 0x201a0,
1062                0x201a8, 0x201b8,
1063                0x201c4, 0x201c8,
1064                0x20200, 0x20318,
1065                0x20400, 0x204b4,
1066                0x204c0, 0x20528,
1067                0x20540, 0x20614,
1068                0x21000, 0x21040,
1069                0x2104c, 0x21060,
1070                0x210c0, 0x210ec,
1071                0x21200, 0x21268,
1072                0x21270, 0x21284,
1073                0x212fc, 0x21388,
1074                0x21400, 0x21404,
1075                0x21500, 0x21500,
1076                0x21510, 0x21518,
1077                0x2152c, 0x21530,
1078                0x2153c, 0x2153c,
1079                0x21550, 0x21554,
1080                0x21600, 0x21600,
1081                0x21608, 0x2161c,
1082                0x21624, 0x21628,
1083                0x21630, 0x21634,
1084                0x2163c, 0x2163c,
1085                0x21700, 0x2171c,
1086                0x21780, 0x2178c,
1087                0x21800, 0x21818,
1088                0x21820, 0x21828,
1089                0x21830, 0x21848,
1090                0x21850, 0x21854,
1091                0x21860, 0x21868,
1092                0x21870, 0x21870,
1093                0x21878, 0x21898,
1094                0x218a0, 0x218a8,
1095                0x218b0, 0x218c8,
1096                0x218d0, 0x218d4,
1097                0x218e0, 0x218e8,
1098                0x218f0, 0x218f0,
1099                0x218f8, 0x21a18,
1100                0x21a20, 0x21a28,
1101                0x21a30, 0x21a48,
1102                0x21a50, 0x21a54,
1103                0x21a60, 0x21a68,
1104                0x21a70, 0x21a70,
1105                0x21a78, 0x21a98,
1106                0x21aa0, 0x21aa8,
1107                0x21ab0, 0x21ac8,
1108                0x21ad0, 0x21ad4,
1109                0x21ae0, 0x21ae8,
1110                0x21af0, 0x21af0,
1111                0x21af8, 0x21c18,
1112                0x21c20, 0x21c20,
1113                0x21c28, 0x21c30,
1114                0x21c38, 0x21c38,
1115                0x21c80, 0x21c98,
1116                0x21ca0, 0x21ca8,
1117                0x21cb0, 0x21cc8,
1118                0x21cd0, 0x21cd4,
1119                0x21ce0, 0x21ce8,
1120                0x21cf0, 0x21cf0,
1121                0x21cf8, 0x21d7c,
1122                0x21e00, 0x21e04,
1123                0x22000, 0x2202c,
1124                0x22100, 0x2213c,
1125                0x22190, 0x221a0,
1126                0x221a8, 0x221b8,
1127                0x221c4, 0x221c8,
1128                0x22200, 0x22318,
1129                0x22400, 0x224b4,
1130                0x224c0, 0x22528,
1131                0x22540, 0x22614,
1132                0x23000, 0x23040,
1133                0x2304c, 0x23060,
1134                0x230c0, 0x230ec,
1135                0x23200, 0x23268,
1136                0x23270, 0x23284,
1137                0x232fc, 0x23388,
1138                0x23400, 0x23404,
1139                0x23500, 0x23500,
1140                0x23510, 0x23518,
1141                0x2352c, 0x23530,
1142                0x2353c, 0x2353c,
1143                0x23550, 0x23554,
1144                0x23600, 0x23600,
1145                0x23608, 0x2361c,
1146                0x23624, 0x23628,
1147                0x23630, 0x23634,
1148                0x2363c, 0x2363c,
1149                0x23700, 0x2371c,
1150                0x23780, 0x2378c,
1151                0x23800, 0x23818,
1152                0x23820, 0x23828,
1153                0x23830, 0x23848,
1154                0x23850, 0x23854,
1155                0x23860, 0x23868,
1156                0x23870, 0x23870,
1157                0x23878, 0x23898,
1158                0x238a0, 0x238a8,
1159                0x238b0, 0x238c8,
1160                0x238d0, 0x238d4,
1161                0x238e0, 0x238e8,
1162                0x238f0, 0x238f0,
1163                0x238f8, 0x23a18,
1164                0x23a20, 0x23a28,
1165                0x23a30, 0x23a48,
1166                0x23a50, 0x23a54,
1167                0x23a60, 0x23a68,
1168                0x23a70, 0x23a70,
1169                0x23a78, 0x23a98,
1170                0x23aa0, 0x23aa8,
1171                0x23ab0, 0x23ac8,
1172                0x23ad0, 0x23ad4,
1173                0x23ae0, 0x23ae8,
1174                0x23af0, 0x23af0,
1175                0x23af8, 0x23c18,
1176                0x23c20, 0x23c20,
1177                0x23c28, 0x23c30,
1178                0x23c38, 0x23c38,
1179                0x23c80, 0x23c98,
1180                0x23ca0, 0x23ca8,
1181                0x23cb0, 0x23cc8,
1182                0x23cd0, 0x23cd4,
1183                0x23ce0, 0x23ce8,
1184                0x23cf0, 0x23cf0,
1185                0x23cf8, 0x23d7c,
1186                0x23e00, 0x23e04,
1187                0x24000, 0x2402c,
1188                0x24100, 0x2413c,
1189                0x24190, 0x241a0,
1190                0x241a8, 0x241b8,
1191                0x241c4, 0x241c8,
1192                0x24200, 0x24318,
1193                0x24400, 0x244b4,
1194                0x244c0, 0x24528,
1195                0x24540, 0x24614,
1196                0x25000, 0x25040,
1197                0x2504c, 0x25060,
1198                0x250c0, 0x250ec,
1199                0x25200, 0x25268,
1200                0x25270, 0x25284,
1201                0x252fc, 0x25388,
1202                0x25400, 0x25404,
1203                0x25500, 0x25500,
1204                0x25510, 0x25518,
1205                0x2552c, 0x25530,
1206                0x2553c, 0x2553c,
1207                0x25550, 0x25554,
1208                0x25600, 0x25600,
1209                0x25608, 0x2561c,
1210                0x25624, 0x25628,
1211                0x25630, 0x25634,
1212                0x2563c, 0x2563c,
1213                0x25700, 0x2571c,
1214                0x25780, 0x2578c,
1215                0x25800, 0x25818,
1216                0x25820, 0x25828,
1217                0x25830, 0x25848,
1218                0x25850, 0x25854,
1219                0x25860, 0x25868,
1220                0x25870, 0x25870,
1221                0x25878, 0x25898,
1222                0x258a0, 0x258a8,
1223                0x258b0, 0x258c8,
1224                0x258d0, 0x258d4,
1225                0x258e0, 0x258e8,
1226                0x258f0, 0x258f0,
1227                0x258f8, 0x25a18,
1228                0x25a20, 0x25a28,
1229                0x25a30, 0x25a48,
1230                0x25a50, 0x25a54,
1231                0x25a60, 0x25a68,
1232                0x25a70, 0x25a70,
1233                0x25a78, 0x25a98,
1234                0x25aa0, 0x25aa8,
1235                0x25ab0, 0x25ac8,
1236                0x25ad0, 0x25ad4,
1237                0x25ae0, 0x25ae8,
1238                0x25af0, 0x25af0,
1239                0x25af8, 0x25c18,
1240                0x25c20, 0x25c20,
1241                0x25c28, 0x25c30,
1242                0x25c38, 0x25c38,
1243                0x25c80, 0x25c98,
1244                0x25ca0, 0x25ca8,
1245                0x25cb0, 0x25cc8,
1246                0x25cd0, 0x25cd4,
1247                0x25ce0, 0x25ce8,
1248                0x25cf0, 0x25cf0,
1249                0x25cf8, 0x25d7c,
1250                0x25e00, 0x25e04,
1251                0x26000, 0x2602c,
1252                0x26100, 0x2613c,
1253                0x26190, 0x261a0,
1254                0x261a8, 0x261b8,
1255                0x261c4, 0x261c8,
1256                0x26200, 0x26318,
1257                0x26400, 0x264b4,
1258                0x264c0, 0x26528,
1259                0x26540, 0x26614,
1260                0x27000, 0x27040,
1261                0x2704c, 0x27060,
1262                0x270c0, 0x270ec,
1263                0x27200, 0x27268,
1264                0x27270, 0x27284,
1265                0x272fc, 0x27388,
1266                0x27400, 0x27404,
1267                0x27500, 0x27500,
1268                0x27510, 0x27518,
1269                0x2752c, 0x27530,
1270                0x2753c, 0x2753c,
1271                0x27550, 0x27554,
1272                0x27600, 0x27600,
1273                0x27608, 0x2761c,
1274                0x27624, 0x27628,
1275                0x27630, 0x27634,
1276                0x2763c, 0x2763c,
1277                0x27700, 0x2771c,
1278                0x27780, 0x2778c,
1279                0x27800, 0x27818,
1280                0x27820, 0x27828,
1281                0x27830, 0x27848,
1282                0x27850, 0x27854,
1283                0x27860, 0x27868,
1284                0x27870, 0x27870,
1285                0x27878, 0x27898,
1286                0x278a0, 0x278a8,
1287                0x278b0, 0x278c8,
1288                0x278d0, 0x278d4,
1289                0x278e0, 0x278e8,
1290                0x278f0, 0x278f0,
1291                0x278f8, 0x27a18,
1292                0x27a20, 0x27a28,
1293                0x27a30, 0x27a48,
1294                0x27a50, 0x27a54,
1295                0x27a60, 0x27a68,
1296                0x27a70, 0x27a70,
1297                0x27a78, 0x27a98,
1298                0x27aa0, 0x27aa8,
1299                0x27ab0, 0x27ac8,
1300                0x27ad0, 0x27ad4,
1301                0x27ae0, 0x27ae8,
1302                0x27af0, 0x27af0,
1303                0x27af8, 0x27c18,
1304                0x27c20, 0x27c20,
1305                0x27c28, 0x27c30,
1306                0x27c38, 0x27c38,
1307                0x27c80, 0x27c98,
1308                0x27ca0, 0x27ca8,
1309                0x27cb0, 0x27cc8,
1310                0x27cd0, 0x27cd4,
1311                0x27ce0, 0x27ce8,
1312                0x27cf0, 0x27cf0,
1313                0x27cf8, 0x27d7c,
1314                0x27e00, 0x27e04,
1315        };
1316
1317        static const unsigned int t5_reg_ranges[] = {
1318                0x1008, 0x10c0,
1319                0x10cc, 0x10f8,
1320                0x1100, 0x1100,
1321                0x110c, 0x1148,
1322                0x1180, 0x1184,
1323                0x1190, 0x1194,
1324                0x11a0, 0x11a4,
1325                0x11b0, 0x11b4,
1326                0x11fc, 0x123c,
1327                0x1280, 0x173c,
1328                0x1800, 0x18fc,
1329                0x3000, 0x3028,
1330                0x3060, 0x30b0,
1331                0x30b8, 0x30d8,
1332                0x30e0, 0x30fc,
1333                0x3140, 0x357c,
1334                0x35a8, 0x35cc,
1335                0x35ec, 0x35ec,
1336                0x3600, 0x5624,
1337                0x56cc, 0x56ec,
1338                0x56f4, 0x5720,
1339                0x5728, 0x575c,
1340                0x580c, 0x5814,
1341                0x5890, 0x589c,
1342                0x58a4, 0x58ac,
1343                0x58b8, 0x58bc,
1344                0x5940, 0x59c8,
1345                0x59d0, 0x59dc,
1346                0x59fc, 0x5a18,
1347                0x5a60, 0x5a70,
1348                0x5a80, 0x5a9c,
1349                0x5b94, 0x5bfc,
1350                0x6000, 0x6020,
1351                0x6028, 0x6040,
1352                0x6058, 0x609c,
1353                0x60a8, 0x614c,
1354                0x7700, 0x7798,
1355                0x77c0, 0x78fc,
1356                0x7b00, 0x7b58,
1357                0x7b60, 0x7b84,
1358                0x7b8c, 0x7c54,
1359                0x7d00, 0x7d38,
1360                0x7d40, 0x7d80,
1361                0x7d8c, 0x7ddc,
1362                0x7de4, 0x7e04,
1363                0x7e10, 0x7e1c,
1364                0x7e24, 0x7e38,
1365                0x7e40, 0x7e44,
1366                0x7e4c, 0x7e78,
1367                0x7e80, 0x7edc,
1368                0x7ee8, 0x7efc,
1369                0x8dc0, 0x8de0,
1370                0x8df8, 0x8e04,
1371                0x8e10, 0x8e84,
1372                0x8ea0, 0x8f84,
1373                0x8fc0, 0x9058,
1374                0x9060, 0x9060,
1375                0x9068, 0x90f8,
1376                0x9400, 0x9408,
1377                0x9410, 0x9470,
1378                0x9600, 0x9600,
1379                0x9608, 0x9638,
1380                0x9640, 0x96f4,
1381                0x9800, 0x9808,
1382                0x9810, 0x9864,
1383                0x9c00, 0x9c6c,
1384                0x9c80, 0x9cec,
1385                0x9d00, 0x9d6c,
1386                0x9d80, 0x9dec,
1387                0x9e00, 0x9e6c,
1388                0x9e80, 0x9eec,
1389                0x9f00, 0x9f6c,
1390                0x9f80, 0xa020,
1391                0xd000, 0xd004,
1392                0xd010, 0xd03c,
1393                0xdfc0, 0xdfe0,
1394                0xe000, 0x1106c,
1395                0x11074, 0x11088,
1396                0x1109c, 0x1117c,
1397                0x11190, 0x11204,
1398                0x19040, 0x1906c,
1399                0x19078, 0x19080,
1400                0x1908c, 0x190e8,
1401                0x190f0, 0x190f8,
1402                0x19100, 0x19110,
1403                0x19120, 0x19124,
1404                0x19150, 0x19194,
1405                0x1919c, 0x191b0,
1406                0x191d0, 0x191e8,
1407                0x19238, 0x19290,
1408                0x193f8, 0x19428,
1409                0x19430, 0x19444,
1410                0x1944c, 0x1946c,
1411                0x19474, 0x19474,
1412                0x19490, 0x194cc,
1413                0x194f0, 0x194f8,
1414                0x19c00, 0x19c08,
1415                0x19c10, 0x19c60,
1416                0x19c94, 0x19ce4,
1417                0x19cf0, 0x19d40,
1418                0x19d50, 0x19d94,
1419                0x19da0, 0x19de8,
1420                0x19df0, 0x19e10,
1421                0x19e50, 0x19e90,
1422                0x19ea0, 0x19f24,
1423                0x19f34, 0x19f34,
1424                0x19f40, 0x19f50,
1425                0x19f90, 0x19fb4,
1426                0x19fc4, 0x19fe4,
1427                0x1a000, 0x1a004,
1428                0x1a010, 0x1a06c,
1429                0x1a0b0, 0x1a0e4,
1430                0x1a0ec, 0x1a0f8,
1431                0x1a100, 0x1a108,
1432                0x1a114, 0x1a130,
1433                0x1a138, 0x1a1c4,
1434                0x1a1fc, 0x1a1fc,
1435                0x1e008, 0x1e00c,
1436                0x1e040, 0x1e044,
1437                0x1e04c, 0x1e04c,
1438                0x1e284, 0x1e290,
1439                0x1e2c0, 0x1e2c0,
1440                0x1e2e0, 0x1e2e0,
1441                0x1e300, 0x1e384,
1442                0x1e3c0, 0x1e3c8,
1443                0x1e408, 0x1e40c,
1444                0x1e440, 0x1e444,
1445                0x1e44c, 0x1e44c,
1446                0x1e684, 0x1e690,
1447                0x1e6c0, 0x1e6c0,
1448                0x1e6e0, 0x1e6e0,
1449                0x1e700, 0x1e784,
1450                0x1e7c0, 0x1e7c8,
1451                0x1e808, 0x1e80c,
1452                0x1e840, 0x1e844,
1453                0x1e84c, 0x1e84c,
1454                0x1ea84, 0x1ea90,
1455                0x1eac0, 0x1eac0,
1456                0x1eae0, 0x1eae0,
1457                0x1eb00, 0x1eb84,
1458                0x1ebc0, 0x1ebc8,
1459                0x1ec08, 0x1ec0c,
1460                0x1ec40, 0x1ec44,
1461                0x1ec4c, 0x1ec4c,
1462                0x1ee84, 0x1ee90,
1463                0x1eec0, 0x1eec0,
1464                0x1eee0, 0x1eee0,
1465                0x1ef00, 0x1ef84,
1466                0x1efc0, 0x1efc8,
1467                0x1f008, 0x1f00c,
1468                0x1f040, 0x1f044,
1469                0x1f04c, 0x1f04c,
1470                0x1f284, 0x1f290,
1471                0x1f2c0, 0x1f2c0,
1472                0x1f2e0, 0x1f2e0,
1473                0x1f300, 0x1f384,
1474                0x1f3c0, 0x1f3c8,
1475                0x1f408, 0x1f40c,
1476                0x1f440, 0x1f444,
1477                0x1f44c, 0x1f44c,
1478                0x1f684, 0x1f690,
1479                0x1f6c0, 0x1f6c0,
1480                0x1f6e0, 0x1f6e0,
1481                0x1f700, 0x1f784,
1482                0x1f7c0, 0x1f7c8,
1483                0x1f808, 0x1f80c,
1484                0x1f840, 0x1f844,
1485                0x1f84c, 0x1f84c,
1486                0x1fa84, 0x1fa90,
1487                0x1fac0, 0x1fac0,
1488                0x1fae0, 0x1fae0,
1489                0x1fb00, 0x1fb84,
1490                0x1fbc0, 0x1fbc8,
1491                0x1fc08, 0x1fc0c,
1492                0x1fc40, 0x1fc44,
1493                0x1fc4c, 0x1fc4c,
1494                0x1fe84, 0x1fe90,
1495                0x1fec0, 0x1fec0,
1496                0x1fee0, 0x1fee0,
1497                0x1ff00, 0x1ff84,
1498                0x1ffc0, 0x1ffc8,
1499                0x30000, 0x30030,
1500                0x30100, 0x30144,
1501                0x30190, 0x301a0,
1502                0x301a8, 0x301b8,
1503                0x301c4, 0x301c8,
1504                0x301d0, 0x301d0,
1505                0x30200, 0x30318,
1506                0x30400, 0x304b4,
1507                0x304c0, 0x3052c,
1508                0x30540, 0x3061c,
1509                0x30800, 0x30828,
1510                0x30834, 0x30834,
1511                0x308c0, 0x30908,
1512                0x30910, 0x309ac,
1513                0x30a00, 0x30a14,
1514                0x30a1c, 0x30a2c,
1515                0x30a44, 0x30a50,
1516                0x30a74, 0x30a74,
1517                0x30a7c, 0x30afc,
1518                0x30b08, 0x30c24,
1519                0x30d00, 0x30d00,
1520                0x30d08, 0x30d14,
1521                0x30d1c, 0x30d20,
1522                0x30d3c, 0x30d3c,
1523                0x30d48, 0x30d50,
1524                0x31200, 0x3120c,
1525                0x31220, 0x31220,
1526                0x31240, 0x31240,
1527                0x31600, 0x3160c,
1528                0x31a00, 0x31a1c,
1529                0x31e00, 0x31e20,
1530                0x31e38, 0x31e3c,
1531                0x31e80, 0x31e80,
1532                0x31e88, 0x31ea8,
1533                0x31eb0, 0x31eb4,
1534                0x31ec8, 0x31ed4,
1535                0x31fb8, 0x32004,
1536                0x32200, 0x32200,
1537                0x32208, 0x32240,
1538                0x32248, 0x32280,
1539                0x32288, 0x322c0,
1540                0x322c8, 0x322fc,
1541                0x32600, 0x32630,
1542                0x32a00, 0x32abc,
1543                0x32b00, 0x32b10,
1544                0x32b20, 0x32b30,
1545                0x32b40, 0x32b50,
1546                0x32b60, 0x32b70,
1547                0x33000, 0x33028,
1548                0x33030, 0x33048,
1549                0x33060, 0x33068,
1550                0x33070, 0x3309c,
1551                0x330f0, 0x33128,
1552                0x33130, 0x33148,
1553                0x33160, 0x33168,
1554                0x33170, 0x3319c,
1555                0x331f0, 0x33238,
1556                0x33240, 0x33240,
1557                0x33248, 0x33250,
1558                0x3325c, 0x33264,
1559                0x33270, 0x332b8,
1560                0x332c0, 0x332e4,
1561                0x332f8, 0x33338,
1562                0x33340, 0x33340,
1563                0x33348, 0x33350,
1564                0x3335c, 0x33364,
1565                0x33370, 0x333b8,
1566                0x333c0, 0x333e4,
1567                0x333f8, 0x33428,
1568                0x33430, 0x33448,
1569                0x33460, 0x33468,
1570                0x33470, 0x3349c,
1571                0x334f0, 0x33528,
1572                0x33530, 0x33548,
1573                0x33560, 0x33568,
1574                0x33570, 0x3359c,
1575                0x335f0, 0x33638,
1576                0x33640, 0x33640,
1577                0x33648, 0x33650,
1578                0x3365c, 0x33664,
1579                0x33670, 0x336b8,
1580                0x336c0, 0x336e4,
1581                0x336f8, 0x33738,
1582                0x33740, 0x33740,
1583                0x33748, 0x33750,
1584                0x3375c, 0x33764,
1585                0x33770, 0x337b8,
1586                0x337c0, 0x337e4,
1587                0x337f8, 0x337fc,
1588                0x33814, 0x33814,
1589                0x3382c, 0x3382c,
1590                0x33880, 0x3388c,
1591                0x338e8, 0x338ec,
1592                0x33900, 0x33928,
1593                0x33930, 0x33948,
1594                0x33960, 0x33968,
1595                0x33970, 0x3399c,
1596                0x339f0, 0x33a38,
1597                0x33a40, 0x33a40,
1598                0x33a48, 0x33a50,
1599                0x33a5c, 0x33a64,
1600                0x33a70, 0x33ab8,
1601                0x33ac0, 0x33ae4,
1602                0x33af8, 0x33b10,
1603                0x33b28, 0x33b28,
1604                0x33b3c, 0x33b50,
1605                0x33bf0, 0x33c10,
1606                0x33c28, 0x33c28,
1607                0x33c3c, 0x33c50,
1608                0x33cf0, 0x33cfc,
1609                0x34000, 0x34030,
1610                0x34100, 0x34144,
1611                0x34190, 0x341a0,
1612                0x341a8, 0x341b8,
1613                0x341c4, 0x341c8,
1614                0x341d0, 0x341d0,
1615                0x34200, 0x34318,
1616                0x34400, 0x344b4,
1617                0x344c0, 0x3452c,
1618                0x34540, 0x3461c,
1619                0x34800, 0x34828,
1620                0x34834, 0x34834,
1621                0x348c0, 0x34908,
1622                0x34910, 0x349ac,
1623                0x34a00, 0x34a14,
1624                0x34a1c, 0x34a2c,
1625                0x34a44, 0x34a50,
1626                0x34a74, 0x34a74,
1627                0x34a7c, 0x34afc,
1628                0x34b08, 0x34c24,
1629                0x34d00, 0x34d00,
1630                0x34d08, 0x34d14,
1631                0x34d1c, 0x34d20,
1632                0x34d3c, 0x34d3c,
1633                0x34d48, 0x34d50,
1634                0x35200, 0x3520c,
1635                0x35220, 0x35220,
1636                0x35240, 0x35240,
1637                0x35600, 0x3560c,
1638                0x35a00, 0x35a1c,
1639                0x35e00, 0x35e20,
1640                0x35e38, 0x35e3c,
1641                0x35e80, 0x35e80,
1642                0x35e88, 0x35ea8,
1643                0x35eb0, 0x35eb4,
1644                0x35ec8, 0x35ed4,
1645                0x35fb8, 0x36004,
1646                0x36200, 0x36200,
1647                0x36208, 0x36240,
1648                0x36248, 0x36280,
1649                0x36288, 0x362c0,
1650                0x362c8, 0x362fc,
1651                0x36600, 0x36630,
1652                0x36a00, 0x36abc,
1653                0x36b00, 0x36b10,
1654                0x36b20, 0x36b30,
1655                0x36b40, 0x36b50,
1656                0x36b60, 0x36b70,
1657                0x37000, 0x37028,
1658                0x37030, 0x37048,
1659                0x37060, 0x37068,
1660                0x37070, 0x3709c,
1661                0x370f0, 0x37128,
1662                0x37130, 0x37148,
1663                0x37160, 0x37168,
1664                0x37170, 0x3719c,
1665                0x371f0, 0x37238,
1666                0x37240, 0x37240,
1667                0x37248, 0x37250,
1668                0x3725c, 0x37264,
1669                0x37270, 0x372b8,
1670                0x372c0, 0x372e4,
1671                0x372f8, 0x37338,
1672                0x37340, 0x37340,
1673                0x37348, 0x37350,
1674                0x3735c, 0x37364,
1675                0x37370, 0x373b8,
1676                0x373c0, 0x373e4,
1677                0x373f8, 0x37428,
1678                0x37430, 0x37448,
1679                0x37460, 0x37468,
1680                0x37470, 0x3749c,
1681                0x374f0, 0x37528,
1682                0x37530, 0x37548,
1683                0x37560, 0x37568,
1684                0x37570, 0x3759c,
1685                0x375f0, 0x37638,
1686                0x37640, 0x37640,
1687                0x37648, 0x37650,
1688                0x3765c, 0x37664,
1689                0x37670, 0x376b8,
1690                0x376c0, 0x376e4,
1691                0x376f8, 0x37738,
1692                0x37740, 0x37740,
1693                0x37748, 0x37750,
1694                0x3775c, 0x37764,
1695                0x37770, 0x377b8,
1696                0x377c0, 0x377e4,
1697                0x377f8, 0x377fc,
1698                0x37814, 0x37814,
1699                0x3782c, 0x3782c,
1700                0x37880, 0x3788c,
1701                0x378e8, 0x378ec,
1702                0x37900, 0x37928,
1703                0x37930, 0x37948,
1704                0x37960, 0x37968,
1705                0x37970, 0x3799c,
1706                0x379f0, 0x37a38,
1707                0x37a40, 0x37a40,
1708                0x37a48, 0x37a50,
1709                0x37a5c, 0x37a64,
1710                0x37a70, 0x37ab8,
1711                0x37ac0, 0x37ae4,
1712                0x37af8, 0x37b10,
1713                0x37b28, 0x37b28,
1714                0x37b3c, 0x37b50,
1715                0x37bf0, 0x37c10,
1716                0x37c28, 0x37c28,
1717                0x37c3c, 0x37c50,
1718                0x37cf0, 0x37cfc,
1719                0x38000, 0x38030,
1720                0x38100, 0x38144,
1721                0x38190, 0x381a0,
1722                0x381a8, 0x381b8,
1723                0x381c4, 0x381c8,
1724                0x381d0, 0x381d0,
1725                0x38200, 0x38318,
1726                0x38400, 0x384b4,
1727                0x384c0, 0x3852c,
1728                0x38540, 0x3861c,
1729                0x38800, 0x38828,
1730                0x38834, 0x38834,
1731                0x388c0, 0x38908,
1732                0x38910, 0x389ac,
1733                0x38a00, 0x38a14,
1734                0x38a1c, 0x38a2c,
1735                0x38a44, 0x38a50,
1736                0x38a74, 0x38a74,
1737                0x38a7c, 0x38afc,
1738                0x38b08, 0x38c24,
1739                0x38d00, 0x38d00,
1740                0x38d08, 0x38d14,
1741                0x38d1c, 0x38d20,
1742                0x38d3c, 0x38d3c,
1743                0x38d48, 0x38d50,
1744                0x39200, 0x3920c,
1745                0x39220, 0x39220,
1746                0x39240, 0x39240,
1747                0x39600, 0x3960c,
1748                0x39a00, 0x39a1c,
1749                0x39e00, 0x39e20,
1750                0x39e38, 0x39e3c,
1751                0x39e80, 0x39e80,
1752                0x39e88, 0x39ea8,
1753                0x39eb0, 0x39eb4,
1754                0x39ec8, 0x39ed4,
1755                0x39fb8, 0x3a004,
1756                0x3a200, 0x3a200,
1757                0x3a208, 0x3a240,
1758                0x3a248, 0x3a280,
1759                0x3a288, 0x3a2c0,
1760                0x3a2c8, 0x3a2fc,
1761                0x3a600, 0x3a630,
1762                0x3aa00, 0x3aabc,
1763                0x3ab00, 0x3ab10,
1764                0x3ab20, 0x3ab30,
1765                0x3ab40, 0x3ab50,
1766                0x3ab60, 0x3ab70,
1767                0x3b000, 0x3b028,
1768                0x3b030, 0x3b048,
1769                0x3b060, 0x3b068,
1770                0x3b070, 0x3b09c,
1771                0x3b0f0, 0x3b128,
1772                0x3b130, 0x3b148,
1773                0x3b160, 0x3b168,
1774                0x3b170, 0x3b19c,
1775                0x3b1f0, 0x3b238,
1776                0x3b240, 0x3b240,
1777                0x3b248, 0x3b250,
1778                0x3b25c, 0x3b264,
1779                0x3b270, 0x3b2b8,
1780                0x3b2c0, 0x3b2e4,
1781                0x3b2f8, 0x3b338,
1782                0x3b340, 0x3b340,
1783                0x3b348, 0x3b350,
1784                0x3b35c, 0x3b364,
1785                0x3b370, 0x3b3b8,
1786                0x3b3c0, 0x3b3e4,
1787                0x3b3f8, 0x3b428,
1788                0x3b430, 0x3b448,
1789                0x3b460, 0x3b468,
1790                0x3b470, 0x3b49c,
1791                0x3b4f0, 0x3b528,
1792                0x3b530, 0x3b548,
1793                0x3b560, 0x3b568,
1794                0x3b570, 0x3b59c,
1795                0x3b5f0, 0x3b638,
1796                0x3b640, 0x3b640,
1797                0x3b648, 0x3b650,
1798                0x3b65c, 0x3b664,
1799                0x3b670, 0x3b6b8,
1800                0x3b6c0, 0x3b6e4,
1801                0x3b6f8, 0x3b738,
1802                0x3b740, 0x3b740,
1803                0x3b748, 0x3b750,
1804                0x3b75c, 0x3b764,
1805                0x3b770, 0x3b7b8,
1806                0x3b7c0, 0x3b7e4,
1807                0x3b7f8, 0x3b7fc,
1808                0x3b814, 0x3b814,
1809                0x3b82c, 0x3b82c,
1810                0x3b880, 0x3b88c,
1811                0x3b8e8, 0x3b8ec,
1812                0x3b900, 0x3b928,
1813                0x3b930, 0x3b948,
1814                0x3b960, 0x3b968,
1815                0x3b970, 0x3b99c,
1816                0x3b9f0, 0x3ba38,
1817                0x3ba40, 0x3ba40,
1818                0x3ba48, 0x3ba50,
1819                0x3ba5c, 0x3ba64,
1820                0x3ba70, 0x3bab8,
1821                0x3bac0, 0x3bae4,
1822                0x3baf8, 0x3bb10,
1823                0x3bb28, 0x3bb28,
1824                0x3bb3c, 0x3bb50,
1825                0x3bbf0, 0x3bc10,
1826                0x3bc28, 0x3bc28,
1827                0x3bc3c, 0x3bc50,
1828                0x3bcf0, 0x3bcfc,
1829                0x3c000, 0x3c030,
1830                0x3c100, 0x3c144,
1831                0x3c190, 0x3c1a0,
1832                0x3c1a8, 0x3c1b8,
1833                0x3c1c4, 0x3c1c8,
1834                0x3c1d0, 0x3c1d0,
1835                0x3c200, 0x3c318,
1836                0x3c400, 0x3c4b4,
1837                0x3c4c0, 0x3c52c,
1838                0x3c540, 0x3c61c,
1839                0x3c800, 0x3c828,
1840                0x3c834, 0x3c834,
1841                0x3c8c0, 0x3c908,
1842                0x3c910, 0x3c9ac,
1843                0x3ca00, 0x3ca14,
1844                0x3ca1c, 0x3ca2c,
1845                0x3ca44, 0x3ca50,
1846                0x3ca74, 0x3ca74,
1847                0x3ca7c, 0x3cafc,
1848                0x3cb08, 0x3cc24,
1849                0x3cd00, 0x3cd00,
1850                0x3cd08, 0x3cd14,
1851                0x3cd1c, 0x3cd20,
1852                0x3cd3c, 0x3cd3c,
1853                0x3cd48, 0x3cd50,
1854                0x3d200, 0x3d20c,
1855                0x3d220, 0x3d220,
1856                0x3d240, 0x3d240,
1857                0x3d600, 0x3d60c,
1858                0x3da00, 0x3da1c,
1859                0x3de00, 0x3de20,
1860                0x3de38, 0x3de3c,
1861                0x3de80, 0x3de80,
1862                0x3de88, 0x3dea8,
1863                0x3deb0, 0x3deb4,
1864                0x3dec8, 0x3ded4,
1865                0x3dfb8, 0x3e004,
1866                0x3e200, 0x3e200,
1867                0x3e208, 0x3e240,
1868                0x3e248, 0x3e280,
1869                0x3e288, 0x3e2c0,
1870                0x3e2c8, 0x3e2fc,
1871                0x3e600, 0x3e630,
1872                0x3ea00, 0x3eabc,
1873                0x3eb00, 0x3eb10,
1874                0x3eb20, 0x3eb30,
1875                0x3eb40, 0x3eb50,
1876                0x3eb60, 0x3eb70,
1877                0x3f000, 0x3f028,
1878                0x3f030, 0x3f048,
1879                0x3f060, 0x3f068,
1880                0x3f070, 0x3f09c,
1881                0x3f0f0, 0x3f128,
1882                0x3f130, 0x3f148,
1883                0x3f160, 0x3f168,
1884                0x3f170, 0x3f19c,
1885                0x3f1f0, 0x3f238,
1886                0x3f240, 0x3f240,
1887                0x3f248, 0x3f250,
1888                0x3f25c, 0x3f264,
1889                0x3f270, 0x3f2b8,
1890                0x3f2c0, 0x3f2e4,
1891                0x3f2f8, 0x3f338,
1892                0x3f340, 0x3f340,
1893                0x3f348, 0x3f350,
1894                0x3f35c, 0x3f364,
1895                0x3f370, 0x3f3b8,
1896                0x3f3c0, 0x3f3e4,
1897                0x3f3f8, 0x3f428,
1898                0x3f430, 0x3f448,
1899                0x3f460, 0x3f468,
1900                0x3f470, 0x3f49c,
1901                0x3f4f0, 0x3f528,
1902                0x3f530, 0x3f548,
1903                0x3f560, 0x3f568,
1904                0x3f570, 0x3f59c,
1905                0x3f5f0, 0x3f638,
1906                0x3f640, 0x3f640,
1907                0x3f648, 0x3f650,
1908                0x3f65c, 0x3f664,
1909                0x3f670, 0x3f6b8,
1910                0x3f6c0, 0x3f6e4,
1911                0x3f6f8, 0x3f738,
1912                0x3f740, 0x3f740,
1913                0x3f748, 0x3f750,
1914                0x3f75c, 0x3f764,
1915                0x3f770, 0x3f7b8,
1916                0x3f7c0, 0x3f7e4,
1917                0x3f7f8, 0x3f7fc,
1918                0x3f814, 0x3f814,
1919                0x3f82c, 0x3f82c,
1920                0x3f880, 0x3f88c,
1921                0x3f8e8, 0x3f8ec,
1922                0x3f900, 0x3f928,
1923                0x3f930, 0x3f948,
1924                0x3f960, 0x3f968,
1925                0x3f970, 0x3f99c,
1926                0x3f9f0, 0x3fa38,
1927                0x3fa40, 0x3fa40,
1928                0x3fa48, 0x3fa50,
1929                0x3fa5c, 0x3fa64,
1930                0x3fa70, 0x3fab8,
1931                0x3fac0, 0x3fae4,
1932                0x3faf8, 0x3fb10,
1933                0x3fb28, 0x3fb28,
1934                0x3fb3c, 0x3fb50,
1935                0x3fbf0, 0x3fc10,
1936                0x3fc28, 0x3fc28,
1937                0x3fc3c, 0x3fc50,
1938                0x3fcf0, 0x3fcfc,
1939                0x40000, 0x4000c,
1940                0x40040, 0x40050,
1941                0x40060, 0x40068,
1942                0x4007c, 0x4008c,
1943                0x40094, 0x400b0,
1944                0x400c0, 0x40144,
1945                0x40180, 0x4018c,
1946                0x40200, 0x40254,
1947                0x40260, 0x40264,
1948                0x40270, 0x40288,
1949                0x40290, 0x40298,
1950                0x402ac, 0x402c8,
1951                0x402d0, 0x402e0,
1952                0x402f0, 0x402f0,
1953                0x40300, 0x4033c,
1954                0x403f8, 0x403fc,
1955                0x41304, 0x413c4,
1956                0x41400, 0x4140c,
1957                0x41414, 0x4141c,
1958                0x41480, 0x414d0,
1959                0x44000, 0x44054,
1960                0x4405c, 0x44078,
1961                0x440c0, 0x44174,
1962                0x44180, 0x441ac,
1963                0x441b4, 0x441b8,
1964                0x441c0, 0x44254,
1965                0x4425c, 0x44278,
1966                0x442c0, 0x44374,
1967                0x44380, 0x443ac,
1968                0x443b4, 0x443b8,
1969                0x443c0, 0x44454,
1970                0x4445c, 0x44478,
1971                0x444c0, 0x44574,
1972                0x44580, 0x445ac,
1973                0x445b4, 0x445b8,
1974                0x445c0, 0x44654,
1975                0x4465c, 0x44678,
1976                0x446c0, 0x44774,
1977                0x44780, 0x447ac,
1978                0x447b4, 0x447b8,
1979                0x447c0, 0x44854,
1980                0x4485c, 0x44878,
1981                0x448c0, 0x44974,
1982                0x44980, 0x449ac,
1983                0x449b4, 0x449b8,
1984                0x449c0, 0x449fc,
1985                0x45000, 0x45004,
1986                0x45010, 0x45030,
1987                0x45040, 0x45060,
1988                0x45068, 0x45068,
1989                0x45080, 0x45084,
1990                0x450a0, 0x450b0,
1991                0x45200, 0x45204,
1992                0x45210, 0x45230,
1993                0x45240, 0x45260,
1994                0x45268, 0x45268,
1995                0x45280, 0x45284,
1996                0x452a0, 0x452b0,
1997                0x460c0, 0x460e4,
1998                0x47000, 0x4703c,
1999                0x47044, 0x4708c,
2000                0x47200, 0x47250,

2001                0x47400, 0x47408,
2002                0x47414, 0x47420,
2003                0x47600, 0x47618,
2004                0x47800, 0x47814,
2005                0x48000, 0x4800c,
2006                0x48040, 0x48050,
2007                0x48060, 0x48068,
2008                0x4807c, 0x4808c,
2009                0x48094, 0x480b0,
2010                0x480c0, 0x48144,
2011                0x48180, 0x4818c,
2012                0x48200, 0x48254,
2013                0x48260, 0x48264,
2014                0x48270, 0x48288,
2015                0x48290, 0x48298,
2016                0x482ac, 0x482c8,
2017                0x482d0, 0x482e0,
2018                0x482f0, 0x482f0,
2019                0x48300, 0x4833c,
2020                0x483f8, 0x483fc,
2021                0x49304, 0x493c4,
2022                0x49400, 0x4940c,
2023                0x49414, 0x4941c,
2024                0x49480, 0x494d0,
2025                0x4c000, 0x4c054,
2026                0x4c05c, 0x4c078,
2027                0x4c0c0, 0x4c174,
2028                0x4c180, 0x4c1ac,
2029                0x4c1b4, 0x4c1b8,
2030                0x4c1c0, 0x4c254,
2031                0x4c25c, 0x4c278,
2032                0x4c2c0, 0x4c374,
2033                0x4c380, 0x4c3ac,
2034                0x4c3b4, 0x4c3b8,
2035                0x4c3c0, 0x4c454,
2036                0x4c45c, 0x4c478,
2037                0x4c4c0, 0x4c574,
2038                0x4c580, 0x4c5ac,
2039                0x4c5b4, 0x4c5b8,
2040                0x4c5c0, 0x4c654,
2041                0x4c65c, 0x4c678,
2042                0x4c6c0, 0x4c774,
2043                0x4c780, 0x4c7ac,
2044                0x4c7b4, 0x4c7b8,
2045                0x4c7c0, 0x4c854,
2046                0x4c85c, 0x4c878,
2047                0x4c8c0, 0x4c974,
2048                0x4c980, 0x4c9ac,
2049                0x4c9b4, 0x4c9b8,
2050                0x4c9c0, 0x4c9fc,
2051                0x4d000, 0x4d004,
2052                0x4d010, 0x4d030,
2053                0x4d040, 0x4d060,
2054                0x4d068, 0x4d068,
2055                0x4d080, 0x4d084,
2056                0x4d0a0, 0x4d0b0,
2057                0x4d200, 0x4d204,
2058                0x4d210, 0x4d230,
2059                0x4d240, 0x4d260,
2060                0x4d268, 0x4d268,
2061                0x4d280, 0x4d284,
2062                0x4d2a0, 0x4d2b0,
2063                0x4e0c0, 0x4e0e4,
2064                0x4f000, 0x4f03c,
2065                0x4f044, 0x4f08c,
2066                0x4f200, 0x4f250,
2067                0x4f400, 0x4f408,
2068                0x4f414, 0x4f420,
2069                0x4f600, 0x4f618,
2070                0x4f800, 0x4f814,
2071                0x50000, 0x50084,
2072                0x50090, 0x500cc,
2073                0x50400, 0x50400,
2074                0x50800, 0x50884,
2075                0x50890, 0x508cc,
2076                0x50c00, 0x50c00,
2077                0x51000, 0x5101c,
2078                0x51300, 0x51308,
2079        };
2080
2081        static const unsigned int t6_reg_ranges[] = {
2082                0x1008, 0x101c,
2083                0x1024, 0x10a8,
2084                0x10b4, 0x10f8,
2085                0x1100, 0x1114,
2086                0x111c, 0x112c,
2087                0x1138, 0x113c,
2088                0x1144, 0x114c,
2089                0x1180, 0x1184,
2090                0x1190, 0x1194,
2091                0x11a0, 0x11a4,
2092                0x11b0, 0x11b4,
2093                0x11fc, 0x123c,
2094                0x1254, 0x1274,
2095                0x1280, 0x133c,
2096                0x1800, 0x18fc,
2097                0x3000, 0x302c,
2098                0x3060, 0x30b0,
2099                0x30b8, 0x30d8,
2100                0x30e0, 0x30fc,
2101                0x3140, 0x357c,
2102                0x35a8, 0x35cc,
2103                0x35ec, 0x35ec,
2104                0x3600, 0x5624,
2105                0x56cc, 0x56ec,
2106                0x56f4, 0x5720,
2107                0x5728, 0x575c,
2108                0x580c, 0x5814,
2109                0x5890, 0x589c,
2110                0x58a4, 0x58ac,
2111                0x58b8, 0x58bc,
2112                0x5940, 0x595c,
2113                0x5980, 0x598c,
2114                0x59b0, 0x59c8,
2115                0x59d0, 0x59dc,
2116                0x59fc, 0x5a18,
2117                0x5a60, 0x5a6c,
2118                0x5a80, 0x5a8c,
2119                0x5a94, 0x5a9c,
2120                0x5b94, 0x5bfc,
2121                0x5c10, 0x5e48,
2122                0x5e50, 0x5e94,
2123                0x5ea0, 0x5eb0,
2124                0x5ec0, 0x5ec0,
2125                0x5ec8, 0x5ed0,
2126                0x5ee0, 0x5ee0,
2127                0x5ef0, 0x5ef0,
2128                0x5f00, 0x5f00,
2129                0x6000, 0x6020,
2130                0x6028, 0x6040,
2131                0x6058, 0x609c,
2132                0x60a8, 0x619c,
2133                0x7700, 0x7798,
2134                0x77c0, 0x7880,
2135                0x78cc, 0x78fc,
2136                0x7b00, 0x7b58,
2137                0x7b60, 0x7b84,
2138                0x7b8c, 0x7c54,
2139                0x7d00, 0x7d38,
2140                0x7d40, 0x7d84,
2141                0x7d8c, 0x7ddc,
2142                0x7de4, 0x7e04,
2143                0x7e10, 0x7e1c,
2144                0x7e24, 0x7e38,
2145                0x7e40, 0x7e44,
2146                0x7e4c, 0x7e78,
2147                0x7e80, 0x7edc,
2148                0x7ee8, 0x7efc,
2149                0x8dc0, 0x8de4,
2150                0x8df8, 0x8e04,
2151                0x8e10, 0x8e84,
2152                0x8ea0, 0x8f88,
2153                0x8fb8, 0x9058,
2154                0x9060, 0x9060,
2155                0x9068, 0x90f8,
2156                0x9100, 0x9124,
2157                0x9400, 0x9470,
2158                0x9600, 0x9600,
2159                0x9608, 0x9638,
2160                0x9640, 0x9704,
2161                0x9710, 0x971c,
2162                0x9800, 0x9808,
2163                0x9810, 0x9864,
2164                0x9c00, 0x9c6c,
2165                0x9c80, 0x9cec,
2166                0x9d00, 0x9d6c,
2167                0x9d80, 0x9dec,
2168                0x9e00, 0x9e6c,
2169                0x9e80, 0x9eec,
2170                0x9f00, 0x9f6c,
2171                0x9f80, 0xa020,
2172                0xd000, 0xd03c,
2173                0xd100, 0xd118,
2174                0xd200, 0xd214,
2175                0xd220, 0xd234,
2176                0xd240, 0xd254,
2177                0xd260, 0xd274,
2178                0xd280, 0xd294,
2179                0xd2a0, 0xd2b4,
2180                0xd2c0, 0xd2d4,
2181                0xd2e0, 0xd2f4,
2182                0xd300, 0xd31c,
2183                0xdfc0, 0xdfe0,
2184                0xe000, 0xf008,
2185                0xf010, 0xf018,
2186                0xf020, 0xf028,
2187                0x11000, 0x11014,
2188                0x11048, 0x1106c,
2189                0x11074, 0x11088,
2190                0x11098, 0x11120,
2191                0x1112c, 0x1117c,
2192                0x11190, 0x112e0,
2193                0x11300, 0x1130c,
2194                0x12000, 0x1206c,
2195                0x19040, 0x1906c,
2196                0x19078, 0x19080,
2197                0x1908c, 0x190e8,
2198                0x190f0, 0x190f8,
2199                0x19100, 0x19110,
2200                0x19120, 0x19124,
2201                0x19150, 0x19194,
2202                0x1919c, 0x191b0,
2203                0x191d0, 0x191e8,
2204                0x19238, 0x19290,
2205                0x192a4, 0x192b0,
2206                0x192bc, 0x192bc,
2207                0x19348, 0x1934c,
2208                0x193f8, 0x19418,
2209                0x19420, 0x19428,
2210                0x19430, 0x19444,
2211                0x1944c, 0x1946c,
2212                0x19474, 0x19474,
2213                0x19490, 0x194cc,
2214                0x194f0, 0x194f8,
2215                0x19c00, 0x19c48,
2216                0x19c50, 0x19c80,
2217                0x19c94, 0x19c98,
2218                0x19ca0, 0x19cbc,
2219                0x19ce4, 0x19ce4,
2220                0x19cf0, 0x19cf8,
2221                0x19d00, 0x19d28,
2222                0x19d50, 0x19d78,
2223                0x19d94, 0x19d98,
2224                0x19da0, 0x19dc8,
2225                0x19df0, 0x19e10,
2226                0x19e50, 0x19e6c,
2227                0x19ea0, 0x19ebc,
2228                0x19ec4, 0x19ef4,
2229                0x19f04, 0x19f2c,
2230                0x19f34, 0x19f34,
2231                0x19f40, 0x19f50,
2232                0x19f90, 0x19fac,
2233                0x19fc4, 0x19fc8,
2234                0x19fd0, 0x19fe4,
2235                0x1a000, 0x1a004,
2236                0x1a010, 0x1a06c,
2237                0x1a0b0, 0x1a0e4,
2238                0x1a0ec, 0x1a0f8,
2239                0x1a100, 0x1a108,
2240                0x1a114, 0x1a130,
2241                0x1a138, 0x1a1c4,
2242                0x1a1fc, 0x1a1fc,
2243                0x1e008, 0x1e00c,
2244                0x1e040, 0x1e044,
2245                0x1e04c, 0x1e04c,
2246                0x1e284, 0x1e290,
2247                0x1e2c0, 0x1e2c0,
2248                0x1e2e0, 0x1e2e0,
2249                0x1e300, 0x1e384,
2250                0x1e3c0, 0x1e3c8,
2251                0x1e408, 0x1e40c,
2252                0x1e440, 0x1e444,
2253                0x1e44c, 0x1e44c,
2254                0x1e684, 0x1e690,
2255                0x1e6c0, 0x1e6c0,
2256                0x1e6e0, 0x1e6e0,
2257                0x1e700, 0x1e784,
2258                0x1e7c0, 0x1e7c8,
2259                0x1e808, 0x1e80c,
2260                0x1e840, 0x1e844,
2261                0x1e84c, 0x1e84c,
2262                0x1ea84, 0x1ea90,
2263                0x1eac0, 0x1eac0,
2264                0x1eae0, 0x1eae0,
2265                0x1eb00, 0x1eb84,
2266                0x1ebc0, 0x1ebc8,
2267                0x1ec08, 0x1ec0c,
2268                0x1ec40, 0x1ec44,
2269                0x1ec4c, 0x1ec4c,
2270                0x1ee84, 0x1ee90,
2271                0x1eec0, 0x1eec0,
2272                0x1eee0, 0x1eee0,
2273                0x1ef00, 0x1ef84,
2274                0x1efc0, 0x1efc8,
2275                0x1f008, 0x1f00c,
2276                0x1f040, 0x1f044,
2277                0x1f04c, 0x1f04c,
2278                0x1f284, 0x1f290,
2279                0x1f2c0, 0x1f2c0,
2280                0x1f2e0, 0x1f2e0,
2281                0x1f300, 0x1f384,
2282                0x1f3c0, 0x1f3c8,
2283                0x1f408, 0x1f40c,
2284                0x1f440, 0x1f444,
2285                0x1f44c, 0x1f44c,
2286                0x1f684, 0x1f690,
2287                0x1f6c0, 0x1f6c0,
2288                0x1f6e0, 0x1f6e0,
2289                0x1f700, 0x1f784,
2290                0x1f7c0, 0x1f7c8,
2291                0x1f808, 0x1f80c,
2292                0x1f840, 0x1f844,
2293                0x1f84c, 0x1f84c,
2294                0x1fa84, 0x1fa90,
2295                0x1fac0, 0x1fac0,
2296                0x1fae0, 0x1fae0,
2297                0x1fb00, 0x1fb84,
2298                0x1fbc0, 0x1fbc8,
2299                0x1fc08, 0x1fc0c,
2300                0x1fc40, 0x1fc44,
2301                0x1fc4c, 0x1fc4c,
2302                0x1fe84, 0x1fe90,
2303                0x1fec0, 0x1fec0,
2304                0x1fee0, 0x1fee0,
2305                0x1ff00, 0x1ff84,
2306                0x1ffc0, 0x1ffc8,
2307                0x30000, 0x30030,
2308                0x30100, 0x30168,
2309                0x30190, 0x301a0,
2310                0x301a8, 0x301b8,
2311                0x301c4, 0x301c8,
2312                0x301d0, 0x301d0,
2313                0x30200, 0x30320,
2314                0x30400, 0x304b4,
2315                0x304c0, 0x3052c,
2316                0x30540, 0x3061c,
2317                0x30800, 0x308a0,
2318                0x308c0, 0x30908,
2319                0x30910, 0x309b8,
2320                0x30a00, 0x30a04,
2321                0x30a0c, 0x30a14,
2322                0x30a1c, 0x30a2c,
2323                0x30a44, 0x30a50,
2324                0x30a74, 0x30a74,
2325                0x30a7c, 0x30afc,
2326                0x30b08, 0x30c24,
2327                0x30d00, 0x30d14,
2328                0x30d1c, 0x30d3c,
2329                0x30d44, 0x30d4c,
2330                0x30d54, 0x30d74,
2331                0x30d7c, 0x30d7c,
2332                0x30de0, 0x30de0,
2333                0x30e00, 0x30ed4,
2334                0x30f00, 0x30fa4,
2335                0x30fc0, 0x30fc4,
2336                0x31000, 0x31004,
2337                0x31080, 0x310fc,
2338                0x31208, 0x31220,
2339                0x3123c, 0x31254,
2340                0x31300, 0x31300,
2341                0x31308, 0x3131c,
2342                0x31338, 0x3133c,
2343                0x31380, 0x31380,
2344                0x31388, 0x313a8,
2345                0x313b4, 0x313b4,
2346                0x31400, 0x31420,
2347                0x31438, 0x3143c,
2348                0x31480, 0x31480,
2349                0x314a8, 0x314a8,
2350                0x314b0, 0x314b4,
2351                0x314c8, 0x314d4,
2352                0x31a40, 0x31a4c,
2353                0x31af0, 0x31b20,
2354                0x31b38, 0x31b3c,
2355                0x31b80, 0x31b80,
2356                0x31ba8, 0x31ba8,
2357                0x31bb0, 0x31bb4,
2358                0x31bc8, 0x31bd4,
2359                0x32140, 0x3218c,
2360                0x321f0, 0x321f4,
2361                0x32200, 0x32200,
2362                0x32218, 0x32218,
2363                0x32400, 0x32400,
2364                0x32408, 0x3241c,
2365                0x32618, 0x32620,
2366                0x32664, 0x32664,
2367                0x326a8, 0x326a8,
2368                0x326ec, 0x326ec,
2369                0x32a00, 0x32abc,
2370                0x32b00, 0x32b18,
2371                0x32b20, 0x32b38,
2372                0x32b40, 0x32b58,
2373                0x32b60, 0x32b78,
2374                0x32c00, 0x32c00,
2375                0x32c08, 0x32c3c,
2376                0x33000, 0x3302c,
2377                0x33034, 0x33050,
2378                0x33058, 0x33058,
2379                0x33060, 0x3308c,
2380                0x3309c, 0x330ac,
2381                0x330c0, 0x330c0,
2382                0x330c8, 0x330d0,
2383                0x330d8, 0x330e0,
2384                0x330ec, 0x3312c,
2385                0x33134, 0x33150,
2386                0x33158, 0x33158,
2387                0x33160, 0x3318c,
2388                0x3319c, 0x331ac,
2389                0x331c0, 0x331c0,
2390                0x331c8, 0x331d0,
2391                0x331d8, 0x331e0,
2392                0x331ec, 0x33290,
2393                0x33298, 0x332c4,
2394                0x332e4, 0x33390,
2395                0x33398, 0x333c4,
2396                0x333e4, 0x3342c,
2397                0x33434, 0x33450,
2398                0x33458, 0x33458,
2399                0x33460, 0x3348c,
2400                0x3349c, 0x334ac,
2401                0x334c0, 0x334c0,
2402                0x334c8, 0x334d0,
2403                0x334d8, 0x334e0,
2404                0x334ec, 0x3352c,
2405                0x33534, 0x33550,
2406                0x33558, 0x33558,
2407                0x33560, 0x3358c,
2408                0x3359c, 0x335ac,
2409                0x335c0, 0x335c0,
2410                0x335c8, 0x335d0,
2411                0x335d8, 0x335e0,
2412                0x335ec, 0x33690,
2413                0x33698, 0x336c4,
2414                0x336e4, 0x33790,
2415                0x33798, 0x337c4,
2416                0x337e4, 0x337fc,
2417                0x33814, 0x33814,
2418                0x33854, 0x33868,
2419                0x33880, 0x3388c,
2420                0x338c0, 0x338d0,
2421                0x338e8, 0x338ec,
2422                0x33900, 0x3392c,
2423                0x33934, 0x33950,
2424                0x33958, 0x33958,
2425                0x33960, 0x3398c,
2426                0x3399c, 0x339ac,
2427                0x339c0, 0x339c0,
2428                0x339c8, 0x339d0,
2429                0x339d8, 0x339e0,
2430                0x339ec, 0x33a90,
2431                0x33a98, 0x33ac4,
2432                0x33ae4, 0x33b10,
2433                0x33b24, 0x33b28,
2434                0x33b38, 0x33b50,
2435                0x33bf0, 0x33c10,
2436                0x33c24, 0x33c28,
2437                0x33c38, 0x33c50,
2438                0x33cf0, 0x33cfc,
2439                0x34000, 0x34030,
2440                0x34100, 0x34168,
2441                0x34190, 0x341a0,
2442                0x341a8, 0x341b8,
2443                0x341c4, 0x341c8,
2444                0x341d0, 0x341d0,
2445                0x34200, 0x34320,
2446                0x34400, 0x344b4,
2447                0x344c0, 0x3452c,
2448                0x34540, 0x3461c,
2449                0x34800, 0x348a0,
2450                0x348c0, 0x34908,
2451                0x34910, 0x349b8,
2452                0x34a00, 0x34a04,
2453                0x34a0c, 0x34a14,
2454                0x34a1c, 0x34a2c,
2455                0x34a44, 0x34a50,
2456                0x34a74, 0x34a74,
2457                0x34a7c, 0x34afc,
2458                0x34b08, 0x34c24,
2459                0x34d00, 0x34d14,
2460                0x34d1c, 0x34d3c,
2461                0x34d44, 0x34d4c,
2462                0x34d54, 0x34d74,
2463                0x34d7c, 0x34d7c,
2464                0x34de0, 0x34de0,
2465                0x34e00, 0x34ed4,
2466                0x34f00, 0x34fa4,
2467                0x34fc0, 0x34fc4,
2468                0x35000, 0x35004,
2469                0x35080, 0x350fc,
2470                0x35208, 0x35220,
2471                0x3523c, 0x35254,
2472                0x35300, 0x35300,
2473                0x35308, 0x3531c,
2474                0x35338, 0x3533c,
2475                0x35380, 0x35380,
2476                0x35388, 0x353a8,
2477                0x353b4, 0x353b4,
2478                0x35400, 0x35420,
2479                0x35438, 0x3543c,
2480                0x35480, 0x35480,
2481                0x354a8, 0x354a8,
2482                0x354b0, 0x354b4,
2483                0x354c8, 0x354d4,
2484                0x35a40, 0x35a4c,
2485                0x35af0, 0x35b20,
2486                0x35b38, 0x35b3c,
2487                0x35b80, 0x35b80,
2488                0x35ba8, 0x35ba8,
2489                0x35bb0, 0x35bb4,
2490                0x35bc8, 0x35bd4,
2491                0x36140, 0x3618c,
2492                0x361f0, 0x361f4,
2493                0x36200, 0x36200,
2494                0x36218, 0x36218,
2495                0x36400, 0x36400,
2496                0x36408, 0x3641c,
2497                0x36618, 0x36620,
2498                0x36664, 0x36664,
2499                0x366a8, 0x366a8,
2500                0x366ec, 0x366ec,
2501                0x36a00, 0x36abc,
2502                0x36b00, 0x36b18,
2503                0x36b20, 0x36b38,
2504                0x36b40, 0x36b58,
2505                0x36b60, 0x36b78,
2506                0x36c00, 0x36c00,
2507                0x36c08, 0x36c3c,
2508                0x37000, 0x3702c,
2509                0x37034, 0x37050,
2510                0x37058, 0x37058,
2511                0x37060, 0x3708c,
2512                0x3709c, 0x370ac,
2513                0x370c0, 0x370c0,
2514                0x370c8, 0x370d0,
2515                0x370d8, 0x370e0,
2516                0x370ec, 0x3712c,
2517                0x37134, 0x37150,
2518                0x37158, 0x37158,
2519                0x37160, 0x3718c,
2520                0x3719c, 0x371ac,
2521                0x371c0, 0x371c0,
2522                0x371c8, 0x371d0,
2523                0x371d8, 0x371e0,
2524                0x371ec, 0x37290,
2525                0x37298, 0x372c4,
2526                0x372e4, 0x37390,
2527                0x37398, 0x373c4,
2528                0x373e4, 0x3742c,
2529                0x37434, 0x37450,
2530                0x37458, 0x37458,
2531                0x37460, 0x3748c,
2532                0x3749c, 0x374ac,
2533                0x374c0, 0x374c0,
2534                0x374c8, 0x374d0,
2535                0x374d8, 0x374e0,
2536                0x374ec, 0x3752c,
2537                0x37534, 0x37550,
2538                0x37558, 0x37558,
2539                0x37560, 0x3758c,
2540                0x3759c, 0x375ac,
2541                0x375c0, 0x375c0,
2542                0x375c8, 0x375d0,
2543                0x375d8, 0x375e0,
2544                0x375ec, 0x37690,
2545                0x37698, 0x376c4,
2546                0x376e4, 0x37790,
2547                0x37798, 0x377c4,
2548                0x377e4, 0x377fc,
2549                0x37814, 0x37814,
2550                0x37854, 0x37868,
2551                0x37880, 0x3788c,
2552                0x378c0, 0x378d0,
2553                0x378e8, 0x378ec,
2554                0x37900, 0x3792c,
2555                0x37934, 0x37950,
2556                0x37958, 0x37958,
2557                0x37960, 0x3798c,
2558                0x3799c, 0x379ac,
2559                0x379c0, 0x379c0,
2560                0x379c8, 0x379d0,
2561                0x379d8, 0x379e0,
2562                0x379ec, 0x37a90,
2563                0x37a98, 0x37ac4,
2564                0x37ae4, 0x37b10,
2565                0x37b24, 0x37b28,
2566                0x37b38, 0x37b50,
2567                0x37bf0, 0x37c10,
2568                0x37c24, 0x37c28,
2569                0x37c38, 0x37c50,
2570                0x37cf0, 0x37cfc,
2571                0x40040, 0x40040,
2572                0x40080, 0x40084,
2573                0x40100, 0x40100,
2574                0x40140, 0x401bc,
2575                0x40200, 0x40214,
2576                0x40228, 0x40228,
2577                0x40240, 0x40258,
2578                0x40280, 0x40280,
2579                0x40304, 0x40304,
2580                0x40330, 0x4033c,
2581                0x41304, 0x413c8,
2582                0x413d0, 0x413dc,
2583                0x413f0, 0x413f0,
2584                0x41400, 0x4140c,
2585                0x41414, 0x4141c,
2586                0x41480, 0x414d0,
2587                0x44000, 0x4407c,
2588                0x440c0, 0x441ac,
2589                0x441b4, 0x4427c,
2590                0x442c0, 0x443ac,
2591                0x443b4, 0x4447c,
2592                0x444c0, 0x445ac,
2593                0x445b4, 0x4467c,
2594                0x446c0, 0x447ac,
2595                0x447b4, 0x4487c,
2596                0x448c0, 0x449ac,
2597                0x449b4, 0x44a7c,
2598                0x44ac0, 0x44bac,
2599                0x44bb4, 0x44c7c,
2600                0x44cc0, 0x44dac,
2601                0x44db4, 0x44e7c,
2602                0x44ec0, 0x44fac,
2603                0x44fb4, 0x4507c,
2604                0x450c0, 0x451ac,
2605                0x451b4, 0x451fc,
2606                0x45800, 0x45804,
2607                0x45810, 0x45830,
2608                0x45840, 0x45860,
2609                0x45868, 0x45868,
2610                0x45880, 0x45884,
2611                0x458a0, 0x458b0,
2612                0x45a00, 0x45a04,
2613                0x45a10, 0x45a30,
2614                0x45a40, 0x45a60,
2615                0x45a68, 0x45a68,
2616                0x45a80, 0x45a84,
2617                0x45aa0, 0x45ab0,
2618                0x460c0, 0x460e4,
2619                0x47000, 0x4703c,
2620                0x47044, 0x4708c,
2621                0x47200, 0x47250,
2622                0x47400, 0x47408,
2623                0x47414, 0x47420,
2624                0x47600, 0x47618,
2625                0x47800, 0x47814,
2626                0x47820, 0x4782c,
2627                0x50000, 0x50084,
2628                0x50090, 0x500cc,
2629                0x50300, 0x50384,
2630                0x50400, 0x50400,
2631                0x50800, 0x50884,
2632                0x50890, 0x508cc,
2633                0x50b00, 0x50b84,
2634                0x50c00, 0x50c00,
2635                0x51000, 0x51020,
2636                0x51028, 0x510b0,
2637                0x51300, 0x51324,
2638        };
2639
2640        u32 *buf_end = (u32 *)((char *)buf + buf_size);
2641        const unsigned int *reg_ranges;
2642        int reg_ranges_size, range;
2643        unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2644
2645        /* Select the right set of register ranges to dump depending on the
2646         * adapter chip type.
2647         */
2648        switch (chip_version) {
2649        case CHELSIO_T4:
2650                reg_ranges = t4_reg_ranges;
2651                reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2652                break;
2653
2654        case CHELSIO_T5:
2655                reg_ranges = t5_reg_ranges;
2656                reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2657                break;
2658
2659        case CHELSIO_T6:
2660                reg_ranges = t6_reg_ranges;
2661                reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2662                break;
2663
2664        default:
2665                dev_err(adap->pdev_dev,
2666                        "Unsupported chip version %d\n", chip_version);
2667                return;
2668        }
2669
2670        /* Clear the register buffer and insert the appropriate register
2671         * values selected by the above register ranges.
2672         */
2673        memset(buf, 0, buf_size);
2674        for (range = 0; range < reg_ranges_size; range += 2) {
2675                unsigned int reg = reg_ranges[range];
2676                unsigned int last_reg = reg_ranges[range + 1];
2677                u32 *bufp = (u32 *)((char *)buf + reg);
2678
2679                /* Iterate across the register range filling in the register
2680                 * buffer but don't write past the end of the register buffer.
2681                 */
2682                while (reg <= last_reg && bufp < buf_end) {
2683                        *bufp++ = t4_read_reg(adap, reg);
2684                        reg += sizeof(u32);
2685                }
2686        }
2687}
2688
2689#define EEPROM_STAT_ADDR   0x7bfc
2690#define VPD_BASE           0x400
2691#define VPD_BASE_OLD       0
2692#define VPD_LEN            1024
2693
2694/**
2695 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2696 * @phys_addr: the physical EEPROM address
2697 * @fn: the PCI function number
2698 * @sz: size of function-specific area
2699 *
2700 * Translate a physical EEPROM address to virtual.  The first 1K is
2701 * accessed through virtual addresses starting at 31K, the rest is
2702 * accessed through virtual addresses starting at 0.
2703 *
2704 * The mapping is as follows:
2705 * [0..1K) -> [31K..32K)
2706 * [1K..1K+A) -> [31K-A..31K)
2707 * [1K+A..ES) -> [0..ES-A-1K)
2708 *
2709 * where A = @fn * @sz, and ES = EEPROM size.
2710 */
2711int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2712{
2713        fn *= sz;
2714        if (phys_addr < 1024)
2715                return phys_addr + (31 << 10);
2716        if (phys_addr < 1024 + fn)
2717                return 31744 - fn + phys_addr - 1024;
2718        if (phys_addr < EEPROMSIZE)
2719                return phys_addr - 1024 - fn;
2720        return -EINVAL;
2721}
2722
2723/**
2724 *      t4_seeprom_wp - enable/disable EEPROM write protection
2725 *      @adapter: the adapter
2726 *      @enable: whether to enable or disable write protection
2727 *
2728 *      Enables or disables write protection on the serial EEPROM.
2729 */
2730int t4_seeprom_wp(struct adapter *adapter, bool enable)
2731{
2732        unsigned int v = enable ? 0xc : 0;
2733        int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2734        return ret < 0 ? ret : 0;
2735}
2736
2737/**
2738 *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2739 *      @adapter: adapter to read
2740 *      @p: where to store the parameters
2741 *
2742 *      Reads card parameters stored in VPD EEPROM.
2743 */
2744int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2745{
2746        int i, ret = 0, addr;
2747        int ec, sn, pn, na;
2748        u8 *vpd, csum, base_val = 0;
2749        unsigned int vpdr_len, kw_offset, id_len;
2750
2751        vpd = vmalloc(VPD_LEN);
2752        if (!vpd)
2753                return -ENOMEM;
2754
2755        /* Card information normally starts at VPD_BASE but early cards had
2756         * it at 0.
2757         */
2758        ret = pci_read_vpd(adapter->pdev, VPD_BASE, 1, &base_val);
2759        if (ret < 0)
2760                goto out;
2761
2762        addr = base_val == PCI_VPD_LRDT_ID_STRING ? VPD_BASE : VPD_BASE_OLD;
2763
2764        ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2765        if (ret < 0)
2766                goto out;
2767
2768        if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2769                dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2770                ret = -EINVAL;
2771                goto out;
2772        }
2773
2774        id_len = pci_vpd_lrdt_size(vpd);
2775        if (id_len > ID_LEN)
2776                id_len = ID_LEN;
2777
2778        i = pci_vpd_find_tag(vpd, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2779        if (i < 0) {
2780                dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2781                ret = -EINVAL;
2782                goto out;
2783        }
2784
2785        vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2786        kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2787        if (vpdr_len + kw_offset > VPD_LEN) {
2788                dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2789                ret = -EINVAL;
2790                goto out;
2791        }
2792
2793#define FIND_VPD_KW(var, name) do { \
2794        var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2795        if (var < 0) { \
2796                dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2797                ret = -EINVAL; \
2798                goto out; \
2799        } \
2800        var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2801} while (0)
2802
2803        FIND_VPD_KW(i, "RV");
2804        for (csum = 0; i >= 0; i--)
2805                csum += vpd[i];
2806
2807        if (csum) {
2808                dev_err(adapter->pdev_dev,
2809                        "corrupted VPD EEPROM, actual csum %u\n", csum);
2810                ret = -EINVAL;
2811                goto out;
2812        }
2813
2814        FIND_VPD_KW(ec, "EC");
2815        FIND_VPD_KW(sn, "SN");
2816        FIND_VPD_KW(pn, "PN");
2817        FIND_VPD_KW(na, "NA");
2818#undef FIND_VPD_KW
2819
2820        memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2821        strim(p->id);
2822        memcpy(p->ec, vpd + ec, EC_LEN);
2823        strim(p->ec);
2824        i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2825        memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2826        strim(p->sn);
2827        i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2828        memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2829        strim(p->pn);
2830        memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2831        strim((char *)p->na);
2832
2833out:
2834        vfree(vpd);
2835        return ret < 0 ? ret : 0;
2836}
2837
2838/**
2839 *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2840 *      @adapter: adapter to read
2841 *      @p: where to store the parameters
2842 *
2843 *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2844 *      Clock.  This can only be called after a connection to the firmware
2845 *      is established.
2846 */
2847int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2848{
2849        u32 cclk_param, cclk_val;
2850        int ret;
2851
2852        /* Grab the raw VPD parameters.
2853         */
2854        ret = t4_get_raw_vpd_params(adapter, p);
2855        if (ret)
2856                return ret;
2857
2858        /* Ask firmware for the Core Clock since it knows how to translate the
2859         * Reference Clock ('V2') VPD field into a Core Clock value ...
2860         */
2861        cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2862                      FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2863        ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2864                              1, &cclk_param, &cclk_val);
2865
2866        if (ret)
2867                return ret;
2868        p->cclk = cclk_val;
2869
2870        return 0;
2871}
2872
2873/**
2874 *      t4_get_pfres - retrieve VF resource limits
2875 *      @adapter: the adapter
2876 *
2877 *      Retrieves configured resource limits and capabilities for a physical
2878 *      function.  The results are stored in @adapter->pfres.
2879 */
2880int t4_get_pfres(struct adapter *adapter)
2881{
2882        struct pf_resources *pfres = &adapter->params.pfres;
2883        struct fw_pfvf_cmd cmd, rpl;
2884        int v;
2885        u32 word;
2886
2887        /* Execute PFVF Read command to get VF resource limits; bail out early
2888         * with error on command failure.
2889         */
2890        memset(&cmd, 0, sizeof(cmd));
2891        cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
2892                                    FW_CMD_REQUEST_F |
2893                                    FW_CMD_READ_F |
2894                                    FW_PFVF_CMD_PFN_V(adapter->pf) |
2895                                    FW_PFVF_CMD_VFN_V(0));
2896        cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2897        v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
2898        if (v != FW_SUCCESS)
2899                return v;
2900
2901        /* Extract PF resource limits and return success.
2902         */
2903        word = be32_to_cpu(rpl.niqflint_niq);
2904        pfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
2905        pfres->niq = FW_PFVF_CMD_NIQ_G(word);
2906
2907        word = be32_to_cpu(rpl.type_to_neq);
2908        pfres->neq = FW_PFVF_CMD_NEQ_G(word);
2909        pfres->pmask = FW_PFVF_CMD_PMASK_G(word);
2910
2911        word = be32_to_cpu(rpl.tc_to_nexactf);
2912        pfres->tc = FW_PFVF_CMD_TC_G(word);
2913        pfres->nvi = FW_PFVF_CMD_NVI_G(word);
2914        pfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
2915
2916        word = be32_to_cpu(rpl.r_caps_to_nethctrl);
2917        pfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
2918        pfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
2919        pfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
2920
2921        return 0;
2922}
2923
2924/* serial flash and firmware constants */
2925enum {
2926        SF_ATTEMPTS = 10,             /* max retries for SF operations */
2927
2928        /* flash command opcodes */
2929        SF_PROG_PAGE    = 2,          /* program page */
2930        SF_WR_DISABLE   = 4,          /* disable writes */
2931        SF_RD_STATUS    = 5,          /* read status register */
2932        SF_WR_ENABLE    = 6,          /* enable writes */
2933        SF_RD_DATA_FAST = 0xb,        /* read flash */
2934        SF_RD_ID        = 0x9f,       /* read ID */
2935        SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2936};
2937
2938/**
2939 *      sf1_read - read data from the serial flash
2940 *      @adapter: the adapter
2941 *      @byte_cnt: number of bytes to read
2942 *      @cont: whether another operation will be chained
2943 *      @lock: whether to lock SF for PL access only
2944 *      @valp: where to store the read data
2945 *
2946 *      Reads up to 4 bytes of data from the serial flash.  The location of
2947 *      the read needs to be specified prior to calling this by issuing the
2948 *      appropriate commands to the serial flash.
2949 */
2950static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2951                    int lock, u32 *valp)
2952{
2953        int ret;
2954
2955        if (!byte_cnt || byte_cnt > 4)
2956                return -EINVAL;
2957        if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2958                return -EBUSY;
2959        t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2960                     SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2961        ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2962        if (!ret)
2963                *valp = t4_read_reg(adapter, SF_DATA_A);
2964        return ret;
2965}
2966
2967/**
2968 *      sf1_write - write data to the serial flash
2969 *      @adapter: the adapter
2970 *      @byte_cnt: number of bytes to write
2971 *      @cont: whether another operation will be chained
2972 *      @lock: whether to lock SF for PL access only
2973 *      @val: value to write
2974 *
2975 *      Writes up to 4 bytes of data to the serial flash.  The location of
2976 *      the write needs to be specified prior to calling this by issuing the
2977 *      appropriate commands to the serial flash.
2978 */
2979static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2980                     int lock, u32 val)
2981{
2982        if (!byte_cnt || byte_cnt > 4)
2983                return -EINVAL;
2984        if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2985                return -EBUSY;
2986        t4_write_reg(adapter, SF_DATA_A, val);
2987        t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2988                     SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2989        return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2990}
2991
2992/**
2993 *      flash_wait_op - wait for a flash operation to complete
2994 *      @adapter: the adapter
2995 *      @attempts: max number of polls of the status register
2996 *      @delay: delay between polls in ms
2997 *
2998 *      Wait for a flash operation to complete by polling the status register.
2999 */
3000static int flash_wait_op(struct adapter *adapter, int attempts, int delay)

3001{
3002        int ret;
3003        u32 status;
3004
3005        while (1) {
3006                if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3007                    (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3008                        return ret;
3009                if (!(status & 1))
3010                        return 0;
3011                if (--attempts == 0)
3012                        return -EAGAIN;
3013                if (delay)
3014                        msleep(delay);
3015        }
3016}
3017
3018/**
3019 *      t4_read_flash - read words from serial flash
3020 *      @adapter: the adapter
3021 *      @addr: the start address for the read
3022 *      @nwords: how many 32-bit words to read
3023 *      @data: where to store the read data
3024 *      @byte_oriented: whether to store data as bytes or as words
3025 *
3026 *      Read the specified number of 32-bit words from the serial flash.
3027 *      If @byte_oriented is set the read data is stored as a byte array
3028 *      (i.e., big-endian), otherwise as 32-bit words in the platform's
3029 *      natural endianness.
3030 */
3031int t4_read_flash(struct adapter *adapter, unsigned int addr,
3032                  unsigned int nwords, u32 *data, int byte_oriented)
3033{
3034        int ret;
3035
3036        if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3037                return -EINVAL;
3038
3039        addr = swab32(addr) | SF_RD_DATA_FAST;
3040
3041        if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3042            (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3043                return ret;
3044
3045        for ( ; nwords; nwords--, data++) {
3046                ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3047                if (nwords == 1)
3048                        t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3049                if (ret)
3050                        return ret;
3051                if (byte_oriented)
3052                        *data = (__force __u32)(cpu_to_be32(*data));
3053        }
3054        return 0;
3055}
3056
3057/**
3058 *      t4_write_flash - write up to a page of data to the serial flash
3059 *      @adapter: the adapter
3060 *      @addr: the start address to write
3061 *      @n: length of data to write in bytes
3062 *      @data: the data to write
3063 *      @byte_oriented: whether to store data as bytes or as words
3064 *
3065 *      Writes up to a page of data (256 bytes) to the serial flash starting
3066 *      at the given address.  All the data must be written to the same page.
3067 *      If @byte_oriented is set the write data is stored as byte stream
3068 *      (i.e. matches what on disk), otherwise in big-endian.
3069 */
3070static int t4_write_flash(struct adapter *adapter, unsigned int addr,
3071                          unsigned int n, const u8 *data, bool byte_oriented)
3072{
3073        unsigned int i, c, left, val, offset = addr & 0xff;
3074        u32 buf[64];
3075        int ret;
3076
3077        if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3078                return -EINVAL;
3079
3080        val = swab32(addr) | SF_PROG_PAGE;
3081
3082        if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3083            (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3084                goto unlock;
3085
3086        for (left = n; left; left -= c, data += c) {
3087                c = min(left, 4U);
3088                for (val = 0, i = 0; i < c; ++i) {
3089                        if (byte_oriented)
3090                                val = (val << 8) + data[i];
3091                        else
3092                                val = (val << 8) + data[c - i - 1];
3093                }
3094
3095                ret = sf1_write(adapter, c, c != left, 1, val);
3096                if (ret)
3097                        goto unlock;
3098        }
3099        ret = flash_wait_op(adapter, 8, 1);
3100        if (ret)
3101                goto unlock;
3102
3103        t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3104
3105        /* Read the page to verify the write succeeded */
3106        ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3107                            byte_oriented);
3108        if (ret)
3109                return ret;
3110
3111        if (memcmp(data - n, (u8 *)buf + offset, n)) {
3112                dev_err(adapter->pdev_dev,
3113                        "failed to correctly write the flash page at %#x\n",
3114                        addr);
3115                return -EIO;
3116        }
3117        return 0;
3118
3119unlock:
3120        t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3121        return ret;
3122}
3123
3124/**
3125 *      t4_get_fw_version - read the firmware version
3126 *      @adapter: the adapter
3127 *      @vers: where to place the version
3128 *
3129 *      Reads the FW version from flash.
3130 */
3131int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3132{
3133        return t4_read_flash(adapter, FLASH_FW_START +
3134                             offsetof(struct fw_hdr, fw_ver), 1,
3135                             vers, 0);
3136}
3137
3138/**
3139 *      t4_get_bs_version - read the firmware bootstrap version
3140 *      @adapter: the adapter
3141 *      @vers: where to place the version
3142 *
3143 *      Reads the FW Bootstrap version from flash.
3144 */
3145int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3146{
3147        return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3148                             offsetof(struct fw_hdr, fw_ver), 1,
3149                             vers, 0);
3150}
3151
3152/**
3153 *      t4_get_tp_version - read the TP microcode version
3154 *      @adapter: the adapter
3155 *      @vers: where to place the version
3156 *
3157 *      Reads the TP microcode version from flash.
3158 */
3159int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3160{
3161        return t4_read_flash(adapter, FLASH_FW_START +
3162                             offsetof(struct fw_hdr, tp_microcode_ver),
3163                             1, vers, 0);
3164}
3165
3166/**
3167 *      t4_get_exprom_version - return the Expansion ROM version (if any)
3168 *      @adap: the adapter
3169 *      @vers: where to place the version
3170 *
3171 *      Reads the Expansion ROM header from FLASH and returns the version
3172 *      number (if present) through the @vers return value pointer.  We return
3173 *      this in the Firmware Version Format since it's convenient.  Return
3174 *      0 on success, -ENOENT if no Expansion ROM is present.
3175 */
3176int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3177{
3178        struct exprom_header {
3179                unsigned char hdr_arr[16];      /* must start with 0x55aa */
3180                unsigned char hdr_ver[4];       /* Expansion ROM version */
3181        } *hdr;
3182        u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3183                                           sizeof(u32))];
3184        int ret;
3185
3186        ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3187                            ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3188                            0);
3189        if (ret)
3190                return ret;
3191
3192        hdr = (struct exprom_header *)exprom_header_buf;
3193        if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3194                return -ENOENT;
3195
3196        *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3197                 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3198                 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3199                 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3200        return 0;
3201}
3202
3203/**
3204 *      t4_get_vpd_version - return the VPD version
3205 *      @adapter: the adapter
3206 *      @vers: where to place the version
3207 *
3208 *      Reads the VPD via the Firmware interface (thus this can only be called
3209 *      once we're ready to issue Firmware commands).  The format of the
3210 *      VPD version is adapter specific.  Returns 0 on success, an error on
3211 *      failure.
3212 *
3213 *      Note that early versions of the Firmware didn't include the ability
3214 *      to retrieve the VPD version, so we zero-out the return-value parameter
3215 *      in that case to avoid leaving it with garbage in it.
3216 *
3217 *      Also note that the Firmware will return its cached copy of the VPD
3218 *      Revision ID, not the actual Revision ID as written in the Serial
3219 *      EEPROM.  This is only an issue if a new VPD has been written and the
3220 *      Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3221 *      to defer calling this routine till after a FW_RESET_CMD has been issued
3222 *      if the Host Driver will be performing a full adapter initialization.
3223 */
3224int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3225{
3226        u32 vpdrev_param;
3227        int ret;
3228
3229        vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3230                        FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3231        ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3232                              1, &vpdrev_param, vers);
3233        if (ret)
3234                *vers = 0;
3235        return ret;
3236}
3237
3238/**
3239 *      t4_get_scfg_version - return the Serial Configuration version
3240 *      @adapter: the adapter
3241 *      @vers: where to place the version
3242 *
3243 *      Reads the Serial Configuration Version via the Firmware interface
3244 *      (thus this can only be called once we're ready to issue Firmware
3245 *      commands).  The format of the Serial Configuration version is
3246 *      adapter specific.  Returns 0 on success, an error on failure.
3247 *
3248 *      Note that early versions of the Firmware didn't include the ability
3249 *      to retrieve the Serial Configuration version, so we zero-out the
3250 *      return-value parameter in that case to avoid leaving it with
3251 *      garbage in it.
3252 *
3253 *      Also note that the Firmware will return its cached copy of the Serial
3254 *      Initialization Revision ID, not the actual Revision ID as written in
3255 *      the Serial EEPROM.  This is only an issue if a new VPD has been written
3256 *      and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3257 *      it's best to defer calling this routine till after a FW_RESET_CMD has
3258 *      been issued if the Host Driver will be performing a full adapter
3259 *      initialization.
3260 */
3261int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3262{
3263        u32 scfgrev_param;
3264        int ret;
3265
3266        scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3267                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3268        ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3269                              1, &scfgrev_param, vers);
3270        if (ret)
3271                *vers = 0;
3272        return ret;
3273}
3274
3275/**
3276 *      t4_get_version_info - extract various chip/firmware version information
3277 *      @adapter: the adapter
3278 *
3279 *      Reads various chip/firmware version numbers and stores them into the
3280 *      adapter Adapter Parameters structure.  If any of the efforts fails
3281 *      the first failure will be returned, but all of the version numbers
3282 *      will be read.
3283 */
3284int t4_get_version_info(struct adapter *adapter)
3285{
3286        int ret = 0;
3287
3288        #define FIRST_RET(__getvinfo) \
3289        do { \
3290                int __ret = __getvinfo; \
3291                if (__ret && !ret) \
3292                        ret = __ret; \
3293        } while (0)
3294
3295        FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3296        FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3297        FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3298        FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3299        FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3300        FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3301
3302        #undef FIRST_RET
3303        return ret;
3304}
3305
3306/**
3307 *      t4_dump_version_info - dump all of the adapter configuration IDs
3308 *      @adapter: the adapter
3309 *
3310 *      Dumps all of the various bits of adapter configuration version/revision
3311 *      IDs information.  This is typically called at some point after
3312 *      t4_get_version_info() has been called.
3313 */
3314void t4_dump_version_info(struct adapter *adapter)
3315{
3316        /* Device information */
3317        dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3318                 adapter->params.vpd.id,
3319                 CHELSIO_CHIP_RELEASE(adapter->params.chip));
3320        dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3321                 adapter->params.vpd.sn, adapter->params.vpd.pn);
3322
3323        /* Firmware Version */
3324        if (!adapter->params.fw_vers)
3325                dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3326        else
3327                dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3328                         FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3329                         FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3330                         FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3331                         FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3332
3333        /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3334         * Firmware, so dev_info() is more appropriate here.)
3335         */
3336        if (!adapter->params.bs_vers)
3337                dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3338        else
3339                dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3340                         FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3341                         FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3342                         FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3343                         FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3344
3345        /* TP Microcode Version */
3346        if (!adapter->params.tp_vers)
3347                dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3348        else
3349                dev_info(adapter->pdev_dev,
3350                         "TP Microcode version: %u.%u.%u.%u\n",
3351                         FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3352                         FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3353                         FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3354                         FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3355
3356        /* Expansion ROM version */
3357        if (!adapter->params.er_vers)
3358                dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3359        else
3360                dev_info(adapter->pdev_dev,
3361                         "Expansion ROM version: %u.%u.%u.%u\n",
3362                         FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3363                         FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3364                         FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3365                         FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3366
3367        /* Serial Configuration version */
3368        dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3369                 adapter->params.scfg_vers);
3370
3371        /* VPD Version */
3372        dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3373                 adapter->params.vpd_vers);
3374}
3375
3376/**
3377 *      t4_check_fw_version - check if the FW is supported with this driver
3378 *      @adap: the adapter
3379 *
3380 *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3381 *      if there's exact match, a negative error if the version could not be
3382 *      read or there's a major version mismatch
3383 */
3384int t4_check_fw_version(struct adapter *adap)
3385{
3386        int i, ret, major, minor, micro;
3387        int exp_major, exp_minor, exp_micro;
3388        unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3389
3390        ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3391        /* Try multiple times before returning error */
3392        for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3393                ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3394
3395        if (ret)
3396                return ret;
3397
3398        major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3399        minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3400        micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3401
3402        switch (chip_version) {
3403        case CHELSIO_T4:
3404                exp_major = T4FW_MIN_VERSION_MAJOR;
3405                exp_minor = T4FW_MIN_VERSION_MINOR;
3406                exp_micro = T4FW_MIN_VERSION_MICRO;
3407                break;
3408        case CHELSIO_T5:
3409                exp_major = T5FW_MIN_VERSION_MAJOR;
3410                exp_minor = T5FW_MIN_VERSION_MINOR;
3411                exp_micro = T5FW_MIN_VERSION_MICRO;
3412                break;
3413        case CHELSIO_T6:
3414                exp_major = T6FW_MIN_VERSION_MAJOR;
3415                exp_minor = T6FW_MIN_VERSION_MINOR;
3416                exp_micro = T6FW_MIN_VERSION_MICRO;
3417                break;
3418        default:
3419                dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3420                        adap->chip);
3421                return -EINVAL;
3422        }
3423
3424        if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3425            (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3426                dev_err(adap->pdev_dev,
3427                        "Card has firmware version %u.%u.%u, minimum "
3428                        "supported firmware is %u.%u.%u.\n", major, minor,
3429                        micro, exp_major, exp_minor, exp_micro);
3430                return -EFAULT;
3431        }
3432        return 0;
3433}
3434
3435/* Is the given firmware API compatible with the one the driver was compiled
3436 * with?
3437 */
3438static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3439{
3440
3441        /* short circuit if it's the exact same firmware version */
3442        if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3443                return 1;
3444
3445#define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3446        if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3447            SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3448                return 1;
3449#undef SAME_INTF
3450
3451        return 0;
3452}
3453
3454/* The firmware in the filesystem is usable, but should it be installed?
3455 * This routine explains itself in detail if it indicates the filesystem
3456 * firmware should be installed.
3457 */
3458static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3459                                int k, int c)
3460{
3461        const char *reason;
3462
3463        if (!card_fw_usable) {
3464                reason = "incompatible or unusable";
3465                goto install;
3466        }
3467
3468        if (k > c) {
3469                reason = "older than the version supported with this driver";
3470                goto install;
3471        }
3472
3473        return 0;
3474
3475install:
3476        dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3477                "installing firmware %u.%u.%u.%u on card.\n",
3478                FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3479                FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3480                FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3481                FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3482
3483        return 1;
3484}
3485
3486int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3487               const u8 *fw_data, unsigned int fw_size,
3488               struct fw_hdr *card_fw, enum dev_state state,
3489               int *reset)
3490{
3491        int ret, card_fw_usable, fs_fw_usable;
3492        const struct fw_hdr *fs_fw;
3493        const struct fw_hdr *drv_fw;
3494
3495        drv_fw = &fw_info->fw_hdr;
3496
3497        /* Read the header of the firmware on the card */
3498        ret = t4_read_flash(adap, FLASH_FW_START,
3499                            sizeof(*card_fw) / sizeof(uint32_t),
3500                            (uint32_t *)card_fw, 1);
3501        if (ret == 0) {
3502                card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3503        } else {
3504                dev_err(adap->pdev_dev,
3505                        "Unable to read card's firmware header: %d\n", ret);
3506                card_fw_usable = 0;
3507        }
3508
3509        if (fw_data != NULL) {
3510                fs_fw = (const void *)fw_data;
3511                fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3512        } else {
3513                fs_fw = NULL;
3514                fs_fw_usable = 0;
3515        }
3516
3517        if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3518            (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3519                /* Common case: the firmware on the card is an exact match and
3520                 * the filesystem one is an exact match too, or the filesystem
3521                 * one is absent/incompatible.
3522                 */
3523        } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3524                   should_install_fs_fw(adap, card_fw_usable,
3525                                        be32_to_cpu(fs_fw->fw_ver),
3526                                        be32_to_cpu(card_fw->fw_ver))) {
3527                ret = t4_fw_upgrade(adap, adap->mbox, fw_data,
3528                                    fw_size, 0);
3529                if (ret != 0) {
3530                        dev_err(adap->pdev_dev,
3531                                "failed to install firmware: %d\n", ret);
3532                        goto bye;
3533                }
3534
3535                /* Installed successfully, update the cached header too. */
3536                *card_fw = *fs_fw;
3537                card_fw_usable = 1;
3538                *reset = 0;     /* already reset as part of load_fw */
3539        }
3540
3541        if (!card_fw_usable) {
3542                uint32_t d, c, k;
3543
3544                d = be32_to_cpu(drv_fw->fw_ver);
3545                c = be32_to_cpu(card_fw->fw_ver);
3546                k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3547
3548                dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3549                        "chip state %d, "
3550                        "driver compiled with %d.%d.%d.%d, "
3551                        "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3552                        state,
3553                        FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3554                        FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3555                        FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3556                        FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3557                        FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3558                        FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3559                ret = -EINVAL;
3560                goto bye;
3561        }
3562
3563        /* We're using whatever's on the card and it's known to be good. */
3564        adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3565        adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3566
3567bye:
3568        return ret;
3569}
3570
3571/**
3572 *      t4_flash_erase_sectors - erase a range of flash sectors
3573 *      @adapter: the adapter
3574 *      @start: the first sector to erase
3575 *      @end: the last sector to erase
3576 *
3577 *      Erases the sectors in the given inclusive range.
3578 */
3579static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3580{
3581        int ret = 0;
3582
3583        if (end >= adapter->params.sf_nsec)
3584                return -EINVAL;
3585
3586        while (start <= end) {
3587                if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3588                    (ret = sf1_write(adapter, 4, 0, 1,
3589                                     SF_ERASE_SECTOR | (start << 8))) != 0 ||
3590                    (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3591                        dev_err(adapter->pdev_dev,
3592                                "erase of flash sector %d failed, error %d\n",
3593                                start, ret);
3594                        break;
3595                }
3596                start++;
3597        }
3598        t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3599        return ret;
3600}
3601
3602/**
3603 *      t4_flash_cfg_addr - return the address of the flash configuration file
3604 *      @adapter: the adapter
3605 *
3606 *      Return the address within the flash where the Firmware Configuration
3607 *      File is stored.
3608 */
3609unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3610{
3611        if (adapter->params.sf_size == 0x100000)
3612                return FLASH_FPGA_CFG_START;
3613        else
3614                return FLASH_CFG_START;
3615}
3616
3617/* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3618 * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3619 * and emit an error message for mismatched firmware to save our caller the
3620 * effort ...
3621 */
3622static bool t4_fw_matches_chip(const struct adapter *adap,
3623                               const struct fw_hdr *hdr)
3624{
3625        /* The expression below will return FALSE for any unsupported adapter
3626         * which will keep us "honest" in the future ...
3627         */
3628        if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3629            (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3630            (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3631                return true;
3632
3633        dev_err(adap->pdev_dev,
3634                "FW image (%d) is not suitable for this adapter (%d)\n",
3635                hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3636        return false;
3637}
3638
3639/**
3640 *      t4_load_fw - download firmware
3641 *      @adap: the adapter
3642 *      @fw_data: the firmware image to write
3643 *      @size: image size
3644 *
3645 *      Write the supplied firmware image to the card's serial flash.
3646 */
3647int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3648{
3649        u32 csum;
3650        int ret, addr;
3651        unsigned int i;
3652        u8 first_page[SF_PAGE_SIZE];
3653        const __be32 *p = (const __be32 *)fw_data;
3654        const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3655        unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3656        unsigned int fw_start_sec = FLASH_FW_START_SEC;
3657        unsigned int fw_size = FLASH_FW_MAX_SIZE;
3658        unsigned int fw_start = FLASH_FW_START;
3659
3660        if (!size) {
3661                dev_err(adap->pdev_dev, "FW image has no data\n");
3662                return -EINVAL;
3663        }
3664        if (size & 511) {
3665                dev_err(adap->pdev_dev,
3666                        "FW image size not multiple of 512 bytes\n");
3667                return -EINVAL;
3668        }
3669        if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3670                dev_err(adap->pdev_dev,
3671                        "FW image size differs from size in FW header\n");
3672                return -EINVAL;
3673        }
3674        if (size > fw_size) {
3675                dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3676                        fw_size);
3677                return -EFBIG;
3678        }
3679        if (!t4_fw_matches_chip(adap, hdr))
3680                return -EINVAL;
3681
3682        for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3683                csum += be32_to_cpu(p[i]);
3684
3685        if (csum != 0xffffffff) {
3686                dev_err(adap->pdev_dev,
3687                        "corrupted firmware image, checksum %#x\n", csum);
3688                return -EINVAL;
3689        }
3690
3691        i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3692        ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3693        if (ret)
3694                goto out;
3695
3696        /*
3697         * We write the correct version at the end so the driver can see a bad
3698         * version if the FW write fails.  Start by writing a copy of the
3699         * first page with a bad version.
3700         */
3701        memcpy(first_page, fw_data, SF_PAGE_SIZE);
3702        ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3703        ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, true);
3704        if (ret)
3705                goto out;
3706
3707        addr = fw_start;
3708        for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3709                addr += SF_PAGE_SIZE;
3710                fw_data += SF_PAGE_SIZE;
3711                ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, true);
3712                if (ret)
3713                        goto out;
3714        }
3715
3716        ret = t4_write_flash(adap, fw_start + offsetof(struct fw_hdr, fw_ver),
3717                             sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver,
3718                             true);
3719out:
3720        if (ret)
3721                dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3722                        ret);
3723        else
3724                ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3725        return ret;
3726}
3727
3728/**
3729 *      t4_phy_fw_ver - return current PHY firmware version
3730 *      @adap: the adapter
3731 *      @phy_fw_ver: return value buffer for PHY firmware version
3732 *
3733 *      Returns the current version of external PHY firmware on the
3734 *      adapter.
3735 */
3736int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3737{
3738        u32 param, val;
3739        int ret;
3740
3741        param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3742                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3743                 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3744                 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3745        ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3746                              &param, &val);
3747        if (ret)
3748                return ret;
3749        *phy_fw_ver = val;
3750        return 0;
3751}
3752
3753/**
3754 *      t4_load_phy_fw - download port PHY firmware
3755 *      @adap: the adapter
3756 *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3757 *      @phy_fw_version: function to check PHY firmware versions
3758 *      @phy_fw_data: the PHY firmware image to write
3759 *      @phy_fw_size: image size
3760 *
3761 *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3762 *      @phy_fw_version is supplied, then it will be used to determine if
3763 *      it's necessary to perform the transfer by comparing the version
3764 *      of any existing adapter PHY firmware with that of the passed in
3765 *      PHY firmware image.
3766 *
3767 *      A negative error number will be returned if an error occurs.  If
3768 *      version number support is available and there's no need to upgrade
3769 *      the firmware, 0 will be returned.  If firmware is successfully
3770 *      transferred to the adapter, 1 will be returned.
3771 *
3772 *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3773 *      a result, a RESET of the adapter would cause that RAM to lose its
3774 *      contents.  Thus, loading PHY firmware on such adapters must happen
3775 *      after any FW_RESET_CMDs ...
3776 */
3777int t4_load_phy_fw(struct adapter *adap, int win,
3778                   int (*phy_fw_version)(const u8 *, size_t),
3779                   const u8 *phy_fw_data, size_t phy_fw_size)
3780{
3781        int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3782        unsigned long mtype = 0, maddr = 0;
3783        u32 param, val;
3784        int ret;
3785
3786        /* If we have version number support, then check to see if the adapter
3787         * already has up-to-date PHY firmware loaded.
3788         */
3789        if (phy_fw_version) {
3790                new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3791                ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3792                if (ret < 0)
3793                        return ret;
3794
3795                if (cur_phy_fw_ver >= new_phy_fw_vers) {
3796                        CH_WARN(adap, "PHY Firmware already up-to-date, "
3797                                "version %#x\n", cur_phy_fw_ver);
3798                        return 0;
3799                }
3800        }
3801
3802        /* Ask the firmware where it wants us to copy the PHY firmware image.
3803         * The size of the file requires a special version of the READ command
3804         * which will pass the file size via the values field in PARAMS_CMD and
3805         * retrieve the return value from firmware and place it in the same
3806         * buffer values
3807         */
3808        param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3809                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3810                 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3811                 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3812        val = phy_fw_size;
3813        ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3814                                 &param, &val, 1, true);
3815        if (ret < 0)
3816                return ret;
3817        mtype = val >> 8;
3818        maddr = (val & 0xff) << 16;
3819
3820        /* Copy the supplied PHY Firmware image to the adapter memory location
3821         * allocated by the adapter firmware.
3822         */
3823        spin_lock_bh(&adap->win0_lock);
3824        ret = t4_memory_rw(adap, win, mtype, maddr,
3825                           phy_fw_size, (__be32 *)phy_fw_data,
3826                           T4_MEMORY_WRITE);
3827        spin_unlock_bh(&adap->win0_lock);
3828        if (ret)
3829                return ret;
3830
3831        /* Tell the firmware that the PHY firmware image has been written to
3832         * RAM and it can now start copying it over to the PHYs.  The chip
3833         * firmware will RESET the affected PHYs as part of this operation
3834         * leaving them running the new PHY firmware image.
3835         */
3836        param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3837                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3838                 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3839                 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3840        ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3841                                    &param, &val, 30000);
3842
3843        /* If we have version number support, then check to see that the new
3844         * firmware got loaded properly.
3845         */
3846        if (phy_fw_version) {
3847                ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3848                if (ret < 0)
3849                        return ret;
3850
3851                if (cur_phy_fw_ver != new_phy_fw_vers) {
3852                        CH_WARN(adap, "PHY Firmware did not update: "
3853                                "version on adapter %#x, "
3854                                "version flashed %#x\n",
3855                                cur_phy_fw_ver, new_phy_fw_vers);
3856                        return -ENXIO;
3857                }
3858        }
3859
3860        return 1;
3861}
3862
3863/**
3864 *      t4_fwcache - firmware cache operation
3865 *      @adap: the adapter
3866 *      @op  : the operation (flush or flush and invalidate)
3867 */
3868int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3869{
3870        struct fw_params_cmd c;
3871
3872        memset(&c, 0, sizeof(c));
3873        c.op_to_vfn =
3874                cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3875                            FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3876                            FW_PARAMS_CMD_PFN_V(adap->pf) |
3877                            FW_PARAMS_CMD_VFN_V(0));
3878        c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3879        c.param[0].mnem =
3880                cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3881                            FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3882        c.param[0].val = cpu_to_be32(op);
3883
3884        return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3885}
3886
3887void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3888                        unsigned int *pif_req_wrptr,
3889                        unsigned int *pif_rsp_wrptr)
3890{
3891        int i, j;
3892        u32 cfg, val, req, rsp;
3893
3894        cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3895        if (cfg & LADBGEN_F)
3896                t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3897
3898        val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3899        req = POLADBGWRPTR_G(val);
3900        rsp = PILADBGWRPTR_G(val);
3901        if (pif_req_wrptr)
3902                *pif_req_wrptr = req;
3903        if (pif_rsp_wrptr)
3904                *pif_rsp_wrptr = rsp;
3905
3906        for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3907                for (j = 0; j < 6; j++) {
3908                        t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3909                                     PILADBGRDPTR_V(rsp));
3910                        *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3911                        *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3912                        req++;
3913                        rsp++;
3914                }
3915                req = (req + 2) & POLADBGRDPTR_M;
3916                rsp = (rsp + 2) & PILADBGRDPTR_M;
3917        }
3918        t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3919}
3920
3921void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3922{
3923        u32 cfg;
3924        int i, j, idx;
3925
3926        cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3927        if (cfg & LADBGEN_F)
3928                t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3929
3930        for (i = 0; i < CIM_MALA_SIZE; i++) {
3931                for (j = 0; j < 5; j++) {
3932                        idx = 8 * i + j;
3933                        t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3934                                     PILADBGRDPTR_V(idx));
3935                        *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3936                        *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3937                }
3938        }
3939        t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3940}
3941
3942void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3943{
3944        unsigned int i, j;
3945
3946        for (i = 0; i < 8; i++) {
3947                u32 *p = la_buf + i;
3948
3949                t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3950                j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3951                t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3952                for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3953                        *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3954        }
3955}
3956
3957/* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
3958 * Capabilities which we control with separate controls -- see, for instance,
3959 * Pause Frames and Forward Error Correction.  In order to determine what the
3960 * full set of Advertised Port Capabilities are, the base Advertised Port
3961 * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
3962 * Port Capabilities associated with those other controls.  See
3963 * t4_link_acaps() for how this is done.
3964 */
3965#define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3966                     FW_PORT_CAP32_ANEG)
3967
3968/**
3969 *      fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3970 *      @caps16: a 16-bit Port Capabilities value
3971 *
3972 *      Returns the equivalent 32-bit Port Capabilities value.
3973 */
3974static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3975{
3976        fw_port_cap32_t caps32 = 0;
3977
3978        #define CAP16_TO_CAP32(__cap) \
3979                do { \
3980                        if (caps16 & FW_PORT_CAP_##__cap) \
3981                                caps32 |= FW_PORT_CAP32_##__cap; \
3982                } while (0)
3983
3984        CAP16_TO_CAP32(SPEED_100M);
3985        CAP16_TO_CAP32(SPEED_1G);
3986        CAP16_TO_CAP32(SPEED_25G);
3987        CAP16_TO_CAP32(SPEED_10G);
3988        CAP16_TO_CAP32(SPEED_40G);
3989        CAP16_TO_CAP32(SPEED_100G);
3990        CAP16_TO_CAP32(FC_RX);
3991        CAP16_TO_CAP32(FC_TX);
3992        CAP16_TO_CAP32(ANEG);
3993        CAP16_TO_CAP32(FORCE_PAUSE);
3994        CAP16_TO_CAP32(MDIAUTO);
3995        CAP16_TO_CAP32(MDISTRAIGHT);
3996        CAP16_TO_CAP32(FEC_RS);
3997        CAP16_TO_CAP32(FEC_BASER_RS);
3998        CAP16_TO_CAP32(802_3_PAUSE);
3999        CAP16_TO_CAP32(802_3_ASM_DIR);
4000

4001        #undef CAP16_TO_CAP32
4002
4003        return caps32;
4004}
4005
4006/**
4007 *      fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4008 *      @caps32: a 32-bit Port Capabilities value
4009 *
4010 *      Returns the equivalent 16-bit Port Capabilities value.  Note that
4011 *      not all 32-bit Port Capabilities can be represented in the 16-bit
4012 *      Port Capabilities and some fields/values may not make it.
4013 */
4014static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
4015{
4016        fw_port_cap16_t caps16 = 0;
4017
4018        #define CAP32_TO_CAP16(__cap) \
4019                do { \
4020                        if (caps32 & FW_PORT_CAP32_##__cap) \
4021                                caps16 |= FW_PORT_CAP_##__cap; \
4022                } while (0)
4023
4024        CAP32_TO_CAP16(SPEED_100M);
4025        CAP32_TO_CAP16(SPEED_1G);
4026        CAP32_TO_CAP16(SPEED_10G);
4027        CAP32_TO_CAP16(SPEED_25G);
4028        CAP32_TO_CAP16(SPEED_40G);
4029        CAP32_TO_CAP16(SPEED_100G);
4030        CAP32_TO_CAP16(FC_RX);
4031        CAP32_TO_CAP16(FC_TX);
4032        CAP32_TO_CAP16(802_3_PAUSE);
4033        CAP32_TO_CAP16(802_3_ASM_DIR);
4034        CAP32_TO_CAP16(ANEG);
4035        CAP32_TO_CAP16(FORCE_PAUSE);
4036        CAP32_TO_CAP16(MDIAUTO);
4037        CAP32_TO_CAP16(MDISTRAIGHT);
4038        CAP32_TO_CAP16(FEC_RS);
4039        CAP32_TO_CAP16(FEC_BASER_RS);
4040
4041        #undef CAP32_TO_CAP16
4042
4043        return caps16;
4044}
4045
4046/* Translate Firmware Port Capabilities Pause specification to Common Code */
4047static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
4048{
4049        enum cc_pause cc_pause = 0;
4050
4051        if (fw_pause & FW_PORT_CAP32_FC_RX)
4052                cc_pause |= PAUSE_RX;
4053        if (fw_pause & FW_PORT_CAP32_FC_TX)
4054                cc_pause |= PAUSE_TX;
4055
4056        return cc_pause;
4057}
4058
4059/* Translate Common Code Pause specification into Firmware Port Capabilities */
4060static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
4061{
4062        /* Translate orthogonal RX/TX Pause Controls for L1 Configure
4063         * commands, etc.
4064         */
4065        fw_port_cap32_t fw_pause = 0;
4066
4067        if (cc_pause & PAUSE_RX)
4068                fw_pause |= FW_PORT_CAP32_FC_RX;
4069        if (cc_pause & PAUSE_TX)
4070                fw_pause |= FW_PORT_CAP32_FC_TX;
4071        if (!(cc_pause & PAUSE_AUTONEG))
4072                fw_pause |= FW_PORT_CAP32_FORCE_PAUSE;
4073
4074        /* Translate orthogonal Pause controls into IEEE 802.3 Pause,
4075         * Asymmetrical Pause for use in reporting to upper layer OS code, etc.
4076         * Note that these bits are ignored in L1 Configure commands.
4077         */
4078        if (cc_pause & PAUSE_RX) {
4079                if (cc_pause & PAUSE_TX)
4080                        fw_pause |= FW_PORT_CAP32_802_3_PAUSE;
4081                else
4082                        fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR |
4083                                    FW_PORT_CAP32_802_3_PAUSE;
4084        } else if (cc_pause & PAUSE_TX) {
4085                fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR;
4086        }
4087
4088        return fw_pause;
4089}
4090
4091/* Translate Firmware Forward Error Correction specification to Common Code */
4092static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
4093{
4094        enum cc_fec cc_fec = 0;
4095
4096        if (fw_fec & FW_PORT_CAP32_FEC_RS)
4097                cc_fec |= FEC_RS;
4098        if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
4099                cc_fec |= FEC_BASER_RS;
4100
4101        return cc_fec;
4102}
4103
4104/* Translate Common Code Forward Error Correction specification to Firmware */
4105static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
4106{
4107        fw_port_cap32_t fw_fec = 0;
4108
4109        if (cc_fec & FEC_RS)
4110                fw_fec |= FW_PORT_CAP32_FEC_RS;
4111        if (cc_fec & FEC_BASER_RS)
4112                fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
4113
4114        return fw_fec;
4115}
4116
4117/**
4118 *      t4_link_acaps - compute Link Advertised Port Capabilities
4119 *      @adapter: the adapter
4120 *      @port: the Port ID
4121 *      @lc: the Port's Link Configuration
4122 *
4123 *      Synthesize the Advertised Port Capabilities we'll be using based on
4124 *      the base Advertised Port Capabilities (which have been filtered by
4125 *      ADVERT_MASK) plus the individual controls for things like Pause
4126 *      Frames, Forward Error Correction, MDI, etc.
4127 */
4128fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
4129                              struct link_config *lc)
4130{
4131        fw_port_cap32_t fw_fc, fw_fec, acaps;
4132        unsigned int fw_mdi;
4133        char cc_fec;
4134
4135        fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps);
4136
4137        /* Convert driver coding of Pause Frame Flow Control settings into the
4138         * Firmware's API.
4139         */
4140        fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4141
4142        /* Convert Common Code Forward Error Control settings into the
4143         * Firmware's API.  If the current Requested FEC has "Automatic"
4144         * (IEEE 802.3) specified, then we use whatever the Firmware
4145         * sent us as part of its IEEE 802.3-based interpretation of
4146         * the Transceiver Module EPROM FEC parameters.  Otherwise we
4147         * use whatever is in the current Requested FEC settings.
4148         */
4149        if (lc->requested_fec & FEC_AUTO)
4150                cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4151        else
4152                cc_fec = lc->requested_fec;
4153        fw_fec = cc_to_fwcap_fec(cc_fec);
4154
4155        /* Figure out what our Requested Port Capabilities are going to be.
4156         * Note parallel structure in t4_handle_get_port_info() and
4157         * init_link_config().
4158         */
4159        if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4160                acaps = lc->acaps | fw_fc | fw_fec;
4161                lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4162                lc->fec = cc_fec;
4163        } else if (lc->autoneg == AUTONEG_DISABLE) {
4164                acaps = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4165                lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4166                lc->fec = cc_fec;
4167        } else {
4168                acaps = lc->acaps | fw_fc | fw_fec | fw_mdi;
4169        }
4170
4171        /* Some Requested Port Capabilities are trivially wrong if they exceed
4172         * the Physical Port Capabilities.  We can check that here and provide
4173         * moderately useful feedback in the system log.
4174         *
4175         * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4176         * we need to exclude this from this check in order to maintain
4177         * compatibility ...
4178         */
4179        if ((acaps & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) {
4180                dev_err(adapter->pdev_dev, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4181                        acaps, lc->pcaps);
4182                return -EINVAL;
4183        }
4184
4185        return acaps;
4186}
4187
4188/**
4189 *      t4_link_l1cfg_core - apply link configuration to MAC/PHY
4190 *      @adapter: the adapter
4191 *      @mbox: the Firmware Mailbox to use
4192 *      @port: the Port ID
4193 *      @lc: the Port's Link Configuration
4194 *      @sleep_ok: if true we may sleep while awaiting command completion
4195 *      @timeout: time to wait for command to finish before timing out
4196 *              (negative implies @sleep_ok=false)
4197 *
4198 *      Set up a port's MAC and PHY according to a desired link configuration.
4199 *      - If the PHY can auto-negotiate first decide what to advertise, then
4200 *        enable/disable auto-negotiation as desired, and reset.
4201 *      - If the PHY does not auto-negotiate just reset it.
4202 *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4203 *        otherwise do it later based on the outcome of auto-negotiation.
4204 */
4205int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
4206                       unsigned int port, struct link_config *lc,
4207                       u8 sleep_ok, int timeout)
4208{
4209        unsigned int fw_caps = adapter->params.fw_caps_support;
4210        struct fw_port_cmd cmd;
4211        fw_port_cap32_t rcap;
4212        int ret;
4213
4214        if (!(lc->pcaps & FW_PORT_CAP32_ANEG) &&
4215            lc->autoneg == AUTONEG_ENABLE) {
4216                return -EINVAL;
4217        }
4218
4219        /* Compute our Requested Port Capabilities and send that on to the
4220         * Firmware.
4221         */
4222        rcap = t4_link_acaps(adapter, port, lc);
4223        memset(&cmd, 0, sizeof(cmd));
4224        cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4225                                       FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4226                                       FW_PORT_CMD_PORTID_V(port));
4227        cmd.action_to_len16 =
4228                cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4229                                                 ? FW_PORT_ACTION_L1_CFG
4230                                                 : FW_PORT_ACTION_L1_CFG32) |
4231                                                 FW_LEN16(cmd));
4232        if (fw_caps == FW_CAPS16)
4233                cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4234        else
4235                cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4236
4237        ret = t4_wr_mbox_meat_timeout(adapter, mbox, &cmd, sizeof(cmd), NULL,
4238                                      sleep_ok, timeout);
4239
4240        /* Unfortunately, even if the Requested Port Capabilities "fit" within
4241         * the Physical Port Capabilities, some combinations of features may
4242         * still not be legal.  For example, 40Gb/s and Reed-Solomon Forward
4243         * Error Correction.  So if the Firmware rejects the L1 Configure
4244         * request, flag that here.
4245         */
4246        if (ret) {
4247                dev_err(adapter->pdev_dev,
4248                        "Requested Port Capabilities %#x rejected, error %d\n",
4249                        rcap, -ret);
4250                return ret;
4251        }
4252        return 0;
4253}
4254
4255/**
4256 *      t4_restart_aneg - restart autonegotiation
4257 *      @adap: the adapter
4258 *      @mbox: mbox to use for the FW command
4259 *      @port: the port id
4260 *
4261 *      Restarts autonegotiation for the selected port.
4262 */
4263int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4264{
4265        unsigned int fw_caps = adap->params.fw_caps_support;
4266        struct fw_port_cmd c;
4267
4268        memset(&c, 0, sizeof(c));
4269        c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4270                                     FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4271                                     FW_PORT_CMD_PORTID_V(port));
4272        c.action_to_len16 =
4273                cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4274                                                 ? FW_PORT_ACTION_L1_CFG
4275                                                 : FW_PORT_ACTION_L1_CFG32) |
4276                            FW_LEN16(c));
4277        if (fw_caps == FW_CAPS16)
4278                c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4279        else
4280                c.u.l1cfg32.rcap32 = cpu_to_be32(FW_PORT_CAP32_ANEG);
4281        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4282}
4283
4284typedef void (*int_handler_t)(struct adapter *adap);
4285
4286struct intr_info {
4287        unsigned int mask;       /* bits to check in interrupt status */
4288        const char *msg;         /* message to print or NULL */
4289        short stat_idx;          /* stat counter to increment or -1 */
4290        unsigned short fatal;    /* whether the condition reported is fatal */
4291        int_handler_t int_handler; /* platform-specific int handler */
4292};
4293
4294/**
4295 *      t4_handle_intr_status - table driven interrupt handler
4296 *      @adapter: the adapter that generated the interrupt
4297 *      @reg: the interrupt status register to process
4298 *      @acts: table of interrupt actions
4299 *
4300 *      A table driven interrupt handler that applies a set of masks to an
4301 *      interrupt status word and performs the corresponding actions if the
4302 *      interrupts described by the mask have occurred.  The actions include
4303 *      optionally emitting a warning or alert message.  The table is terminated
4304 *      by an entry specifying mask 0.  Returns the number of fatal interrupt
4305 *      conditions.
4306 */
4307static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4308                                 const struct intr_info *acts)
4309{
4310        int fatal = 0;
4311        unsigned int mask = 0;
4312        unsigned int status = t4_read_reg(adapter, reg);
4313
4314        for ( ; acts->mask; ++acts) {
4315                if (!(status & acts->mask))
4316                        continue;
4317                if (acts->fatal) {
4318                        fatal++;
4319                        dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4320                                  status & acts->mask);
4321                } else if (acts->msg && printk_ratelimit())
4322                        dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4323                                 status & acts->mask);
4324                if (acts->int_handler)
4325                        acts->int_handler(adapter);
4326                mask |= acts->mask;
4327        }
4328        status &= mask;
4329        if (status)                           /* clear processed interrupts */
4330                t4_write_reg(adapter, reg, status);
4331        return fatal;
4332}
4333
4334/*
4335 * Interrupt handler for the PCIE module.
4336 */
4337static void pcie_intr_handler(struct adapter *adapter)
4338{
4339        static const struct intr_info sysbus_intr_info[] = {
4340                { RNPP_F, "RXNP array parity error", -1, 1 },
4341                { RPCP_F, "RXPC array parity error", -1, 1 },
4342                { RCIP_F, "RXCIF array parity error", -1, 1 },
4343                { RCCP_F, "Rx completions control array parity error", -1, 1 },
4344                { RFTP_F, "RXFT array parity error", -1, 1 },
4345                { 0 }
4346        };
4347        static const struct intr_info pcie_port_intr_info[] = {
4348                { TPCP_F, "TXPC array parity error", -1, 1 },
4349                { TNPP_F, "TXNP array parity error", -1, 1 },
4350                { TFTP_F, "TXFT array parity error", -1, 1 },
4351                { TCAP_F, "TXCA array parity error", -1, 1 },
4352                { TCIP_F, "TXCIF array parity error", -1, 1 },
4353                { RCAP_F, "RXCA array parity error", -1, 1 },
4354                { OTDD_F, "outbound request TLP discarded", -1, 1 },
4355                { RDPE_F, "Rx data parity error", -1, 1 },
4356                { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4357                { 0 }
4358        };
4359        static const struct intr_info pcie_intr_info[] = {
4360                { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4361                { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4362                { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4363                { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4364                { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4365                { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4366                { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4367                { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4368                { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4369                { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4370                { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4371                { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4372                { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4373                { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4374                { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4375                { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4376                { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4377                { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4378                { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4379                { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4380                { FIDPERR_F, "PCI FID parity error", -1, 1 },
4381                { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4382                { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4383                { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4384                { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4385                { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4386                { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4387                { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4388                { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4389                { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4390                  -1, 0 },
4391                { 0 }
4392        };
4393
4394        static struct intr_info t5_pcie_intr_info[] = {
4395                { MSTGRPPERR_F, "Master Response Read Queue parity error",
4396                  -1, 1 },
4397                { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4398                { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4399                { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4400                { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4401                { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4402                { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4403                { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4404                  -1, 1 },
4405                { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4406                  -1, 1 },
4407                { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4408                { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4409                { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4410                { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4411                { DREQWRPERR_F, "PCI DMA channel write request parity error",
4412                  -1, 1 },
4413                { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4414                { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4415                { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4416                { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4417                { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4418                { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4419                { FIDPERR_F, "PCI FID parity error", -1, 1 },
4420                { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4421                { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4422                { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4423                { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4424                  -1, 1 },
4425                { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4426                  -1, 1 },
4427                { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4428                { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4429                { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4430                { READRSPERR_F, "Outbound read error", -1, 0 },
4431                { 0 }
4432        };
4433
4434        int fat;
4435
4436        if (is_t4(adapter->params.chip))
4437                fat = t4_handle_intr_status(adapter,
4438                                PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4439                                sysbus_intr_info) +
4440                        t4_handle_intr_status(adapter,
4441                                        PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4442                                        pcie_port_intr_info) +
4443                        t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4444                                              pcie_intr_info);
4445        else
4446                fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4447                                            t5_pcie_intr_info);
4448
4449        if (fat)
4450                t4_fatal_err(adapter);
4451}
4452
4453/*
4454 * TP interrupt handler.
4455 */
4456static void tp_intr_handler(struct adapter *adapter)
4457{
4458        static const struct intr_info tp_intr_info[] = {
4459                { 0x3fffffff, "TP parity error", -1, 1 },
4460                { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4461                { 0 }
4462        };
4463
4464        if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4465                t4_fatal_err(adapter);
4466}
4467
4468/*
4469 * SGE interrupt handler.
4470 */
4471static void sge_intr_handler(struct adapter *adapter)
4472{
4473        u32 v = 0, perr;
4474        u32 err;
4475
4476        static const struct intr_info sge_intr_info[] = {
4477                { ERR_CPL_EXCEED_IQE_SIZE_F,
4478                  "SGE received CPL exceeding IQE size", -1, 1 },
4479                { ERR_INVALID_CIDX_INC_F,
4480                  "SGE GTS CIDX increment too large", -1, 0 },
4481                { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4482                { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4483                { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4484                  "SGE IQID > 1023 received CPL for FL", -1, 0 },
4485                { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4486                  0 },
4487                { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4488                  0 },
4489                { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4490                  0 },
4491                { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4492                  0 },
4493                { ERR_ING_CTXT_PRIO_F,
4494                  "SGE too many priority ingress contexts", -1, 0 },
4495                { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4496                { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4497                { 0 }
4498        };
4499
4500        static struct intr_info t4t5_sge_intr_info[] = {
4501                { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4502                { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4503                { ERR_EGR_CTXT_PRIO_F,
4504                  "SGE too many priority egress contexts", -1, 0 },
4505                { 0 }
4506        };
4507
4508        perr = t4_read_reg(adapter, SGE_INT_CAUSE1_A);
4509        if (perr) {
4510                v |= perr;
4511                dev_alert(adapter->pdev_dev, "SGE Cause1 Parity Error %#x\n",
4512                          perr);
4513        }
4514
4515        perr = t4_read_reg(adapter, SGE_INT_CAUSE2_A);
4516        if (perr) {
4517                v |= perr;
4518                dev_alert(adapter->pdev_dev, "SGE Cause2 Parity Error %#x\n",
4519                          perr);
4520        }
4521
4522        if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {
4523                perr = t4_read_reg(adapter, SGE_INT_CAUSE5_A);
4524                /* Parity error (CRC) for err_T_RxCRC is trivial, ignore it */
4525                perr &= ~ERR_T_RXCRC_F;
4526                if (perr) {
4527                        v |= perr;
4528                        dev_alert(adapter->pdev_dev,
4529                                  "SGE Cause5 Parity Error %#x\n", perr);
4530                }
4531        }
4532
4533        v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4534        if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4535                v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4536                                           t4t5_sge_intr_info);
4537
4538        err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4539        if (err & ERROR_QID_VALID_F) {
4540                dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4541                        ERROR_QID_G(err));
4542                if (err & UNCAPTURED_ERROR_F)
4543                        dev_err(adapter->pdev_dev,
4544                                "SGE UNCAPTURED_ERROR set (clearing)\n");
4545                t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4546                             UNCAPTURED_ERROR_F);
4547        }
4548
4549        if (v != 0)
4550                t4_fatal_err(adapter);
4551}
4552
4553#define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4554                      OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4555#define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4556                      IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4557
4558/*
4559 * CIM interrupt handler.
4560 */
4561static void cim_intr_handler(struct adapter *adapter)
4562{
4563        static const struct intr_info cim_intr_info[] = {
4564                { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4565                { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4566                { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4567                { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4568                { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4569                { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4570                { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4571                { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4572                { 0 }
4573        };
4574        static const struct intr_info cim_upintr_info[] = {
4575                { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4576                { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4577                { ILLWRINT_F, "CIM illegal write", -1, 1 },
4578                { ILLRDINT_F, "CIM illegal read", -1, 1 },
4579                { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4580                { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4581                { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4582                { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4583                { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4584                { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4585                { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4586                { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4587                { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4588                { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4589                { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4590                { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4591                { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4592                { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4593                { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4594                { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4595                { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4596                { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4597                { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4598                { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4599                { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4600                { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4601                { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4602                { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4603                { 0 }
4604        };
4605
4606        u32 val, fw_err;
4607        int fat;
4608
4609        fw_err = t4_read_reg(adapter, PCIE_FW_A);
4610        if (fw_err & PCIE_FW_ERR_F)
4611                t4_report_fw_error(adapter);
4612
4613        /* When the Firmware detects an internal error which normally
4614         * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4615         * in order to make sure the Host sees the Firmware Crash.  So
4616         * if we have a Timer0 interrupt and don't see a Firmware Crash,
4617         * ignore the Timer0 interrupt.
4618         */
4619
4620        val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4621        if (val & TIMER0INT_F)
4622                if (!(fw_err & PCIE_FW_ERR_F) ||
4623                    (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4624                        t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4625                                     TIMER0INT_F);
4626
4627        fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4628                                    cim_intr_info) +
4629              t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4630                                    cim_upintr_info);
4631        if (fat)
4632                t4_fatal_err(adapter);
4633}
4634
4635/*
4636 * ULP RX interrupt handler.
4637 */
4638static void ulprx_intr_handler(struct adapter *adapter)
4639{
4640        static const struct intr_info ulprx_intr_info[] = {
4641                { 0x1800000, "ULPRX context error", -1, 1 },
4642                { 0x7fffff, "ULPRX parity error", -1, 1 },
4643                { 0 }
4644        };
4645
4646        if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4647                t4_fatal_err(adapter);
4648}
4649
4650/*
4651 * ULP TX interrupt handler.
4652 */
4653static void ulptx_intr_handler(struct adapter *adapter)
4654{
4655        static const struct intr_info ulptx_intr_info[] = {
4656                { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4657                  0 },
4658                { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4659                  0 },
4660                { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4661                  0 },
4662                { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4663                  0 },
4664                { 0xfffffff, "ULPTX parity error", -1, 1 },
4665                { 0 }
4666        };
4667
4668        if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4669                t4_fatal_err(adapter);
4670}
4671
4672/*
4673 * PM TX interrupt handler.
4674 */
4675static void pmtx_intr_handler(struct adapter *adapter)
4676{
4677        static const struct intr_info pmtx_intr_info[] = {
4678                { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4679                { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4680                { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4681                { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4682                { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4683                { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4684                { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4685                  -1, 1 },
4686                { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4687                { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4688                { 0 }
4689        };
4690
4691        if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4692                t4_fatal_err(adapter);
4693}
4694
4695/*
4696 * PM RX interrupt handler.
4697 */
4698static void pmrx_intr_handler(struct adapter *adapter)
4699{
4700        static const struct intr_info pmrx_intr_info[] = {
4701                { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4702                { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4703                { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4704                { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4705                  -1, 1 },
4706                { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4707                { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4708                { 0 }
4709        };
4710
4711        if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4712                t4_fatal_err(adapter);
4713}
4714
4715/*
4716 * CPL switch interrupt handler.
4717 */
4718static void cplsw_intr_handler(struct adapter *adapter)
4719{
4720        static const struct intr_info cplsw_intr_info[] = {
4721                { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4722                { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4723                { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4724                { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4725                { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4726                { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4727                { 0 }
4728        };
4729
4730        if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4731                t4_fatal_err(adapter);
4732}
4733
4734/*
4735 * LE interrupt handler.
4736 */
4737static void le_intr_handler(struct adapter *adap)
4738{
4739        enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4740        static const struct intr_info le_intr_info[] = {
4741                { LIPMISS_F, "LE LIP miss", -1, 0 },
4742                { LIP0_F, "LE 0 LIP error", -1, 0 },
4743                { PARITYERR_F, "LE parity error", -1, 1 },
4744                { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4745                { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4746                { 0 }
4747        };
4748
4749        static struct intr_info t6_le_intr_info[] = {
4750                { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4751                { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4752                { CMDTIDERR_F, "LE cmd tid error", -1, 1 },
4753                { TCAMINTPERR_F, "LE parity error", -1, 1 },
4754                { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4755                { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4756                { HASHTBLMEMCRCERR_F, "LE hash table mem crc error", -1, 0 },
4757                { 0 }
4758        };
4759
4760        if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4761                                  (chip <= CHELSIO_T5) ?
4762                                  le_intr_info : t6_le_intr_info))
4763                t4_fatal_err(adap);
4764}
4765
4766/*
4767 * MPS interrupt handler.
4768 */
4769static void mps_intr_handler(struct adapter *adapter)
4770{
4771        static const struct intr_info mps_rx_intr_info[] = {
4772                { 0xffffff, "MPS Rx parity error", -1, 1 },
4773                { 0 }
4774        };
4775        static const struct intr_info mps_tx_intr_info[] = {
4776                { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4777                { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4778                { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4779                  -1, 1 },
4780                { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4781                  -1, 1 },
4782                { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4783                { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4784                { FRMERR_F, "MPS Tx framing error", -1, 1 },
4785                { 0 }
4786        };
4787        static const struct intr_info t6_mps_tx_intr_info[] = {
4788                { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4789                { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4790                { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4791                  -1, 1 },
4792                { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4793                  -1, 1 },
4794                /* MPS Tx Bubble is normal for T6 */
4795                { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4796                { FRMERR_F, "MPS Tx framing error", -1, 1 },
4797                { 0 }
4798        };
4799        static const struct intr_info mps_trc_intr_info[] = {
4800                { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4801                { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4802                  -1, 1 },
4803                { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4804                { 0 }
4805        };
4806        static const struct intr_info mps_stat_sram_intr_info[] = {
4807                { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4808                { 0 }
4809        };
4810        static const struct intr_info mps_stat_tx_intr_info[] = {
4811                { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4812                { 0 }
4813        };
4814        static const struct intr_info mps_stat_rx_intr_info[] = {
4815                { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4816                { 0 }
4817        };
4818        static const struct intr_info mps_cls_intr_info[] = {
4819                { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4820                { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4821                { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4822                { 0 }
4823        };
4824
4825        int fat;
4826
4827        fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4828                                    mps_rx_intr_info) +
4829              t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4830                                    is_t6(adapter->params.chip)
4831                                    ? t6_mps_tx_intr_info
4832                                    : mps_tx_intr_info) +
4833              t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4834                                    mps_trc_intr_info) +
4835              t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4836                                    mps_stat_sram_intr_info) +
4837              t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4838                                    mps_stat_tx_intr_info) +
4839              t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4840                                    mps_stat_rx_intr_info) +
4841              t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4842                                    mps_cls_intr_info);
4843
4844        t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4845        t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4846        if (fat)
4847                t4_fatal_err(adapter);
4848}
4849
4850#define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4851                      ECC_UE_INT_CAUSE_F)
4852
4853/*
4854 * EDC/MC interrupt handler.
4855 */
4856static void mem_intr_handler(struct adapter *adapter, int idx)
4857{
4858        static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4859
4860        unsigned int addr, cnt_addr, v;
4861
4862        if (idx <= MEM_EDC1) {
4863                addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4864                cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4865        } else if (idx == MEM_MC) {
4866                if (is_t4(adapter->params.chip)) {
4867                        addr = MC_INT_CAUSE_A;
4868                        cnt_addr = MC_ECC_STATUS_A;
4869                } else {
4870                        addr = MC_P_INT_CAUSE_A;
4871                        cnt_addr = MC_P_ECC_STATUS_A;
4872                }
4873        } else {
4874                addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4875                cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4876        }
4877
4878        v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4879        if (v & PERR_INT_CAUSE_F)
4880                dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4881                          name[idx]);
4882        if (v & ECC_CE_INT_CAUSE_F) {
4883                u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4884
4885                t4_edc_err_read(adapter, idx);
4886
4887                t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4888                if (printk_ratelimit())
4889                        dev_warn(adapter->pdev_dev,
4890                                 "%u %s correctable ECC data error%s\n",
4891                                 cnt, name[idx], cnt > 1 ? "s" : "");
4892        }
4893        if (v & ECC_UE_INT_CAUSE_F)
4894                dev_alert(adapter->pdev_dev,
4895                          "%s uncorrectable ECC data error\n", name[idx]);
4896
4897        t4_write_reg(adapter, addr, v);
4898        if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4899                t4_fatal_err(adapter);
4900}
4901
4902/*
4903 * MA interrupt handler.
4904 */
4905static void ma_intr_handler(struct adapter *adap)
4906{
4907        u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4908
4909        if (status & MEM_PERR_INT_CAUSE_F) {
4910                dev_alert(adap->pdev_dev,
4911                          "MA parity error, parity status %#x\n",
4912                          t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4913                if (is_t5(adap->params.chip))
4914                        dev_alert(adap->pdev_dev,
4915                                  "MA parity error, parity status %#x\n",
4916                                  t4_read_reg(adap,
4917                                              MA_PARITY_ERROR_STATUS2_A));
4918        }
4919        if (status & MEM_WRAP_INT_CAUSE_F) {
4920                v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4921                dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4922                          "client %u to address %#x\n",
4923                          MEM_WRAP_CLIENT_NUM_G(v),
4924                          MEM_WRAP_ADDRESS_G(v) << 4);
4925        }
4926        t4_write_reg(adap, MA_INT_CAUSE_A, status);
4927        t4_fatal_err(adap);
4928}
4929
4930/*
4931 * SMB interrupt handler.
4932 */
4933static void smb_intr_handler(struct adapter *adap)
4934{
4935        static const struct intr_info smb_intr_info[] = {
4936                { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4937                { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4938                { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4939                { 0 }
4940        };
4941
4942        if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4943                t4_fatal_err(adap);
4944}
4945
4946/*
4947 * NC-SI interrupt handler.
4948 */
4949static void ncsi_intr_handler(struct adapter *adap)
4950{
4951        static const struct intr_info ncsi_intr_info[] = {
4952                { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4953                { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4954                { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4955                { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4956                { 0 }
4957        };
4958
4959        if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4960                t4_fatal_err(adap);
4961}
4962
4963/*
4964 * XGMAC interrupt handler.
4965 */
4966static void xgmac_intr_handler(struct adapter *adap, int port)
4967{
4968        u32 v, int_cause_reg;
4969
4970        if (is_t4(adap->params.chip))
4971                int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4972        else
4973                int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4974
4975        v = t4_read_reg(adap, int_cause_reg);
4976
4977        v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4978        if (!v)
4979                return;
4980
4981        if (v & TXFIFO_PRTY_ERR_F)
4982                dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4983                          port);
4984        if (v & RXFIFO_PRTY_ERR_F)
4985                dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4986                          port);
4987        t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4988        t4_fatal_err(adap);
4989}
4990
4991/*
4992 * PL interrupt handler.
4993 */
4994static void pl_intr_handler(struct adapter *adap)
4995{
4996        static const struct intr_info pl_intr_info[] = {
4997                { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4998                { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4999                { 0 }
5000        };

5001
5002        if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
5003                t4_fatal_err(adap);
5004}
5005
5006#define PF_INTR_MASK (PFSW_F)
5007#define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
5008                EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
5009                CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
5010
5011/**
5012 *      t4_slow_intr_handler - control path interrupt handler
5013 *      @adapter: the adapter
5014 *
5015 *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
5016 *      The designation 'slow' is because it involves register reads, while
5017 *      data interrupts typically don't involve any MMIOs.
5018 */
5019int t4_slow_intr_handler(struct adapter *adapter)
5020{
5021        /* There are rare cases where a PL_INT_CAUSE bit may end up getting
5022         * set when the corresponding PL_INT_ENABLE bit isn't set.  It's
5023         * easiest just to mask that case here.
5024         */
5025        u32 raw_cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
5026        u32 enable = t4_read_reg(adapter, PL_INT_ENABLE_A);
5027        u32 cause = raw_cause & enable;
5028
5029        if (!(cause & GLBL_INTR_MASK))
5030                return 0;
5031        if (cause & CIM_F)
5032                cim_intr_handler(adapter);
5033        if (cause & MPS_F)
5034                mps_intr_handler(adapter);
5035        if (cause & NCSI_F)
5036                ncsi_intr_handler(adapter);
5037        if (cause & PL_F)
5038                pl_intr_handler(adapter);
5039        if (cause & SMB_F)
5040                smb_intr_handler(adapter);
5041        if (cause & XGMAC0_F)
5042                xgmac_intr_handler(adapter, 0);
5043        if (cause & XGMAC1_F)
5044                xgmac_intr_handler(adapter, 1);
5045        if (cause & XGMAC_KR0_F)
5046                xgmac_intr_handler(adapter, 2);
5047        if (cause & XGMAC_KR1_F)
5048                xgmac_intr_handler(adapter, 3);
5049        if (cause & PCIE_F)
5050                pcie_intr_handler(adapter);
5051        if (cause & MC_F)
5052                mem_intr_handler(adapter, MEM_MC);
5053        if (is_t5(adapter->params.chip) && (cause & MC1_F))
5054                mem_intr_handler(adapter, MEM_MC1);
5055        if (cause & EDC0_F)
5056                mem_intr_handler(adapter, MEM_EDC0);
5057        if (cause & EDC1_F)
5058                mem_intr_handler(adapter, MEM_EDC1);
5059        if (cause & LE_F)
5060                le_intr_handler(adapter);
5061        if (cause & TP_F)
5062                tp_intr_handler(adapter);
5063        if (cause & MA_F)
5064                ma_intr_handler(adapter);
5065        if (cause & PM_TX_F)
5066                pmtx_intr_handler(adapter);
5067        if (cause & PM_RX_F)
5068                pmrx_intr_handler(adapter);
5069        if (cause & ULP_RX_F)
5070                ulprx_intr_handler(adapter);
5071        if (cause & CPL_SWITCH_F)
5072                cplsw_intr_handler(adapter);
5073        if (cause & SGE_F)
5074                sge_intr_handler(adapter);
5075        if (cause & ULP_TX_F)
5076                ulptx_intr_handler(adapter);
5077
5078        /* Clear the interrupts just processed for which we are the master. */
5079        t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & GLBL_INTR_MASK);
5080        (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
5081        return 1;
5082}
5083
5084/**
5085 *      t4_intr_enable - enable interrupts
5086 *      @adapter: the adapter whose interrupts should be enabled
5087 *
5088 *      Enable PF-specific interrupts for the calling function and the top-level
5089 *      interrupt concentrator for global interrupts.  Interrupts are already
5090 *      enabled at each module, here we just enable the roots of the interrupt
5091 *      hierarchies.
5092 *
5093 *      Note: this function should be called only when the driver manages
5094 *      non PF-specific interrupts from the various HW modules.  Only one PCI
5095 *      function at a time should be doing this.
5096 */
5097void t4_intr_enable(struct adapter *adapter)
5098{
5099        u32 val = 0;
5100        u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5101        u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5102                        SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5103
5104        if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
5105                val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
5106        t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
5107                     ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
5108                     ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
5109                     ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
5110                     ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
5111                     ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
5112                     DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
5113        t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
5114        t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
5115}
5116
5117/**
5118 *      t4_intr_disable - disable interrupts
5119 *      @adapter: the adapter whose interrupts should be disabled
5120 *
5121 *      Disable interrupts.  We only disable the top-level interrupt
5122 *      concentrators.  The caller must be a PCI function managing global
5123 *      interrupts.
5124 */
5125void t4_intr_disable(struct adapter *adapter)
5126{
5127        u32 whoami, pf;
5128
5129        if (pci_channel_offline(adapter->pdev))
5130                return;
5131
5132        whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5133        pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5134                        SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5135
5136        t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
5137        t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
5138}
5139
5140unsigned int t4_chip_rss_size(struct adapter *adap)
5141{
5142        if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
5143                return RSS_NENTRIES;
5144        else
5145                return T6_RSS_NENTRIES;
5146}
5147
5148/**
5149 *      t4_config_rss_range - configure a portion of the RSS mapping table
5150 *      @adapter: the adapter
5151 *      @mbox: mbox to use for the FW command
5152 *      @viid: virtual interface whose RSS subtable is to be written
5153 *      @start: start entry in the table to write
5154 *      @n: how many table entries to write
5155 *      @rspq: values for the response queue lookup table
5156 *      @nrspq: number of values in @rspq
5157 *
5158 *      Programs the selected part of the VI's RSS mapping table with the
5159 *      provided values.  If @nrspq < @n the supplied values are used repeatedly
5160 *      until the full table range is populated.
5161 *
5162 *      The caller must ensure the values in @rspq are in the range allowed for
5163 *      @viid.
5164 */
5165int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5166                        int start, int n, const u16 *rspq, unsigned int nrspq)
5167{
5168        int ret;
5169        const u16 *rsp = rspq;
5170        const u16 *rsp_end = rspq + nrspq;
5171        struct fw_rss_ind_tbl_cmd cmd;
5172
5173        memset(&cmd, 0, sizeof(cmd));
5174        cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
5175                               FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5176                               FW_RSS_IND_TBL_CMD_VIID_V(viid));
5177        cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5178
5179        /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5180        while (n > 0) {
5181                int nq = min(n, 32);
5182                __be32 *qp = &cmd.iq0_to_iq2;
5183
5184                cmd.niqid = cpu_to_be16(nq);
5185                cmd.startidx = cpu_to_be16(start);
5186
5187                start += nq;
5188                n -= nq;
5189
5190                while (nq > 0) {
5191                        unsigned int v;
5192
5193                        v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
5194                        if (++rsp >= rsp_end)
5195                                rsp = rspq;
5196                        v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
5197                        if (++rsp >= rsp_end)
5198                                rsp = rspq;
5199                        v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
5200                        if (++rsp >= rsp_end)
5201                                rsp = rspq;
5202
5203                        *qp++ = cpu_to_be32(v);
5204                        nq -= 3;
5205                }
5206
5207                ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5208                if (ret)
5209                        return ret;
5210        }
5211        return 0;
5212}
5213
5214/**
5215 *      t4_config_glbl_rss - configure the global RSS mode
5216 *      @adapter: the adapter
5217 *      @mbox: mbox to use for the FW command
5218 *      @mode: global RSS mode
5219 *      @flags: mode-specific flags
5220 *
5221 *      Sets the global RSS mode.
5222 */
5223int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5224                       unsigned int flags)
5225{
5226        struct fw_rss_glb_config_cmd c;
5227
5228        memset(&c, 0, sizeof(c));
5229        c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5230                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5231        c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5232        if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5233                c.u.manual.mode_pkd =
5234                        cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5235        } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5236                c.u.basicvirtual.mode_pkd =
5237                        cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5238                c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5239        } else
5240                return -EINVAL;
5241        return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5242}
5243
5244/**
5245 *      t4_config_vi_rss - configure per VI RSS settings
5246 *      @adapter: the adapter
5247 *      @mbox: mbox to use for the FW command
5248 *      @viid: the VI id
5249 *      @flags: RSS flags
5250 *      @defq: id of the default RSS queue for the VI.
5251 *
5252 *      Configures VI-specific RSS properties.
5253 */
5254int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5255                     unsigned int flags, unsigned int defq)
5256{
5257        struct fw_rss_vi_config_cmd c;
5258
5259        memset(&c, 0, sizeof(c));
5260        c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5261                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5262                                   FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5263        c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5264        c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5265                                        FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5266        return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5267}
5268
5269/* Read an RSS table row */
5270static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5271{
5272        t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5273        return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5274                                   5, 0, val);
5275}
5276
5277/**
5278 *      t4_read_rss - read the contents of the RSS mapping table
5279 *      @adapter: the adapter
5280 *      @map: holds the contents of the RSS mapping table
5281 *
5282 *      Reads the contents of the RSS hash->queue mapping table.
5283 */
5284int t4_read_rss(struct adapter *adapter, u16 *map)
5285{
5286        int i, ret, nentries;
5287        u32 val;
5288
5289        nentries = t4_chip_rss_size(adapter);
5290        for (i = 0; i < nentries / 2; ++i) {
5291                ret = rd_rss_row(adapter, i, &val);
5292                if (ret)
5293                        return ret;
5294                *map++ = LKPTBLQUEUE0_G(val);
5295                *map++ = LKPTBLQUEUE1_G(val);
5296        }
5297        return 0;
5298}
5299
5300static unsigned int t4_use_ldst(struct adapter *adap)
5301{
5302        return (adap->flags & CXGB4_FW_OK) && !adap->use_bd;
5303}
5304
5305/**
5306 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5307 * @adap: the adapter
5308 * @cmd: TP fw ldst address space type
5309 * @vals: where the indirect register values are stored/written
5310 * @nregs: how many indirect registers to read/write
5311 * @start_index: index of first indirect register to read/write
5312 * @rw: Read (1) or Write (0)
5313 * @sleep_ok: if true we may sleep while awaiting command completion
5314 *
5315 * Access TP indirect registers through LDST
5316 */
5317static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5318                            unsigned int nregs, unsigned int start_index,
5319                            unsigned int rw, bool sleep_ok)
5320{
5321        int ret = 0;
5322        unsigned int i;
5323        struct fw_ldst_cmd c;
5324
5325        for (i = 0; i < nregs; i++) {
5326                memset(&c, 0, sizeof(c));
5327                c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5328                                                FW_CMD_REQUEST_F |
5329                                                (rw ? FW_CMD_READ_F :
5330                                                      FW_CMD_WRITE_F) |
5331                                                FW_LDST_CMD_ADDRSPACE_V(cmd));
5332                c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5333
5334                c.u.addrval.addr = cpu_to_be32(start_index + i);
5335                c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
5336                ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5337                                      sleep_ok);
5338                if (ret)
5339                        return ret;
5340
5341                if (rw)
5342                        vals[i] = be32_to_cpu(c.u.addrval.val);
5343        }
5344        return 0;
5345}
5346
5347/**
5348 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5349 * @adap: the adapter
5350 * @reg_addr: Address Register
5351 * @reg_data: Data register
5352 * @buff: where the indirect register values are stored/written
5353 * @nregs: how many indirect registers to read/write
5354 * @start_index: index of first indirect register to read/write
5355 * @rw: READ(1) or WRITE(0)
5356 * @sleep_ok: if true we may sleep while awaiting command completion
5357 *
5358 * Read/Write TP indirect registers through LDST if possible.
5359 * Else, use backdoor access
5360 **/
5361static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5362                              u32 *buff, u32 nregs, u32 start_index, int rw,
5363                              bool sleep_ok)
5364{
5365        int rc = -EINVAL;
5366        int cmd;
5367
5368        switch (reg_addr) {
5369        case TP_PIO_ADDR_A:
5370                cmd = FW_LDST_ADDRSPC_TP_PIO;
5371                break;
5372        case TP_TM_PIO_ADDR_A:
5373                cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5374                break;
5375        case TP_MIB_INDEX_A:
5376                cmd = FW_LDST_ADDRSPC_TP_MIB;
5377                break;
5378        default:
5379                goto indirect_access;
5380        }
5381
5382        if (t4_use_ldst(adap))
5383                rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5384                                      sleep_ok);
5385
5386indirect_access:
5387
5388        if (rc) {
5389                if (rw)
5390                        t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5391                                         start_index);
5392                else
5393                        t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5394                                          start_index);
5395        }
5396}
5397
5398/**
5399 * t4_tp_pio_read - Read TP PIO registers
5400 * @adap: the adapter
5401 * @buff: where the indirect register values are written
5402 * @nregs: how many indirect registers to read
5403 * @start_index: index of first indirect register to read
5404 * @sleep_ok: if true we may sleep while awaiting command completion
5405 *
5406 * Read TP PIO Registers
5407 **/
5408void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5409                    u32 start_index, bool sleep_ok)
5410{
5411        t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5412                          start_index, 1, sleep_ok);
5413}
5414
5415/**
5416 * t4_tp_pio_write - Write TP PIO registers
5417 * @adap: the adapter
5418 * @buff: where the indirect register values are stored
5419 * @nregs: how many indirect registers to write
5420 * @start_index: index of first indirect register to write
5421 * @sleep_ok: if true we may sleep while awaiting command completion
5422 *
5423 * Write TP PIO Registers
5424 **/
5425static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5426                            u32 start_index, bool sleep_ok)
5427{
5428        t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5429                          start_index, 0, sleep_ok);
5430}
5431
5432/**
5433 * t4_tp_tm_pio_read - Read TP TM PIO registers
5434 * @adap: the adapter
5435 * @buff: where the indirect register values are written
5436 * @nregs: how many indirect registers to read
5437 * @start_index: index of first indirect register to read
5438 * @sleep_ok: if true we may sleep while awaiting command completion
5439 *
5440 * Read TP TM PIO Registers
5441 **/
5442void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5443                       u32 start_index, bool sleep_ok)
5444{
5445        t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5446                          nregs, start_index, 1, sleep_ok);
5447}
5448
5449/**
5450 * t4_tp_mib_read - Read TP MIB registers
5451 * @adap: the adapter
5452 * @buff: where the indirect register values are written
5453 * @nregs: how many indirect registers to read
5454 * @start_index: index of first indirect register to read
5455 * @sleep_ok: if true we may sleep while awaiting command completion
5456 *
5457 * Read TP MIB Registers
5458 **/
5459void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5460                    bool sleep_ok)
5461{
5462        t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5463                          start_index, 1, sleep_ok);
5464}
5465
5466/**
5467 *      t4_read_rss_key - read the global RSS key
5468 *      @adap: the adapter
5469 *      @key: 10-entry array holding the 320-bit RSS key
5470 *      @sleep_ok: if true we may sleep while awaiting command completion
5471 *
5472 *      Reads the global 320-bit RSS key.
5473 */
5474void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5475{
5476        t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5477}
5478
5479/**
5480 *      t4_write_rss_key - program one of the RSS keys
5481 *      @adap: the adapter
5482 *      @key: 10-entry array holding the 320-bit RSS key
5483 *      @idx: which RSS key to write
5484 *      @sleep_ok: if true we may sleep while awaiting command completion
5485 *
5486 *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
5487 *      0..15 the corresponding entry in the RSS key table is written,
5488 *      otherwise the global RSS key is written.
5489 */
5490void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5491                      bool sleep_ok)
5492{
5493        u8 rss_key_addr_cnt = 16;
5494        u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5495
5496        /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5497         * allows access to key addresses 16-63 by using KeyWrAddrX
5498         * as index[5:4](upper 2) into key table
5499         */
5500        if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5501            (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5502                rss_key_addr_cnt = 32;
5503
5504        t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5505
5506        if (idx >= 0 && idx < rss_key_addr_cnt) {
5507                if (rss_key_addr_cnt > 16)
5508                        t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5509                                     KEYWRADDRX_V(idx >> 4) |
5510                                     T6_VFWRADDR_V(idx) | KEYWREN_F);
5511                else
5512                        t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5513                                     KEYWRADDR_V(idx) | KEYWREN_F);
5514        }
5515}
5516
5517/**
5518 *      t4_read_rss_pf_config - read PF RSS Configuration Table
5519 *      @adapter: the adapter
5520 *      @index: the entry in the PF RSS table to read
5521 *      @valp: where to store the returned value
5522 *      @sleep_ok: if true we may sleep while awaiting command completion
5523 *
5524 *      Reads the PF RSS Configuration Table at the specified index and returns
5525 *      the value found there.
5526 */
5527void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5528                           u32 *valp, bool sleep_ok)
5529{
5530        t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5531}
5532
5533/**
5534 *      t4_read_rss_vf_config - read VF RSS Configuration Table
5535 *      @adapter: the adapter
5536 *      @index: the entry in the VF RSS table to read
5537 *      @vfl: where to store the returned VFL
5538 *      @vfh: where to store the returned VFH
5539 *      @sleep_ok: if true we may sleep while awaiting command completion
5540 *
5541 *      Reads the VF RSS Configuration Table at the specified index and returns
5542 *      the (VFL, VFH) values found there.
5543 */
5544void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5545                           u32 *vfl, u32 *vfh, bool sleep_ok)
5546{
5547        u32 vrt, mask, data;
5548
5549        if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5550                mask = VFWRADDR_V(VFWRADDR_M);
5551                data = VFWRADDR_V(index);
5552        } else {
5553                 mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
5554                 data = T6_VFWRADDR_V(index);
5555        }
5556
5557        /* Request that the index'th VF Table values be read into VFL/VFH.
5558         */
5559        vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5560        vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5561        vrt |= data | VFRDEN_F;
5562        t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5563
5564        /* Grab the VFL/VFH values ...
5565         */
5566        t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5567        t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5568}
5569
5570/**
5571 *      t4_read_rss_pf_map - read PF RSS Map
5572 *      @adapter: the adapter
5573 *      @sleep_ok: if true we may sleep while awaiting command completion
5574 *
5575 *      Reads the PF RSS Map register and returns its value.
5576 */
5577u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5578{
5579        u32 pfmap;
5580
5581        t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5582        return pfmap;
5583}
5584
5585/**
5586 *      t4_read_rss_pf_mask - read PF RSS Mask
5587 *      @adapter: the adapter
5588 *      @sleep_ok: if true we may sleep while awaiting command completion
5589 *
5590 *      Reads the PF RSS Mask register and returns its value.
5591 */
5592u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5593{
5594        u32 pfmask;
5595
5596        t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5597        return pfmask;
5598}
5599
5600/**
5601 *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
5602 *      @adap: the adapter
5603 *      @v4: holds the TCP/IP counter values
5604 *      @v6: holds the TCP/IPv6 counter values
5605 *      @sleep_ok: if true we may sleep while awaiting command completion
5606 *
5607 *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5608 *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5609 */
5610void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5611                         struct tp_tcp_stats *v6, bool sleep_ok)
5612{
5613        u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5614
5615#define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5616#define STAT(x)     val[STAT_IDX(x)]
5617#define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5618
5619        if (v4) {
5620                t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5621                               TP_MIB_TCP_OUT_RST_A, sleep_ok);
5622                v4->tcp_out_rsts = STAT(OUT_RST);
5623                v4->tcp_in_segs  = STAT64(IN_SEG);
5624                v4->tcp_out_segs = STAT64(OUT_SEG);
5625                v4->tcp_retrans_segs = STAT64(RXT_SEG);
5626        }
5627        if (v6) {
5628                t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5629                               TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5630                v6->tcp_out_rsts = STAT(OUT_RST);
5631                v6->tcp_in_segs  = STAT64(IN_SEG);
5632                v6->tcp_out_segs = STAT64(OUT_SEG);
5633                v6->tcp_retrans_segs = STAT64(RXT_SEG);
5634        }
5635#undef STAT64
5636#undef STAT
5637#undef STAT_IDX
5638}
5639
5640/**
5641 *      t4_tp_get_err_stats - read TP's error MIB counters
5642 *      @adap: the adapter
5643 *      @st: holds the counter values
5644 *      @sleep_ok: if true we may sleep while awaiting command completion
5645 *
5646 *      Returns the values of TP's error counters.
5647 */
5648void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5649                         bool sleep_ok)
5650{
5651        int nchan = adap->params.arch.nchan;
5652
5653        t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5654                       sleep_ok);
5655        t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5656                       sleep_ok);
5657        t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5658                       sleep_ok);
5659        t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5660                       TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5661        t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5662                       TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5663        t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5664                       sleep_ok);
5665        t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5666                       TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5667        t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5668                       TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5669        t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5670                       sleep_ok);
5671}
5672
5673/**
5674 *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
5675 *      @adap: the adapter
5676 *      @st: holds the counter values
5677 *      @sleep_ok: if true we may sleep while awaiting command completion
5678 *
5679 *      Returns the values of TP's CPL counters.
5680 */
5681void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5682                         bool sleep_ok)
5683{
5684        int nchan = adap->params.arch.nchan;
5685
5686        t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5687
5688        t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5689}
5690
5691/**
5692 *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5693 *      @adap: the adapter
5694 *      @st: holds the counter values
5695 *      @sleep_ok: if true we may sleep while awaiting command completion
5696 *
5697 *      Returns the values of TP's RDMA counters.
5698 */
5699void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5700                          bool sleep_ok)
5701{
5702        t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5703                       sleep_ok);
5704}
5705
5706/**
5707 *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5708 *      @adap: the adapter
5709 *      @idx: the port index
5710 *      @st: holds the counter values
5711 *      @sleep_ok: if true we may sleep while awaiting command completion
5712 *
5713 *      Returns the values of TP's FCoE counters for the selected port.
5714 */
5715void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5716                       struct tp_fcoe_stats *st, bool sleep_ok)
5717{
5718        u32 val[2];
5719
5720        t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5721                       sleep_ok);
5722
5723        t4_tp_mib_read(adap, &st->frames_drop, 1,
5724                       TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5725
5726        t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5727                       sleep_ok);
5728
5729        st->octets_ddp = ((u64)val[0] << 32) | val[1];
5730}
5731
5732/**
5733 *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5734 *      @adap: the adapter
5735 *      @st: holds the counter values
5736 *      @sleep_ok: if true we may sleep while awaiting command completion
5737 *
5738 *      Returns the values of TP's counters for non-TCP directly-placed packets.
5739 */
5740void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5741                      bool sleep_ok)
5742{
5743        u32 val[4];
5744
5745        t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5746        st->frames = val[0];
5747        st->drops = val[1];
5748        st->octets = ((u64)val[2] << 32) | val[3];
5749}
5750
5751/**
5752 *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5753 *      @adap: the adapter
5754 *      @mtus: where to store the MTU values
5755 *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5756 *
5757 *      Reads the HW path MTU table.
5758 */
5759void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5760{
5761        u32 v;
5762        int i;
5763
5764        for (i = 0; i < NMTUS; ++i) {
5765                t4_write_reg(adap, TP_MTU_TABLE_A,
5766                             MTUINDEX_V(0xff) | MTUVALUE_V(i));
5767                v = t4_read_reg(adap, TP_MTU_TABLE_A);
5768                mtus[i] = MTUVALUE_G(v);
5769                if (mtu_log)
5770                        mtu_log[i] = MTUWIDTH_G(v);
5771        }
5772}
5773
5774/**
5775 *      t4_read_cong_tbl - reads the congestion control table
5776 *      @adap: the adapter
5777 *      @incr: where to store the alpha values
5778 *
5779 *      Reads the additive increments programmed into the HW congestion
5780 *      control table.
5781 */
5782void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5783{
5784        unsigned int mtu, w;
5785
5786        for (mtu = 0; mtu < NMTUS; ++mtu)
5787                for (w = 0; w < NCCTRL_WIN; ++w) {
5788                        t4_write_reg(adap, TP_CCTRL_TABLE_A,
5789                                     ROWINDEX_V(0xffff) | (mtu << 5) | w);
5790                        incr[mtu][w] = (u16)t4_read_reg(adap,
5791                                                TP_CCTRL_TABLE_A) & 0x1fff;
5792                }
5793}
5794
5795/**
5796 *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5797 *      @adap: the adapter
5798 *      @addr: the indirect TP register address
5799 *      @mask: specifies the field within the register to modify
5800 *      @val: new value for the field
5801 *
5802 *      Sets a field of an indirect TP register to the given value.
5803 */
5804void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5805                            unsigned int mask, unsigned int val)
5806{
5807        t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5808        val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5809        t4_write_reg(adap, TP_PIO_DATA_A, val);
5810}
5811
5812/**
5813 *      init_cong_ctrl - initialize congestion control parameters
5814 *      @a: the alpha values for congestion control
5815 *      @b: the beta values for congestion control
5816 *
5817 *      Initialize the congestion control parameters.
5818 */
5819static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5820{
5821        a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5822        a[9] = 2;
5823        a[10] = 3;
5824        a[11] = 4;
5825        a[12] = 5;
5826        a[13] = 6;
5827        a[14] = 7;
5828        a[15] = 8;
5829        a[16] = 9;
5830        a[17] = 10;
5831        a[18] = 14;
5832        a[19] = 17;
5833        a[20] = 21;
5834        a[21] = 25;
5835        a[22] = 30;
5836        a[23] = 35;
5837        a[24] = 45;
5838        a[25] = 60;
5839        a[26] = 80;
5840        a[27] = 100;
5841        a[28] = 200;
5842        a[29] = 300;
5843        a[30] = 400;
5844        a[31] = 500;
5845
5846        b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5847        b[9] = b[10] = 1;
5848        b[11] = b[12] = 2;
5849        b[13] = b[14] = b[15] = b[16] = 3;
5850        b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5851        b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5852        b[28] = b[29] = 6;
5853        b[30] = b[31] = 7;
5854}
5855
5856/* The minimum additive increment value for the congestion control table */
5857#define CC_MIN_INCR 2U
5858
5859/**
5860 *      t4_load_mtus - write the MTU and congestion control HW tables
5861 *      @adap: the adapter
5862 *      @mtus: the values for the MTU table
5863 *      @alpha: the values for the congestion control alpha parameter
5864 *      @beta: the values for the congestion control beta parameter
5865 *
5866 *      Write the HW MTU table with the supplied MTUs and the high-speed
5867 *      congestion control table with the supplied alpha, beta, and MTUs.
5868 *      We write the two tables together because the additive increments
5869 *      depend on the MTUs.
5870 */
5871void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5872                  const unsigned short *alpha, const unsigned short *beta)
5873{
5874        static const unsigned int avg_pkts[NCCTRL_WIN] = {
5875                2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5876                896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5877                28672, 40960, 57344, 81920, 114688, 163840, 229376
5878        };
5879
5880        unsigned int i, w;
5881
5882        for (i = 0; i < NMTUS; ++i) {
5883                unsigned int mtu = mtus[i];
5884                unsigned int log2 = fls(mtu);
5885
5886                if (!(mtu & ((1 << log2) >> 2)))     /* round */
5887                        log2--;
5888                t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5889                             MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5890
5891                for (w = 0; w < NCCTRL_WIN; ++w) {
5892                        unsigned int inc;
5893
5894                        inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5895                                  CC_MIN_INCR);
5896
5897                        t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5898                                     (w << 16) | (beta[w] << 13) | inc);
5899                }
5900        }
5901}
5902
5903/* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5904 * clocks.  The formula is
5905 *
5906 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5907 *
5908 * which is equivalent to
5909 *
5910 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5911 */
5912static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5913{
5914        u64 v = bytes256 * adap->params.vpd.cclk;
5915
5916        return v * 62 + v / 2;
5917}
5918
5919/**
5920 *      t4_get_chan_txrate - get the current per channel Tx rates
5921 *      @adap: the adapter
5922 *      @nic_rate: rates for NIC traffic
5923 *      @ofld_rate: rates for offloaded traffic
5924 *
5925 *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5926 *      for each channel.
5927 */
5928void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5929{
5930        u32 v;
5931
5932        v = t4_read_reg(adap, TP_TX_TRATE_A);
5933        nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5934        nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5935        if (adap->params.arch.nchan == NCHAN) {
5936                nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5937                nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5938        }
5939
5940        v = t4_read_reg(adap, TP_TX_ORATE_A);
5941        ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5942        ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5943        if (adap->params.arch.nchan == NCHAN) {
5944                ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5945                ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5946        }
5947}
5948
5949/**
5950 *      t4_set_trace_filter - configure one of the tracing filters
5951 *      @adap: the adapter
5952 *      @tp: the desired trace filter parameters
5953 *      @idx: which filter to configure
5954 *      @enable: whether to enable or disable the filter
5955 *
5956 *      Configures one of the tracing filters available in HW.  If @enable is
5957 *      %0 @tp is not examined and may be %NULL. The user is responsible to
5958 *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5959 */
5960int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5961                        int idx, int enable)
5962{
5963        int i, ofst = idx * 4;
5964        u32 data_reg, mask_reg, cfg;
5965
5966        if (!enable) {
5967                t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5968                return 0;
5969        }
5970
5971        cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5972        if (cfg & TRCMULTIFILTER_F) {
5973                /* If multiple tracers are enabled, then maximum
5974                 * capture size is 2.5KB (FIFO size of a single channel)
5975                 * minus 2 flits for CPL_TRACE_PKT header.
5976                 */
5977                if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5978                        return -EINVAL;
5979        } else {
5980                /* If multiple tracers are disabled, to avoid deadlocks
5981                 * maximum packet capture size of 9600 bytes is recommended.
5982                 * Also in this mode, only trace0 can be enabled and running.
5983                 */
5984                if (tp->snap_len > 9600 || idx)
5985                        return -EINVAL;
5986        }
5987
5988        if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5989            tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5990            tp->min_len > TFMINPKTSIZE_M)
5991                return -EINVAL;
5992
5993        /* stop the tracer we'll be changing */
5994        t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5995
5996        idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5997        data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5998        mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5999
6000        for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {

6001                t4_write_reg(adap, data_reg, tp->data[i]);
6002                t4_write_reg(adap, mask_reg, ~tp->mask[i]);
6003        }
6004        t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
6005                     TFCAPTUREMAX_V(tp->snap_len) |
6006                     TFMINPKTSIZE_V(tp->min_len));
6007        t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
6008                     TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
6009                     (is_t4(adap->params.chip) ?
6010                     TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
6011                     T5_TFPORT_V(tp->port) | T5_TFEN_F |
6012                     T5_TFINVERTMATCH_V(tp->invert)));
6013
6014        return 0;
6015}
6016
6017/**
6018 *      t4_get_trace_filter - query one of the tracing filters
6019 *      @adap: the adapter
6020 *      @tp: the current trace filter parameters
6021 *      @idx: which trace filter to query
6022 *      @enabled: non-zero if the filter is enabled
6023 *
6024 *      Returns the current settings of one of the HW tracing filters.
6025 */
6026void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6027                         int *enabled)
6028{
6029        u32 ctla, ctlb;
6030        int i, ofst = idx * 4;
6031        u32 data_reg, mask_reg;
6032
6033        ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
6034        ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
6035
6036        if (is_t4(adap->params.chip)) {
6037                *enabled = !!(ctla & TFEN_F);
6038                tp->port =  TFPORT_G(ctla);
6039                tp->invert = !!(ctla & TFINVERTMATCH_F);
6040        } else {
6041                *enabled = !!(ctla & T5_TFEN_F);
6042                tp->port = T5_TFPORT_G(ctla);
6043                tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
6044        }
6045        tp->snap_len = TFCAPTUREMAX_G(ctlb);
6046        tp->min_len = TFMINPKTSIZE_G(ctlb);
6047        tp->skip_ofst = TFOFFSET_G(ctla);
6048        tp->skip_len = TFLENGTH_G(ctla);
6049
6050        ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
6051        data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
6052        mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
6053
6054        for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6055                tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6056                tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6057        }
6058}
6059
6060/**
6061 *      t4_pmtx_get_stats - returns the HW stats from PMTX
6062 *      @adap: the adapter
6063 *      @cnt: where to store the count statistics
6064 *      @cycles: where to store the cycle statistics
6065 *
6066 *      Returns performance statistics from PMTX.
6067 */
6068void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6069{
6070        int i;
6071        u32 data[2];
6072
6073        for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6074                t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
6075                cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
6076                if (is_t4(adap->params.chip)) {
6077                        cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
6078                } else {
6079                        t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
6080                                         PM_TX_DBG_DATA_A, data, 2,
6081                                         PM_TX_DBG_STAT_MSB_A);
6082                        cycles[i] = (((u64)data[0] << 32) | data[1]);
6083                }
6084        }
6085}
6086
6087/**
6088 *      t4_pmrx_get_stats - returns the HW stats from PMRX
6089 *      @adap: the adapter
6090 *      @cnt: where to store the count statistics
6091 *      @cycles: where to store the cycle statistics
6092 *
6093 *      Returns performance statistics from PMRX.
6094 */
6095void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6096{
6097        int i;
6098        u32 data[2];
6099
6100        for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6101                t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
6102                cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
6103                if (is_t4(adap->params.chip)) {
6104                        cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
6105                } else {
6106                        t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
6107                                         PM_RX_DBG_DATA_A, data, 2,
6108                                         PM_RX_DBG_STAT_MSB_A);
6109                        cycles[i] = (((u64)data[0] << 32) | data[1]);
6110                }
6111        }
6112}
6113
6114/**
6115 *      compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6116 *      @adapter: the adapter
6117 *      @pidx: the port index
6118 *
6119 *      Computes and returns a bitmap indicating which MPS buffer groups are
6120 *      associated with the given Port.  Bit i is set if buffer group i is
6121 *      used by the Port.
6122 */
6123static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
6124                                              int pidx)
6125{
6126        unsigned int chip_version, nports;
6127
6128        chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6129        nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6130
6131        switch (chip_version) {
6132        case CHELSIO_T4:
6133        case CHELSIO_T5:
6134                switch (nports) {
6135                case 1: return 0xf;
6136                case 2: return 3 << (2 * pidx);
6137                case 4: return 1 << pidx;
6138                }
6139                break;
6140
6141        case CHELSIO_T6:
6142                switch (nports) {
6143                case 2: return 1 << (2 * pidx);
6144                }
6145                break;
6146        }
6147
6148        dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6149                chip_version, nports);
6150
6151        return 0;
6152}
6153
6154/**
6155 *      t4_get_mps_bg_map - return the buffer groups associated with a port
6156 *      @adapter: the adapter
6157 *      @pidx: the port index
6158 *
6159 *      Returns a bitmap indicating which MPS buffer groups are associated
6160 *      with the given Port.  Bit i is set if buffer group i is used by the
6161 *      Port.
6162 */
6163unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
6164{
6165        u8 *mps_bg_map;
6166        unsigned int nports;
6167
6168        nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6169        if (pidx >= nports) {
6170                CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
6171                        pidx, nports);
6172                return 0;
6173        }
6174
6175        /* If we've already retrieved/computed this, just return the result.
6176         */
6177        mps_bg_map = adapter->params.mps_bg_map;
6178        if (mps_bg_map[pidx])
6179                return mps_bg_map[pidx];
6180
6181        /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6182         * If we're talking to such Firmware, let it tell us.  If the new
6183         * API isn't supported, revert back to old hardcoded way.  The value
6184         * obtained from Firmware is encoded in below format:
6185         *
6186         * val = (( MPSBGMAP[Port 3] << 24 ) |
6187         *        ( MPSBGMAP[Port 2] << 16 ) |
6188         *        ( MPSBGMAP[Port 1] <<  8 ) |
6189         *        ( MPSBGMAP[Port 0] <<  0 ))
6190         */
6191        if (adapter->flags & CXGB4_FW_OK) {
6192                u32 param, val;
6193                int ret;
6194
6195                param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6196                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
6197                ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6198                                         0, 1, &param, &val);
6199                if (!ret) {
6200                        int p;
6201
6202                        /* Store the BG Map for all of the Ports in order to
6203                         * avoid more calls to the Firmware in the future.
6204                         */
6205                        for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
6206                                mps_bg_map[p] = val & 0xff;
6207
6208                        return mps_bg_map[pidx];
6209                }
6210        }
6211
6212        /* Either we're not talking to the Firmware or we're dealing with
6213         * older Firmware which doesn't support the new API to get the MPS
6214         * Buffer Group Map.  Fall back to computing it ourselves.
6215         */
6216        mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
6217        return mps_bg_map[pidx];
6218}
6219
6220/**
6221 *      t4_get_tp_e2c_map - return the E2C channel map associated with a port
6222 *      @adapter: the adapter
6223 *      @pidx: the port index
6224 */
6225static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
6226{
6227        unsigned int nports;
6228        u32 param, val = 0;
6229        int ret;
6230
6231        nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6232        if (pidx >= nports) {
6233                CH_WARN(adapter, "TP E2C Channel Port Index %d >= Nports %d\n",
6234                        pidx, nports);
6235                return 0;
6236        }
6237
6238        /* FW version >= 1.16.44.0 can determine E2C channel map using
6239         * FW_PARAMS_PARAM_DEV_TPCHMAP API.
6240         */
6241        param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6242                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP));
6243        ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6244                                 0, 1, &param, &val);
6245        if (!ret)
6246                return (val >> (8 * pidx)) & 0xff;
6247
6248        return 0;
6249}
6250
6251/**
6252 *      t4_get_tp_ch_map - return TP ingress channels associated with a port
6253 *      @adap: the adapter
6254 *      @pidx: the port index
6255 *
6256 *      Returns a bitmap indicating which TP Ingress Channels are associated
6257 *      with a given Port.  Bit i is set if TP Ingress Channel i is used by
6258 *      the Port.
6259 */
6260unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6261{
6262        unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6263        unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6264
6265        if (pidx >= nports) {
6266                dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6267                         pidx, nports);
6268                return 0;
6269        }
6270
6271        switch (chip_version) {
6272        case CHELSIO_T4:
6273        case CHELSIO_T5:
6274                /* Note that this happens to be the same values as the MPS
6275                 * Buffer Group Map for these Chips.  But we replicate the code
6276                 * here because they're really separate concepts.
6277                 */
6278                switch (nports) {
6279                case 1: return 0xf;
6280                case 2: return 3 << (2 * pidx);
6281                case 4: return 1 << pidx;
6282                }
6283                break;
6284
6285        case CHELSIO_T6:
6286                switch (nports) {
6287                case 1:
6288                case 2: return 1 << pidx;
6289                }
6290                break;
6291        }
6292
6293        dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6294                chip_version, nports);
6295        return 0;
6296}
6297
6298/**
6299 *      t4_get_port_type_description - return Port Type string description
6300 *      @port_type: firmware Port Type enumeration
6301 */
6302const char *t4_get_port_type_description(enum fw_port_type port_type)
6303{
6304        static const char *const port_type_description[] = {
6305                "Fiber_XFI",
6306                "Fiber_XAUI",
6307                "BT_SGMII",
6308                "BT_XFI",
6309                "BT_XAUI",
6310                "KX4",
6311                "CX4",
6312                "KX",
6313                "KR",
6314                "SFP",
6315                "BP_AP",
6316                "BP4_AP",
6317                "QSFP_10G",
6318                "QSA",
6319                "QSFP",
6320                "BP40_BA",
6321                "KR4_100G",
6322                "CR4_QSFP",
6323                "CR_QSFP",
6324                "CR2_QSFP",
6325                "SFP28",
6326                "KR_SFP28",
6327                "KR_XLAUI"
6328        };
6329
6330        if (port_type < ARRAY_SIZE(port_type_description))
6331                return port_type_description[port_type];
6332        return "UNKNOWN";
6333}
6334
6335/**
6336 *      t4_get_port_stats_offset - collect port stats relative to a previous
6337 *                                 snapshot
6338 *      @adap: The adapter
6339 *      @idx: The port
6340 *      @stats: Current stats to fill
6341 *      @offset: Previous stats snapshot
6342 */
6343void t4_get_port_stats_offset(struct adapter *adap, int idx,
6344                              struct port_stats *stats,
6345                              struct port_stats *offset)
6346{
6347        u64 *s, *o;
6348        int i;
6349
6350        t4_get_port_stats(adap, idx, stats);
6351        for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6352                        i < (sizeof(struct port_stats) / sizeof(u64));
6353                        i++, s++, o++)
6354                *s -= *o;
6355}
6356
6357/**
6358 *      t4_get_port_stats - collect port statistics
6359 *      @adap: the adapter
6360 *      @idx: the port index
6361 *      @p: the stats structure to fill
6362 *
6363 *      Collect statistics related to the given port from HW.
6364 */
6365void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6366{
6367        u32 bgmap = t4_get_mps_bg_map(adap, idx);
6368        u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6369
6370#define GET_STAT(name) \
6371        t4_read_reg64(adap, \
6372        (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6373        T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6374#define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6375
6376        p->tx_octets           = GET_STAT(TX_PORT_BYTES);
6377        p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
6378        p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
6379        p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
6380        p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
6381        p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
6382        p->tx_frames_64        = GET_STAT(TX_PORT_64B);
6383        p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
6384        p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
6385        p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
6386        p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
6387        p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6388        p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
6389        p->tx_drop             = GET_STAT(TX_PORT_DROP);
6390        p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
6391        p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
6392        p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
6393        p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
6394        p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
6395        p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
6396        p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
6397        p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
6398        p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
6399
6400        if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6401                if (stat_ctl & COUNTPAUSESTATTX_F)
6402                        p->tx_frames_64 -= p->tx_pause;
6403                if (stat_ctl & COUNTPAUSEMCTX_F)
6404                        p->tx_mcast_frames -= p->tx_pause;
6405        }
6406        p->rx_octets           = GET_STAT(RX_PORT_BYTES);
6407        p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
6408        p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
6409        p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
6410        p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
6411        p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
6412        p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6413        p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
6414        p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
6415        p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
6416        p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
6417        p->rx_frames_64        = GET_STAT(RX_PORT_64B);
6418        p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
6419        p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
6420        p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
6421        p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
6422        p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6423        p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
6424        p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
6425        p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
6426        p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
6427        p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
6428        p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
6429        p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
6430        p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
6431        p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
6432        p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
6433
6434        if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6435                if (stat_ctl & COUNTPAUSESTATRX_F)
6436                        p->rx_frames_64 -= p->rx_pause;
6437                if (stat_ctl & COUNTPAUSEMCRX_F)
6438                        p->rx_mcast_frames -= p->rx_pause;
6439        }
6440
6441        p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6442        p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6443        p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6444        p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6445        p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6446        p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6447        p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6448        p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6449
6450#undef GET_STAT
6451#undef GET_STAT_COM
6452}
6453
6454/**
6455 *      t4_get_lb_stats - collect loopback port statistics
6456 *      @adap: the adapter
6457 *      @idx: the loopback port index
6458 *      @p: the stats structure to fill
6459 *
6460 *      Return HW statistics for the given loopback port.
6461 */
6462void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6463{
6464        u32 bgmap = t4_get_mps_bg_map(adap, idx);
6465
6466#define GET_STAT(name) \
6467        t4_read_reg64(adap, \
6468        (is_t4(adap->params.chip) ? \
6469        PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6470        T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6471#define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6472
6473        p->octets           = GET_STAT(BYTES);
6474        p->frames           = GET_STAT(FRAMES);
6475        p->bcast_frames     = GET_STAT(BCAST);
6476        p->mcast_frames     = GET_STAT(MCAST);
6477        p->ucast_frames     = GET_STAT(UCAST);
6478        p->error_frames     = GET_STAT(ERROR);
6479
6480        p->frames_64        = GET_STAT(64B);
6481        p->frames_65_127    = GET_STAT(65B_127B);
6482        p->frames_128_255   = GET_STAT(128B_255B);
6483        p->frames_256_511   = GET_STAT(256B_511B);
6484        p->frames_512_1023  = GET_STAT(512B_1023B);
6485        p->frames_1024_1518 = GET_STAT(1024B_1518B);
6486        p->frames_1519_max  = GET_STAT(1519B_MAX);
6487        p->drop             = GET_STAT(DROP_FRAMES);
6488
6489        p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6490        p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6491        p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6492        p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6493        p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6494        p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6495        p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6496        p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6497
6498#undef GET_STAT
6499#undef GET_STAT_COM
6500}
6501
6502/*     t4_mk_filtdelwr - create a delete filter WR
6503 *     @ftid: the filter ID
6504 *     @wr: the filter work request to populate
6505 *     @qid: ingress queue to receive the delete notification
6506 *
6507 *     Creates a filter work request to delete the supplied filter.  If @qid is
6508 *     negative the delete notification is suppressed.
6509 */
6510void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6511{
6512        memset(wr, 0, sizeof(*wr));
6513        wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6514        wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6515        wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6516                                    FW_FILTER_WR_NOREPLY_V(qid < 0));
6517        wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6518        if (qid >= 0)
6519                wr->rx_chan_rx_rpl_iq =
6520                        cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6521}
6522
6523#define INIT_CMD(var, cmd, rd_wr) do { \
6524        (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6525                                        FW_CMD_REQUEST_F | \
6526                                        FW_CMD_##rd_wr##_F); \
6527        (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6528} while (0)
6529
6530int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6531                          u32 addr, u32 val)
6532{
6533        u32 ldst_addrspace;
6534        struct fw_ldst_cmd c;
6535
6536        memset(&c, 0, sizeof(c));
6537        ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6538        c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6539                                        FW_CMD_REQUEST_F |
6540                                        FW_CMD_WRITE_F |
6541                                        ldst_addrspace);
6542        c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6543        c.u.addrval.addr = cpu_to_be32(addr);
6544        c.u.addrval.val = cpu_to_be32(val);
6545
6546        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6547}
6548
6549/**
6550 *      t4_mdio_rd - read a PHY register through MDIO
6551 *      @adap: the adapter
6552 *      @mbox: mailbox to use for the FW command
6553 *      @phy_addr: the PHY address
6554 *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6555 *      @reg: the register to read
6556 *      @valp: where to store the value
6557 *
6558 *      Issues a FW command through the given mailbox to read a PHY register.
6559 */
6560int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6561               unsigned int mmd, unsigned int reg, u16 *valp)
6562{
6563        int ret;
6564        u32 ldst_addrspace;
6565        struct fw_ldst_cmd c;
6566
6567        memset(&c, 0, sizeof(c));
6568        ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6569        c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6570                                        FW_CMD_REQUEST_F | FW_CMD_READ_F |
6571                                        ldst_addrspace);
6572        c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6573        c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6574                                         FW_LDST_CMD_MMD_V(mmd));
6575        c.u.mdio.raddr = cpu_to_be16(reg);
6576
6577        ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6578        if (ret == 0)
6579                *valp = be16_to_cpu(c.u.mdio.rval);
6580        return ret;
6581}
6582
6583/**
6584 *      t4_mdio_wr - write a PHY register through MDIO
6585 *      @adap: the adapter
6586 *      @mbox: mailbox to use for the FW command
6587 *      @phy_addr: the PHY address
6588 *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6589 *      @reg: the register to write
6590 *      @val: value to write
6591 *
6592 *      Issues a FW command through the given mailbox to write a PHY register.
6593 */
6594int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6595               unsigned int mmd, unsigned int reg, u16 val)
6596{
6597        u32 ldst_addrspace;
6598        struct fw_ldst_cmd c;
6599
6600        memset(&c, 0, sizeof(c));
6601        ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6602        c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6603                                        FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6604                                        ldst_addrspace);
6605        c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6606        c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6607                                         FW_LDST_CMD_MMD_V(mmd));
6608        c.u.mdio.raddr = cpu_to_be16(reg);
6609        c.u.mdio.rval = cpu_to_be16(val);
6610
6611        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6612}
6613
6614/**
6615 *      t4_sge_decode_idma_state - decode the idma state
6616 *      @adapter: the adapter
6617 *      @state: the state idma is stuck in
6618 */
6619void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6620{
6621        static const char * const t4_decode[] = {
6622                "IDMA_IDLE",
6623                "IDMA_PUSH_MORE_CPL_FIFO",
6624                "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6625                "Not used",
6626                "IDMA_PHYSADDR_SEND_PCIEHDR",
6627                "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6628                "IDMA_PHYSADDR_SEND_PAYLOAD",
6629                "IDMA_SEND_FIFO_TO_IMSG",
6630                "IDMA_FL_REQ_DATA_FL_PREP",
6631                "IDMA_FL_REQ_DATA_FL",
6632                "IDMA_FL_DROP",
6633                "IDMA_FL_H_REQ_HEADER_FL",
6634                "IDMA_FL_H_SEND_PCIEHDR",
6635                "IDMA_FL_H_PUSH_CPL_FIFO",
6636                "IDMA_FL_H_SEND_CPL",
6637                "IDMA_FL_H_SEND_IP_HDR_FIRST",
6638                "IDMA_FL_H_SEND_IP_HDR",
6639                "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6640                "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6641                "IDMA_FL_H_SEND_IP_HDR_PADDING",
6642                "IDMA_FL_D_SEND_PCIEHDR",
6643                "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6644                "IDMA_FL_D_REQ_NEXT_DATA_FL",
6645                "IDMA_FL_SEND_PCIEHDR",
6646                "IDMA_FL_PUSH_CPL_FIFO",
6647                "IDMA_FL_SEND_CPL",
6648                "IDMA_FL_SEND_PAYLOAD_FIRST",
6649                "IDMA_FL_SEND_PAYLOAD",
6650                "IDMA_FL_REQ_NEXT_DATA_FL",
6651                "IDMA_FL_SEND_NEXT_PCIEHDR",
6652                "IDMA_FL_SEND_PADDING",
6653                "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6654                "IDMA_FL_SEND_FIFO_TO_IMSG",
6655                "IDMA_FL_REQ_DATAFL_DONE",
6656                "IDMA_FL_REQ_HEADERFL_DONE",
6657        };
6658        static const char * const t5_decode[] = {
6659                "IDMA_IDLE",
6660                "IDMA_ALMOST_IDLE",
6661                "IDMA_PUSH_MORE_CPL_FIFO",
6662                "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6663                "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6664                "IDMA_PHYSADDR_SEND_PCIEHDR",
6665                "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6666                "IDMA_PHYSADDR_SEND_PAYLOAD",
6667                "IDMA_SEND_FIFO_TO_IMSG",
6668                "IDMA_FL_REQ_DATA_FL",
6669                "IDMA_FL_DROP",
6670                "IDMA_FL_DROP_SEND_INC",
6671                "IDMA_FL_H_REQ_HEADER_FL",
6672                "IDMA_FL_H_SEND_PCIEHDR",
6673                "IDMA_FL_H_PUSH_CPL_FIFO",
6674                "IDMA_FL_H_SEND_CPL",
6675                "IDMA_FL_H_SEND_IP_HDR_FIRST",
6676                "IDMA_FL_H_SEND_IP_HDR",
6677                "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6678                "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6679                "IDMA_FL_H_SEND_IP_HDR_PADDING",
6680                "IDMA_FL_D_SEND_PCIEHDR",
6681                "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6682                "IDMA_FL_D_REQ_NEXT_DATA_FL",
6683                "IDMA_FL_SEND_PCIEHDR",
6684                "IDMA_FL_PUSH_CPL_FIFO",
6685                "IDMA_FL_SEND_CPL",
6686                "IDMA_FL_SEND_PAYLOAD_FIRST",
6687                "IDMA_FL_SEND_PAYLOAD",
6688                "IDMA_FL_REQ_NEXT_DATA_FL",
6689                "IDMA_FL_SEND_NEXT_PCIEHDR",
6690                "IDMA_FL_SEND_PADDING",
6691                "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6692        };
6693        static const char * const t6_decode[] = {
6694                "IDMA_IDLE",
6695                "IDMA_PUSH_MORE_CPL_FIFO",
6696                "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6697                "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6698                "IDMA_PHYSADDR_SEND_PCIEHDR",
6699                "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6700                "IDMA_PHYSADDR_SEND_PAYLOAD",
6701                "IDMA_FL_REQ_DATA_FL",
6702                "IDMA_FL_DROP",
6703                "IDMA_FL_DROP_SEND_INC",
6704                "IDMA_FL_H_REQ_HEADER_FL",
6705                "IDMA_FL_H_SEND_PCIEHDR",
6706                "IDMA_FL_H_PUSH_CPL_FIFO",
6707                "IDMA_FL_H_SEND_CPL",
6708                "IDMA_FL_H_SEND_IP_HDR_FIRST",
6709                "IDMA_FL_H_SEND_IP_HDR",
6710                "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6711                "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6712                "IDMA_FL_H_SEND_IP_HDR_PADDING",
6713                "IDMA_FL_D_SEND_PCIEHDR",
6714                "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6715                "IDMA_FL_D_REQ_NEXT_DATA_FL",
6716                "IDMA_FL_SEND_PCIEHDR",
6717                "IDMA_FL_PUSH_CPL_FIFO",
6718                "IDMA_FL_SEND_CPL",
6719                "IDMA_FL_SEND_PAYLOAD_FIRST",
6720                "IDMA_FL_SEND_PAYLOAD",
6721                "IDMA_FL_REQ_NEXT_DATA_FL",
6722                "IDMA_FL_SEND_NEXT_PCIEHDR",
6723                "IDMA_FL_SEND_PADDING",
6724                "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6725        };
6726        static const u32 sge_regs[] = {
6727                SGE_DEBUG_DATA_LOW_INDEX_2_A,
6728                SGE_DEBUG_DATA_LOW_INDEX_3_A,
6729                SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6730        };
6731        const char **sge_idma_decode;
6732        int sge_idma_decode_nstates;
6733        int i;
6734        unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6735
6736        /* Select the right set of decode strings to dump depending on the
6737         * adapter chip type.
6738         */
6739        switch (chip_version) {
6740        case CHELSIO_T4:
6741                sge_idma_decode = (const char **)t4_decode;
6742                sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6743                break;
6744
6745        case CHELSIO_T5:
6746                sge_idma_decode = (const char **)t5_decode;
6747                sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6748                break;
6749
6750        case CHELSIO_T6:
6751                sge_idma_decode = (const char **)t6_decode;
6752                sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6753                break;
6754
6755        default:
6756                dev_err(adapter->pdev_dev,
6757                        "Unsupported chip version %d\n", chip_version);
6758                return;
6759        }
6760
6761        if (is_t4(adapter->params.chip)) {
6762                sge_idma_decode = (const char **)t4_decode;
6763                sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6764        } else {
6765                sge_idma_decode = (const char **)t5_decode;
6766                sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6767        }
6768
6769        if (state < sge_idma_decode_nstates)
6770                CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6771        else
6772                CH_WARN(adapter, "idma state %d unknown\n", state);
6773
6774        for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6775                CH_WARN(adapter, "SGE register %#x value %#x\n",
6776                        sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6777}
6778
6779/**
6780 *      t4_sge_ctxt_flush - flush the SGE context cache
6781 *      @adap: the adapter
6782 *      @mbox: mailbox to use for the FW command
6783 *      @ctxt_type: Egress or Ingress
6784 *
6785 *      Issues a FW command through the given mailbox to flush the
6786 *      SGE context cache.
6787 */
6788int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6789{
6790        int ret;
6791        u32 ldst_addrspace;
6792        struct fw_ldst_cmd c;
6793
6794        memset(&c, 0, sizeof(c));
6795        ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(ctxt_type == CTXT_EGRESS ?
6796                                                 FW_LDST_ADDRSPC_SGE_EGRC :
6797                                                 FW_LDST_ADDRSPC_SGE_INGC);
6798        c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6799                                        FW_CMD_REQUEST_F | FW_CMD_READ_F |
6800                                        ldst_addrspace);
6801        c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6802        c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6803
6804        ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6805        return ret;
6806}
6807
6808/**
6809 *      t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6810 *      @adap: the adapter
6811 *      @ndbqtimers: size of the provided SGE Doorbell Queue Timer table
6812 *      @dbqtimers: SGE Doorbell Queue Timer table
6813 *
6814 *      Reads the SGE Doorbell Queue Timer values into the provided table.
6815 *      Returns 0 on success (Firmware and Hardware support this feature),
6816 *      an error on failure.
6817 */
6818int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
6819                          u16 *dbqtimers)
6820{
6821        int ret, dbqtimerix;
6822
6823        ret = 0;
6824        dbqtimerix = 0;
6825        while (dbqtimerix < ndbqtimers) {
6826                int nparams, param;
6827                u32 params[7], vals[7];
6828
6829                nparams = ndbqtimers - dbqtimerix;
6830                if (nparams > ARRAY_SIZE(params))
6831                        nparams = ARRAY_SIZE(params);
6832
6833                for (param = 0; param < nparams; param++)
6834                        params[param] =
6835                          (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6836                           FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMER) |
6837                           FW_PARAMS_PARAM_Y_V(dbqtimerix + param));
6838                ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
6839                                      nparams, params, vals);
6840                if (ret)
6841                        break;
6842
6843                for (param = 0; param < nparams; param++)
6844                        dbqtimers[dbqtimerix++] = vals[param];
6845        }
6846        return ret;
6847}
6848
6849/**
6850 *      t4_fw_hello - establish communication with FW
6851 *      @adap: the adapter
6852 *      @mbox: mailbox to use for the FW command
6853 *      @evt_mbox: mailbox to receive async FW events
6854 *      @master: specifies the caller's willingness to be the device master
6855 *      @state: returns the current device state (if non-NULL)
6856 *
6857 *      Issues a command to establish communication with FW.  Returns either
6858 *      an error (negative integer) or the mailbox of the Master PF.
6859 */
6860int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6861                enum dev_master master, enum dev_state *state)
6862{
6863        int ret;
6864        struct fw_hello_cmd c;
6865        u32 v;
6866        unsigned int master_mbox;
6867        int retries = FW_CMD_HELLO_RETRIES;
6868
6869retry:
6870        memset(&c, 0, sizeof(c));
6871        INIT_CMD(c, HELLO, WRITE);
6872        c.err_to_clearinit = cpu_to_be32(
6873                FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6874                FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6875                FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6876                                        mbox : FW_HELLO_CMD_MBMASTER_M) |
6877                FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6878                FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6879                FW_HELLO_CMD_CLEARINIT_F);
6880
6881        /*
6882         * Issue the HELLO command to the firmware.  If it's not successful
6883         * but indicates that we got a "busy" or "timeout" condition, retry
6884         * the HELLO until we exhaust our retry limit.  If we do exceed our
6885         * retry limit, check to see if the firmware left us any error
6886         * information and report that if so.
6887         */
6888        ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6889        if (ret < 0) {
6890                if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6891                        goto retry;
6892                if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6893                        t4_report_fw_error(adap);
6894                return ret;
6895        }
6896
6897        v = be32_to_cpu(c.err_to_clearinit);
6898        master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6899        if (state) {
6900                if (v & FW_HELLO_CMD_ERR_F)
6901                        *state = DEV_STATE_ERR;
6902                else if (v & FW_HELLO_CMD_INIT_F)
6903                        *state = DEV_STATE_INIT;
6904                else
6905                        *state = DEV_STATE_UNINIT;
6906        }
6907
6908        /*
6909         * If we're not the Master PF then we need to wait around for the
6910         * Master PF Driver to finish setting up the adapter.
6911         *
6912         * Note that we also do this wait if we're a non-Master-capable PF and
6913         * there is no current Master PF; a Master PF may show up momentarily
6914         * and we wouldn't want to fail pointlessly.  (This can happen when an
6915         * OS loads lots of different drivers rapidly at the same time).  In
6916         * this case, the Master PF returned by the firmware will be
6917         * PCIE_FW_MASTER_M so the test below will work ...
6918         */
6919        if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6920            master_mbox != mbox) {
6921                int waiting = FW_CMD_HELLO_TIMEOUT;
6922
6923                /*
6924                 * Wait for the firmware to either indicate an error or
6925                 * initialized state.  If we see either of these we bail out
6926                 * and report the issue to the caller.  If we exhaust the
6927                 * "hello timeout" and we haven't exhausted our retries, try
6928                 * again.  Otherwise bail with a timeout error.
6929                 */
6930                for (;;) {
6931                        u32 pcie_fw;
6932
6933                        msleep(50);
6934                        waiting -= 50;
6935
6936                        /*
6937                         * If neither Error nor Initialized are indicated
6938                         * by the firmware keep waiting till we exhaust our
6939                         * timeout ... and then retry if we haven't exhausted
6940                         * our retries ...
6941                         */
6942                        pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6943                        if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6944                                if (waiting <= 0) {
6945                                        if (retries-- > 0)
6946                                                goto retry;
6947
6948                                        return -ETIMEDOUT;
6949                                }
6950                                continue;
6951                        }
6952
6953                        /*
6954                         * We either have an Error or Initialized condition
6955                         * report errors preferentially.
6956                         */
6957                        if (state) {
6958                                if (pcie_fw & PCIE_FW_ERR_F)
6959                                        *state = DEV_STATE_ERR;
6960                                else if (pcie_fw & PCIE_FW_INIT_F)
6961                                        *state = DEV_STATE_INIT;
6962                        }
6963
6964                        /*
6965                         * If we arrived before a Master PF was selected and
6966                         * there's not a valid Master PF, grab its identity
6967                         * for our caller.
6968                         */
6969                        if (master_mbox == PCIE_FW_MASTER_M &&
6970                            (pcie_fw & PCIE_FW_MASTER_VLD_F))
6971                                master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6972                        break;
6973                }
6974        }
6975
6976        return master_mbox;
6977}
6978
6979/**
6980 *      t4_fw_bye - end communication with FW
6981 *      @adap: the adapter
6982 *      @mbox: mailbox to use for the FW command
6983 *
6984 *      Issues a command to terminate communication with FW.
6985 */
6986int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6987{
6988        struct fw_bye_cmd c;
6989
6990        memset(&c, 0, sizeof(c));
6991        INIT_CMD(c, BYE, WRITE);
6992        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6993}
6994
6995/**
6996 *      t4_early_init - ask FW to initialize the device
6997 *      @adap: the adapter
6998 *      @mbox: mailbox to use for the FW command
6999 *
7000 *      Issues a command to FW to partially initialize the device.  This

7001 *      performs initialization that generally doesn't depend on user input.
7002 */
7003int t4_early_init(struct adapter *adap, unsigned int mbox)
7004{
7005        struct fw_initialize_cmd c;
7006
7007        memset(&c, 0, sizeof(c));
7008        INIT_CMD(c, INITIALIZE, WRITE);
7009        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7010}
7011
7012/**
7013 *      t4_fw_reset - issue a reset to FW
7014 *      @adap: the adapter
7015 *      @mbox: mailbox to use for the FW command
7016 *      @reset: specifies the type of reset to perform
7017 *
7018 *      Issues a reset command of the specified type to FW.
7019 */
7020int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7021{
7022        struct fw_reset_cmd c;
7023
7024        memset(&c, 0, sizeof(c));
7025        INIT_CMD(c, RESET, WRITE);
7026        c.val = cpu_to_be32(reset);
7027        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7028}
7029
7030/**
7031 *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7032 *      @adap: the adapter
7033 *      @mbox: mailbox to use for the FW RESET command (if desired)
7034 *      @force: force uP into RESET even if FW RESET command fails
7035 *
7036 *      Issues a RESET command to firmware (if desired) with a HALT indication
7037 *      and then puts the microprocessor into RESET state.  The RESET command
7038 *      will only be issued if a legitimate mailbox is provided (mbox <=
7039 *      PCIE_FW_MASTER_M).
7040 *
7041 *      This is generally used in order for the host to safely manipulate the
7042 *      adapter without fear of conflicting with whatever the firmware might
7043 *      be doing.  The only way out of this state is to RESTART the firmware
7044 *      ...
7045 */
7046static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7047{
7048        int ret = 0;
7049
7050        /*
7051         * If a legitimate mailbox is provided, issue a RESET command
7052         * with a HALT indication.
7053         */
7054        if (mbox <= PCIE_FW_MASTER_M) {
7055                struct fw_reset_cmd c;
7056
7057                memset(&c, 0, sizeof(c));
7058                INIT_CMD(c, RESET, WRITE);
7059                c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
7060                c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
7061                ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7062        }
7063
7064        /*
7065         * Normally we won't complete the operation if the firmware RESET
7066         * command fails but if our caller insists we'll go ahead and put the
7067         * uP into RESET.  This can be useful if the firmware is hung or even
7068         * missing ...  We'll have to take the risk of putting the uP into
7069         * RESET without the cooperation of firmware in that case.
7070         *
7071         * We also force the firmware's HALT flag to be on in case we bypassed
7072         * the firmware RESET command above or we're dealing with old firmware
7073         * which doesn't have the HALT capability.  This will serve as a flag
7074         * for the incoming firmware to know that it's coming out of a HALT
7075         * rather than a RESET ... if it's new enough to understand that ...
7076         */
7077        if (ret == 0 || force) {
7078                t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
7079                t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
7080                                 PCIE_FW_HALT_F);
7081        }
7082
7083        /*
7084         * And we always return the result of the firmware RESET command
7085         * even when we force the uP into RESET ...
7086         */
7087        return ret;
7088}
7089
7090/**
7091 *      t4_fw_restart - restart the firmware by taking the uP out of RESET
7092 *      @adap: the adapter
7093 *      @mbox: mailbox to use for the FW command
7094 *      @reset: if we want to do a RESET to restart things
7095 *
7096 *      Restart firmware previously halted by t4_fw_halt().  On successful
7097 *      return the previous PF Master remains as the new PF Master and there
7098 *      is no need to issue a new HELLO command, etc.
7099 *
7100 *      We do this in two ways:
7101 *
7102 *       1. If we're dealing with newer firmware we'll simply want to take
7103 *          the chip's microprocessor out of RESET.  This will cause the
7104 *          firmware to start up from its start vector.  And then we'll loop
7105 *          until the firmware indicates it's started again (PCIE_FW.HALT
7106 *          reset to 0) or we timeout.
7107 *
7108 *       2. If we're dealing with older firmware then we'll need to RESET
7109 *          the chip since older firmware won't recognize the PCIE_FW.HALT
7110 *          flag and automatically RESET itself on startup.
7111 */
7112static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
7113{
7114        if (reset) {
7115                /*
7116                 * Since we're directing the RESET instead of the firmware
7117                 * doing it automatically, we need to clear the PCIE_FW.HALT
7118                 * bit.
7119                 */
7120                t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
7121
7122                /*
7123                 * If we've been given a valid mailbox, first try to get the
7124                 * firmware to do the RESET.  If that works, great and we can
7125                 * return success.  Otherwise, if we haven't been given a
7126                 * valid mailbox or the RESET command failed, fall back to
7127                 * hitting the chip with a hammer.
7128                 */
7129                if (mbox <= PCIE_FW_MASTER_M) {
7130                        t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7131                        msleep(100);
7132                        if (t4_fw_reset(adap, mbox,
7133                                        PIORST_F | PIORSTMODE_F) == 0)
7134                                return 0;
7135                }
7136
7137                t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
7138                msleep(2000);
7139        } else {
7140                int ms;
7141
7142                t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7143                for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7144                        if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
7145                                return 0;
7146                        msleep(100);
7147                        ms += 100;
7148                }
7149                return -ETIMEDOUT;
7150        }
7151        return 0;
7152}
7153
7154/**
7155 *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7156 *      @adap: the adapter
7157 *      @mbox: mailbox to use for the FW RESET command (if desired)
7158 *      @fw_data: the firmware image to write
7159 *      @size: image size
7160 *      @force: force upgrade even if firmware doesn't cooperate
7161 *
7162 *      Perform all of the steps necessary for upgrading an adapter's
7163 *      firmware image.  Normally this requires the cooperation of the
7164 *      existing firmware in order to halt all existing activities
7165 *      but if an invalid mailbox token is passed in we skip that step
7166 *      (though we'll still put the adapter microprocessor into RESET in
7167 *      that case).
7168 *
7169 *      On successful return the new firmware will have been loaded and
7170 *      the adapter will have been fully RESET losing all previous setup
7171 *      state.  On unsuccessful return the adapter may be completely hosed ...
7172 *      positive errno indicates that the adapter is ~probably~ intact, a
7173 *      negative errno indicates that things are looking bad ...
7174 */
7175int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7176                  const u8 *fw_data, unsigned int size, int force)
7177{
7178        const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7179        int reset, ret;
7180
7181        if (!t4_fw_matches_chip(adap, fw_hdr))
7182                return -EINVAL;
7183
7184        /* Disable CXGB4_FW_OK flag so that mbox commands with CXGB4_FW_OK flag
7185         * set wont be sent when we are flashing FW.
7186         */
7187        adap->flags &= ~CXGB4_FW_OK;
7188
7189        ret = t4_fw_halt(adap, mbox, force);
7190        if (ret < 0 && !force)
7191                goto out;
7192
7193        ret = t4_load_fw(adap, fw_data, size);
7194        if (ret < 0)
7195                goto out;
7196
7197        /*
7198         * If there was a Firmware Configuration File stored in FLASH,
7199         * there's a good chance that it won't be compatible with the new
7200         * Firmware.  In order to prevent difficult to diagnose adapter
7201         * initialization issues, we clear out the Firmware Configuration File
7202         * portion of the FLASH .  The user will need to re-FLASH a new
7203         * Firmware Configuration File which is compatible with the new
7204         * Firmware if that's desired.
7205         */
7206        (void)t4_load_cfg(adap, NULL, 0);
7207
7208        /*
7209         * Older versions of the firmware don't understand the new
7210         * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7211         * restart.  So for newly loaded older firmware we'll have to do the
7212         * RESET for it so it starts up on a clean slate.  We can tell if
7213         * the newly loaded firmware will handle this right by checking
7214         * its header flags to see if it advertises the capability.
7215         */
7216        reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
7217        ret = t4_fw_restart(adap, mbox, reset);
7218
7219        /* Grab potentially new Firmware Device Log parameters so we can see
7220         * how healthy the new Firmware is.  It's okay to contact the new
7221         * Firmware for these parameters even though, as far as it's
7222         * concerned, we've never said "HELLO" to it ...
7223         */
7224        (void)t4_init_devlog_params(adap);
7225out:
7226        adap->flags |= CXGB4_FW_OK;
7227        return ret;
7228}
7229
7230/**
7231 *      t4_fl_pkt_align - return the fl packet alignment
7232 *      @adap: the adapter
7233 *
7234 *      T4 has a single field to specify the packing and padding boundary.
7235 *      T5 onwards has separate fields for this and hence the alignment for
7236 *      next packet offset is maximum of these two.
7237 *
7238 */
7239int t4_fl_pkt_align(struct adapter *adap)
7240{
7241        u32 sge_control, sge_control2;
7242        unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
7243
7244        sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7245
7246        /* T4 uses a single control field to specify both the PCIe Padding and
7247         * Packing Boundary.  T5 introduced the ability to specify these
7248         * separately.  The actual Ingress Packet Data alignment boundary
7249         * within Packed Buffer Mode is the maximum of these two
7250         * specifications.  (Note that it makes no real practical sense to
7251         * have the Padding Boundary be larger than the Packing Boundary but you
7252         * could set the chip up that way and, in fact, legacy T4 code would
7253         * end doing this because it would initialize the Padding Boundary and
7254         * leave the Packing Boundary initialized to 0 (16 bytes).)
7255         * Padding Boundary values in T6 starts from 8B,
7256         * where as it is 32B for T4 and T5.
7257         */
7258        if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
7259                ingpad_shift = INGPADBOUNDARY_SHIFT_X;
7260        else
7261                ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
7262
7263        ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
7264
7265        fl_align = ingpadboundary;
7266        if (!is_t4(adap->params.chip)) {
7267                /* T5 has a weird interpretation of one of the PCIe Packing
7268                 * Boundary values.  No idea why ...
7269                 */
7270                sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7271                ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
7272                if (ingpackboundary == INGPACKBOUNDARY_16B_X)
7273                        ingpackboundary = 16;
7274                else
7275                        ingpackboundary = 1 << (ingpackboundary +
7276                                                INGPACKBOUNDARY_SHIFT_X);
7277
7278                fl_align = max(ingpadboundary, ingpackboundary);
7279        }
7280        return fl_align;
7281}
7282
7283/**
7284 *      t4_fixup_host_params - fix up host-dependent parameters
7285 *      @adap: the adapter
7286 *      @page_size: the host's Base Page Size
7287 *      @cache_line_size: the host's Cache Line Size
7288 *
7289 *      Various registers in T4 contain values which are dependent on the
7290 *      host's Base Page and Cache Line Sizes.  This function will fix all of
7291 *      those registers with the appropriate values as passed in ...
7292 */
7293int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7294                         unsigned int cache_line_size)
7295{
7296        unsigned int page_shift = fls(page_size) - 1;
7297        unsigned int sge_hps = page_shift - 10;
7298        unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7299        unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7300        unsigned int fl_align_log = fls(fl_align) - 1;
7301
7302        t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7303                     HOSTPAGESIZEPF0_V(sge_hps) |
7304                     HOSTPAGESIZEPF1_V(sge_hps) |
7305                     HOSTPAGESIZEPF2_V(sge_hps) |
7306                     HOSTPAGESIZEPF3_V(sge_hps) |
7307                     HOSTPAGESIZEPF4_V(sge_hps) |
7308                     HOSTPAGESIZEPF5_V(sge_hps) |
7309                     HOSTPAGESIZEPF6_V(sge_hps) |
7310                     HOSTPAGESIZEPF7_V(sge_hps));
7311
7312        if (is_t4(adap->params.chip)) {
7313                t4_set_reg_field(adap, SGE_CONTROL_A,
7314                                 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7315                                 EGRSTATUSPAGESIZE_F,
7316                                 INGPADBOUNDARY_V(fl_align_log -
7317                                                  INGPADBOUNDARY_SHIFT_X) |
7318                                 EGRSTATUSPAGESIZE_V(stat_len != 64));
7319        } else {
7320                unsigned int pack_align;
7321                unsigned int ingpad, ingpack;
7322
7323                /* T5 introduced the separation of the Free List Padding and
7324                 * Packing Boundaries.  Thus, we can select a smaller Padding
7325                 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7326                 * Bandwidth, and use a Packing Boundary which is large enough
7327                 * to avoid false sharing between CPUs, etc.
7328                 *
7329                 * For the PCI Link, the smaller the Padding Boundary the
7330                 * better.  For the Memory Controller, a smaller Padding
7331                 * Boundary is better until we cross under the Memory Line
7332                 * Size (the minimum unit of transfer to/from Memory).  If we
7333                 * have a Padding Boundary which is smaller than the Memory
7334                 * Line Size, that'll involve a Read-Modify-Write cycle on the
7335                 * Memory Controller which is never good.
7336                 */
7337
7338                /* We want the Packing Boundary to be based on the Cache Line
7339                 * Size in order to help avoid False Sharing performance
7340                 * issues between CPUs, etc.  We also want the Packing
7341                 * Boundary to incorporate the PCI-E Maximum Payload Size.  We
7342                 * get best performance when the Packing Boundary is a
7343                 * multiple of the Maximum Payload Size.
7344                 */
7345                pack_align = fl_align;
7346                if (pci_is_pcie(adap->pdev)) {
7347                        unsigned int mps, mps_log;
7348                        u16 devctl;
7349
7350                        /* The PCIe Device Control Maximum Payload Size field
7351                         * [bits 7:5] encodes sizes as powers of 2 starting at
7352                         * 128 bytes.
7353                         */
7354                        pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL,
7355                                                  &devctl);
7356                        mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7357                        mps = 1 << mps_log;
7358                        if (mps > pack_align)
7359                                pack_align = mps;
7360                }
7361
7362                /* N.B. T5/T6 have a crazy special interpretation of the "0"
7363                 * value for the Packing Boundary.  This corresponds to 16
7364                 * bytes instead of the expected 32 bytes.  So if we want 32
7365                 * bytes, the best we can really do is 64 bytes ...
7366                 */
7367                if (pack_align <= 16) {
7368                        ingpack = INGPACKBOUNDARY_16B_X;
7369                        fl_align = 16;
7370                } else if (pack_align == 32) {
7371                        ingpack = INGPACKBOUNDARY_64B_X;
7372                        fl_align = 64;
7373                } else {
7374                        unsigned int pack_align_log = fls(pack_align) - 1;
7375
7376                        ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7377                        fl_align = pack_align;
7378                }
7379
7380                /* Use the smallest Ingress Padding which isn't smaller than
7381                 * the Memory Controller Read/Write Size.  We'll take that as
7382                 * being 8 bytes since we don't know of any system with a
7383                 * wider Memory Controller Bus Width.
7384                 */
7385                if (is_t5(adap->params.chip))
7386                        ingpad = INGPADBOUNDARY_32B_X;
7387                else
7388                        ingpad = T6_INGPADBOUNDARY_8B_X;
7389
7390                t4_set_reg_field(adap, SGE_CONTROL_A,
7391                                 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7392                                 EGRSTATUSPAGESIZE_F,
7393                                 INGPADBOUNDARY_V(ingpad) |
7394                                 EGRSTATUSPAGESIZE_V(stat_len != 64));
7395                t4_set_reg_field(adap, SGE_CONTROL2_A,
7396                                 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7397                                 INGPACKBOUNDARY_V(ingpack));
7398        }
7399        /*
7400         * Adjust various SGE Free List Host Buffer Sizes.
7401         *
7402         * This is something of a crock since we're using fixed indices into
7403         * the array which are also known by the sge.c code and the T4
7404         * Firmware Configuration File.  We need to come up with a much better
7405         * approach to managing this array.  For now, the first four entries
7406         * are:
7407         *
7408         *   0: Host Page Size
7409         *   1: 64KB
7410         *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7411         *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7412         *
7413         * For the single-MTU buffers in unpacked mode we need to include
7414         * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7415         * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7416         * Padding boundary.  All of these are accommodated in the Factory
7417         * Default Firmware Configuration File but we need to adjust it for
7418         * this host's cache line size.
7419         */
7420        t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7421        t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7422                     (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7423                     & ~(fl_align-1));
7424        t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7425                     (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7426                     & ~(fl_align-1));
7427
7428        t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7429
7430        return 0;
7431}
7432
7433/**
7434 *      t4_fw_initialize - ask FW to initialize the device
7435 *      @adap: the adapter
7436 *      @mbox: mailbox to use for the FW command
7437 *
7438 *      Issues a command to FW to partially initialize the device.  This
7439 *      performs initialization that generally doesn't depend on user input.
7440 */
7441int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7442{
7443        struct fw_initialize_cmd c;
7444
7445        memset(&c, 0, sizeof(c));
7446        INIT_CMD(c, INITIALIZE, WRITE);
7447        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7448}
7449
7450/**
7451 *      t4_query_params_rw - query FW or device parameters
7452 *      @adap: the adapter
7453 *      @mbox: mailbox to use for the FW command
7454 *      @pf: the PF
7455 *      @vf: the VF
7456 *      @nparams: the number of parameters
7457 *      @params: the parameter names
7458 *      @val: the parameter values
7459 *      @rw: Write and read flag
7460 *      @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7461 *
7462 *      Reads the value of FW or device parameters.  Up to 7 parameters can be
7463 *      queried at once.
7464 */
7465int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7466                       unsigned int vf, unsigned int nparams, const u32 *params,
7467                       u32 *val, int rw, bool sleep_ok)
7468{
7469        int i, ret;
7470        struct fw_params_cmd c;
7471        __be32 *p = &c.param[0].mnem;
7472
7473        if (nparams > 7)
7474                return -EINVAL;
7475
7476        memset(&c, 0, sizeof(c));
7477        c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7478                                  FW_CMD_REQUEST_F | FW_CMD_READ_F |
7479                                  FW_PARAMS_CMD_PFN_V(pf) |
7480                                  FW_PARAMS_CMD_VFN_V(vf));
7481        c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7482
7483        for (i = 0; i < nparams; i++) {
7484                *p++ = cpu_to_be32(*params++);
7485                if (rw)
7486                        *p = cpu_to_be32(*(val + i));
7487                p++;
7488        }
7489
7490        ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7491        if (ret == 0)
7492                for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7493                        *val++ = be32_to_cpu(*p);
7494        return ret;
7495}
7496
7497int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7498                    unsigned int vf, unsigned int nparams, const u32 *params,
7499                    u32 *val)
7500{
7501        return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7502                                  true);
7503}
7504
7505int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7506                       unsigned int vf, unsigned int nparams, const u32 *params,
7507                       u32 *val)
7508{
7509        return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7510                                  false);
7511}
7512
7513/**
7514 *      t4_set_params_timeout - sets FW or device parameters
7515 *      @adap: the adapter
7516 *      @mbox: mailbox to use for the FW command
7517 *      @pf: the PF
7518 *      @vf: the VF
7519 *      @nparams: the number of parameters
7520 *      @params: the parameter names
7521 *      @val: the parameter values
7522 *      @timeout: the timeout time
7523 *
7524 *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7525 *      specified at once.
7526 */
7527int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7528                          unsigned int pf, unsigned int vf,
7529                          unsigned int nparams, const u32 *params,
7530                          const u32 *val, int timeout)
7531{
7532        struct fw_params_cmd c;
7533        __be32 *p = &c.param[0].mnem;
7534
7535        if (nparams > 7)
7536                return -EINVAL;
7537
7538        memset(&c, 0, sizeof(c));
7539        c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7540                                  FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7541                                  FW_PARAMS_CMD_PFN_V(pf) |
7542                                  FW_PARAMS_CMD_VFN_V(vf));
7543        c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7544
7545        while (nparams--) {
7546                *p++ = cpu_to_be32(*params++);
7547                *p++ = cpu_to_be32(*val++);
7548        }
7549
7550        return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7551}
7552
7553/**
7554 *      t4_set_params - sets FW or device parameters
7555 *      @adap: the adapter
7556 *      @mbox: mailbox to use for the FW command
7557 *      @pf: the PF
7558 *      @vf: the VF
7559 *      @nparams: the number of parameters
7560 *      @params: the parameter names
7561 *      @val: the parameter values
7562 *
7563 *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7564 *      specified at once.
7565 */
7566int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7567                  unsigned int vf, unsigned int nparams, const u32 *params,
7568                  const u32 *val)
7569{
7570        return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7571                                     FW_CMD_MAX_TIMEOUT);
7572}
7573
7574/**
7575 *      t4_cfg_pfvf - configure PF/VF resource limits
7576 *      @adap: the adapter
7577 *      @mbox: mailbox to use for the FW command
7578 *      @pf: the PF being configured
7579 *      @vf: the VF being configured
7580 *      @txq: the max number of egress queues
7581 *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
7582 *      @rxqi: the max number of interrupt-capable ingress queues
7583 *      @rxq: the max number of interruptless ingress queues
7584 *      @tc: the PCI traffic class
7585 *      @vi: the max number of virtual interfaces
7586 *      @cmask: the channel access rights mask for the PF/VF
7587 *      @pmask: the port access rights mask for the PF/VF
7588 *      @nexact: the maximum number of exact MPS filters
7589 *      @rcaps: read capabilities
7590 *      @wxcaps: write/execute capabilities
7591 *
7592 *      Configures resource limits and capabilities for a physical or virtual
7593 *      function.
7594 */
7595int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7596                unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7597                unsigned int rxqi, unsigned int rxq, unsigned int tc,
7598                unsigned int vi, unsigned int cmask, unsigned int pmask,
7599                unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7600{
7601        struct fw_pfvf_cmd c;
7602
7603        memset(&c, 0, sizeof(c));
7604        c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7605                                  FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7606                                  FW_PFVF_CMD_VFN_V(vf));
7607        c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7608        c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7609                                     FW_PFVF_CMD_NIQ_V(rxq));
7610        c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7611                                    FW_PFVF_CMD_PMASK_V(pmask) |
7612                                    FW_PFVF_CMD_NEQ_V(txq));
7613        c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7614                                      FW_PFVF_CMD_NVI_V(vi) |
7615                                      FW_PFVF_CMD_NEXACTF_V(nexact));
7616        c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7617                                        FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7618                                        FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7619        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7620}
7621
7622/**
7623 *      t4_alloc_vi - allocate a virtual interface
7624 *      @adap: the adapter
7625 *      @mbox: mailbox to use for the FW command
7626 *      @port: physical port associated with the VI
7627 *      @pf: the PF owning the VI
7628 *      @vf: the VF owning the VI
7629 *      @nmac: number of MAC addresses needed (1 to 5)
7630 *      @mac: the MAC addresses of the VI
7631 *      @rss_size: size of RSS table slice associated with this VI
7632 *      @vivld: the destination to store the VI Valid value.
7633 *      @vin: the destination to store the VIN value.
7634 *
7635 *      Allocates a virtual interface for the given physical port.  If @mac is
7636 *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
7637 *      @mac should be large enough to hold @nmac Ethernet addresses, they are
7638 *      stored consecutively so the space needed is @nmac * 6 bytes.
7639 *      Returns a negative error number or the non-negative VI id.
7640 */
7641int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7642                unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7643                unsigned int *rss_size, u8 *vivld, u8 *vin)
7644{
7645        int ret;
7646        struct fw_vi_cmd c;
7647
7648        memset(&c, 0, sizeof(c));
7649        c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7650                                  FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7651                                  FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7652        c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7653        c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7654        c.nmac = nmac - 1;
7655
7656        ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7657        if (ret)
7658                return ret;
7659
7660        if (mac) {
7661                memcpy(mac, c.mac, sizeof(c.mac));
7662                switch (nmac) {
7663                case 5:
7664                        memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7665                        fallthrough;
7666                case 4:
7667                        memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7668                        fallthrough;
7669                case 3:
7670                        memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7671                        fallthrough;
7672                case 2:
7673                        memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7674                }
7675        }
7676        if (rss_size)
7677                *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7678
7679        if (vivld)
7680                *vivld = FW_VI_CMD_VFVLD_G(be32_to_cpu(c.alloc_to_len16));
7681
7682        if (vin)
7683                *vin = FW_VI_CMD_VIN_G(be32_to_cpu(c.alloc_to_len16));
7684
7685        return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7686}
7687
7688/**
7689 *      t4_free_vi - free a virtual interface
7690 *      @adap: the adapter
7691 *      @mbox: mailbox to use for the FW command
7692 *      @pf: the PF owning the VI
7693 *      @vf: the VF owning the VI
7694 *      @viid: virtual interface identifiler
7695 *
7696 *      Free a previously allocated virtual interface.
7697 */
7698int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7699               unsigned int vf, unsigned int viid)
7700{
7701        struct fw_vi_cmd c;
7702
7703        memset(&c, 0, sizeof(c));
7704        c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7705                                  FW_CMD_REQUEST_F |
7706                                  FW_CMD_EXEC_F |
7707                                  FW_VI_CMD_PFN_V(pf) |
7708                                  FW_VI_CMD_VFN_V(vf));
7709        c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7710        c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7711
7712        return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7713}
7714
7715/**
7716 *      t4_set_rxmode - set Rx properties of a virtual interface
7717 *      @adap: the adapter
7718 *      @mbox: mailbox to use for the FW command
7719 *      @viid: the VI id
7720 *      @viid_mirror: the mirror VI id
7721 *      @mtu: the new MTU or -1
7722 *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7723 *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7724 *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7725 *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7726 *      @sleep_ok: if true we may sleep while awaiting command completion
7727 *
7728 *      Sets Rx properties of a virtual interface.
7729 */
7730int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7731                  unsigned int viid_mirror, int mtu, int promisc, int all_multi,
7732                  int bcast, int vlanex, bool sleep_ok)
7733{
7734        struct fw_vi_rxmode_cmd c, c_mirror;
7735        int ret;
7736
7737        /* convert to FW values */
7738        if (mtu < 0)
7739                mtu = FW_RXMODE_MTU_NO_CHG;
7740        if (promisc < 0)
7741                promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7742        if (all_multi < 0)
7743                all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7744        if (bcast < 0)
7745                bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7746        if (vlanex < 0)
7747                vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7748
7749        memset(&c, 0, sizeof(c));
7750        c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7751                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7752                                   FW_VI_RXMODE_CMD_VIID_V(viid));
7753        c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7754        c.mtu_to_vlanexen =
7755                cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7756                            FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7757                            FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7758                            FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7759                            FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7760
7761        if (viid_mirror) {
7762                memcpy(&c_mirror, &c, sizeof(c_mirror));
7763                c_mirror.op_to_viid =
7764                        cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7765                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7766                                    FW_VI_RXMODE_CMD_VIID_V(viid_mirror));
7767        }
7768
7769        ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7770        if (ret)
7771                return ret;
7772
7773        if (viid_mirror)
7774                ret = t4_wr_mbox_meat(adap, mbox, &c_mirror, sizeof(c_mirror),
7775                                      NULL, sleep_ok);
7776
7777        return ret;
7778}
7779
7780/**
7781 *      t4_free_encap_mac_filt - frees MPS entry at given index
7782 *      @adap: the adapter
7783 *      @viid: the VI id
7784 *      @idx: index of MPS entry to be freed
7785 *      @sleep_ok: call is allowed to sleep
7786 *
7787 *      Frees the MPS entry at supplied index
7788 *
7789 *      Returns a negative error number or zero on success
7790 */
7791int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
7792                           int idx, bool sleep_ok)
7793{
7794        struct fw_vi_mac_exact *p;
7795        struct fw_vi_mac_cmd c;
7796        int ret = 0;
7797        u32 exact;
7798
7799        memset(&c, 0, sizeof(c));
7800        c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7801                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7802                                   FW_CMD_EXEC_V(0) |
7803                                   FW_VI_MAC_CMD_VIID_V(viid));
7804        exact = FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC);
7805        c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7806                                          exact |
7807                                          FW_CMD_LEN16_V(1));
7808        p = c.u.exact;
7809        p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7810                                      FW_VI_MAC_CMD_IDX_V(idx));
7811        eth_zero_addr(p->macaddr);
7812        ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7813        return ret;
7814}
7815
7816/**
7817 *      t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7818 *      @adap: the adapter
7819 *      @viid: the VI id
7820 *      @addr: the MAC address
7821 *      @mask: the mask
7822 *      @idx: index of the entry in mps tcam
7823 *      @lookup_type: MAC address for inner (1) or outer (0) header
7824 *      @port_id: the port index
7825 *      @sleep_ok: call is allowed to sleep
7826 *
7827 *      Removes the mac entry at the specified index using raw mac interface.
7828 *
7829 *      Returns a negative error number on failure.
7830 */
7831int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
7832                         const u8 *addr, const u8 *mask, unsigned int idx,
7833                         u8 lookup_type, u8 port_id, bool sleep_ok)
7834{
7835        struct fw_vi_mac_cmd c;
7836        struct fw_vi_mac_raw *p = &c.u.raw;
7837        u32 val;
7838
7839        memset(&c, 0, sizeof(c));
7840        c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7841                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7842                                   FW_CMD_EXEC_V(0) |
7843                                   FW_VI_MAC_CMD_VIID_V(viid));
7844        val = FW_CMD_LEN16_V(1) |
7845              FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7846        c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7847                                          FW_CMD_LEN16_V(val));
7848
7849        p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) |
7850                                     FW_VI_MAC_ID_BASED_FREE);
7851
7852        /* Lookup Type. Outer header: 0, Inner header: 1 */
7853        p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7854                                   DATAPORTNUM_V(port_id));
7855        /* Lookup mask and port mask */
7856        p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7857                                    DATAPORTNUM_V(DATAPORTNUM_M));
7858
7859        /* Copy the address and the mask */
7860        memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7861        memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7862
7863        return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7864}
7865
7866/**
7867 *      t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7868 *      @adap: the adapter
7869 *      @viid: the VI id
7870 *      @addr: the MAC address
7871 *      @mask: the mask
7872 *      @vni: the VNI id for the tunnel protocol
7873 *      @vni_mask: mask for the VNI id
7874 *      @dip_hit: to enable DIP match for the MPS entry
7875 *      @lookup_type: MAC address for inner (1) or outer (0) header
7876 *      @sleep_ok: call is allowed to sleep
7877 *
7878 *      Allocates an MPS entry with specified MAC address and VNI value.
7879 *
7880 *      Returns a negative error number or the allocated index for this mac.
7881 */
7882int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
7883                            const u8 *addr, const u8 *mask, unsigned int vni,
7884                            unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
7885                            bool sleep_ok)
7886{
7887        struct fw_vi_mac_cmd c;
7888        struct fw_vi_mac_vni *p = c.u.exact_vni;
7889        int ret = 0;
7890        u32 val;
7891
7892        memset(&c, 0, sizeof(c));
7893        c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7894                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7895                                   FW_VI_MAC_CMD_VIID_V(viid));
7896        val = FW_CMD_LEN16_V(1) |
7897              FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI);
7898        c.freemacs_to_len16 = cpu_to_be32(val);
7899        p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7900                                      FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
7901        memcpy(p->macaddr, addr, sizeof(p->macaddr));
7902        memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
7903
7904        p->lookup_type_to_vni =
7905                cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni) |
7906                            FW_VI_MAC_CMD_DIP_HIT_V(dip_hit) |
7907                            FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type));
7908        p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask));
7909        ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7910        if (ret == 0)
7911                ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7912        return ret;
7913}
7914
7915/**
7916 *      t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7917 *      @adap: the adapter
7918 *      @viid: the VI id
7919 *      @addr: the MAC address
7920 *      @mask: the mask
7921 *      @idx: index at which to add this entry
7922 *      @lookup_type: MAC address for inner (1) or outer (0) header
7923 *      @port_id: the port index
7924 *      @sleep_ok: call is allowed to sleep
7925 *
7926 *      Adds the mac entry at the specified index using raw mac interface.
7927 *
7928 *      Returns a negative error number or the allocated index for this mac.
7929 */
7930int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
7931                          const u8 *addr, const u8 *mask, unsigned int idx,
7932                          u8 lookup_type, u8 port_id, bool sleep_ok)
7933{
7934        int ret = 0;
7935        struct fw_vi_mac_cmd c;
7936        struct fw_vi_mac_raw *p = &c.u.raw;
7937        u32 val;
7938
7939        memset(&c, 0, sizeof(c));
7940        c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7941                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7942                                   FW_VI_MAC_CMD_VIID_V(viid));
7943        val = FW_CMD_LEN16_V(1) |
7944              FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7945        c.freemacs_to_len16 = cpu_to_be32(val);
7946
7947        /* Specify that this is an inner mac address */
7948        p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx));
7949
7950        /* Lookup Type. Outer header: 0, Inner header: 1 */
7951        p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7952                                   DATAPORTNUM_V(port_id));
7953        /* Lookup mask and port mask */
7954        p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7955                                    DATAPORTNUM_V(DATAPORTNUM_M));
7956
7957        /* Copy the address and the mask */
7958        memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7959        memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7960
7961        ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7962        if (ret == 0) {
7963                ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd));
7964                if (ret != idx)
7965                        ret = -ENOMEM;
7966        }
7967
7968        return ret;
7969}
7970
7971/**
7972 *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7973 *      @adap: the adapter
7974 *      @mbox: mailbox to use for the FW command
7975 *      @viid: the VI id
7976 *      @free: if true any existing filters for this VI id are first removed
7977 *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7978 *      @addr: the MAC address(es)
7979 *      @idx: where to store the index of each allocated filter
7980 *      @hash: pointer to hash address filter bitmap
7981 *      @sleep_ok: call is allowed to sleep
7982 *
7983 *      Allocates an exact-match filter for each of the supplied addresses and
7984 *      sets it to the corresponding address.  If @idx is not %NULL it should
7985 *      have at least @naddr entries, each of which will be set to the index of
7986 *      the filter allocated for the corresponding MAC address.  If a filter
7987 *      could not be allocated for an address its index is set to 0xffff.
7988 *      If @hash is not %NULL addresses that fail to allocate an exact filter
7989 *      are hashed and update the hash filter bitmap pointed at by @hash.
7990 *
7991 *      Returns a negative error number or the number of filters allocated.
7992 */
7993int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7994                      unsigned int viid, bool free, unsigned int naddr,
7995                      const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7996{
7997        int offset, ret = 0;
7998        struct fw_vi_mac_cmd c;
7999        unsigned int nfilters = 0;
8000        unsigned int max_naddr = adap->params.arch.mps_tcam_size;

8001        unsigned int rem = naddr;
8002
8003        if (naddr > max_naddr)
8004                return -EINVAL;
8005
8006        for (offset = 0; offset < naddr ; /**/) {
8007                unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
8008                                         rem : ARRAY_SIZE(c.u.exact));
8009                size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8010                                                     u.exact[fw_naddr]), 16);
8011                struct fw_vi_mac_exact *p;
8012                int i;
8013
8014                memset(&c, 0, sizeof(c));
8015                c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8016                                           FW_CMD_REQUEST_F |
8017                                           FW_CMD_WRITE_F |
8018                                           FW_CMD_EXEC_V(free) |
8019                                           FW_VI_MAC_CMD_VIID_V(viid));
8020                c.freemacs_to_len16 =
8021                        cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
8022                                    FW_CMD_LEN16_V(len16));
8023
8024                for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8025                        p->valid_to_idx =
8026                                cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8027                                            FW_VI_MAC_CMD_IDX_V(
8028                                                    FW_VI_MAC_ADD_MAC));
8029                        memcpy(p->macaddr, addr[offset + i],
8030                               sizeof(p->macaddr));
8031                }
8032
8033                /* It's okay if we run out of space in our MAC address arena.
8034                 * Some of the addresses we submit may get stored so we need
8035                 * to run through the reply to see what the results were ...
8036                 */
8037                ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8038                if (ret && ret != -FW_ENOMEM)
8039                        break;
8040
8041                for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8042                        u16 index = FW_VI_MAC_CMD_IDX_G(
8043                                        be16_to_cpu(p->valid_to_idx));
8044
8045                        if (idx)
8046                                idx[offset + i] = (index >= max_naddr ?
8047                                                   0xffff : index);
8048                        if (index < max_naddr)
8049                                nfilters++;
8050                        else if (hash)
8051                                *hash |= (1ULL <<
8052                                          hash_mac_addr(addr[offset + i]));
8053                }
8054
8055                free = false;
8056                offset += fw_naddr;
8057                rem -= fw_naddr;
8058        }
8059
8060        if (ret == 0 || ret == -FW_ENOMEM)
8061                ret = nfilters;
8062        return ret;
8063}
8064
8065/**
8066 *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
8067 *      @adap: the adapter
8068 *      @mbox: mailbox to use for the FW command
8069 *      @viid: the VI id
8070 *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
8071 *      @addr: the MAC address(es)
8072 *      @sleep_ok: call is allowed to sleep
8073 *
8074 *      Frees the exact-match filter for each of the supplied addresses
8075 *
8076 *      Returns a negative error number or the number of filters freed.
8077 */
8078int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
8079                     unsigned int viid, unsigned int naddr,
8080                     const u8 **addr, bool sleep_ok)
8081{
8082        int offset, ret = 0;
8083        struct fw_vi_mac_cmd c;
8084        unsigned int nfilters = 0;
8085        unsigned int max_naddr = is_t4(adap->params.chip) ?
8086                                       NUM_MPS_CLS_SRAM_L_INSTANCES :
8087                                       NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8088        unsigned int rem = naddr;
8089
8090        if (naddr > max_naddr)
8091                return -EINVAL;
8092
8093        for (offset = 0; offset < (int)naddr ; /**/) {
8094                unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8095                                         ? rem
8096                                         : ARRAY_SIZE(c.u.exact));
8097                size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8098                                                     u.exact[fw_naddr]), 16);
8099                struct fw_vi_mac_exact *p;
8100                int i;
8101
8102                memset(&c, 0, sizeof(c));
8103                c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8104                                     FW_CMD_REQUEST_F |
8105                                     FW_CMD_WRITE_F |
8106                                     FW_CMD_EXEC_V(0) |
8107                                     FW_VI_MAC_CMD_VIID_V(viid));
8108                c.freemacs_to_len16 =
8109                                cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
8110                                            FW_CMD_LEN16_V(len16));
8111
8112                for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
8113                        p->valid_to_idx = cpu_to_be16(
8114                                FW_VI_MAC_CMD_VALID_F |
8115                                FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
8116                        memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8117                }
8118
8119                ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8120                if (ret)
8121                        break;
8122
8123                for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8124                        u16 index = FW_VI_MAC_CMD_IDX_G(
8125                                                be16_to_cpu(p->valid_to_idx));
8126
8127                        if (index < max_naddr)
8128                                nfilters++;
8129                }
8130
8131                offset += fw_naddr;
8132                rem -= fw_naddr;
8133        }
8134
8135        if (ret == 0)
8136                ret = nfilters;
8137        return ret;
8138}
8139
8140/**
8141 *      t4_change_mac - modifies the exact-match filter for a MAC address
8142 *      @adap: the adapter
8143 *      @mbox: mailbox to use for the FW command
8144 *      @viid: the VI id
8145 *      @idx: index of existing filter for old value of MAC address, or -1
8146 *      @addr: the new MAC address value
8147 *      @persist: whether a new MAC allocation should be persistent
8148 *      @smt_idx: the destination to store the new SMT index.
8149 *
8150 *      Modifies an exact-match filter and sets it to the new MAC address.
8151 *      Note that in general it is not possible to modify the value of a given
8152 *      filter so the generic way to modify an address filter is to free the one
8153 *      being used by the old address value and allocate a new filter for the
8154 *      new address value.  @idx can be -1 if the address is a new addition.
8155 *
8156 *      Returns a negative error number or the index of the filter with the new
8157 *      MAC value.
8158 */
8159int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8160                  int idx, const u8 *addr, bool persist, u8 *smt_idx)
8161{
8162        int ret, mode;
8163        struct fw_vi_mac_cmd c;
8164        struct fw_vi_mac_exact *p = c.u.exact;
8165        unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
8166
8167        if (idx < 0)                             /* new allocation */
8168                idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8169        mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8170
8171        memset(&c, 0, sizeof(c));
8172        c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8173                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8174                                   FW_VI_MAC_CMD_VIID_V(viid));
8175        c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
8176        p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8177                                      FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
8178                                      FW_VI_MAC_CMD_IDX_V(idx));
8179        memcpy(p->macaddr, addr, sizeof(p->macaddr));
8180
8181        ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8182        if (ret == 0) {
8183                ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
8184                if (ret >= max_mac_addr)
8185                        ret = -ENOMEM;
8186                if (smt_idx) {
8187                        if (adap->params.viid_smt_extn_support) {
8188                                *smt_idx = FW_VI_MAC_CMD_SMTID_G
8189                                                    (be32_to_cpu(c.op_to_viid));
8190                        } else {
8191                                /* In T4/T5, SMT contains 256 SMAC entries
8192                                 * organized in 128 rows of 2 entries each.
8193                                 * In T6, SMT contains 256 SMAC entries in
8194                                 * 256 rows.
8195                                 */
8196                                if (CHELSIO_CHIP_VERSION(adap->params.chip) <=
8197                                                                     CHELSIO_T5)
8198                                        *smt_idx = (viid & FW_VIID_VIN_M) << 1;
8199                                else
8200                                        *smt_idx = (viid & FW_VIID_VIN_M);
8201                        }
8202                }
8203        }
8204        return ret;
8205}
8206
8207/**
8208 *      t4_set_addr_hash - program the MAC inexact-match hash filter
8209 *      @adap: the adapter
8210 *      @mbox: mailbox to use for the FW command
8211 *      @viid: the VI id
8212 *      @ucast: whether the hash filter should also match unicast addresses
8213 *      @vec: the value to be written to the hash filter
8214 *      @sleep_ok: call is allowed to sleep
8215 *
8216 *      Sets the 64-bit inexact-match hash filter for a virtual interface.
8217 */
8218int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8219                     bool ucast, u64 vec, bool sleep_ok)
8220{
8221        struct fw_vi_mac_cmd c;
8222
8223        memset(&c, 0, sizeof(c));
8224        c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8225                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8226                                   FW_VI_ENABLE_CMD_VIID_V(viid));
8227        c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
8228                                          FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
8229                                          FW_CMD_LEN16_V(1));
8230        c.u.hash.hashvec = cpu_to_be64(vec);
8231        return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8232}
8233
8234/**
8235 *      t4_enable_vi_params - enable/disable a virtual interface
8236 *      @adap: the adapter
8237 *      @mbox: mailbox to use for the FW command
8238 *      @viid: the VI id
8239 *      @rx_en: 1=enable Rx, 0=disable Rx
8240 *      @tx_en: 1=enable Tx, 0=disable Tx
8241 *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
8242 *
8243 *      Enables/disables a virtual interface.  Note that setting DCB Enable
8244 *      only makes sense when enabling a Virtual Interface ...
8245 */
8246int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8247                        unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8248{
8249        struct fw_vi_enable_cmd c;
8250
8251        memset(&c, 0, sizeof(c));
8252        c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8253                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8254                                   FW_VI_ENABLE_CMD_VIID_V(viid));
8255        c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
8256                                     FW_VI_ENABLE_CMD_EEN_V(tx_en) |
8257                                     FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
8258                                     FW_LEN16(c));
8259        return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8260}
8261
8262/**
8263 *      t4_enable_vi - enable/disable a virtual interface
8264 *      @adap: the adapter
8265 *      @mbox: mailbox to use for the FW command
8266 *      @viid: the VI id
8267 *      @rx_en: 1=enable Rx, 0=disable Rx
8268 *      @tx_en: 1=enable Tx, 0=disable Tx
8269 *
8270 *      Enables/disables a virtual interface.
8271 */
8272int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8273                 bool rx_en, bool tx_en)
8274{
8275        return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8276}
8277
8278/**
8279 *      t4_enable_pi_params - enable/disable a Port's Virtual Interface
8280 *      @adap: the adapter
8281 *      @mbox: mailbox to use for the FW command
8282 *      @pi: the Port Information structure
8283 *      @rx_en: 1=enable Rx, 0=disable Rx
8284 *      @tx_en: 1=enable Tx, 0=disable Tx
8285 *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
8286 *
8287 *      Enables/disables a Port's Virtual Interface.  Note that setting DCB
8288 *      Enable only makes sense when enabling a Virtual Interface ...
8289 *      If the Virtual Interface enable/disable operation is successful,
8290 *      we notify the OS-specific code of a potential Link Status change
8291 *      via the OS Contract API t4_os_link_changed().
8292 */
8293int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
8294                        struct port_info *pi,
8295                        bool rx_en, bool tx_en, bool dcb_en)
8296{
8297        int ret = t4_enable_vi_params(adap, mbox, pi->viid,
8298                                      rx_en, tx_en, dcb_en);
8299        if (ret)
8300                return ret;
8301        t4_os_link_changed(adap, pi->port_id,
8302                           rx_en && tx_en && pi->link_cfg.link_ok);
8303        return 0;
8304}
8305
8306/**
8307 *      t4_identify_port - identify a VI's port by blinking its LED
8308 *      @adap: the adapter
8309 *      @mbox: mailbox to use for the FW command
8310 *      @viid: the VI id
8311 *      @nblinks: how many times to blink LED at 2.5 Hz
8312 *
8313 *      Identifies a VI's port by blinking its LED.
8314 */
8315int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8316                     unsigned int nblinks)
8317{
8318        struct fw_vi_enable_cmd c;
8319
8320        memset(&c, 0, sizeof(c));
8321        c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8322                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8323                                   FW_VI_ENABLE_CMD_VIID_V(viid));
8324        c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
8325        c.blinkdur = cpu_to_be16(nblinks);
8326        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8327}
8328
8329/**
8330 *      t4_iq_stop - stop an ingress queue and its FLs
8331 *      @adap: the adapter
8332 *      @mbox: mailbox to use for the FW command
8333 *      @pf: the PF owning the queues
8334 *      @vf: the VF owning the queues
8335 *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8336 *      @iqid: ingress queue id
8337 *      @fl0id: FL0 queue id or 0xffff if no attached FL0
8338 *      @fl1id: FL1 queue id or 0xffff if no attached FL1
8339 *
8340 *      Stops an ingress queue and its associated FLs, if any.  This causes
8341 *      any current or future data/messages destined for these queues to be
8342 *      tossed.
8343 */
8344int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8345               unsigned int vf, unsigned int iqtype, unsigned int iqid,
8346               unsigned int fl0id, unsigned int fl1id)
8347{
8348        struct fw_iq_cmd c;
8349
8350        memset(&c, 0, sizeof(c));
8351        c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8352                                  FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8353                                  FW_IQ_CMD_VFN_V(vf));
8354        c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
8355        c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8356        c.iqid = cpu_to_be16(iqid);
8357        c.fl0id = cpu_to_be16(fl0id);
8358        c.fl1id = cpu_to_be16(fl1id);
8359        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8360}
8361
8362/**
8363 *      t4_iq_free - free an ingress queue and its FLs
8364 *      @adap: the adapter
8365 *      @mbox: mailbox to use for the FW command
8366 *      @pf: the PF owning the queues
8367 *      @vf: the VF owning the queues
8368 *      @iqtype: the ingress queue type
8369 *      @iqid: ingress queue id
8370 *      @fl0id: FL0 queue id or 0xffff if no attached FL0
8371 *      @fl1id: FL1 queue id or 0xffff if no attached FL1
8372 *
8373 *      Frees an ingress queue and its associated FLs, if any.
8374 */
8375int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8376               unsigned int vf, unsigned int iqtype, unsigned int iqid,
8377               unsigned int fl0id, unsigned int fl1id)
8378{
8379        struct fw_iq_cmd c;
8380
8381        memset(&c, 0, sizeof(c));
8382        c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8383                                  FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8384                                  FW_IQ_CMD_VFN_V(vf));
8385        c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
8386        c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8387        c.iqid = cpu_to_be16(iqid);
8388        c.fl0id = cpu_to_be16(fl0id);
8389        c.fl1id = cpu_to_be16(fl1id);
8390        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8391}
8392
8393/**
8394 *      t4_eth_eq_free - free an Ethernet egress queue
8395 *      @adap: the adapter
8396 *      @mbox: mailbox to use for the FW command
8397 *      @pf: the PF owning the queue
8398 *      @vf: the VF owning the queue
8399 *      @eqid: egress queue id
8400 *
8401 *      Frees an Ethernet egress queue.
8402 */
8403int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8404                   unsigned int vf, unsigned int eqid)
8405{
8406        struct fw_eq_eth_cmd c;
8407
8408        memset(&c, 0, sizeof(c));
8409        c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
8410                                  FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8411                                  FW_EQ_ETH_CMD_PFN_V(pf) |
8412                                  FW_EQ_ETH_CMD_VFN_V(vf));
8413        c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
8414        c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
8415        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8416}
8417
8418/**
8419 *      t4_ctrl_eq_free - free a control egress queue
8420 *      @adap: the adapter
8421 *      @mbox: mailbox to use for the FW command
8422 *      @pf: the PF owning the queue
8423 *      @vf: the VF owning the queue
8424 *      @eqid: egress queue id
8425 *
8426 *      Frees a control egress queue.
8427 */
8428int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8429                    unsigned int vf, unsigned int eqid)
8430{
8431        struct fw_eq_ctrl_cmd c;
8432
8433        memset(&c, 0, sizeof(c));
8434        c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
8435                                  FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8436                                  FW_EQ_CTRL_CMD_PFN_V(pf) |
8437                                  FW_EQ_CTRL_CMD_VFN_V(vf));
8438        c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
8439        c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
8440        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8441}
8442
8443/**
8444 *      t4_ofld_eq_free - free an offload egress queue
8445 *      @adap: the adapter
8446 *      @mbox: mailbox to use for the FW command
8447 *      @pf: the PF owning the queue
8448 *      @vf: the VF owning the queue
8449 *      @eqid: egress queue id
8450 *
8451 *      Frees a control egress queue.
8452 */
8453int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8454                    unsigned int vf, unsigned int eqid)
8455{
8456        struct fw_eq_ofld_cmd c;
8457
8458        memset(&c, 0, sizeof(c));
8459        c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
8460                                  FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8461                                  FW_EQ_OFLD_CMD_PFN_V(pf) |
8462                                  FW_EQ_OFLD_CMD_VFN_V(vf));
8463        c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
8464        c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
8465        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8466}
8467
8468/**
8469 *      t4_link_down_rc_str - return a string for a Link Down Reason Code
8470 *      @link_down_rc: Link Down Reason Code
8471 *
8472 *      Returns a string representation of the Link Down Reason Code.
8473 */
8474static const char *t4_link_down_rc_str(unsigned char link_down_rc)
8475{
8476        static const char * const reason[] = {
8477                "Link Down",
8478                "Remote Fault",
8479                "Auto-negotiation Failure",
8480                "Reserved",
8481                "Insufficient Airflow",
8482                "Unable To Determine Reason",
8483                "No RX Signal Detected",
8484                "Reserved",
8485        };
8486
8487        if (link_down_rc >= ARRAY_SIZE(reason))
8488                return "Bad Reason Code";
8489
8490        return reason[link_down_rc];
8491}
8492
8493/* Return the highest speed set in the port capabilities, in Mb/s. */
8494static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
8495{
8496        #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8497                do { \
8498                        if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8499                                return __speed; \
8500                } while (0)
8501
8502        TEST_SPEED_RETURN(400G, 400000);
8503        TEST_SPEED_RETURN(200G, 200000);
8504        TEST_SPEED_RETURN(100G, 100000);
8505        TEST_SPEED_RETURN(50G,   50000);
8506        TEST_SPEED_RETURN(40G,   40000);
8507        TEST_SPEED_RETURN(25G,   25000);
8508        TEST_SPEED_RETURN(10G,   10000);
8509        TEST_SPEED_RETURN(1G,     1000);
8510        TEST_SPEED_RETURN(100M,    100);
8511
8512        #undef TEST_SPEED_RETURN
8513
8514        return 0;
8515}
8516
8517/**
8518 *      fwcap_to_fwspeed - return highest speed in Port Capabilities
8519 *      @acaps: advertised Port Capabilities
8520 *
8521 *      Get the highest speed for the port from the advertised Port
8522 *      Capabilities.  It will be either the highest speed from the list of
8523 *      speeds or whatever user has set using ethtool.
8524 */
8525static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
8526{
8527        #define TEST_SPEED_RETURN(__caps_speed) \
8528                do { \
8529                        if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8530                                return FW_PORT_CAP32_SPEED_##__caps_speed; \
8531                } while (0)
8532
8533        TEST_SPEED_RETURN(400G);
8534        TEST_SPEED_RETURN(200G);
8535        TEST_SPEED_RETURN(100G);
8536        TEST_SPEED_RETURN(50G);
8537        TEST_SPEED_RETURN(40G);
8538        TEST_SPEED_RETURN(25G);
8539        TEST_SPEED_RETURN(10G);
8540        TEST_SPEED_RETURN(1G);
8541        TEST_SPEED_RETURN(100M);
8542
8543        #undef TEST_SPEED_RETURN
8544
8545        return 0;
8546}
8547
8548/**
8549 *      lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8550 *      @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8551 *
8552 *      Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8553 *      32-bit Port Capabilities value.
8554 */
8555static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
8556{
8557        fw_port_cap32_t linkattr = 0;
8558
8559        /* Unfortunately the format of the Link Status in the old
8560         * 16-bit Port Information message isn't the same as the
8561         * 16-bit Port Capabilities bitfield used everywhere else ...
8562         */
8563        if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8564                linkattr |= FW_PORT_CAP32_FC_RX;
8565        if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8566                linkattr |= FW_PORT_CAP32_FC_TX;
8567        if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8568                linkattr |= FW_PORT_CAP32_SPEED_100M;
8569        if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8570                linkattr |= FW_PORT_CAP32_SPEED_1G;
8571        if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8572                linkattr |= FW_PORT_CAP32_SPEED_10G;
8573        if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8574                linkattr |= FW_PORT_CAP32_SPEED_25G;
8575        if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8576                linkattr |= FW_PORT_CAP32_SPEED_40G;
8577        if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8578                linkattr |= FW_PORT_CAP32_SPEED_100G;
8579
8580        return linkattr;
8581}
8582
8583/**
8584 *      t4_handle_get_port_info - process a FW reply message
8585 *      @pi: the port info
8586 *      @rpl: start of the FW message
8587 *
8588 *      Processes a GET_PORT_INFO FW reply message.
8589 */
8590void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8591{
8592        const struct fw_port_cmd *cmd = (const void *)rpl;
8593        fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8594        struct link_config *lc = &pi->link_cfg;
8595        struct adapter *adapter = pi->adapter;
8596        unsigned int speed, fc, fec, adv_fc;
8597        enum fw_port_module_type mod_type;
8598        int action, link_ok, linkdnrc;
8599        enum fw_port_type port_type;
8600
8601        /* Extract the various fields from the Port Information message.
8602         */
8603        action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8604        switch (action) {
8605        case FW_PORT_ACTION_GET_PORT_INFO: {
8606                u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8607
8608                link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8609                linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8610                port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8611                mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8612                pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8613                acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8614                lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8615                linkattr = lstatus_to_fwcap(lstatus);
8616                break;
8617        }
8618
8619        case FW_PORT_ACTION_GET_PORT_INFO32: {
8620                u32 lstatus32;
8621
8622                lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8623                link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8624                linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8625                port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8626                mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8627                pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8628                acaps = be32_to_cpu(cmd->u.info32.acaps32);
8629                lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8630                linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8631                break;
8632        }
8633
8634        default:
8635                dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8636                        be32_to_cpu(cmd->action_to_len16));
8637                return;
8638        }
8639
8640        fec = fwcap_to_cc_fec(acaps);
8641        adv_fc = fwcap_to_cc_pause(acaps);
8642        fc = fwcap_to_cc_pause(linkattr);
8643        speed = fwcap_to_speed(linkattr);
8644
8645        /* Reset state for communicating new Transceiver Module status and
8646         * whether the OS-dependent layer wants us to redo the current
8647         * "sticky" L1 Configure Link Parameters.
8648         */
8649        lc->new_module = false;
8650        lc->redo_l1cfg = false;
8651
8652        if (mod_type != pi->mod_type) {
8653                /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8654                 * various fundamental Port Capabilities which used to be
8655                 * immutable can now change radically.  We can now have
8656                 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8657                 * all change based on what Transceiver Module is inserted.
8658                 * So we need to record the Physical "Port" Capabilities on
8659                 * every Transceiver Module change.
8660                 */
8661                lc->pcaps = pcaps;
8662
8663                /* When a new Transceiver Module is inserted, the Firmware
8664                 * will examine its i2c EPROM to determine its type and
8665                 * general operating parameters including things like Forward
8666                 * Error Control, etc.  Various IEEE 802.3 standards dictate
8667                 * how to interpret these i2c values to determine default
8668                 * "sutomatic" settings.  We record these for future use when
8669                 * the user explicitly requests these standards-based values.
8670                 */
8671                lc->def_acaps = acaps;
8672
8673                /* Some versions of the early T6 Firmware "cheated" when
8674                 * handling different Transceiver Modules by changing the
8675                 * underlaying Port Type reported to the Host Drivers.  As
8676                 * such we need to capture whatever Port Type the Firmware
8677                 * sends us and record it in case it's different from what we
8678                 * were told earlier.  Unfortunately, since Firmware is
8679                 * forever, we'll need to keep this code here forever, but in
8680                 * later T6 Firmware it should just be an assignment of the
8681                 * same value already recorded.
8682                 */
8683                pi->port_type = port_type;
8684
8685                /* Record new Module Type information.
8686                 */
8687                pi->mod_type = mod_type;
8688
8689                /* Let the OS-dependent layer know if we have a new
8690                 * Transceiver Module inserted.
8691                 */
8692                lc->new_module = t4_is_inserted_mod_type(mod_type);
8693
8694                t4_os_portmod_changed(adapter, pi->port_id);
8695        }
8696
8697        if (link_ok != lc->link_ok || speed != lc->speed ||
8698            fc != lc->fc || adv_fc != lc->advertised_fc ||
8699            fec != lc->fec) {
8700                /* something changed */
8701                if (!link_ok && lc->link_ok) {
8702                        lc->link_down_rc = linkdnrc;
8703                        dev_warn_ratelimited(adapter->pdev_dev,
8704                                             "Port %d link down, reason: %s\n",
8705                                             pi->tx_chan,
8706                                             t4_link_down_rc_str(linkdnrc));
8707                }
8708                lc->link_ok = link_ok;
8709                lc->speed = speed;
8710                lc->advertised_fc = adv_fc;
8711                lc->fc = fc;
8712                lc->fec = fec;
8713
8714                lc->lpacaps = lpacaps;
8715                lc->acaps = acaps & ADVERT_MASK;
8716
8717                /* If we're not physically capable of Auto-Negotiation, note
8718                 * this as Auto-Negotiation disabled.  Otherwise, we track
8719                 * what Auto-Negotiation settings we have.  Note parallel
8720                 * structure in t4_link_l1cfg_core() and init_link_config().
8721                 */
8722                if (!(lc->acaps & FW_PORT_CAP32_ANEG)) {
8723                        lc->autoneg = AUTONEG_DISABLE;
8724                } else if (lc->acaps & FW_PORT_CAP32_ANEG) {
8725                        lc->autoneg = AUTONEG_ENABLE;
8726                } else {
8727                        /* When Autoneg is disabled, user needs to set
8728                         * single speed.
8729                         * Similar to cxgb4_ethtool.c: set_link_ksettings
8730                         */
8731                        lc->acaps = 0;
8732                        lc->speed_caps = fwcap_to_fwspeed(acaps);
8733                        lc->autoneg = AUTONEG_DISABLE;
8734                }
8735
8736                t4_os_link_changed(adapter, pi->port_id, link_ok);
8737        }
8738
8739        /* If we have a new Transceiver Module and the OS-dependent code has
8740         * told us that it wants us to redo whatever "sticky" L1 Configuration
8741         * Link Parameters are set, do that now.
8742         */
8743        if (lc->new_module && lc->redo_l1cfg) {
8744                struct link_config old_lc;
8745                int ret;
8746
8747                /* Save the current L1 Configuration and restore it if an
8748                 * error occurs.  We probably should fix the l1_cfg*()
8749                 * routines not to change the link_config when an error
8750                 * occurs ...
8751                 */
8752                old_lc = *lc;
8753                ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc);
8754                if (ret) {
8755                        *lc = old_lc;
8756                        dev_warn(adapter->pdev_dev,
8757                                 "Attempt to update new Transceiver Module settings failed\n");
8758                }
8759        }
8760        lc->new_module = false;
8761        lc->redo_l1cfg = false;
8762}
8763
8764/**
8765 *      t4_update_port_info - retrieve and update port information if changed
8766 *      @pi: the port_info
8767 *
8768 *      We issue a Get Port Information Command to the Firmware and, if
8769 *      successful, we check to see if anything is different from what we
8770 *      last recorded and update things accordingly.
8771 */
8772int t4_update_port_info(struct port_info *pi)
8773{
8774        unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8775        struct fw_port_cmd port_cmd;
8776        int ret;
8777
8778        memset(&port_cmd, 0, sizeof(port_cmd));
8779        port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8780                                            FW_CMD_REQUEST_F | FW_CMD_READ_F |
8781                                            FW_PORT_CMD_PORTID_V(pi->tx_chan));
8782        port_cmd.action_to_len16 = cpu_to_be32(
8783                FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8784                                     ? FW_PORT_ACTION_GET_PORT_INFO
8785                                     : FW_PORT_ACTION_GET_PORT_INFO32) |
8786                FW_LEN16(port_cmd));
8787        ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8788                         &port_cmd, sizeof(port_cmd), &port_cmd);
8789        if (ret)
8790                return ret;
8791
8792        t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8793        return 0;
8794}
8795
8796/**
8797 *      t4_get_link_params - retrieve basic link parameters for given port
8798 *      @pi: the port
8799 *      @link_okp: value return pointer for link up/down
8800 *      @speedp: value return pointer for speed (Mb/s)
8801 *      @mtup: value return pointer for mtu
8802 *
8803 *      Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8804 *      and MTU for a specified port.  A negative error is returned on
8805 *      failure; 0 on success.
8806 */
8807int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8808                       unsigned int *speedp, unsigned int *mtup)
8809{
8810        unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8811        unsigned int action, link_ok, mtu;
8812        struct fw_port_cmd port_cmd;
8813        fw_port_cap32_t linkattr;
8814        int ret;
8815
8816        memset(&port_cmd, 0, sizeof(port_cmd));
8817        port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8818                                            FW_CMD_REQUEST_F | FW_CMD_READ_F |
8819                                            FW_PORT_CMD_PORTID_V(pi->tx_chan));
8820        action = (fw_caps == FW_CAPS16
8821                  ? FW_PORT_ACTION_GET_PORT_INFO
8822                  : FW_PORT_ACTION_GET_PORT_INFO32);
8823        port_cmd.action_to_len16 = cpu_to_be32(
8824                FW_PORT_CMD_ACTION_V(action) |
8825                FW_LEN16(port_cmd));
8826        ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8827                         &port_cmd, sizeof(port_cmd), &port_cmd);
8828        if (ret)
8829                return ret;
8830
8831        if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8832                u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8833
8834                link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8835                linkattr = lstatus_to_fwcap(lstatus);
8836                mtu = be16_to_cpu(port_cmd.u.info.mtu);
8837        } else {
8838                u32 lstatus32 =
8839                           be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8840
8841                link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8842                linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8843                mtu = FW_PORT_CMD_MTU32_G(
8844                        be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8845        }
8846
8847        if (link_okp)
8848                *link_okp = link_ok;
8849        if (speedp)
8850                *speedp = fwcap_to_speed(linkattr);
8851        if (mtup)
8852                *mtup = mtu;
8853
8854        return 0;
8855}
8856
8857/**
8858 *      t4_handle_fw_rpl - process a FW reply message
8859 *      @adap: the adapter
8860 *      @rpl: start of the FW message
8861 *
8862 *      Processes a FW message, such as link state change messages.
8863 */
8864int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8865{
8866        u8 opcode = *(const u8 *)rpl;
8867
8868        /* This might be a port command ... this simplifies the following
8869         * conditionals ...  We can get away with pre-dereferencing
8870         * action_to_len16 because it's in the first 16 bytes and all messages
8871         * will be at least that long.
8872         */
8873        const struct fw_port_cmd *p = (const void *)rpl;
8874        unsigned int action =
8875                FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8876
8877        if (opcode == FW_PORT_CMD &&
8878            (action == FW_PORT_ACTION_GET_PORT_INFO ||
8879             action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8880                int i;
8881                int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8882                struct port_info *pi = NULL;
8883
8884                for_each_port(adap, i) {
8885                        pi = adap2pinfo(adap, i);
8886                        if (pi->tx_chan == chan)
8887                                break;
8888                }
8889
8890                t4_handle_get_port_info(pi, rpl);
8891        } else {
8892                dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8893                         opcode);
8894                return -EINVAL;
8895        }
8896        return 0;
8897}
8898
8899static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8900{
8901        u16 val;
8902
8903        if (pci_is_pcie(adapter->pdev)) {
8904                pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8905                p->speed = val & PCI_EXP_LNKSTA_CLS;
8906                p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8907        }
8908}
8909
8910/**
8911 *      init_link_config - initialize a link's SW state
8912 *      @lc: pointer to structure holding the link state
8913 *      @pcaps: link Port Capabilities
8914 *      @acaps: link current Advertised Port Capabilities
8915 *
8916 *      Initializes the SW state maintained for each link, including the link's
8917 *      capabilities and default speed/flow-control/autonegotiation settings.
8918 */
8919static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8920                             fw_port_cap32_t acaps)
8921{
8922        lc->pcaps = pcaps;
8923        lc->def_acaps = acaps;
8924        lc->lpacaps = 0;
8925        lc->speed_caps = 0;
8926        lc->speed = 0;
8927        lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8928
8929        /* For Forward Error Control, we default to whatever the Firmware
8930         * tells us the Link is currently advertising.
8931         */
8932        lc->requested_fec = FEC_AUTO;
8933        lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8934
8935        /* If the Port is capable of Auto-Negtotiation, initialize it as
8936         * "enabled" and copy over all of the Physical Port Capabilities
8937         * to the Advertised Port Capabilities.  Otherwise mark it as
8938         * Auto-Negotiate disabled and select the highest supported speed
8939         * for the link.  Note parallel structure in t4_link_l1cfg_core()
8940         * and t4_handle_get_port_info().
8941         */
8942        if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8943                lc->acaps = lc->pcaps & ADVERT_MASK;
8944                lc->autoneg = AUTONEG_ENABLE;
8945                lc->requested_fc |= PAUSE_AUTONEG;
8946        } else {
8947                lc->acaps = 0;
8948                lc->autoneg = AUTONEG_DISABLE;
8949                lc->speed_caps = fwcap_to_fwspeed(acaps);
8950        }
8951}
8952
8953#define CIM_PF_NOACCESS 0xeeeeeeee
8954
8955int t4_wait_dev_ready(void __iomem *regs)
8956{
8957        u32 whoami;
8958
8959        whoami = readl(regs + PL_WHOAMI_A);
8960        if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8961                return 0;
8962
8963        msleep(500);
8964        whoami = readl(regs + PL_WHOAMI_A);
8965        return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8966}
8967
8968struct flash_desc {
8969        u32 vendor_and_model_id;
8970        u32 size_mb;
8971};
8972
8973static int t4_get_flash_params(struct adapter *adap)
8974{
8975        /* Table for non-Numonix supported flash parts.  Numonix parts are left
8976         * to the preexisting code.  All flash parts have 64KB sectors.
8977         */
8978        static struct flash_desc supported_flash[] = {
8979                { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
8980        };
8981
8982        unsigned int part, manufacturer;
8983        unsigned int density, size = 0;
8984        u32 flashid = 0;
8985        int ret;
8986
8987        /* Issue a Read ID Command to the Flash part.  We decode supported
8988         * Flash parts and their sizes from this.  There's a newer Query
8989         * Command which can retrieve detailed geometry information but many
8990         * Flash parts don't support it.
8991         */
8992
8993        ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8994        if (!ret)
8995                ret = sf1_read(adap, 3, 0, 1, &flashid);
8996        t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
8997        if (ret)
8998                return ret;
8999
9000        /* Check to see if it's one of our non-standard supported Flash parts.

9001         */
9002        for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
9003                if (supported_flash[part].vendor_and_model_id == flashid) {
9004                        adap->params.sf_size = supported_flash[part].size_mb;
9005                        adap->params.sf_nsec =
9006                                adap->params.sf_size / SF_SEC_SIZE;
9007                        goto found;
9008                }
9009
9010        /* Decode Flash part size.  The code below looks repetitive with
9011         * common encodings, but that's not guaranteed in the JEDEC
9012         * specification for the Read JEDEC ID command.  The only thing that
9013         * we're guaranteed by the JEDEC specification is where the
9014         * Manufacturer ID is in the returned result.  After that each
9015         * Manufacturer ~could~ encode things completely differently.
9016         * Note, all Flash parts must have 64KB sectors.
9017         */
9018        manufacturer = flashid & 0xff;
9019        switch (manufacturer) {
9020        case 0x20: { /* Micron/Numonix */
9021                /* This Density -> Size decoding table is taken from Micron
9022                 * Data Sheets.
9023                 */
9024                density = (flashid >> 16) & 0xff;
9025                switch (density) {
9026                case 0x14: /* 1MB */
9027                        size = 1 << 20;
9028                        break;
9029                case 0x15: /* 2MB */
9030                        size = 1 << 21;
9031                        break;
9032                case 0x16: /* 4MB */
9033                        size = 1 << 22;
9034                        break;
9035                case 0x17: /* 8MB */
9036                        size = 1 << 23;
9037                        break;
9038                case 0x18: /* 16MB */
9039                        size = 1 << 24;
9040                        break;
9041                case 0x19: /* 32MB */
9042                        size = 1 << 25;
9043                        break;
9044                case 0x20: /* 64MB */
9045                        size = 1 << 26;
9046                        break;
9047                case 0x21: /* 128MB */
9048                        size = 1 << 27;
9049                        break;
9050                case 0x22: /* 256MB */
9051                        size = 1 << 28;
9052                        break;
9053                }
9054                break;
9055        }
9056        case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
9057                /* This Density -> Size decoding table is taken from ISSI
9058                 * Data Sheets.
9059                 */
9060                density = (flashid >> 16) & 0xff;
9061                switch (density) {
9062                case 0x16: /* 32 MB */
9063                        size = 1 << 25;
9064                        break;
9065                case 0x17: /* 64MB */
9066                        size = 1 << 26;
9067                        break;
9068                }
9069                break;
9070        }
9071        case 0xc2: { /* Macronix */
9072                /* This Density -> Size decoding table is taken from Macronix
9073                 * Data Sheets.
9074                 */
9075                density = (flashid >> 16) & 0xff;
9076                switch (density) {
9077                case 0x17: /* 8MB */
9078                        size = 1 << 23;
9079                        break;
9080                case 0x18: /* 16MB */
9081                        size = 1 << 24;
9082                        break;
9083                }
9084                break;
9085        }
9086        case 0xef: { /* Winbond */
9087                /* This Density -> Size decoding table is taken from Winbond
9088                 * Data Sheets.
9089                 */
9090                density = (flashid >> 16) & 0xff;
9091                switch (density) {
9092                case 0x17: /* 8MB */
9093                        size = 1 << 23;
9094                        break;
9095                case 0x18: /* 16MB */
9096                        size = 1 << 24;
9097                        break;
9098                }
9099                break;
9100        }
9101        }
9102
9103        /* If we didn't recognize the FLASH part, that's no real issue: the
9104         * Hardware/Software contract says that Hardware will _*ALWAYS*_
9105         * use a FLASH part which is at least 4MB in size and has 64KB
9106         * sectors.  The unrecognized FLASH part is likely to be much larger
9107         * than 4MB, but that's all we really need.
9108         */
9109        if (size == 0) {
9110                dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
9111                         flashid);
9112                size = 1 << 22;
9113        }
9114
9115        /* Store decoded Flash size and fall through into vetting code. */
9116        adap->params.sf_size = size;
9117        adap->params.sf_nsec = size / SF_SEC_SIZE;
9118
9119found:
9120        if (adap->params.sf_size < FLASH_MIN_SIZE)
9121                dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9122                         flashid, adap->params.sf_size, FLASH_MIN_SIZE);
9123        return 0;
9124}
9125
9126/**
9127 *      t4_prep_adapter - prepare SW and HW for operation
9128 *      @adapter: the adapter
9129 *
9130 *      Initialize adapter SW state for the various HW modules, set initial
9131 *      values for some adapter tunables, take PHYs out of reset, and
9132 *      initialize the MDIO interface.
9133 */
9134int t4_prep_adapter(struct adapter *adapter)
9135{
9136        int ret, ver;
9137        uint16_t device_id;
9138        u32 pl_rev;
9139
9140        get_pci_mode(adapter, &adapter->params.pci);
9141        pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
9142
9143        ret = t4_get_flash_params(adapter);
9144        if (ret < 0) {
9145                dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
9146                return ret;
9147        }
9148
9149        /* Retrieve adapter's device ID
9150         */
9151        pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
9152        ver = device_id >> 12;
9153        adapter->params.chip = 0;
9154        switch (ver) {
9155        case CHELSIO_T4:
9156                adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
9157                adapter->params.arch.sge_fl_db = DBPRIO_F;
9158                adapter->params.arch.mps_tcam_size =
9159                                 NUM_MPS_CLS_SRAM_L_INSTANCES;
9160                adapter->params.arch.mps_rplc_size = 128;
9161                adapter->params.arch.nchan = NCHAN;
9162                adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9163                adapter->params.arch.vfcount = 128;
9164                /* Congestion map is for 4 channels so that
9165                 * MPS can have 4 priority per port.
9166                 */
9167                adapter->params.arch.cng_ch_bits_log = 2;
9168                break;
9169        case CHELSIO_T5:
9170                adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
9171                adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
9172                adapter->params.arch.mps_tcam_size =
9173                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9174                adapter->params.arch.mps_rplc_size = 128;
9175                adapter->params.arch.nchan = NCHAN;
9176                adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9177                adapter->params.arch.vfcount = 128;
9178                adapter->params.arch.cng_ch_bits_log = 2;
9179                break;
9180        case CHELSIO_T6:
9181                adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
9182                adapter->params.arch.sge_fl_db = 0;
9183                adapter->params.arch.mps_tcam_size =
9184                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9185                adapter->params.arch.mps_rplc_size = 256;
9186                adapter->params.arch.nchan = 2;
9187                adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
9188                adapter->params.arch.vfcount = 256;
9189                /* Congestion map will be for 2 channels so that
9190                 * MPS can have 8 priority per port.
9191                 */
9192                adapter->params.arch.cng_ch_bits_log = 3;
9193                break;
9194        default:
9195                dev_err(adapter->pdev_dev, "Device %d is not supported\n",
9196                        device_id);
9197                return -EINVAL;
9198        }
9199
9200        adapter->params.cim_la_size = CIMLA_SIZE;
9201        init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
9202
9203        /*
9204         * Default port for debugging in case we can't reach FW.
9205         */
9206        adapter->params.nports = 1;
9207        adapter->params.portvec = 1;
9208        adapter->params.vpd.cclk = 50000;
9209
9210        /* Set PCIe completion timeout to 4 seconds. */
9211        pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
9212                                           PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
9213        return 0;
9214}
9215
9216/**
9217 *      t4_shutdown_adapter - shut down adapter, host & wire
9218 *      @adapter: the adapter
9219 *
9220 *      Perform an emergency shutdown of the adapter and stop it from
9221 *      continuing any further communication on the ports or DMA to the
9222 *      host.  This is typically used when the adapter and/or firmware
9223 *      have crashed and we want to prevent any further accidental
9224 *      communication with the rest of the world.  This will also force
9225 *      the port Link Status to go down -- if register writes work --
9226 *      which should help our peers figure out that we're down.
9227 */
9228int t4_shutdown_adapter(struct adapter *adapter)
9229{
9230        int port;
9231
9232        t4_intr_disable(adapter);
9233        t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
9234        for_each_port(adapter, port) {
9235                u32 a_port_cfg = is_t4(adapter->params.chip) ?
9236                                       PORT_REG(port, XGMAC_PORT_CFG_A) :
9237                                       T5_PORT_REG(port, MAC_PORT_CFG_A);
9238
9239                t4_write_reg(adapter, a_port_cfg,
9240                             t4_read_reg(adapter, a_port_cfg)
9241                             & ~SIGNAL_DET_V(1));
9242        }
9243        t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
9244
9245        return 0;
9246}
9247
9248/**
9249 *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9250 *      @adapter: the adapter
9251 *      @qid: the Queue ID
9252 *      @qtype: the Ingress or Egress type for @qid
9253 *      @user: true if this request is for a user mode queue
9254 *      @pbar2_qoffset: BAR2 Queue Offset
9255 *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9256 *
9257 *      Returns the BAR2 SGE Queue Registers information associated with the
9258 *      indicated Absolute Queue ID.  These are passed back in return value
9259 *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9260 *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9261 *
9262 *      This may return an error which indicates that BAR2 SGE Queue
9263 *      registers aren't available.  If an error is not returned, then the
9264 *      following values are returned:
9265 *
9266 *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9267 *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9268 *
9269 *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9270 *      require the "Inferred Queue ID" ability may be used.  E.g. the
9271 *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9272 *      then these "Inferred Queue ID" register may not be used.
9273 */
9274int t4_bar2_sge_qregs(struct adapter *adapter,
9275                      unsigned int qid,
9276                      enum t4_bar2_qtype qtype,
9277                      int user,
9278                      u64 *pbar2_qoffset,
9279                      unsigned int *pbar2_qid)
9280{
9281        unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9282        u64 bar2_page_offset, bar2_qoffset;
9283        unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9284
9285        /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9286        if (!user && is_t4(adapter->params.chip))
9287                return -EINVAL;
9288
9289        /* Get our SGE Page Size parameters.
9290         */
9291        page_shift = adapter->params.sge.hps + 10;
9292        page_size = 1 << page_shift;
9293
9294        /* Get the right Queues per Page parameters for our Queue.
9295         */
9296        qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9297                     ? adapter->params.sge.eq_qpp
9298                     : adapter->params.sge.iq_qpp);
9299        qpp_mask = (1 << qpp_shift) - 1;
9300
9301        /*  Calculate the basics of the BAR2 SGE Queue register area:
9302         *  o The BAR2 page the Queue registers will be in.
9303         *  o The BAR2 Queue ID.
9304         *  o The BAR2 Queue ID Offset into the BAR2 page.
9305         */
9306        bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9307        bar2_qid = qid & qpp_mask;
9308        bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9309
9310        /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9311         * hardware will infer the Absolute Queue ID simply from the writes to
9312         * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9313         * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
9314         * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9315         * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9316         * from the BAR2 Page and BAR2 Queue ID.
9317         *
9318         * One important censequence of this is that some BAR2 SGE registers
9319         * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9320         * there.  But other registers synthesize the SGE Queue ID purely
9321         * from the writes to the registers -- the Write Combined Doorbell
9322         * Buffer is a good example.  These BAR2 SGE Registers are only
9323         * available for those BAR2 SGE Register areas where the SGE Absolute
9324         * Queue ID can be inferred from simple writes.
9325         */
9326        bar2_qoffset = bar2_page_offset;
9327        bar2_qinferred = (bar2_qid_offset < page_size);
9328        if (bar2_qinferred) {
9329                bar2_qoffset += bar2_qid_offset;
9330                bar2_qid = 0;
9331        }
9332
9333        *pbar2_qoffset = bar2_qoffset;
9334        *pbar2_qid = bar2_qid;
9335        return 0;
9336}
9337
9338/**
9339 *      t4_init_devlog_params - initialize adapter->params.devlog
9340 *      @adap: the adapter
9341 *
9342 *      Initialize various fields of the adapter's Firmware Device Log
9343 *      Parameters structure.
9344 */
9345int t4_init_devlog_params(struct adapter *adap)
9346{
9347        struct devlog_params *dparams = &adap->params.devlog;
9348        u32 pf_dparams;
9349        unsigned int devlog_meminfo;
9350        struct fw_devlog_cmd devlog_cmd;
9351        int ret;
9352
9353        /* If we're dealing with newer firmware, the Device Log Parameters
9354         * are stored in a designated register which allows us to access the
9355         * Device Log even if we can't talk to the firmware.
9356         */
9357        pf_dparams =
9358                t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9359        if (pf_dparams) {
9360                unsigned int nentries, nentries128;
9361
9362                dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
9363                dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
9364
9365                nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
9366                nentries = (nentries128 + 1) * 128;
9367                dparams->size = nentries * sizeof(struct fw_devlog_e);
9368
9369                return 0;
9370        }
9371
9372        /* Otherwise, ask the firmware for it's Device Log Parameters.
9373         */
9374        memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9375        devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
9376                                             FW_CMD_REQUEST_F | FW_CMD_READ_F);
9377        devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9378        ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9379                         &devlog_cmd);
9380        if (ret)
9381                return ret;
9382
9383        devlog_meminfo =
9384                be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9385        dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
9386        dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
9387        dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9388
9389        return 0;
9390}
9391
9392/**
9393 *      t4_init_sge_params - initialize adap->params.sge
9394 *      @adapter: the adapter
9395 *
9396 *      Initialize various fields of the adapter's SGE Parameters structure.
9397 */
9398int t4_init_sge_params(struct adapter *adapter)
9399{
9400        struct sge_params *sge_params = &adapter->params.sge;
9401        u32 hps, qpp;
9402        unsigned int s_hps, s_qpp;
9403
9404        /* Extract the SGE Page Size for our PF.
9405         */
9406        hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
9407        s_hps = (HOSTPAGESIZEPF0_S +
9408                 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
9409        sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
9410
9411        /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9412         */
9413        s_qpp = (QUEUESPERPAGEPF0_S +
9414                (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
9415        qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
9416        sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9417        qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
9418        sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9419
9420        return 0;
9421}
9422
9423/**
9424 *      t4_init_tp_params - initialize adap->params.tp
9425 *      @adap: the adapter
9426 *      @sleep_ok: if true we may sleep while awaiting command completion
9427 *
9428 *      Initialize various fields of the adapter's TP Parameters structure.
9429 */
9430int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9431{
9432        u32 param, val, v;
9433        int chan, ret;
9434
9435
9436        v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9437        adap->params.tp.tre = TIMERRESOLUTION_G(v);
9438        adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
9439
9440        /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9441        for (chan = 0; chan < NCHAN; chan++)
9442                adap->params.tp.tx_modq[chan] = chan;
9443
9444        /* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
9445         * Configuration.
9446         */
9447        param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
9448                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FILTER) |
9449                 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_FILTER_MODE_MASK));
9450
9451        /* Read current value */
9452        ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
9453                              &param, &val);
9454        if (ret == 0) {
9455                dev_info(adap->pdev_dev,
9456                         "Current filter mode/mask 0x%x:0x%x\n",
9457                         FW_PARAMS_PARAM_FILTER_MODE_G(val),
9458                         FW_PARAMS_PARAM_FILTER_MASK_G(val));
9459                adap->params.tp.vlan_pri_map =
9460                        FW_PARAMS_PARAM_FILTER_MODE_G(val);
9461                adap->params.tp.filter_mask =
9462                        FW_PARAMS_PARAM_FILTER_MASK_G(val);
9463        } else {
9464                dev_info(adap->pdev_dev,
9465                         "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");
9466
9467                /* Incase of older-fw (which doesn't expose the api
9468                 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
9469                 * the fw api) combination, fall-back to older method of reading
9470                 * the filter mode from indirect-register
9471                 */
9472                t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
9473                               TP_VLAN_PRI_MAP_A, sleep_ok);
9474
9475                /* With the older-fw and newer-driver combination we might run
9476                 * into an issue when user wants to use hash filter region but
9477                 * the filter_mask is zero, in this case filter_mask validation
9478                 * is tough. To avoid that we set the filter_mask same as filter
9479                 * mode, which will behave exactly as the older way of ignoring
9480                 * the filter mask validation.
9481                 */
9482                adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
9483        }
9484
9485        t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
9486                       TP_INGRESS_CONFIG_A, sleep_ok);
9487
9488        /* For T6, cache the adapter's compressed error vector
9489         * and passing outer header info for encapsulated packets.
9490         */
9491        if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
9492                v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9493                adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
9494        }
9495
9496        /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9497         * shift positions of several elements of the Compressed Filter Tuple
9498         * for this adapter which we need frequently ...
9499         */
9500        adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
9501        adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
9502        adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
9503        adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
9504        adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
9505        adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
9506                                                               PROTOCOL_F);
9507        adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
9508                                                                ETHERTYPE_F);
9509        adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
9510                                                               MACMATCH_F);
9511        adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
9512                                                                MPSHITTYPE_F);
9513        adap->params.tp.frag_shift = t4_filter_field_shift(adap,
9514                                                           FRAGMENTATION_F);
9515
9516        /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9517         * represents the presence of an Outer VLAN instead of a VNIC ID.
9518         */
9519        if ((adap->params.tp.ingress_config & VNIC_F) == 0)
9520                adap->params.tp.vnic_shift = -1;
9521
9522        v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9523        adap->params.tp.hash_filter_mask = v;
9524        v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9525        adap->params.tp.hash_filter_mask |= ((u64)v << 32);
9526        return 0;
9527}
9528
9529/**
9530 *      t4_filter_field_shift - calculate filter field shift
9531 *      @adap: the adapter
9532 *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9533 *
9534 *      Return the shift position of a filter field within the Compressed
9535 *      Filter Tuple.  The filter field is specified via its selection bit
9536 *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
9537 */
9538int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9539{
9540        unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9541        unsigned int sel;
9542        int field_shift;
9543
9544        if ((filter_mode & filter_sel) == 0)
9545                return -1;
9546
9547        for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9548                switch (filter_mode & sel) {
9549                case FCOE_F:
9550                        field_shift += FT_FCOE_W;
9551                        break;
9552                case PORT_F:
9553                        field_shift += FT_PORT_W;
9554                        break;
9555                case VNIC_ID_F:
9556                        field_shift += FT_VNIC_ID_W;
9557                        break;
9558                case VLAN_F:
9559                        field_shift += FT_VLAN_W;
9560                        break;
9561                case TOS_F:
9562                        field_shift += FT_TOS_W;
9563                        break;
9564                case PROTOCOL_F:
9565                        field_shift += FT_PROTOCOL_W;
9566                        break;
9567                case ETHERTYPE_F:
9568                        field_shift += FT_ETHERTYPE_W;
9569                        break;
9570                case MACMATCH_F:
9571                        field_shift += FT_MACMATCH_W;
9572                        break;
9573                case MPSHITTYPE_F:
9574                        field_shift += FT_MPSHITTYPE_W;
9575                        break;
9576                case FRAGMENTATION_F:
9577                        field_shift += FT_FRAGMENTATION_W;
9578                        break;
9579                }
9580        }
9581        return field_shift;
9582}
9583
9584int t4_init_rss_mode(struct adapter *adap, int mbox)
9585{
9586        int i, ret;
9587        struct fw_rss_vi_config_cmd rvc;
9588
9589        memset(&rvc, 0, sizeof(rvc));
9590
9591        for_each_port(adap, i) {
9592                struct port_info *p = adap2pinfo(adap, i);
9593
9594                rvc.op_to_viid =
9595                        cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
9596                                    FW_CMD_REQUEST_F | FW_CMD_READ_F |
9597                                    FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
9598                rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
9599                ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
9600                if (ret)
9601                        return ret;
9602                p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
9603        }
9604        return 0;
9605}
9606
9607/**
9608 *      t4_init_portinfo - allocate a virtual interface and initialize port_info
9609 *      @pi: the port_info
9610 *      @mbox: mailbox to use for the FW command
9611 *      @port: physical port associated with the VI
9612 *      @pf: the PF owning the VI
9613 *      @vf: the VF owning the VI
9614 *      @mac: the MAC address of the VI
9615 *
9616 *      Allocates a virtual interface for the given physical port.  If @mac is
9617 *      not %NULL it contains the MAC address of the VI as assigned by FW.
9618 *      @mac should be large enough to hold an Ethernet address.
9619 *      Returns < 0 on error.
9620 */
9621int t4_init_portinfo(struct port_info *pi, int mbox,
9622                     int port, int pf, int vf, u8 mac[])
9623{
9624        struct adapter *adapter = pi->adapter;
9625        unsigned int fw_caps = adapter->params.fw_caps_support;
9626        struct fw_port_cmd cmd;
9627        unsigned int rss_size;
9628        enum fw_port_type port_type;
9629        int mdio_addr;
9630        fw_port_cap32_t pcaps, acaps;
9631        u8 vivld = 0, vin = 0;
9632        int ret;
9633
9634        /* If we haven't yet determined whether we're talking to Firmware
9635         * which knows the new 32-bit Port Capabilities, it's time to find
9636         * out now.  This will also tell new Firmware to send us Port Status
9637         * Updates using the new 32-bit Port Capabilities version of the
9638         * Port Information message.
9639         */
9640        if (fw_caps == FW_CAPS_UNKNOWN) {
9641                u32 param, val;
9642
9643                param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
9644                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
9645                val = 1;
9646                ret = t4_set_params(adapter, mbox, pf, vf, 1, &param, &val);
9647                fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
9648                adapter->params.fw_caps_support = fw_caps;
9649        }
9650
9651        memset(&cmd, 0, sizeof(cmd));
9652        cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9653                                       FW_CMD_REQUEST_F | FW_CMD_READ_F |
9654                                       FW_PORT_CMD_PORTID_V(port));
9655        cmd.action_to_len16 = cpu_to_be32(
9656                FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9657                                     ? FW_PORT_ACTION_GET_PORT_INFO
9658                                     : FW_PORT_ACTION_GET_PORT_INFO32) |
9659                FW_LEN16(cmd));
9660        ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9661        if (ret)
9662                return ret;
9663
9664        /* Extract the various fields from the Port Information message.
9665         */
9666        if (fw_caps == FW_CAPS16) {
9667                u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9668
9669                port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9670                mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9671                             ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9672                             : -1);
9673                pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9674                acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9675        } else {
9676                u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9677
9678                port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9679                mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9680                             ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9681                             : -1);
9682                pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9683                acaps = be32_to_cpu(cmd.u.info32.acaps32);
9684        }
9685
9686        ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size,
9687                          &vivld, &vin);
9688        if (ret < 0)
9689                return ret;
9690
9691        pi->viid = ret;
9692        pi->tx_chan = port;
9693        pi->lport = port;
9694        pi->rss_size = rss_size;
9695        pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port);
9696
9697        /* If fw supports returning the VIN as part of FW_VI_CMD,
9698         * save the returned values.
9699         */
9700        if (adapter->params.viid_smt_extn_support) {
9701                pi->vivld = vivld;
9702                pi->vin = vin;
9703        } else {
9704                /* Retrieve the values from VIID */
9705                pi->vivld = FW_VIID_VIVLD_G(pi->viid);
9706                pi->vin =  FW_VIID_VIN_G(pi->viid);
9707        }
9708
9709        pi->port_type = port_type;
9710        pi->mdio_addr = mdio_addr;
9711        pi->mod_type = FW_PORT_MOD_TYPE_NA;
9712
9713        init_link_config(&pi->link_cfg, pcaps, acaps);
9714        return 0;
9715}
9716
9717int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9718{
9719        u8 addr[6];
9720        int ret, i, j = 0;
9721
9722        for_each_port(adap, i) {
9723                struct port_info *pi = adap2pinfo(adap, i);
9724
9725                while ((adap->params.portvec & (1 << j)) == 0)
9726                        j++;
9727
9728                ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9729                if (ret)
9730                        return ret;
9731
9732                memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9733                j++;
9734        }
9735        return 0;
9736}
9737
9738int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf,
9739                        u16 *mirror_viid)
9740{
9741        int ret;
9742
9743        ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, NULL, NULL,
9744                          NULL, NULL);
9745        if (ret < 0)
9746                return ret;
9747
9748        if (mirror_viid)
9749                *mirror_viid = ret;
9750
9751        return 0;
9752}
9753
9754/**
9755 *      t4_read_cimq_cfg - read CIM queue configuration
9756 *      @adap: the adapter
9757 *      @base: holds the queue base addresses in bytes
9758 *      @size: holds the queue sizes in bytes
9759 *      @thres: holds the queue full thresholds in bytes
9760 *
9761 *      Returns the current configuration of the CIM queues, starting with
9762 *      the IBQs, then the OBQs.
9763 */
9764void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9765{
9766        unsigned int i, v;
9767        int cim_num_obq = is_t4(adap->params.chip) ?
9768                                CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9769
9770        for (i = 0; i < CIM_NUM_IBQ; i++) {
9771                t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9772                             QUENUMSELECT_V(i));
9773                v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9774                /* value is in 256-byte units */
9775                *base++ = CIMQBASE_G(v) * 256;
9776                *size++ = CIMQSIZE_G(v) * 256;
9777                *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9778        }
9779        for (i = 0; i < cim_num_obq; i++) {
9780                t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9781                             QUENUMSELECT_V(i));
9782                v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9783                /* value is in 256-byte units */
9784                *base++ = CIMQBASE_G(v) * 256;
9785                *size++ = CIMQSIZE_G(v) * 256;
9786        }
9787}
9788
9789/**
9790 *      t4_read_cim_ibq - read the contents of a CIM inbound queue
9791 *      @adap: the adapter
9792 *      @qid: the queue index
9793 *      @data: where to store the queue contents
9794 *      @n: capacity of @data in 32-bit words
9795 *
9796 *      Reads the contents of the selected CIM queue starting at address 0 up
9797 *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9798 *      error and the number of 32-bit words actually read on success.
9799 */
9800int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9801{
9802        int i, err, attempts;
9803        unsigned int addr;
9804        const unsigned int nwords = CIM_IBQ_SIZE * 4;
9805
9806        if (qid > 5 || (n & 3))
9807                return -EINVAL;
9808
9809        addr = qid * nwords;
9810        if (n > nwords)
9811                n = nwords;
9812
9813        /* It might take 3-10ms before the IBQ debug read access is allowed.
9814         * Wait for 1 Sec with a delay of 1 usec.
9815         */
9816        attempts = 1000000;
9817
9818        for (i = 0; i < n; i++, addr++) {
9819                t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9820                             IBQDBGEN_F);
9821                err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9822                                      attempts, 1);
9823                if (err)
9824                        return err;
9825                *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9826        }
9827        t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9828        return i;
9829}
9830
9831/**
9832 *      t4_read_cim_obq - read the contents of a CIM outbound queue
9833 *      @adap: the adapter
9834 *      @qid: the queue index
9835 *      @data: where to store the queue contents
9836 *      @n: capacity of @data in 32-bit words
9837 *
9838 *      Reads the contents of the selected CIM queue starting at address 0 up
9839 *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9840 *      error and the number of 32-bit words actually read on success.
9841 */
9842int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9843{
9844        int i, err;
9845        unsigned int addr, v, nwords;
9846        int cim_num_obq = is_t4(adap->params.chip) ?
9847                                CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9848
9849        if ((qid > (cim_num_obq - 1)) || (n & 3))
9850                return -EINVAL;
9851
9852        t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9853                     QUENUMSELECT_V(qid));
9854        v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9855
9856        addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
9857        nwords = CIMQSIZE_G(v) * 64;  /* same */
9858        if (n > nwords)
9859                n = nwords;
9860
9861        for (i = 0; i < n; i++, addr++) {
9862                t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9863                             OBQDBGEN_F);
9864                err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9865                                      2, 1);
9866                if (err)
9867                        return err;
9868                *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9869        }
9870        t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9871        return i;
9872}
9873
9874/**
9875 *      t4_cim_read - read a block from CIM internal address space
9876 *      @adap: the adapter
9877 *      @addr: the start address within the CIM address space
9878 *      @n: number of words to read
9879 *      @valp: where to store the result
9880 *
9881 *      Reads a block of 4-byte words from the CIM intenal address space.
9882 */
9883int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9884                unsigned int *valp)
9885{
9886        int ret = 0;
9887
9888        if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9889                return -EBUSY;
9890
9891        for ( ; !ret && n--; addr += 4) {
9892                t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9893                ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9894                                      0, 5, 2);
9895                if (!ret)
9896                        *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9897        }
9898        return ret;
9899}
9900
9901/**
9902 *      t4_cim_write - write a block into CIM internal address space
9903 *      @adap: the adapter
9904 *      @addr: the start address within the CIM address space
9905 *      @n: number of words to write
9906 *      @valp: set of values to write
9907 *
9908 *      Writes a block of 4-byte words into the CIM intenal address space.
9909 */
9910int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9911                 const unsigned int *valp)
9912{
9913        int ret = 0;
9914
9915        if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9916                return -EBUSY;
9917
9918        for ( ; !ret && n--; addr += 4) {
9919                t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9920                t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9921                ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9922                                      0, 5, 2);
9923        }
9924        return ret;
9925}
9926
9927static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9928                         unsigned int val)
9929{
9930        return t4_cim_write(adap, addr, 1, &val);
9931}
9932
9933/**
9934 *      t4_cim_read_la - read CIM LA capture buffer
9935 *      @adap: the adapter
9936 *      @la_buf: where to store the LA data
9937 *      @wrptr: the HW write pointer within the capture buffer
9938 *
9939 *      Reads the contents of the CIM LA buffer with the most recent entry at
9940 *      the end of the returned data and with the entry at @wrptr first.
9941 *      We try to leave the LA in the running state we find it in.
9942 */
9943int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9944{
9945        int i, ret;
9946        unsigned int cfg, val, idx;
9947
9948        ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9949        if (ret)
9950                return ret;
9951
9952        if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
9953                ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9954                if (ret)
9955                        return ret;
9956        }
9957
9958        ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9959        if (ret)
9960                goto restart;
9961
9962        idx = UPDBGLAWRPTR_G(val);
9963        if (wrptr)
9964                *wrptr = idx;
9965
9966        for (i = 0; i < adap->params.cim_la_size; i++) {
9967                ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9968                                    UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9969                if (ret)
9970                        break;
9971                ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9972                if (ret)
9973                        break;
9974                if (val & UPDBGLARDEN_F) {
9975                        ret = -ETIMEDOUT;
9976                        break;
9977                }
9978                ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9979                if (ret)
9980                        break;
9981
9982                /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9983                 * identify the 32-bit portion of the full 312-bit data
9984                 */
9985                if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9986                        idx = (idx & 0xff0) + 0x10;
9987                else
9988                        idx++;
9989                /* address can't exceed 0xfff */
9990                idx &= UPDBGLARDPTR_M;
9991        }
9992restart:
9993        if (cfg & UPDBGLAEN_F) {
9994                int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9995                                      cfg & ~UPDBGLARDEN_F);
9996                if (!ret)
9997                        ret = r;
9998        }
9999        return ret;
10000}

10001
10002/**
10003 *      t4_tp_read_la - read TP LA capture buffer
10004 *      @adap: the adapter
10005 *      @la_buf: where to store the LA data
10006 *      @wrptr: the HW write pointer within the capture buffer
10007 *
10008 *      Reads the contents of the TP LA buffer with the most recent entry at
10009 *      the end of the returned data and with the entry at @wrptr first.
10010 *      We leave the LA in the running state we find it in.
10011 */
10012void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
10013{
10014        bool last_incomplete;
10015        unsigned int i, cfg, val, idx;
10016
10017        cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
10018        if (cfg & DBGLAENABLE_F)                        /* freeze LA */
10019                t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10020                             adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
10021
10022        val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
10023        idx = DBGLAWPTR_G(val);
10024        last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
10025        if (last_incomplete)
10026                idx = (idx + 1) & DBGLARPTR_M;
10027        if (wrptr)
10028                *wrptr = idx;
10029
10030        val &= 0xffff;
10031        val &= ~DBGLARPTR_V(DBGLARPTR_M);
10032        val |= adap->params.tp.la_mask;
10033
10034        for (i = 0; i < TPLA_SIZE; i++) {
10035                t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
10036                la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
10037                idx = (idx + 1) & DBGLARPTR_M;
10038        }
10039
10040        /* Wipe out last entry if it isn't valid */
10041        if (last_incomplete)
10042                la_buf[TPLA_SIZE - 1] = ~0ULL;
10043
10044        if (cfg & DBGLAENABLE_F)                    /* restore running state */
10045                t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10046                             cfg | adap->params.tp.la_mask);
10047}
10048
10049/* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10050 * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
10051 * state for more than the Warning Threshold then we'll issue a warning about
10052 * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
10053 * appears to be hung every Warning Repeat second till the situation clears.
10054 * If the situation clears, we'll note that as well.
10055 */
10056#define SGE_IDMA_WARN_THRESH 1
10057#define SGE_IDMA_WARN_REPEAT 300
10058
10059/**
10060 *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10061 *      @adapter: the adapter
10062 *      @idma: the adapter IDMA Monitor state
10063 *
10064 *      Initialize the state of an SGE Ingress DMA Monitor.
10065 */
10066void t4_idma_monitor_init(struct adapter *adapter,
10067                          struct sge_idma_monitor_state *idma)
10068{
10069        /* Initialize the state variables for detecting an SGE Ingress DMA
10070         * hang.  The SGE has internal counters which count up on each clock
10071         * tick whenever the SGE finds its Ingress DMA State Engines in the
10072         * same state they were on the previous clock tick.  The clock used is
10073         * the Core Clock so we have a limit on the maximum "time" they can
10074         * record; typically a very small number of seconds.  For instance,
10075         * with a 600MHz Core Clock, we can only count up to a bit more than
10076         * 7s.  So we'll synthesize a larger counter in order to not run the
10077         * risk of having the "timers" overflow and give us the flexibility to
10078         * maintain a Hung SGE State Machine of our own which operates across
10079         * a longer time frame.
10080         */
10081        idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
10082        idma->idma_stalled[0] = 0;
10083        idma->idma_stalled[1] = 0;
10084}
10085
10086/**
10087 *      t4_idma_monitor - monitor SGE Ingress DMA state
10088 *      @adapter: the adapter
10089 *      @idma: the adapter IDMA Monitor state
10090 *      @hz: number of ticks/second
10091 *      @ticks: number of ticks since the last IDMA Monitor call
10092 */
10093void t4_idma_monitor(struct adapter *adapter,
10094                     struct sge_idma_monitor_state *idma,
10095                     int hz, int ticks)
10096{
10097        int i, idma_same_state_cnt[2];
10098
10099         /* Read the SGE Debug Ingress DMA Same State Count registers.  These
10100          * are counters inside the SGE which count up on each clock when the
10101          * SGE finds its Ingress DMA State Engines in the same states they
10102          * were in the previous clock.  The counters will peg out at
10103          * 0xffffffff without wrapping around so once they pass the 1s
10104          * threshold they'll stay above that till the IDMA state changes.
10105          */
10106        t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
10107        idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
10108        idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10109
10110        for (i = 0; i < 2; i++) {
10111                u32 debug0, debug11;
10112
10113                /* If the Ingress DMA Same State Counter ("timer") is less
10114                 * than 1s, then we can reset our synthesized Stall Timer and
10115                 * continue.  If we have previously emitted warnings about a
10116                 * potential stalled Ingress Queue, issue a note indicating
10117                 * that the Ingress Queue has resumed forward progress.
10118                 */
10119                if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
10120                        if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
10121                                dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
10122                                         "resumed after %d seconds\n",
10123                                         i, idma->idma_qid[i],
10124                                         idma->idma_stalled[i] / hz);
10125                        idma->idma_stalled[i] = 0;
10126                        continue;
10127                }
10128
10129                /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10130                 * domain.  The first time we get here it'll be because we
10131                 * passed the 1s Threshold; each additional time it'll be
10132                 * because the RX Timer Callback is being fired on its regular
10133                 * schedule.
10134                 *
10135                 * If the stall is below our Potential Hung Ingress Queue
10136                 * Warning Threshold, continue.
10137                 */
10138                if (idma->idma_stalled[i] == 0) {
10139                        idma->idma_stalled[i] = hz;
10140                        idma->idma_warn[i] = 0;
10141                } else {
10142                        idma->idma_stalled[i] += ticks;
10143                        idma->idma_warn[i] -= ticks;
10144                }
10145
10146                if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
10147                        continue;
10148
10149                /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10150                 */
10151                if (idma->idma_warn[i] > 0)
10152                        continue;
10153                idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
10154
10155                /* Read and save the SGE IDMA State and Queue ID information.
10156                 * We do this every time in case it changes across time ...
10157                 * can't be too careful ...
10158                 */
10159                t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
10160                debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10161                idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
10162
10163                t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
10164                debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10165                idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
10166
10167                dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
10168                         "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10169                         i, idma->idma_qid[i], idma->idma_state[i],
10170                         idma->idma_stalled[i] / hz,
10171                         debug0, debug11);
10172                t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
10173        }
10174}
10175
10176/**
10177 *      t4_load_cfg - download config file
10178 *      @adap: the adapter
10179 *      @cfg_data: the cfg text file to write
10180 *      @size: text file size
10181 *
10182 *      Write the supplied config text file to the card's serial flash.
10183 */
10184int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10185{
10186        int ret, i, n, cfg_addr;
10187        unsigned int addr;
10188        unsigned int flash_cfg_start_sec;
10189        unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10190
10191        cfg_addr = t4_flash_cfg_addr(adap);
10192        if (cfg_addr < 0)
10193                return cfg_addr;
10194
10195        addr = cfg_addr;
10196        flash_cfg_start_sec = addr / SF_SEC_SIZE;
10197
10198        if (size > FLASH_CFG_MAX_SIZE) {
10199                dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
10200                        FLASH_CFG_MAX_SIZE);
10201                return -EFBIG;
10202        }
10203
10204        i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,    /* # of sectors spanned */
10205                         sf_sec_size);
10206        ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10207                                     flash_cfg_start_sec + i - 1);
10208        /* If size == 0 then we're simply erasing the FLASH sectors associated
10209         * with the on-adapter Firmware Configuration File.
10210         */
10211        if (ret || size == 0)
10212                goto out;
10213
10214        /* this will write to the flash up to SF_PAGE_SIZE at a time */
10215        for (i = 0; i < size; i += SF_PAGE_SIZE) {
10216                if ((size - i) <  SF_PAGE_SIZE)
10217                        n = size - i;
10218                else
10219                        n = SF_PAGE_SIZE;
10220                ret = t4_write_flash(adap, addr, n, cfg_data, true);
10221                if (ret)
10222                        goto out;
10223
10224                addr += SF_PAGE_SIZE;
10225                cfg_data += SF_PAGE_SIZE;
10226        }
10227
10228out:
10229        if (ret)
10230                dev_err(adap->pdev_dev, "config file %s failed %d\n",
10231                        (size == 0 ? "clear" : "download"), ret);
10232        return ret;
10233}
10234
10235/**
10236 *      t4_set_vf_mac_acl - Set MAC address for the specified VF
10237 *      @adapter: The adapter
10238 *      @vf: one of the VFs instantiated by the specified PF
10239 *      @naddr: the number of MAC addresses
10240 *      @addr: the MAC address(es) to be set to the specified VF
10241 */
10242int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
10243                      unsigned int naddr, u8 *addr)
10244{
10245        struct fw_acl_mac_cmd cmd;
10246
10247        memset(&cmd, 0, sizeof(cmd));
10248        cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
10249                                    FW_CMD_REQUEST_F |
10250                                    FW_CMD_WRITE_F |
10251                                    FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
10252                                    FW_ACL_MAC_CMD_VFN_V(vf));
10253
10254        /* Note: Do not enable the ACL */
10255        cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
10256        cmd.nmac = naddr;
10257
10258        switch (adapter->pf) {
10259        case 3:
10260                memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
10261                break;
10262        case 2:
10263                memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
10264                break;
10265        case 1:
10266                memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
10267                break;
10268        case 0:
10269                memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
10270                break;
10271        }
10272
10273        return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
10274}
10275
10276/**
10277 * t4_read_pace_tbl - read the pace table
10278 * @adap: the adapter
10279 * @pace_vals: holds the returned values
10280 *
10281 * Returns the values of TP's pace table in microseconds.
10282 */
10283void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
10284{
10285        unsigned int i, v;
10286
10287        for (i = 0; i < NTX_SCHED; i++) {
10288                t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
10289                v = t4_read_reg(adap, TP_PACE_TABLE_A);
10290                pace_vals[i] = dack_ticks_to_usec(adap, v);
10291        }
10292}
10293
10294/**
10295 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10296 * @adap: the adapter
10297 * @sched: the scheduler index
10298 * @kbps: the byte rate in Kbps
10299 * @ipg: the interpacket delay in tenths of nanoseconds
10300 * @sleep_ok: if true we may sleep while awaiting command completion
10301 *
10302 * Return the current configuration of a HW Tx scheduler.
10303 */
10304void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
10305                     unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
10306{
10307        unsigned int v, addr, bpt, cpt;
10308
10309        if (kbps) {
10310                addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
10311                t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10312                if (sched & 1)
10313                        v >>= 16;
10314                bpt = (v >> 8) & 0xff;
10315                cpt = v & 0xff;
10316                if (!cpt) {
10317                        *kbps = 0;      /* scheduler disabled */
10318                } else {
10319                        v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10320                        *kbps = (v * bpt) / 125;
10321                }
10322        }
10323        if (ipg) {
10324                addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
10325                t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10326                if (sched & 1)
10327                        v >>= 16;
10328                v &= 0xffff;
10329                *ipg = (10000 * v) / core_ticks_per_usec(adap);
10330        }
10331}
10332
10333/* t4_sge_ctxt_rd - read an SGE context through FW
10334 * @adap: the adapter
10335 * @mbox: mailbox to use for the FW command
10336 * @cid: the context id
10337 * @ctype: the context type
10338 * @data: where to store the context data
10339 *
10340 * Issues a FW command through the given mailbox to read an SGE context.
10341 */
10342int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10343                   enum ctxt_type ctype, u32 *data)
10344{
10345        struct fw_ldst_cmd c;
10346        int ret;
10347
10348        if (ctype == CTXT_FLM)
10349                ret = FW_LDST_ADDRSPC_SGE_FLMC;
10350        else
10351                ret = FW_LDST_ADDRSPC_SGE_CONMC;
10352
10353        memset(&c, 0, sizeof(c));
10354        c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10355                                        FW_CMD_REQUEST_F | FW_CMD_READ_F |
10356                                        FW_LDST_CMD_ADDRSPACE_V(ret));
10357        c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10358        c.u.idctxt.physid = cpu_to_be32(cid);
10359
10360        ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10361        if (ret == 0) {
10362                data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10363                data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10364                data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10365                data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10366                data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10367                data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10368        }
10369        return ret;
10370}
10371
10372/**
10373 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10374 * @adap: the adapter
10375 * @cid: the context id
10376 * @ctype: the context type
10377 * @data: where to store the context data
10378 *
10379 * Reads an SGE context directly, bypassing FW.  This is only for
10380 * debugging when FW is unavailable.
10381 */
10382int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
10383                      enum ctxt_type ctype, u32 *data)
10384{
10385        int i, ret;
10386
10387        t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
10388        ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
10389        if (!ret)
10390                for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
10391                        *data++ = t4_read_reg(adap, i);
10392        return ret;
10393}
10394
10395int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
10396                    u8 rateunit, u8 ratemode, u8 channel, u8 class,
10397                    u32 minrate, u32 maxrate, u16 weight, u16 pktsize,
10398                    u16 burstsize)
10399{
10400        struct fw_sched_cmd cmd;
10401
10402        memset(&cmd, 0, sizeof(cmd));
10403        cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
10404                                      FW_CMD_REQUEST_F |
10405                                      FW_CMD_WRITE_F);
10406        cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10407
10408        cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10409        cmd.u.params.type = type;
10410        cmd.u.params.level = level;
10411        cmd.u.params.mode = mode;
10412        cmd.u.params.ch = channel;
10413        cmd.u.params.cl = class;
10414        cmd.u.params.unit = rateunit;
10415        cmd.u.params.rate = ratemode;
10416        cmd.u.params.min = cpu_to_be32(minrate);
10417        cmd.u.params.max = cpu_to_be32(maxrate);
10418        cmd.u.params.weight = cpu_to_be16(weight);
10419        cmd.u.params.pktsize = cpu_to_be16(pktsize);
10420        cmd.u.params.burstsize = cpu_to_be16(burstsize);
10421
10422        return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
10423                               NULL, 1);
10424}
10425
10426/**
10427 *      t4_i2c_rd - read I2C data from adapter
10428 *      @adap: the adapter
10429 *      @mbox: mailbox to use for the FW command
10430 *      @port: Port number if per-port device; <0 if not
10431 *      @devid: per-port device ID or absolute device ID
10432 *      @offset: byte offset into device I2C space
10433 *      @len: byte length of I2C space data
10434 *      @buf: buffer in which to return I2C data
10435 *
10436 *      Reads the I2C data from the indicated device and location.
10437 */
10438int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
10439              unsigned int devid, unsigned int offset,
10440              unsigned int len, u8 *buf)
10441{
10442        struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10443        unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10444        int ret = 0;
10445
10446        if (len > I2C_PAGE_SIZE)
10447                return -EINVAL;
10448
10449        /* Dont allow reads that spans multiple pages */
10450        if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10451                return -EINVAL;
10452
10453        memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10454        ldst_cmd.op_to_addrspace =
10455                cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10456                            FW_CMD_REQUEST_F |
10457                            FW_CMD_READ_F |
10458                            FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C));
10459        ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10460        ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10461        ldst_cmd.u.i2c.did = devid;
10462
10463        while (len > 0) {
10464                unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
10465
10466                ldst_cmd.u.i2c.boffset = offset;
10467                ldst_cmd.u.i2c.blen = i2c_len;
10468
10469                ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10470                                 &ldst_rpl);
10471                if (ret)
10472                        break;
10473
10474                memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
10475                offset += i2c_len;
10476                buf += i2c_len;
10477                len -= i2c_len;
10478        }
10479
10480        return ret;
10481}
10482
10483/**
10484 *      t4_set_vlan_acl - Set a VLAN id for the specified VF
10485 *      @adap: the adapter
10486 *      @mbox: mailbox to use for the FW command
10487 *      @vf: one of the VFs instantiated by the specified PF
10488 *      @vlan: The vlanid to be set
10489 */
10490int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
10491                    u16 vlan)
10492{
10493        struct fw_acl_vlan_cmd vlan_cmd;
10494        unsigned int enable;
10495
10496        enable = (vlan ? FW_ACL_VLAN_CMD_EN_F : 0);
10497        memset(&vlan_cmd, 0, sizeof(vlan_cmd));
10498        vlan_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
10499                                         FW_CMD_REQUEST_F |
10500                                         FW_CMD_WRITE_F |
10501                                         FW_CMD_EXEC_F |
10502                                         FW_ACL_VLAN_CMD_PFN_V(adap->pf) |
10503                                         FW_ACL_VLAN_CMD_VFN_V(vf));
10504        vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
10505        /* Drop all packets that donot match vlan id */
10506        vlan_cmd.dropnovlan_fm = (enable
10507                                  ? (FW_ACL_VLAN_CMD_DROPNOVLAN_F |
10508                                     FW_ACL_VLAN_CMD_FM_F) : 0);
10509        if (enable != 0) {
10510                vlan_cmd.nvlan = 1;
10511                vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
10512        }
10513
10514        return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
10515}
10516
10517/**
10518 *      modify_device_id - Modifies the device ID of the Boot BIOS image
10519 *      @device_id: the device ID to write.
10520 *      @boot_data: the boot image to modify.
10521 *
10522 *      Write the supplied device ID to the boot BIOS image.
10523 */
10524static void modify_device_id(int device_id, u8 *boot_data)
10525{
10526        struct cxgb4_pcir_data *pcir_header;
10527        struct legacy_pci_rom_hdr *header;
10528        u8 *cur_header = boot_data;
10529        u16 pcir_offset;
10530
10531         /* Loop through all chained images and change the device ID's */
10532        do {
10533                header = (struct legacy_pci_rom_hdr *)cur_header;
10534                pcir_offset = le16_to_cpu(header->pcir_offset);
10535                pcir_header = (struct cxgb4_pcir_data *)(cur_header +
10536                              pcir_offset);
10537
10538                /**
10539                 * Only modify the Device ID if code type is Legacy or HP.
10540                 * 0x00: Okay to modify
10541                 * 0x01: FCODE. Do not modify
10542                 * 0x03: Okay to modify
10543                 * 0x04-0xFF: Do not modify
10544                 */
10545                if (pcir_header->code_type == CXGB4_HDR_CODE1) {
10546                        u8 csum = 0;
10547                        int i;
10548
10549                        /**
10550                         * Modify Device ID to match current adatper
10551                         */
10552                        pcir_header->device_id = cpu_to_le16(device_id);
10553
10554                        /**
10555                         * Set checksum temporarily to 0.
10556                         * We will recalculate it later.
10557                         */
10558                        header->cksum = 0x0;
10559
10560                        /**
10561                         * Calculate and update checksum
10562                         */
10563                        for (i = 0; i < (header->size512 * 512); i++)
10564                                csum += cur_header[i];
10565
10566                        /**
10567                         * Invert summed value to create the checksum
10568                         * Writing new checksum value directly to the boot data
10569                         */
10570                        cur_header[7] = -csum;
10571
10572                } else if (pcir_header->code_type == CXGB4_HDR_CODE2) {
10573                        /**
10574                         * Modify Device ID to match current adatper
10575                         */
10576                        pcir_header->device_id = cpu_to_le16(device_id);
10577                }
10578
10579                /**
10580                 * Move header pointer up to the next image in the ROM.
10581                 */
10582                cur_header += header->size512 * 512;
10583        } while (!(pcir_header->indicator & CXGB4_HDR_INDI));
10584}
10585
10586/**
10587 *      t4_load_boot - download boot flash
10588 *      @adap: the adapter
10589 *      @boot_data: the boot image to write
10590 *      @boot_addr: offset in flash to write boot_data
10591 *      @size: image size
10592 *
10593 *      Write the supplied boot image to the card's serial flash.
10594 *      The boot image has the following sections: a 28-byte header and the
10595 *      boot image.
10596 */
10597int t4_load_boot(struct adapter *adap, u8 *boot_data,
10598                 unsigned int boot_addr, unsigned int size)
10599{
10600        unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10601        unsigned int boot_sector = (boot_addr * 1024);
10602        struct cxgb4_pci_exp_rom_header *header;
10603        struct cxgb4_pcir_data *pcir_header;
10604        int pcir_offset;
10605        unsigned int i;
10606        u16 device_id;
10607        int ret, addr;
10608
10609        /**
10610         * Make sure the boot image does not encroach on the firmware region
10611         */
10612        if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
10613                dev_err(adap->pdev_dev, "boot image encroaching on firmware region\n");
10614                return -EFBIG;
10615        }
10616
10617        /* Get boot header */
10618        header = (struct cxgb4_pci_exp_rom_header *)boot_data;
10619        pcir_offset = le16_to_cpu(header->pcir_offset);
10620        /* PCIR Data Structure */
10621        pcir_header = (struct cxgb4_pcir_data *)&boot_data[pcir_offset];
10622
10623        /**
10624         * Perform some primitive sanity testing to avoid accidentally
10625         * writing garbage over the boot sectors.  We ought to check for
10626         * more but it's not worth it for now ...
10627         */
10628        if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
10629                dev_err(adap->pdev_dev, "boot image too small/large\n");
10630                return -EFBIG;
10631        }
10632
10633        if (le16_to_cpu(header->signature) != BOOT_SIGNATURE) {
10634                dev_err(adap->pdev_dev, "Boot image missing signature\n");
10635                return -EINVAL;
10636        }
10637
10638        /* Check PCI header signature */
10639        if (le32_to_cpu(pcir_header->signature) != PCIR_SIGNATURE) {
10640                dev_err(adap->pdev_dev, "PCI header missing signature\n");
10641                return -EINVAL;
10642        }
10643
10644        /* Check Vendor ID matches Chelsio ID*/
10645        if (le16_to_cpu(pcir_header->vendor_id) != PCI_VENDOR_ID_CHELSIO) {
10646                dev_err(adap->pdev_dev, "Vendor ID missing signature\n");
10647                return -EINVAL;
10648        }
10649
10650        /**
10651         * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10652         * and Boot configuration data sections. These 3 boot sections span
10653         * sectors 0 to 7 in flash and live right before the FW image location.
10654         */
10655        i = DIV_ROUND_UP(size ? size : FLASH_FW_START,  sf_sec_size);
10656        ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10657                                     (boot_sector >> 16) + i - 1);
10658
10659        /**
10660         * If size == 0 then we're simply erasing the FLASH sectors associated
10661         * with the on-adapter option ROM file
10662         */
10663        if (ret || size == 0)
10664                goto out;
10665        /* Retrieve adapter's device ID */
10666        pci_read_config_word(adap->pdev, PCI_DEVICE_ID, &device_id);
10667       /* Want to deal with PF 0 so I strip off PF 4 indicator */
10668        device_id = device_id & 0xf0ff;
10669
10670         /* Check PCIE Device ID */
10671        if (le16_to_cpu(pcir_header->device_id) != device_id) {
10672                /**
10673                 * Change the device ID in the Boot BIOS image to match
10674                 * the Device ID of the current adapter.
10675                 */
10676                modify_device_id(device_id, boot_data);
10677        }
10678
10679        /**
10680         * Skip over the first SF_PAGE_SIZE worth of data and write it after
10681         * we finish copying the rest of the boot image. This will ensure
10682         * that the BIOS boot header will only be written if the boot image
10683         * was written in full.
10684         */
10685        addr = boot_sector;
10686        for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
10687                addr += SF_PAGE_SIZE;
10688                boot_data += SF_PAGE_SIZE;
10689                ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data,
10690                                     false);
10691                if (ret)
10692                        goto out;
10693        }
10694
10695        ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10696                             (const u8 *)header, false);
10697
10698out:
10699        if (ret)
10700                dev_err(adap->pdev_dev, "boot image load failed, error %d\n",
10701                        ret);
10702        return ret;
10703}
10704
10705/**
10706 *      t4_flash_bootcfg_addr - return the address of the flash
10707 *      optionrom configuration
10708 *      @adapter: the adapter
10709 *
10710 *      Return the address within the flash where the OptionROM Configuration
10711 *      is stored, or an error if the device FLASH is too small to contain
10712 *      a OptionROM Configuration.
10713 */
10714static int t4_flash_bootcfg_addr(struct adapter *adapter)
10715{
10716        /**
10717         * If the device FLASH isn't large enough to hold a Firmware
10718         * Configuration File, return an error.
10719         */
10720        if (adapter->params.sf_size <
10721            FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
10722                return -ENOSPC;
10723
10724        return FLASH_BOOTCFG_START;
10725}
10726
10727int t4_load_bootcfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10728{
10729        unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10730        struct cxgb4_bootcfg_data *header;
10731        unsigned int flash_cfg_start_sec;
10732        unsigned int addr, npad;
10733        int ret, i, n, cfg_addr;
10734
10735        cfg_addr = t4_flash_bootcfg_addr(adap);
10736        if (cfg_addr < 0)
10737                return cfg_addr;
10738
10739        addr = cfg_addr;
10740        flash_cfg_start_sec = addr / SF_SEC_SIZE;
10741
10742        if (size > FLASH_BOOTCFG_MAX_SIZE) {
10743                dev_err(adap->pdev_dev, "bootcfg file too large, max is %u bytes\n",
10744                        FLASH_BOOTCFG_MAX_SIZE);
10745                return -EFBIG;
10746        }
10747
10748        header = (struct cxgb4_bootcfg_data *)cfg_data;
10749        if (le16_to_cpu(header->signature) != BOOT_CFG_SIG) {
10750                dev_err(adap->pdev_dev, "Wrong bootcfg signature\n");
10751                ret = -EINVAL;
10752                goto out;
10753        }
10754
10755        i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,
10756                         sf_sec_size);
10757        ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10758                                     flash_cfg_start_sec + i - 1);
10759
10760        /**
10761         * If size == 0 then we're simply erasing the FLASH sectors associated
10762         * with the on-adapter OptionROM Configuration File.
10763         */
10764        if (ret || size == 0)
10765                goto out;
10766
10767        /* this will write to the flash up to SF_PAGE_SIZE at a time */
10768        for (i = 0; i < size; i += SF_PAGE_SIZE) {
10769                n = min_t(u32, size - i, SF_PAGE_SIZE);
10770
10771                ret = t4_write_flash(adap, addr, n, cfg_data, false);
10772                if (ret)
10773                        goto out;
10774
10775                addr += SF_PAGE_SIZE;
10776                cfg_data += SF_PAGE_SIZE;
10777        }
10778
10779        npad = ((size + 4 - 1) & ~3) - size;
10780        for (i = 0; i < npad; i++) {
10781                u8 data = 0;
10782
10783                ret = t4_write_flash(adap, cfg_addr + size + i, 1, &data,
10784                                     false);
10785                if (ret)
10786                        goto out;
10787        }
10788
10789out:
10790        if (ret)
10791                dev_err(adap->pdev_dev, "boot config data %s failed %d\n",
10792                        (size == 0 ? "clear" : "download"), ret);
10793        return ret;
10794}
10795