1
2
3
4#include <asm/unaligned.h>
5#include <linux/mdio.h>
6#include <linux/module.h>
7#include <linux/fsl/enetc_mdio.h>
8#include <linux/of_platform.h>
9#include <linux/of_mdio.h>
10#include <linux/of_net.h>
11#include "enetc_ierb.h"
12#include "enetc_pf.h"
13
14#define ENETC_DRV_NAME_STR "ENETC PF driver"
15
16static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
17{
18 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
19 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
20
21 put_unaligned_le32(upper, addr);
22 put_unaligned_le16(lower, addr + 4);
23}
24
25static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
26 const u8 *addr)
27{
28 u32 upper = get_unaligned_le32(addr);
29 u16 lower = get_unaligned_le16(addr + 4);
30
31 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
32 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
33}
34
35static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr)
36{
37 struct enetc_ndev_priv *priv = netdev_priv(ndev);
38 struct sockaddr *saddr = addr;
39
40 if (!is_valid_ether_addr(saddr->sa_data))
41 return -EADDRNOTAVAIL;
42
43 memcpy(ndev->dev_addr, saddr->sa_data, ndev->addr_len);
44 enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data);
45
46 return 0;
47}
48
49static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
50{
51 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
52
53 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
54 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
55}
56
57static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
58{
59 pf->vlan_promisc_simap |= BIT(si_idx);
60 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
61}
62
63static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
64{
65 pf->vlan_promisc_simap &= ~BIT(si_idx);
66 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
67}
68
69static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
70{
71 u32 val = 0;
72
73 if (vlan)
74 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
75
76 enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
77}
78
79static int enetc_mac_addr_hash_idx(const u8 *addr)
80{
81 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16;
82 u64 mask = 0;
83 int res = 0;
84 int i;
85
86 for (i = 0; i < 8; i++)
87 mask |= BIT_ULL(i * 6);
88
89 for (i = 0; i < 6; i++)
90 res |= (hweight64(fold & (mask << i)) & 0x1) << i;
91
92 return res;
93}
94
95static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter)
96{
97 filter->mac_addr_cnt = 0;
98
99 bitmap_zero(filter->mac_hash_table,
100 ENETC_MADDR_HASH_TBL_SZ);
101}
102
103static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
104 const unsigned char *addr)
105{
106
107 ether_addr_copy(filter->mac_addr, addr);
108 filter->mac_addr_cnt++;
109}
110
111static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter,
112 const unsigned char *addr)
113{
114 int idx = enetc_mac_addr_hash_idx(addr);
115
116
117 __set_bit(idx, filter->mac_hash_table);
118 filter->mac_addr_cnt++;
119}
120
121static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
122{
123 bool err = si->errata & ENETC_ERR_UCMCSWP;
124
125 if (type == UC) {
126 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
127 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
128 } else {
129 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
130 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
131 }
132}
133
134static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
135 unsigned long hash)
136{
137 bool err = si->errata & ENETC_ERR_UCMCSWP;
138
139 if (type == UC) {
140 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),
141 lower_32_bits(hash));
142 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),
143 upper_32_bits(hash));
144 } else {
145 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),
146 lower_32_bits(hash));
147 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),
148 upper_32_bits(hash));
149 }
150}
151
152static void enetc_sync_mac_filters(struct enetc_pf *pf)
153{
154 struct enetc_mac_filter *f = pf->mac_filter;
155 struct enetc_si *si = pf->si;
156 int i, pos;
157
158 pos = EMETC_MAC_ADDR_FILT_RES;
159
160 for (i = 0; i < MADDR_TYPE; i++, f++) {
161 bool em = (f->mac_addr_cnt == 1) && (i == UC);
162 bool clear = !f->mac_addr_cnt;
163
164 if (clear) {
165 if (i == UC)
166 enetc_clear_mac_flt_entry(si, pos);
167
168 enetc_clear_mac_ht_flt(si, 0, i);
169 continue;
170 }
171
172
173 if (em) {
174 int err;
175
176 enetc_clear_mac_ht_flt(si, 0, UC);
177
178 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
179 BIT(0));
180 if (!err)
181 continue;
182
183
184 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
185 err);
186 }
187
188
189 if (i == UC)
190 enetc_clear_mac_flt_entry(si, pos);
191
192 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);
193 }
194}
195
196static void enetc_pf_set_rx_mode(struct net_device *ndev)
197{
198 struct enetc_ndev_priv *priv = netdev_priv(ndev);
199 struct enetc_pf *pf = enetc_si_priv(priv->si);
200 struct enetc_hw *hw = &priv->si->hw;
201 bool uprom = false, mprom = false;
202 struct enetc_mac_filter *filter;
203 struct netdev_hw_addr *ha;
204 u32 psipmr = 0;
205 bool em;
206
207 if (ndev->flags & IFF_PROMISC) {
208
209 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
210 uprom = true;
211 mprom = true;
212 } else if (ndev->flags & IFF_ALLMULTI) {
213
214 psipmr = ENETC_PSIPMR_SET_MP(0);
215 mprom = true;
216 }
217
218
219 if (!uprom) {
220
221 filter = &pf->mac_filter[UC];
222 enetc_reset_mac_addr_filter(filter);
223
224 em = (netdev_uc_count(ndev) == 1);
225 netdev_for_each_uc_addr(ha, ndev) {
226 if (em) {
227 enetc_add_mac_addr_em_filter(filter, ha->addr);
228 break;
229 }
230
231 enetc_add_mac_addr_ht_filter(filter, ha->addr);
232 }
233 }
234
235 if (!mprom) {
236
237 filter = &pf->mac_filter[MC];
238 enetc_reset_mac_addr_filter(filter);
239
240 netdev_for_each_mc_addr(ha, ndev) {
241 if (!is_multicast_ether_addr(ha->addr))
242 continue;
243
244 enetc_add_mac_addr_ht_filter(filter, ha->addr);
245 }
246 }
247
248 if (!uprom || !mprom)
249
250 enetc_sync_mac_filters(pf);
251
252 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
253 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
254 enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
255}
256
257static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx,
258 unsigned long hash)
259{
260 enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash));
261 enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash));
262}
263
264static int enetc_vid_hash_idx(unsigned int vid)
265{
266 int res = 0;
267 int i;
268
269 for (i = 0; i < 6; i++)
270 res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i;
271
272 return res;
273}
274
275static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash)
276{
277 int i;
278
279 if (rehash) {
280 bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE);
281
282 for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) {
283 int hidx = enetc_vid_hash_idx(i);
284
285 __set_bit(hidx, pf->vlan_ht_filter);
286 }
287 }
288
289 enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter);
290}
291
292static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid)
293{
294 struct enetc_ndev_priv *priv = netdev_priv(ndev);
295 struct enetc_pf *pf = enetc_si_priv(priv->si);
296 int idx;
297
298 __set_bit(vid, pf->active_vlans);
299
300 idx = enetc_vid_hash_idx(vid);
301 if (!__test_and_set_bit(idx, pf->vlan_ht_filter))
302 enetc_sync_vlan_ht_filter(pf, false);
303
304 return 0;
305}
306
307static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)
308{
309 struct enetc_ndev_priv *priv = netdev_priv(ndev);
310 struct enetc_pf *pf = enetc_si_priv(priv->si);
311
312 __clear_bit(vid, pf->active_vlans);
313 enetc_sync_vlan_ht_filter(pf, true);
314
315 return 0;
316}
317
318static void enetc_set_loopback(struct net_device *ndev, bool en)
319{
320 struct enetc_ndev_priv *priv = netdev_priv(ndev);
321 struct enetc_hw *hw = &priv->si->hw;
322 u32 reg;
323
324 reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
325 if (reg & ENETC_PM0_IFM_RG) {
326
327 reg = (reg & ~ENETC_PM0_IFM_RLP) |
328 (en ? ENETC_PM0_IFM_RLP : 0);
329 enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg);
330 } else {
331
332 reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
333 reg = (reg & ~ENETC_PM0_CMD_XGLP) |
334 (en ? ENETC_PM0_CMD_XGLP : 0);
335 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
336 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
337 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg);
338 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg);
339 }
340}
341
342static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
343{
344 struct enetc_ndev_priv *priv = netdev_priv(ndev);
345 struct enetc_pf *pf = enetc_si_priv(priv->si);
346 struct enetc_vf_state *vf_state;
347
348 if (vf >= pf->total_vfs)
349 return -EINVAL;
350
351 if (!is_valid_ether_addr(mac))
352 return -EADDRNOTAVAIL;
353
354 vf_state = &pf->vf_state[vf];
355 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
356 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
357 return 0;
358}
359
360static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
361 u8 qos, __be16 proto)
362{
363 struct enetc_ndev_priv *priv = netdev_priv(ndev);
364 struct enetc_pf *pf = enetc_si_priv(priv->si);
365
366 if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
367 return -EOPNOTSUPP;
368
369 if (vf >= pf->total_vfs)
370 return -EINVAL;
371
372 if (proto != htons(ETH_P_8021Q))
373
374 return -EPROTONOSUPPORT;
375
376 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
377 return 0;
378}
379
380static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
381{
382 struct enetc_ndev_priv *priv = netdev_priv(ndev);
383 struct enetc_pf *pf = enetc_si_priv(priv->si);
384 u32 cfgr;
385
386 if (vf >= pf->total_vfs)
387 return -EINVAL;
388
389 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
390 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
391 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
392
393 return 0;
394}
395
396static int enetc_setup_mac_address(struct device_node *np, struct enetc_pf *pf,
397 int si)
398{
399 struct device *dev = &pf->si->pdev->dev;
400 struct enetc_hw *hw = &pf->si->hw;
401 u8 mac_addr[ETH_ALEN] = { 0 };
402 int err;
403
404
405 if (np) {
406 err = of_get_mac_address(np, mac_addr);
407 if (err == -EPROBE_DEFER)
408 return err;
409 }
410
411
412 if (is_zero_ether_addr(mac_addr))
413 enetc_pf_get_primary_mac_addr(hw, si, mac_addr);
414
415
416 if (is_zero_ether_addr(mac_addr)) {
417 eth_random_addr(mac_addr);
418 dev_info(dev, "no MAC address specified for SI%d, using %pM\n",
419 si, mac_addr);
420 }
421
422 enetc_pf_set_primary_mac_addr(hw, si, mac_addr);
423
424 return 0;
425}
426
427static int enetc_setup_mac_addresses(struct device_node *np,
428 struct enetc_pf *pf)
429{
430 int err, i;
431
432
433 err = enetc_setup_mac_address(np, pf, 0);
434 if (err)
435 return err;
436
437 for (i = 0; i < pf->total_vfs; i++) {
438 err = enetc_setup_mac_address(NULL, pf, i + 1);
439 if (err)
440 return err;
441 }
442
443 return 0;
444}
445
446static void enetc_port_assign_rfs_entries(struct enetc_si *si)
447{
448 struct enetc_pf *pf = enetc_si_priv(si);
449 struct enetc_hw *hw = &si->hw;
450 int num_entries, vf_entries, i;
451 u32 val;
452
453
454 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
455 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
456 vf_entries = num_entries / (pf->total_vfs + 1);
457
458 for (i = 0; i < pf->total_vfs; i++)
459 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
460 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
461 num_entries - vf_entries * pf->total_vfs);
462
463
464 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
465}
466
467static void enetc_port_si_configure(struct enetc_si *si)
468{
469 struct enetc_pf *pf = enetc_si_priv(si);
470 struct enetc_hw *hw = &si->hw;
471 int num_rings, i;
472 u32 val;
473
474 val = enetc_port_rd(hw, ENETC_PCAPR0);
475 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
476
477 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
478 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
479
480 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
481 val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
482 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
483
484 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
485 num_rings, ENETC_PF_NUM_RINGS);
486
487 num_rings = 0;
488 }
489
490
491 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
492
493 enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
494
495 if (num_rings)
496 num_rings -= ENETC_PF_NUM_RINGS;
497
498
499 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
500 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
501
502 if (num_rings) {
503 num_rings /= pf->total_vfs;
504 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
505 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
506 }
507
508 for (i = 0; i < pf->total_vfs; i++)
509 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
510
511
512 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
513 enetc_port_wr(hw, ENETC_PVCLCTR, val);
514
515 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
516}
517
518static void enetc_configure_port_mac(struct enetc_hw *hw)
519{
520 enetc_port_wr(hw, ENETC_PM0_MAXFRM,
521 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
522
523 enetc_port_wr(hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE);
524
525 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
526 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
527
528 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
529 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
530
531
532
533
534
535 enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
536}
537
538static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode)
539{
540 u32 val;
541
542 if (phy_interface_mode_is_rgmii(phy_mode)) {
543 val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
544 val &= ~ENETC_PM0_IFM_EN_AUTO;
545 val &= ENETC_PM0_IFM_IFMODE_MASK;
546 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
547 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
548 }
549
550 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
551 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
552 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
553 }
554}
555
556static void enetc_mac_enable(struct enetc_hw *hw, bool en)
557{
558 u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
559
560 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
561 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
562
563 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val);
564 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val);
565}
566
567static void enetc_configure_port_pmac(struct enetc_hw *hw)
568{
569 u32 temp;
570
571
572 temp = enetc_port_rd(hw, ENETC_PFPMR);
573 enetc_port_wr(hw, ENETC_PFPMR,
574 temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM);
575
576 temp = enetc_port_rd(hw, ENETC_MMCSR);
577 enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME);
578}
579
580static void enetc_configure_port(struct enetc_pf *pf)
581{
582 u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
583 struct enetc_hw *hw = &pf->si->hw;
584
585 enetc_configure_port_pmac(hw);
586
587 enetc_configure_port_mac(hw);
588
589 enetc_port_si_configure(pf->si);
590
591
592 get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE);
593 enetc_set_rss_key(hw, hash_key);
594
595
596 enetc_port_assign_rfs_entries(pf->si);
597
598
599 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
600 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
601
602 enetc_port_wr(hw, ENETC_PSIPMR, 0);
603
604
605 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
606}
607
608
609static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
610 int vf_id)
611{
612 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
613 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
614 struct enetc_msg_cmd_set_primary_mac *cmd;
615 struct device *dev = &pf->si->pdev->dev;
616 u16 cmd_id;
617 char *addr;
618
619 cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;
620 cmd_id = cmd->header.id;
621 if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
622 return ENETC_MSG_CMD_STATUS_FAIL;
623
624 addr = cmd->mac.sa_data;
625 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)
626 dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",
627 vf_id);
628 else
629 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
630
631 return ENETC_MSG_CMD_STATUS_OK;
632}
633
634void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
635{
636 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
637 struct device *dev = &pf->si->pdev->dev;
638 struct enetc_msg_cmd_header *cmd_hdr;
639 u16 cmd_type;
640
641 *status = ENETC_MSG_CMD_STATUS_OK;
642 cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;
643 cmd_type = cmd_hdr->type;
644
645 switch (cmd_type) {
646 case ENETC_MSG_CMD_MNG_MAC:
647 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);
648 break;
649 default:
650 dev_err(dev, "command not supported (cmd_type: 0x%x)\n",
651 cmd_type);
652 }
653}
654
655#ifdef CONFIG_PCI_IOV
656static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
657{
658 struct enetc_si *si = pci_get_drvdata(pdev);
659 struct enetc_pf *pf = enetc_si_priv(si);
660 int err;
661
662 if (!num_vfs) {
663 enetc_msg_psi_free(pf);
664 kfree(pf->vf_state);
665 pf->num_vfs = 0;
666 pci_disable_sriov(pdev);
667 } else {
668 pf->num_vfs = num_vfs;
669
670 pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state),
671 GFP_KERNEL);
672 if (!pf->vf_state) {
673 pf->num_vfs = 0;
674 return -ENOMEM;
675 }
676
677 err = enetc_msg_psi_init(pf);
678 if (err) {
679 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
680 goto err_msg_psi;
681 }
682
683 err = pci_enable_sriov(pdev, num_vfs);
684 if (err) {
685 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
686 goto err_en_sriov;
687 }
688 }
689
690 return num_vfs;
691
692err_en_sriov:
693 enetc_msg_psi_free(pf);
694err_msg_psi:
695 kfree(pf->vf_state);
696 pf->num_vfs = 0;
697
698 return err;
699}
700#else
701#define enetc_sriov_configure(pdev, num_vfs) (void)0
702#endif
703
704static int enetc_pf_set_features(struct net_device *ndev,
705 netdev_features_t features)
706{
707 netdev_features_t changed = ndev->features ^ features;
708 struct enetc_ndev_priv *priv = netdev_priv(ndev);
709
710 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
711 struct enetc_pf *pf = enetc_si_priv(priv->si);
712
713 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
714 enetc_disable_si_vlan_promisc(pf, 0);
715 else
716 enetc_enable_si_vlan_promisc(pf, 0);
717 }
718
719 if (changed & NETIF_F_LOOPBACK)
720 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
721
722 return enetc_set_features(ndev, features);
723}
724
725static const struct net_device_ops enetc_ndev_ops = {
726 .ndo_open = enetc_open,
727 .ndo_stop = enetc_close,
728 .ndo_start_xmit = enetc_xmit,
729 .ndo_get_stats = enetc_get_stats,
730 .ndo_set_mac_address = enetc_pf_set_mac_addr,
731 .ndo_set_rx_mode = enetc_pf_set_rx_mode,
732 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
733 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
734 .ndo_set_vf_mac = enetc_pf_set_vf_mac,
735 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan,
736 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,
737 .ndo_set_features = enetc_pf_set_features,
738 .ndo_do_ioctl = enetc_ioctl,
739 .ndo_setup_tc = enetc_setup_tc,
740 .ndo_bpf = enetc_setup_bpf,
741 .ndo_xdp_xmit = enetc_xdp_xmit,
742};
743
744static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev,
745 const struct net_device_ops *ndev_ops)
746{
747 struct enetc_ndev_priv *priv = netdev_priv(ndev);
748
749 SET_NETDEV_DEV(ndev, &si->pdev->dev);
750 priv->ndev = ndev;
751 priv->si = si;
752 priv->dev = &si->pdev->dev;
753 si->ndev = ndev;
754
755 priv->msg_enable = (NETIF_MSG_WOL << 1) - 1;
756 ndev->netdev_ops = ndev_ops;
757 enetc_set_ethtool_ops(ndev);
758 ndev->watchdog_timeo = 5 * HZ;
759 ndev->max_mtu = ENETC_MAX_MTU;
760
761 ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
762 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
763 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK;
764 ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM |
765 NETIF_F_HW_VLAN_CTAG_TX |
766 NETIF_F_HW_VLAN_CTAG_RX;
767
768 if (si->num_rss)
769 ndev->hw_features |= NETIF_F_RXHASH;
770
771 ndev->priv_flags |= IFF_UNICAST_FLT;
772
773 if (si->hw_features & ENETC_SI_F_QBV)
774 priv->active_offloads |= ENETC_F_QBV;
775
776 if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) {
777 priv->active_offloads |= ENETC_F_QCI;
778 ndev->features |= NETIF_F_HW_TC;
779 ndev->hw_features |= NETIF_F_HW_TC;
780 }
781
782
783 enetc_get_primary_mac_addr(&si->hw, ndev->dev_addr);
784}
785
786static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np)
787{
788 struct device *dev = &pf->si->pdev->dev;
789 struct enetc_mdio_priv *mdio_priv;
790 struct mii_bus *bus;
791 int err;
792
793 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
794 if (!bus)
795 return -ENOMEM;
796
797 bus->name = "Freescale ENETC MDIO Bus";
798 bus->read = enetc_mdio_read;
799 bus->write = enetc_mdio_write;
800 bus->parent = dev;
801 mdio_priv = bus->priv;
802 mdio_priv->hw = &pf->si->hw;
803 mdio_priv->mdio_base = ENETC_EMDIO_BASE;
804 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
805
806 err = of_mdiobus_register(bus, np);
807 if (err) {
808 dev_err(dev, "cannot register MDIO bus\n");
809 return err;
810 }
811
812 pf->mdio = bus;
813
814 return 0;
815}
816
817static void enetc_mdio_remove(struct enetc_pf *pf)
818{
819 if (pf->mdio)
820 mdiobus_unregister(pf->mdio);
821}
822
823static int enetc_imdio_create(struct enetc_pf *pf)
824{
825 struct device *dev = &pf->si->pdev->dev;
826 struct enetc_mdio_priv *mdio_priv;
827 struct lynx_pcs *pcs_lynx;
828 struct mdio_device *pcs;
829 struct mii_bus *bus;
830 int err;
831
832 bus = mdiobus_alloc_size(sizeof(*mdio_priv));
833 if (!bus)
834 return -ENOMEM;
835
836 bus->name = "Freescale ENETC internal MDIO Bus";
837 bus->read = enetc_mdio_read;
838 bus->write = enetc_mdio_write;
839 bus->parent = dev;
840 bus->phy_mask = ~0;
841 mdio_priv = bus->priv;
842 mdio_priv->hw = &pf->si->hw;
843 mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
844 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
845
846 err = mdiobus_register(bus);
847 if (err) {
848 dev_err(dev, "cannot register internal MDIO bus (%d)\n", err);
849 goto free_mdio_bus;
850 }
851
852 pcs = mdio_device_create(bus, 0);
853 if (IS_ERR(pcs)) {
854 err = PTR_ERR(pcs);
855 dev_err(dev, "cannot create pcs (%d)\n", err);
856 goto unregister_mdiobus;
857 }
858
859 pcs_lynx = lynx_pcs_create(pcs);
860 if (!pcs_lynx) {
861 mdio_device_free(pcs);
862 err = -ENOMEM;
863 dev_err(dev, "cannot create lynx pcs (%d)\n", err);
864 goto unregister_mdiobus;
865 }
866
867 pf->imdio = bus;
868 pf->pcs = pcs_lynx;
869
870 return 0;
871
872unregister_mdiobus:
873 mdiobus_unregister(bus);
874free_mdio_bus:
875 mdiobus_free(bus);
876 return err;
877}
878
879static void enetc_imdio_remove(struct enetc_pf *pf)
880{
881 if (pf->pcs) {
882 mdio_device_free(pf->pcs->mdio);
883 lynx_pcs_destroy(pf->pcs);
884 }
885 if (pf->imdio) {
886 mdiobus_unregister(pf->imdio);
887 mdiobus_free(pf->imdio);
888 }
889}
890
891static bool enetc_port_has_pcs(struct enetc_pf *pf)
892{
893 return (pf->if_mode == PHY_INTERFACE_MODE_SGMII ||
894 pf->if_mode == PHY_INTERFACE_MODE_2500BASEX ||
895 pf->if_mode == PHY_INTERFACE_MODE_USXGMII);
896}
897
898static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node)
899{
900 struct device_node *mdio_np;
901 int err;
902
903 mdio_np = of_get_child_by_name(node, "mdio");
904 if (mdio_np) {
905 err = enetc_mdio_probe(pf, mdio_np);
906
907 of_node_put(mdio_np);
908 if (err)
909 return err;
910 }
911
912 if (enetc_port_has_pcs(pf)) {
913 err = enetc_imdio_create(pf);
914 if (err) {
915 enetc_mdio_remove(pf);
916 return err;
917 }
918 }
919
920 return 0;
921}
922
923static void enetc_mdiobus_destroy(struct enetc_pf *pf)
924{
925 enetc_mdio_remove(pf);
926 enetc_imdio_remove(pf);
927}
928
929static void enetc_pl_mac_validate(struct phylink_config *config,
930 unsigned long *supported,
931 struct phylink_link_state *state)
932{
933 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
934
935 if (state->interface != PHY_INTERFACE_MODE_NA &&
936 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
937 state->interface != PHY_INTERFACE_MODE_SGMII &&
938 state->interface != PHY_INTERFACE_MODE_2500BASEX &&
939 state->interface != PHY_INTERFACE_MODE_USXGMII &&
940 !phy_interface_mode_is_rgmii(state->interface)) {
941 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
942 return;
943 }
944
945 phylink_set_port_modes(mask);
946 phylink_set(mask, Autoneg);
947 phylink_set(mask, Pause);
948 phylink_set(mask, Asym_Pause);
949 phylink_set(mask, 10baseT_Half);
950 phylink_set(mask, 10baseT_Full);
951 phylink_set(mask, 100baseT_Half);
952 phylink_set(mask, 100baseT_Full);
953 phylink_set(mask, 100baseT_Half);
954 phylink_set(mask, 1000baseT_Half);
955 phylink_set(mask, 1000baseT_Full);
956
957 if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
958 state->interface == PHY_INTERFACE_MODE_2500BASEX ||
959 state->interface == PHY_INTERFACE_MODE_USXGMII) {
960 phylink_set(mask, 2500baseT_Full);
961 phylink_set(mask, 2500baseX_Full);
962 }
963
964 bitmap_and(supported, supported, mask,
965 __ETHTOOL_LINK_MODE_MASK_NBITS);
966 bitmap_and(state->advertising, state->advertising, mask,
967 __ETHTOOL_LINK_MODE_MASK_NBITS);
968}
969
970static void enetc_pl_mac_config(struct phylink_config *config,
971 unsigned int mode,
972 const struct phylink_link_state *state)
973{
974 struct enetc_pf *pf = phylink_to_enetc_pf(config);
975 struct enetc_ndev_priv *priv;
976
977 enetc_mac_config(&pf->si->hw, state->interface);
978
979 priv = netdev_priv(pf->si->ndev);
980 if (pf->pcs)
981 phylink_set_pcs(priv->phylink, &pf->pcs->pcs);
982}
983
984static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex)
985{
986 u32 old_val, val;
987
988 old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
989
990 if (speed == SPEED_1000) {
991 val &= ~ENETC_PM0_IFM_SSP_MASK;
992 val |= ENETC_PM0_IFM_SSP_1000;
993 } else if (speed == SPEED_100) {
994 val &= ~ENETC_PM0_IFM_SSP_MASK;
995 val |= ENETC_PM0_IFM_SSP_100;
996 } else if (speed == SPEED_10) {
997 val &= ~ENETC_PM0_IFM_SSP_MASK;
998 val |= ENETC_PM0_IFM_SSP_10;
999 }
1000
1001 if (duplex == DUPLEX_FULL)
1002 val |= ENETC_PM0_IFM_FULL_DPX;
1003 else
1004 val &= ~ENETC_PM0_IFM_FULL_DPX;
1005
1006 if (val == old_val)
1007 return;
1008
1009 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
1010}
1011
1012static void enetc_pl_mac_link_up(struct phylink_config *config,
1013 struct phy_device *phy, unsigned int mode,
1014 phy_interface_t interface, int speed,
1015 int duplex, bool tx_pause, bool rx_pause)
1016{
1017 struct enetc_pf *pf = phylink_to_enetc_pf(config);
1018 u32 pause_off_thresh = 0, pause_on_thresh = 0;
1019 u32 init_quanta = 0, refresh_quanta = 0;
1020 struct enetc_hw *hw = &pf->si->hw;
1021 struct enetc_ndev_priv *priv;
1022 u32 rbmr, cmd_cfg;
1023 int idx;
1024
1025 priv = netdev_priv(pf->si->ndev);
1026 if (priv->active_offloads & ENETC_F_QBV)
1027 enetc_sched_speed_set(priv, speed);
1028
1029 if (!phylink_autoneg_inband(mode) &&
1030 phy_interface_mode_is_rgmii(interface))
1031 enetc_force_rgmii_mac(hw, speed, duplex);
1032
1033
1034 for (idx = 0; idx < priv->num_rx_rings; idx++) {
1035 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
1036
1037 if (tx_pause)
1038 rbmr |= ENETC_RBMR_CM;
1039 else
1040 rbmr &= ~ENETC_RBMR_CM;
1041
1042 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
1043 }
1044
1045 if (tx_pause) {
1046
1047
1048
1049
1050
1051 init_quanta = 0xffff;
1052
1053
1054
1055
1056
1057 refresh_quanta = 0xffff / 2;
1058
1059
1060
1061
1062
1063 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;
1064 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
1065 }
1066
1067 enetc_port_wr(hw, ENETC_PM0_PAUSE_QUANTA, init_quanta);
1068 enetc_port_wr(hw, ENETC_PM1_PAUSE_QUANTA, init_quanta);
1069 enetc_port_wr(hw, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
1070 enetc_port_wr(hw, ENETC_PM1_PAUSE_THRESH, refresh_quanta);
1071 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
1072 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
1073
1074 cmd_cfg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
1075
1076 if (rx_pause)
1077 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
1078 else
1079 cmd_cfg |= ENETC_PM0_PAUSE_IGN;
1080
1081 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, cmd_cfg);
1082 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, cmd_cfg);
1083
1084 enetc_mac_enable(hw, true);
1085}
1086
1087static void enetc_pl_mac_link_down(struct phylink_config *config,
1088 unsigned int mode,
1089 phy_interface_t interface)
1090{
1091 struct enetc_pf *pf = phylink_to_enetc_pf(config);
1092
1093 enetc_mac_enable(&pf->si->hw, false);
1094}
1095
1096static const struct phylink_mac_ops enetc_mac_phylink_ops = {
1097 .validate = enetc_pl_mac_validate,
1098 .mac_config = enetc_pl_mac_config,
1099 .mac_link_up = enetc_pl_mac_link_up,
1100 .mac_link_down = enetc_pl_mac_link_down,
1101};
1102
1103static int enetc_phylink_create(struct enetc_ndev_priv *priv,
1104 struct device_node *node)
1105{
1106 struct enetc_pf *pf = enetc_si_priv(priv->si);
1107 struct phylink *phylink;
1108 int err;
1109
1110 pf->phylink_config.dev = &priv->ndev->dev;
1111 pf->phylink_config.type = PHYLINK_NETDEV;
1112
1113 phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node),
1114 pf->if_mode, &enetc_mac_phylink_ops);
1115 if (IS_ERR(phylink)) {
1116 err = PTR_ERR(phylink);
1117 return err;
1118 }
1119
1120 priv->phylink = phylink;
1121
1122 return 0;
1123}
1124
1125static void enetc_phylink_destroy(struct enetc_ndev_priv *priv)
1126{
1127 if (priv->phylink)
1128 phylink_destroy(priv->phylink);
1129}
1130
1131
1132
1133
1134static int enetc_init_port_rfs_memory(struct enetc_si *si)
1135{
1136 struct enetc_cmd_rfse rfse = {0};
1137 struct enetc_hw *hw = &si->hw;
1138 int num_rfs, i, err = 0;
1139 u32 val;
1140
1141 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
1142 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
1143
1144 for (i = 0; i < num_rfs; i++) {
1145 err = enetc_set_fs_entry(si, &rfse, i);
1146 if (err)
1147 break;
1148 }
1149
1150 return err;
1151}
1152
1153static int enetc_init_port_rss_memory(struct enetc_si *si)
1154{
1155 struct enetc_hw *hw = &si->hw;
1156 int num_rss, err;
1157 int *rss_table;
1158 u32 val;
1159
1160 val = enetc_port_rd(hw, ENETC_PRSSCAPR);
1161 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
1162 if (!num_rss)
1163 return 0;
1164
1165 rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
1166 if (!rss_table)
1167 return -ENOMEM;
1168
1169 err = enetc_set_rss_table(si, rss_table, num_rss);
1170
1171 kfree(rss_table);
1172
1173 return err;
1174}
1175
1176static int enetc_pf_register_with_ierb(struct pci_dev *pdev)
1177{
1178 struct device_node *node = pdev->dev.of_node;
1179 struct platform_device *ierb_pdev;
1180 struct device_node *ierb_node;
1181
1182
1183 if (!node || !of_device_is_available(node))
1184 return 0;
1185
1186 ierb_node = of_find_compatible_node(NULL, NULL,
1187 "fsl,ls1028a-enetc-ierb");
1188 if (!ierb_node || !of_device_is_available(ierb_node))
1189 return -ENODEV;
1190
1191 ierb_pdev = of_find_device_by_node(ierb_node);
1192 of_node_put(ierb_node);
1193
1194 if (!ierb_pdev)
1195 return -EPROBE_DEFER;
1196
1197 return enetc_ierb_register_pf(ierb_pdev, pdev);
1198}
1199
1200static int enetc_pf_probe(struct pci_dev *pdev,
1201 const struct pci_device_id *ent)
1202{
1203 struct device_node *node = pdev->dev.of_node;
1204 struct enetc_ndev_priv *priv;
1205 struct net_device *ndev;
1206 struct enetc_si *si;
1207 struct enetc_pf *pf;
1208 int err;
1209
1210 err = enetc_pf_register_with_ierb(pdev);
1211 if (err == -EPROBE_DEFER)
1212 return err;
1213 if (err)
1214 dev_warn(&pdev->dev,
1215 "Could not register with IERB driver: %pe, please update the device tree\n",
1216 ERR_PTR(err));
1217
1218 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf));
1219 if (err) {
1220 dev_err(&pdev->dev, "PCI probing failed\n");
1221 return err;
1222 }
1223
1224 si = pci_get_drvdata(pdev);
1225 if (!si->hw.port || !si->hw.global) {
1226 err = -ENODEV;
1227 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
1228 goto err_map_pf_space;
1229 }
1230
1231 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,
1232 &si->cbd_ring);
1233 if (err)
1234 goto err_setup_cbdr;
1235
1236 err = enetc_init_port_rfs_memory(si);
1237 if (err) {
1238 dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
1239 goto err_init_port_rfs;
1240 }
1241
1242 err = enetc_init_port_rss_memory(si);
1243 if (err) {
1244 dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
1245 goto err_init_port_rss;
1246 }
1247
1248 if (node && !of_device_is_available(node)) {
1249 dev_info(&pdev->dev, "device is disabled, skipping\n");
1250 err = -ENODEV;
1251 goto err_device_disabled;
1252 }
1253
1254 pf = enetc_si_priv(si);
1255 pf->si = si;
1256 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
1257
1258 err = enetc_setup_mac_addresses(node, pf);
1259 if (err)
1260 goto err_setup_mac_addresses;
1261
1262 enetc_configure_port(pf);
1263
1264 enetc_get_si_caps(si);
1265
1266 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
1267 if (!ndev) {
1268 err = -ENOMEM;
1269 dev_err(&pdev->dev, "netdev creation failed\n");
1270 goto err_alloc_netdev;
1271 }
1272
1273 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
1274
1275 priv = netdev_priv(ndev);
1276
1277 enetc_init_si_rings_params(priv);
1278
1279 err = enetc_alloc_si_resources(priv);
1280 if (err) {
1281 dev_err(&pdev->dev, "SI resource alloc failed\n");
1282 goto err_alloc_si_res;
1283 }
1284
1285 err = enetc_configure_si(priv);
1286 if (err) {
1287 dev_err(&pdev->dev, "Failed to configure SI\n");
1288 goto err_config_si;
1289 }
1290
1291 err = enetc_alloc_msix(priv);
1292 if (err) {
1293 dev_err(&pdev->dev, "MSIX alloc failed\n");
1294 goto err_alloc_msix;
1295 }
1296
1297 if (!of_get_phy_mode(node, &pf->if_mode)) {
1298 err = enetc_mdiobus_create(pf, node);
1299 if (err)
1300 goto err_mdiobus_create;
1301
1302 err = enetc_phylink_create(priv, node);
1303 if (err)
1304 goto err_phylink_create;
1305 }
1306
1307 err = register_netdev(ndev);
1308 if (err)
1309 goto err_reg_netdev;
1310
1311 return 0;
1312
1313err_reg_netdev:
1314 enetc_phylink_destroy(priv);
1315err_phylink_create:
1316 enetc_mdiobus_destroy(pf);
1317err_mdiobus_create:
1318 enetc_free_msix(priv);
1319err_config_si:
1320err_alloc_msix:
1321 enetc_free_si_resources(priv);
1322err_alloc_si_res:
1323 si->ndev = NULL;
1324 free_netdev(ndev);
1325err_alloc_netdev:
1326err_init_port_rss:
1327err_init_port_rfs:
1328err_device_disabled:
1329err_setup_mac_addresses:
1330 enetc_teardown_cbdr(&si->cbd_ring);
1331err_setup_cbdr:
1332err_map_pf_space:
1333 enetc_pci_remove(pdev);
1334
1335 return err;
1336}
1337
1338static void enetc_pf_remove(struct pci_dev *pdev)
1339{
1340 struct enetc_si *si = pci_get_drvdata(pdev);
1341 struct enetc_pf *pf = enetc_si_priv(si);
1342 struct enetc_ndev_priv *priv;
1343
1344 priv = netdev_priv(si->ndev);
1345
1346 if (pf->num_vfs)
1347 enetc_sriov_configure(pdev, 0);
1348
1349 unregister_netdev(si->ndev);
1350
1351 enetc_phylink_destroy(priv);
1352 enetc_mdiobus_destroy(pf);
1353
1354 enetc_free_msix(priv);
1355
1356 enetc_free_si_resources(priv);
1357 enetc_teardown_cbdr(&si->cbd_ring);
1358
1359 free_netdev(si->ndev);
1360
1361 enetc_pci_remove(pdev);
1362}
1363
1364static const struct pci_device_id enetc_pf_id_table[] = {
1365 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
1366 { 0, }
1367};
1368MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
1369
1370static struct pci_driver enetc_pf_driver = {
1371 .name = KBUILD_MODNAME,
1372 .id_table = enetc_pf_id_table,
1373 .probe = enetc_pf_probe,
1374 .remove = enetc_pf_remove,
1375#ifdef CONFIG_PCI_IOV
1376 .sriov_configure = enetc_sriov_configure,
1377#endif
1378};
1379module_pci_driver(enetc_pf_driver);
1380
1381MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
1382MODULE_LICENSE("Dual BSD/GPL");
1383
