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33#ifndef __MLX5_CORE_H__
34#define __MLX5_CORE_H__
35
36#include <linux/types.h>
37#include <linux/kernel.h>
38#include <linux/sched.h>
39#include <linux/if_link.h>
40#include <linux/firmware.h>
41#include <linux/mlx5/cq.h>
42#include <linux/mlx5/fs.h>
43#include <linux/mlx5/driver.h>
44
45extern uint mlx5_core_debug_mask;
46
47#define mlx5_core_dbg(__dev, format, ...) \
48 dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, \
49 __func__, __LINE__, current->pid, \
50 ##__VA_ARGS__)
51
52#define mlx5_core_dbg_once(__dev, format, ...) \
53 dev_dbg_once((__dev)->device, \
54 "%s:%d:(pid %d): " format, \
55 __func__, __LINE__, current->pid, \
56 ##__VA_ARGS__)
57
58#define mlx5_core_dbg_mask(__dev, mask, format, ...) \
59do { \
60 if ((mask) & mlx5_core_debug_mask) \
61 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \
62} while (0)
63
64#define mlx5_core_err(__dev, format, ...) \
65 dev_err((__dev)->device, "%s:%d:(pid %d): " format, \
66 __func__, __LINE__, current->pid, \
67 ##__VA_ARGS__)
68
69#define mlx5_core_err_rl(__dev, format, ...) \
70 dev_err_ratelimited((__dev)->device, \
71 "%s:%d:(pid %d): " format, \
72 __func__, __LINE__, current->pid, \
73 ##__VA_ARGS__)
74
75#define mlx5_core_warn(__dev, format, ...) \
76 dev_warn((__dev)->device, "%s:%d:(pid %d): " format, \
77 __func__, __LINE__, current->pid, \
78 ##__VA_ARGS__)
79
80#define mlx5_core_warn_once(__dev, format, ...) \
81 dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, \
82 __func__, __LINE__, current->pid, \
83 ##__VA_ARGS__)
84
85#define mlx5_core_warn_rl(__dev, format, ...) \
86 dev_warn_ratelimited((__dev)->device, \
87 "%s:%d:(pid %d): " format, \
88 __func__, __LINE__, current->pid, \
89 ##__VA_ARGS__)
90
91#define mlx5_core_info(__dev, format, ...) \
92 dev_info((__dev)->device, format, ##__VA_ARGS__)
93
94#define mlx5_core_info_rl(__dev, format, ...) \
95 dev_info_ratelimited((__dev)->device, \
96 "%s:%d:(pid %d): " format, \
97 __func__, __LINE__, current->pid, \
98 ##__VA_ARGS__)
99
100static inline struct device *mlx5_core_dma_dev(struct mlx5_core_dev *dev)
101{
102 return &dev->pdev->dev;
103}
104
105enum {
106 MLX5_CMD_DATA,
107 MLX5_CMD_TIME,
108};
109
110enum {
111 MLX5_DRIVER_STATUS_ABORTED = 0xfe,
112 MLX5_DRIVER_SYND = 0xbadd00de,
113};
114
115enum mlx5_semaphore_space_address {
116 MLX5_SEMAPHORE_SPACE_DOMAIN = 0xA,
117 MLX5_SEMAPHORE_SW_RESET = 0x20,
118};
119
120#define MLX5_DEFAULT_PROF 2
121
122int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
123int mlx5_query_board_id(struct mlx5_core_dev *dev);
124int mlx5_cmd_init(struct mlx5_core_dev *dev);
125void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
126void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
127 enum mlx5_cmdif_state cmdif_state);
128int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
129int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
130int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
131int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev);
132void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force);
133void mlx5_error_sw_reset(struct mlx5_core_dev *dev);
134u32 mlx5_health_check_fatal_sensors(struct mlx5_core_dev *dev);
135int mlx5_health_wait_pci_up(struct mlx5_core_dev *dev);
136void mlx5_disable_device(struct mlx5_core_dev *dev);
137int mlx5_recover_device(struct mlx5_core_dev *dev);
138int mlx5_sriov_init(struct mlx5_core_dev *dev);
139void mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
140int mlx5_sriov_attach(struct mlx5_core_dev *dev);
141void mlx5_sriov_detach(struct mlx5_core_dev *dev);
142int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs);
143int mlx5_core_sriov_set_msix_vec_count(struct pci_dev *vf, int msix_vec_count);
144int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
145int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
146int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
147 void *context, u32 *element_id);
148int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
149 void *context, u32 element_id,
150 u32 modify_bitmask);
151int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
152 u32 element_id);
153int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages);
154
155void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev);
156void mlx5_cmd_flush(struct mlx5_core_dev *dev);
157void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
158void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
159
160int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
161 u8 access_reg_group);
162int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
163 u8 access_reg_group);
164int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
165 u8 feature_group, u8 access_reg_group);
166
167void mlx5_lag_add_netdev(struct mlx5_core_dev *dev, struct net_device *netdev);
168void mlx5_lag_remove_netdev(struct mlx5_core_dev *dev, struct net_device *netdev);
169void mlx5_lag_add_mdev(struct mlx5_core_dev *dev);
170void mlx5_lag_remove_mdev(struct mlx5_core_dev *dev);
171
172int mlx5_events_init(struct mlx5_core_dev *dev);
173void mlx5_events_cleanup(struct mlx5_core_dev *dev);
174void mlx5_events_start(struct mlx5_core_dev *dev);
175void mlx5_events_stop(struct mlx5_core_dev *dev);
176
177int mlx5_adev_idx_alloc(void);
178void mlx5_adev_idx_free(int idx);
179void mlx5_adev_cleanup(struct mlx5_core_dev *dev);
180int mlx5_adev_init(struct mlx5_core_dev *dev);
181
182int mlx5_attach_device(struct mlx5_core_dev *dev);
183void mlx5_detach_device(struct mlx5_core_dev *dev);
184int mlx5_register_device(struct mlx5_core_dev *dev);
185void mlx5_unregister_device(struct mlx5_core_dev *dev);
186struct mlx5_core_dev *mlx5_get_next_phys_dev(struct mlx5_core_dev *dev);
187void mlx5_dev_list_lock(void);
188void mlx5_dev_list_unlock(void);
189int mlx5_dev_list_trylock(void);
190
191int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size);
192int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);
193int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);
194int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);
195
196struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev);
197void mlx5_dm_cleanup(struct mlx5_core_dev *dev);
198
199#define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
200 MLX5_CAP_GEN((mdev), pps_modify) && \
201 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \
202 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
203
204int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw,
205 struct netlink_ext_ack *extack);
206int mlx5_fw_version_query(struct mlx5_core_dev *dev,
207 u32 *running_ver, u32 *stored_ver);
208
209#ifdef CONFIG_MLX5_CORE_EN
210int mlx5e_init(void);
211void mlx5e_cleanup(void);
212#else
213static inline int mlx5e_init(void){ return 0; }
214static inline void mlx5e_cleanup(void){}
215#endif
216
217static inline bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev)
218{
219 return pci_num_vf(dev->pdev) ? true : false;
220}
221
222static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
223{
224
225
226
227
228
229 return MLX5_CAP_GEN(dev, vport_group_manager) &&
230 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
231 MLX5_CAP_GEN(dev, lag_master);
232}
233
234int mlx5_rescan_drivers_locked(struct mlx5_core_dev *dev);
235static inline int mlx5_rescan_drivers(struct mlx5_core_dev *dev)
236{
237 int ret;
238
239 mlx5_dev_list_lock();
240 ret = mlx5_rescan_drivers_locked(dev);
241 mlx5_dev_list_unlock();
242 return ret;
243}
244
245void mlx5_lag_update(struct mlx5_core_dev *dev);
246
247enum {
248 MLX5_NIC_IFC_FULL = 0,
249 MLX5_NIC_IFC_DISABLED = 1,
250 MLX5_NIC_IFC_NO_DRAM_NIC = 2,
251 MLX5_NIC_IFC_SW_RESET = 7
252};
253
254u8 mlx5_get_nic_state(struct mlx5_core_dev *dev);
255void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state);
256
257static inline bool mlx5_core_is_sf(const struct mlx5_core_dev *dev)
258{
259 return dev->coredev_type == MLX5_COREDEV_SF;
260}
261
262int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx);
263void mlx5_mdev_uninit(struct mlx5_core_dev *dev);
264int mlx5_init_one(struct mlx5_core_dev *dev);
265void mlx5_uninit_one(struct mlx5_core_dev *dev);
266void mlx5_unload_one(struct mlx5_core_dev *dev);
267int mlx5_load_one(struct mlx5_core_dev *dev);
268
269int mlx5_vport_get_other_func_cap(struct mlx5_core_dev *dev, u16 function_id, void *out);
270
271void mlx5_events_work_enqueue(struct mlx5_core_dev *dev, struct work_struct *work);
272static inline u32 mlx5_sriov_get_vf_total_msix(struct pci_dev *pdev)
273{
274 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
275
276 return MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix);
277}
278#endif
279