LXR linux/drivers/net/ethernet/microchip/enc28j60

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * enc28j60_hw.h: EDTP FrameThrower style enc28j60 registers
   4 *
   5 * $Id: enc28j60_hw.h,v 1.9 2007/12/14 11:59:16 claudio Exp $
   6 */
   7
   8#ifndef _ENC28J60_HW_H
   9#define _ENC28J60_HW_H
  10
  11/*
  12 * ENC28J60 Control Registers
  13 * Control register definitions are a combination of address,
  14 * bank number, and Ethernet/MAC/PHY indicator bits.
  15 * - Register address   (bits 0-4)
  16 * - Bank number        (bits 5-6)
  17 * - MAC/MII indicator  (bit 7)
  18 */
  19#define ADDR_MASK       0x1F
  20#define BANK_MASK       0x60
  21#define SPRD_MASK       0x80
  22/* All-bank registers */
  23#define EIE             0x1B
  24#define EIR             0x1C
  25#define ESTAT           0x1D
  26#define ECON2           0x1E
  27#define ECON1           0x1F
  28/* Bank 0 registers */
  29#define ERDPTL          (0x00|0x00)
  30#define ERDPTH          (0x01|0x00)
  31#define EWRPTL          (0x02|0x00)
  32#define EWRPTH          (0x03|0x00)
  33#define ETXSTL          (0x04|0x00)
  34#define ETXSTH          (0x05|0x00)
  35#define ETXNDL          (0x06|0x00)
  36#define ETXNDH          (0x07|0x00)
  37#define ERXSTL          (0x08|0x00)
  38#define ERXSTH          (0x09|0x00)
  39#define ERXNDL          (0x0A|0x00)
  40#define ERXNDH          (0x0B|0x00)
  41#define ERXRDPTL        (0x0C|0x00)
  42#define ERXRDPTH        (0x0D|0x00)
  43#define ERXWRPTL        (0x0E|0x00)
  44#define ERXWRPTH        (0x0F|0x00)
  45#define EDMASTL         (0x10|0x00)
  46#define EDMASTH         (0x11|0x00)
  47#define EDMANDL         (0x12|0x00)
  48#define EDMANDH         (0x13|0x00)
  49#define EDMADSTL        (0x14|0x00)
  50#define EDMADSTH        (0x15|0x00)
  51#define EDMACSL         (0x16|0x00)
  52#define EDMACSH         (0x17|0x00)
  53/* Bank 1 registers */
  54#define EHT0            (0x00|0x20)
  55#define EHT1            (0x01|0x20)
  56#define EHT2            (0x02|0x20)
  57#define EHT3            (0x03|0x20)
  58#define EHT4            (0x04|0x20)
  59#define EHT5            (0x05|0x20)
  60#define EHT6            (0x06|0x20)
  61#define EHT7            (0x07|0x20)
  62#define EPMM0           (0x08|0x20)
  63#define EPMM1           (0x09|0x20)
  64#define EPMM2           (0x0A|0x20)
  65#define EPMM3           (0x0B|0x20)
  66#define EPMM4           (0x0C|0x20)
  67#define EPMM5           (0x0D|0x20)
  68#define EPMM6           (0x0E|0x20)
  69#define EPMM7           (0x0F|0x20)
  70#define EPMCSL          (0x10|0x20)
  71#define EPMCSH          (0x11|0x20)
  72#define EPMOL           (0x14|0x20)
  73#define EPMOH           (0x15|0x20)
  74#define EWOLIE          (0x16|0x20)
  75#define EWOLIR          (0x17|0x20)
  76#define ERXFCON         (0x18|0x20)
  77#define EPKTCNT         (0x19|0x20)
  78/* Bank 2 registers */
  79#define MACON1          (0x00|0x40|SPRD_MASK)
  80/* #define MACON2       (0x01|0x40|SPRD_MASK) */
  81#define MACON3          (0x02|0x40|SPRD_MASK)
  82#define MACON4          (0x03|0x40|SPRD_MASK)
  83#define MABBIPG         (0x04|0x40|SPRD_MASK)
  84#define MAIPGL          (0x06|0x40|SPRD_MASK)
  85#define MAIPGH          (0x07|0x40|SPRD_MASK)
  86#define MACLCON1        (0x08|0x40|SPRD_MASK)
  87#define MACLCON2        (0x09|0x40|SPRD_MASK)
  88#define MAMXFLL         (0x0A|0x40|SPRD_MASK)
  89#define MAMXFLH         (0x0B|0x40|SPRD_MASK)
  90#define MAPHSUP         (0x0D|0x40|SPRD_MASK)
  91#define MICON           (0x11|0x40|SPRD_MASK)
  92#define MICMD           (0x12|0x40|SPRD_MASK)
  93#define MIREGADR        (0x14|0x40|SPRD_MASK)
  94#define MIWRL           (0x16|0x40|SPRD_MASK)
  95#define MIWRH           (0x17|0x40|SPRD_MASK)
  96#define MIRDL           (0x18|0x40|SPRD_MASK)
  97#define MIRDH           (0x19|0x40|SPRD_MASK)
  98/* Bank 3 registers */
  99#define MAADR1          (0x00|0x60|SPRD_MASK)
 100#define MAADR0          (0x01|0x60|SPRD_MASK)
 101#define MAADR3          (0x02|0x60|SPRD_MASK)
 102#define MAADR2          (0x03|0x60|SPRD_MASK)
 103#define MAADR5          (0x04|0x60|SPRD_MASK)
 104#define MAADR4          (0x05|0x60|SPRD_MASK)
 105#define EBSTSD          (0x06|0x60)
 106#define EBSTCON         (0x07|0x60)
 107#define EBSTCSL         (0x08|0x60)
 108#define EBSTCSH         (0x09|0x60)
 109#define MISTAT          (0x0A|0x60|SPRD_MASK)
 110#define EREVID          (0x12|0x60)
 111#define ECOCON          (0x15|0x60)
 112#define EFLOCON         (0x17|0x60)
 113#define EPAUSL          (0x18|0x60)
 114#define EPAUSH          (0x19|0x60)
 115/* PHY registers */
 116#define PHCON1          0x00
 117#define PHSTAT1         0x01
 118#define PHHID1          0x02
 119#define PHHID2          0x03
 120#define PHCON2          0x10
 121#define PHSTAT2         0x11
 122#define PHIE            0x12
 123#define PHIR            0x13
 124#define PHLCON          0x14
 125
 126/* ENC28J60 EIE Register Bit Definitions */
 127#define EIE_INTIE       0x80
 128#define EIE_PKTIE       0x40
 129#define EIE_DMAIE       0x20
 130#define EIE_LINKIE      0x10
 131#define EIE_TXIE        0x08
 132/* #define EIE_WOLIE    0x04 (reserved) */
 133#define EIE_TXERIE      0x02
 134#define EIE_RXERIE      0x01
 135/* ENC28J60 EIR Register Bit Definitions */
 136#define EIR_PKTIF       0x40
 137#define EIR_DMAIF       0x20
 138#define EIR_LINKIF      0x10
 139#define EIR_TXIF        0x08
 140/* #define EIR_WOLIF    0x04 (reserved) */
 141#define EIR_TXERIF      0x02
 142#define EIR_RXERIF      0x01
 143/* ENC28J60 ESTAT Register Bit Definitions */
 144#define ESTAT_INT       0x80
 145#define ESTAT_LATECOL   0x10
 146#define ESTAT_RXBUSY    0x04
 147#define ESTAT_TXABRT    0x02
 148#define ESTAT_CLKRDY    0x01
 149/* ENC28J60 ECON2 Register Bit Definitions */
 150#define ECON2_AUTOINC   0x80
 151#define ECON2_PKTDEC    0x40
 152#define ECON2_PWRSV     0x20
 153#define ECON2_VRPS      0x08
 154/* ENC28J60 ECON1 Register Bit Definitions */
 155#define ECON1_TXRST     0x80
 156#define ECON1_RXRST     0x40
 157#define ECON1_DMAST     0x20
 158#define ECON1_CSUMEN    0x10
 159#define ECON1_TXRTS     0x08
 160#define ECON1_RXEN      0x04
 161#define ECON1_BSEL1     0x02
 162#define ECON1_BSEL0     0x01
 163/* ENC28J60 MACON1 Register Bit Definitions */
 164#define MACON1_LOOPBK   0x10
 165#define MACON1_TXPAUS   0x08
 166#define MACON1_RXPAUS   0x04
 167#define MACON1_PASSALL  0x02
 168#define MACON1_MARXEN   0x01
 169/* ENC28J60 MACON2 Register Bit Definitions */
 170#define MACON2_MARST    0x80
 171#define MACON2_RNDRST   0x40
 172#define MACON2_MARXRST  0x08
 173#define MACON2_RFUNRST  0x04
 174#define MACON2_MATXRST  0x02
 175#define MACON2_TFUNRST  0x01
 176/* ENC28J60 MACON3 Register Bit Definitions */
 177#define MACON3_PADCFG2  0x80
 178#define MACON3_PADCFG1  0x40
 179#define MACON3_PADCFG0  0x20
 180#define MACON3_TXCRCEN  0x10
 181#define MACON3_PHDRLEN  0x08
 182#define MACON3_HFRMLEN  0x04
 183#define MACON3_FRMLNEN  0x02
 184#define MACON3_FULDPX   0x01
 185/* ENC28J60 MICMD Register Bit Definitions */
 186#define MICMD_MIISCAN   0x02
 187#define MICMD_MIIRD     0x01
 188/* ENC28J60 MISTAT Register Bit Definitions */
 189#define MISTAT_NVALID   0x04
 190#define MISTAT_SCAN     0x02
 191#define MISTAT_BUSY     0x01
 192/* ENC28J60 ERXFCON Register Bit Definitions */
 193#define ERXFCON_UCEN    0x80
 194#define ERXFCON_ANDOR   0x40
 195#define ERXFCON_CRCEN   0x20
 196#define ERXFCON_PMEN    0x10
 197#define ERXFCON_MPEN    0x08
 198#define ERXFCON_HTEN    0x04
 199#define ERXFCON_MCEN    0x02
 200#define ERXFCON_BCEN    0x01
 201
 202/* ENC28J60 PHY PHCON1 Register Bit Definitions */
 203#define PHCON1_PRST     0x8000
 204#define PHCON1_PLOOPBK  0x4000
 205#define PHCON1_PPWRSV   0x0800
 206#define PHCON1_PDPXMD   0x0100
 207/* ENC28J60 PHY PHSTAT1 Register Bit Definitions */
 208#define PHSTAT1_PFDPX   0x1000
 209#define PHSTAT1_PHDPX   0x0800
 210#define PHSTAT1_LLSTAT  0x0004
 211#define PHSTAT1_JBSTAT  0x0002
 212/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
 213#define PHSTAT2_TXSTAT  (1 << 13)
 214#define PHSTAT2_RXSTAT  (1 << 12)
 215#define PHSTAT2_COLSTAT (1 << 11)
 216#define PHSTAT2_LSTAT   (1 << 10)
 217#define PHSTAT2_DPXSTAT (1 << 9)
 218#define PHSTAT2_PLRITY  (1 << 5)
 219/* ENC28J60 PHY PHCON2 Register Bit Definitions */
 220#define PHCON2_FRCLINK  0x4000
 221#define PHCON2_TXDIS    0x2000
 222#define PHCON2_JABBER   0x0400
 223#define PHCON2_HDLDIS   0x0100
 224/* ENC28J60 PHY PHIE Register Bit Definitions */
 225#define PHIE_PLNKIE     (1 << 4)
 226#define PHIE_PGEIE      (1 << 1)
 227/* ENC28J60 PHY PHIR Register Bit Definitions */
 228#define PHIR_PLNKIF     (1 << 4)
 229#define PHIR_PGEIF      (1 << 1)
 230
 231/* ENC28J60 Packet Control Byte Bit Definitions */
 232#define PKTCTRL_PHUGEEN         0x08
 233#define PKTCTRL_PPADEN          0x04
 234#define PKTCTRL_PCRCEN          0x02
 235#define PKTCTRL_POVERRIDE       0x01
 236
 237/* ENC28J60 Transmit Status Vector */
 238#define TSV_TXBYTECNT           0
 239#define TSV_TXCOLLISIONCNT      16
 240#define TSV_TXCRCERROR          20
 241#define TSV_TXLENCHKERROR       21
 242#define TSV_TXLENOUTOFRANGE     22
 243#define TSV_TXDONE              23
 244#define TSV_TXMULTICAST         24
 245#define TSV_TXBROADCAST         25
 246#define TSV_TXPACKETDEFER       26
 247#define TSV_TXEXDEFER           27
 248#define TSV_TXEXCOLLISION       28
 249#define TSV_TXLATECOLLISION     29
 250#define TSV_TXGIANT             30
 251#define TSV_TXUNDERRUN          31
 252#define TSV_TOTBYTETXONWIRE     32
 253#define TSV_TXCONTROLFRAME      48
 254#define TSV_TXPAUSEFRAME        49
 255#define TSV_BACKPRESSUREAPP     50
 256#define TSV_TXVLANTAGFRAME      51
 257
 258#define TSV_SIZE                7
 259#define TSV_BYTEOF(x)           ((x) / 8)
 260#define TSV_BITMASK(x)          (1 << ((x) % 8))
 261#define TSV_GETBIT(x, y)        (((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0)
 262
 263/* ENC28J60 Receive Status Vector */
 264#define RSV_RXLONGEVDROPEV      16
 265#define RSV_CARRIEREV           18
 266#define RSV_CRCERROR            20
 267#define RSV_LENCHECKERR         21
 268#define RSV_LENOUTOFRANGE       22
 269#define RSV_RXOK                23
 270#define RSV_RXMULTICAST         24
 271#define RSV_RXBROADCAST         25
 272#define RSV_DRIBBLENIBBLE       26
 273#define RSV_RXCONTROLFRAME      27
 274#define RSV_RXPAUSEFRAME        28
 275#define RSV_RXUNKNOWNOPCODE     29
 276#define RSV_RXTYPEVLAN          30
 277
 278#define RSV_SIZE                6
 279#define RSV_BITMASK(x)          (1 << ((x) - 16))
 280#define RSV_GETBIT(x, y)        (((x) & RSV_BITMASK(y)) ? 1 : 0)
 281
 282
 283/* SPI operation codes */
 284#define ENC28J60_READ_CTRL_REG  0x00
 285#define ENC28J60_READ_BUF_MEM   0x3A
 286#define ENC28J60_WRITE_CTRL_REG 0x40
 287#define ENC28J60_WRITE_BUF_MEM  0x7A
 288#define ENC28J60_BIT_FIELD_SET  0x80
 289#define ENC28J60_BIT_FIELD_CLR  0xA0
 290#define ENC28J60_SOFT_RESET     0xFF
 291
 292
 293/* buffer boundaries applied to internal 8K ram
 294 * entire available packet buffer space is allocated.
 295 * Give TX buffer space for one full ethernet frame (~1500 bytes)
 296 * receive buffer gets the rest */
 297#define TXSTART_INIT            0x1A00
 298#define TXEND_INIT              0x1FFF
 299
 300/* Put RX buffer at 0 as suggested by the Errata datasheet */
 301#define RXSTART_INIT            0x0000
 302#define RXEND_INIT              0x19FF
 303
 304/* maximum ethernet frame length */
 305#define MAX_FRAMELEN            1518
 306
 307/* Preferred half duplex: LEDA: Link status LEDB: Rx/Tx activity */
 308#define ENC28J60_LAMPS_MODE     0x3476
 309
 310#endif
 311