LXR linux/drivers/net/ethernet/pensando/ionic/ionic

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
   3
   4#ifndef _IONIC_LIF_H_
   5#define _IONIC_LIF_H_
   6
   7#include <linux/ptp_clock_kernel.h>
   8#include <linux/timecounter.h>
   9#include <uapi/linux/net_tstamp.h>
  10#include <linux/dim.h>
  11#include <linux/pci.h>
  12#include "ionic_rx_filter.h"
  13
  14#define IONIC_ADMINQ_LENGTH     16      /* must be a power of two */
  15#define IONIC_NOTIFYQ_LENGTH    64      /* must be a power of two */
  16
  17#define IONIC_MAX_NUM_NAPI_CNTR         (NAPI_POLL_WEIGHT + 1)
  18#define IONIC_MAX_NUM_SG_CNTR           (IONIC_TX_MAX_SG_ELEMS + 1)
  19
  20#define ADD_ADDR        true
  21#define DEL_ADDR        false
  22#define CAN_SLEEP       true
  23#define CAN_NOT_SLEEP   false
  24
  25#define IONIC_RX_COPYBREAK_DEFAULT      256
  26#define IONIC_TX_BUDGET_DEFAULT         256
  27
  28struct ionic_tx_stats {
  29        u64 pkts;
  30        u64 bytes;
  31        u64 csum_none;
  32        u64 csum;
  33        u64 tso;
  34        u64 tso_bytes;
  35        u64 frags;
  36        u64 vlan_inserted;
  37        u64 clean;
  38        u64 linearize;
  39        u64 crc32_csum;
  40        u64 sg_cntr[IONIC_MAX_NUM_SG_CNTR];
  41        u64 dma_map_err;
  42        u64 hwstamp_valid;
  43        u64 hwstamp_invalid;
  44};
  45
  46struct ionic_rx_stats {
  47        u64 pkts;
  48        u64 bytes;
  49        u64 csum_none;
  50        u64 csum_complete;
  51        u64 buffers_posted;
  52        u64 dropped;
  53        u64 vlan_stripped;
  54        u64 csum_error;
  55        u64 dma_map_err;
  56        u64 alloc_err;
  57        u64 hwstamp_valid;
  58        u64 hwstamp_invalid;
  59};
  60
  61#define IONIC_QCQ_F_INITED              BIT(0)
  62#define IONIC_QCQ_F_SG                  BIT(1)
  63#define IONIC_QCQ_F_INTR                BIT(2)
  64#define IONIC_QCQ_F_TX_STATS            BIT(3)
  65#define IONIC_QCQ_F_RX_STATS            BIT(4)
  66#define IONIC_QCQ_F_NOTIFYQ             BIT(5)
  67
  68struct ionic_napi_stats {
  69        u64 poll_count;
  70        u64 work_done_cntr[IONIC_MAX_NUM_NAPI_CNTR];
  71};
  72
  73struct ionic_qcq {
  74        void *q_base;
  75        dma_addr_t q_base_pa;
  76        u32 q_size;
  77        void *cq_base;
  78        dma_addr_t cq_base_pa;
  79        u32 cq_size;
  80        void *sg_base;
  81        dma_addr_t sg_base_pa;
  82        u32 sg_size;
  83        struct dim dim;
  84        struct ionic_queue q;
  85        struct ionic_cq cq;
  86        struct ionic_intr_info intr;
  87        struct napi_struct napi;
  88        struct ionic_napi_stats napi_stats;
  89        unsigned int flags;
  90        struct dentry *dentry;
  91};
  92
  93#define q_to_qcq(q)             container_of(q, struct ionic_qcq, q)
  94#define q_to_tx_stats(q)        (&(q)->lif->txqstats[(q)->index])
  95#define q_to_rx_stats(q)        (&(q)->lif->rxqstats[(q)->index])
  96#define napi_to_qcq(napi)       container_of(napi, struct ionic_qcq, napi)
  97#define napi_to_cq(napi)        (&napi_to_qcq(napi)->cq)
  98
  99enum ionic_deferred_work_type {
 100        IONIC_DW_TYPE_RX_MODE,
 101        IONIC_DW_TYPE_RX_ADDR_ADD,
 102        IONIC_DW_TYPE_RX_ADDR_DEL,
 103        IONIC_DW_TYPE_LINK_STATUS,
 104        IONIC_DW_TYPE_LIF_RESET,
 105};
 106
 107struct ionic_deferred_work {
 108        struct list_head list;
 109        enum ionic_deferred_work_type type;
 110        union {
 111                u8 addr[ETH_ALEN];
 112                u8 fw_status;
 113        };
 114};
 115
 116struct ionic_deferred {
 117        spinlock_t lock;                /* lock for deferred work list */
 118        struct list_head list;
 119        struct work_struct work;
 120};
 121
 122struct ionic_lif_sw_stats {
 123        u64 tx_packets;
 124        u64 tx_bytes;
 125        u64 rx_packets;
 126        u64 rx_bytes;
 127        u64 tx_tso;
 128        u64 tx_tso_bytes;
 129        u64 tx_csum_none;
 130        u64 tx_csum;
 131        u64 rx_csum_none;
 132        u64 rx_csum_complete;
 133        u64 rx_csum_error;
 134        u64 tx_hwstamp_valid;
 135        u64 tx_hwstamp_invalid;
 136        u64 rx_hwstamp_valid;
 137        u64 rx_hwstamp_invalid;
 138        u64 hw_tx_dropped;
 139        u64 hw_rx_dropped;
 140        u64 hw_rx_over_errors;
 141        u64 hw_rx_missed_errors;
 142        u64 hw_tx_aborted_errors;
 143};
 144
 145enum ionic_lif_state_flags {
 146        IONIC_LIF_F_INITED,
 147        IONIC_LIF_F_SW_DEBUG_STATS,
 148        IONIC_LIF_F_UP,
 149        IONIC_LIF_F_LINK_CHECK_REQUESTED,
 150        IONIC_LIF_F_FW_RESET,
 151        IONIC_LIF_F_SPLIT_INTR,
 152        IONIC_LIF_F_BROKEN,
 153        IONIC_LIF_F_TX_DIM_INTR,
 154        IONIC_LIF_F_RX_DIM_INTR,
 155
 156        /* leave this as last */
 157        IONIC_LIF_F_STATE_SIZE
 158};
 159
 160struct ionic_qtype_info {
 161        u8  version;
 162        u8  supported;
 163        u64 features;
 164        u16 desc_sz;
 165        u16 comp_sz;
 166        u16 sg_desc_sz;
 167        u16 max_sg_elems;
 168        u16 sg_desc_stride;
 169};
 170
 171struct ionic_phc;
 172
 173#define IONIC_LIF_NAME_MAX_SZ           32
 174struct ionic_lif {
 175        struct net_device *netdev;
 176        DECLARE_BITMAP(state, IONIC_LIF_F_STATE_SIZE);
 177        struct ionic *ionic;
 178        unsigned int index;
 179        unsigned int hw_index;
 180        struct mutex queue_lock;        /* lock for queue structures */
 181        struct mutex config_lock;       /* lock for config actions */
 182        spinlock_t adminq_lock;         /* lock for AdminQ operations */
 183        struct ionic_qcq *adminqcq;
 184        struct ionic_qcq *notifyqcq;
 185        struct ionic_qcq **txqcqs;
 186        struct ionic_qcq *hwstamp_txq;
 187        struct ionic_tx_stats *txqstats;
 188        struct ionic_qcq **rxqcqs;
 189        struct ionic_qcq *hwstamp_rxq;
 190        struct ionic_rx_stats *rxqstats;
 191        struct ionic_deferred deferred;
 192        struct work_struct tx_timeout_work;
 193        u64 last_eid;
 194        unsigned int kern_pid;
 195        u64 __iomem *kern_dbpage;
 196        unsigned int neqs;
 197        unsigned int nxqs;
 198        unsigned int ntxq_descs;
 199        unsigned int nrxq_descs;
 200        u32 rx_copybreak;
 201        u64 rxq_features;
 202        u16 rx_mode;
 203        u64 hw_features;
 204        bool registered;
 205        bool mc_overflow;
 206        bool uc_overflow;
 207        u16 lif_type;
 208        unsigned int nmcast;
 209        unsigned int nucast;
 210        char name[IONIC_LIF_NAME_MAX_SZ];
 211
 212        union ionic_lif_identity *identity;
 213        struct ionic_lif_info *info;
 214        dma_addr_t info_pa;
 215        u32 info_sz;
 216        struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX];
 217
 218        u16 rss_types;
 219        u8 rss_hash_key[IONIC_RSS_HASH_KEY_SIZE];
 220        u8 *rss_ind_tbl;
 221        dma_addr_t rss_ind_tbl_pa;
 222        u32 rss_ind_tbl_sz;
 223
 224        struct ionic_rx_filters rx_filters;
 225        u32 rx_coalesce_usecs;          /* what the user asked for */
 226        u32 rx_coalesce_hw;             /* what the hw is using */
 227        u32 tx_coalesce_usecs;          /* what the user asked for */
 228        u32 tx_coalesce_hw;             /* what the hw is using */
 229        unsigned long *dbid_inuse;
 230        unsigned int dbid_count;
 231
 232        struct ionic_phc *phc;
 233
 234        struct dentry *dentry;
 235};
 236
 237struct ionic_phc {
 238        spinlock_t lock; /* lock for cc and tc */
 239        struct cyclecounter cc;
 240        struct timecounter tc;
 241
 242        struct mutex config_lock; /* lock for ts_config */
 243        struct hwtstamp_config ts_config;
 244        u64 ts_config_rx_filt;
 245        u32 ts_config_tx_mode;
 246
 247        u32 init_cc_mult;
 248        long aux_work_delay;
 249
 250        struct ptp_clock_info ptp_info;
 251        struct ptp_clock *ptp;
 252        struct ionic_lif *lif;
 253};
 254
 255struct ionic_queue_params {
 256        unsigned int nxqs;
 257        unsigned int ntxq_descs;
 258        unsigned int nrxq_descs;
 259        unsigned int intr_split;
 260        u64 rxq_features;
 261};
 262
 263static inline void ionic_init_queue_params(struct ionic_lif *lif,
 264                                           struct ionic_queue_params *qparam)
 265{
 266        qparam->nxqs = lif->nxqs;
 267        qparam->ntxq_descs = lif->ntxq_descs;
 268        qparam->nrxq_descs = lif->nrxq_descs;
 269        qparam->intr_split = test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
 270        qparam->rxq_features = lif->rxq_features;
 271}
 272
 273static inline u32 ionic_coal_usec_to_hw(struct ionic *ionic, u32 usecs)
 274{
 275        u32 mult = le32_to_cpu(ionic->ident.dev.intr_coal_mult);
 276        u32 div = le32_to_cpu(ionic->ident.dev.intr_coal_div);
 277
 278        /* Div-by-zero should never be an issue, but check anyway */
 279        if (!div || !mult)
 280                return 0;
 281
 282        /* Round up in case usecs is close to the next hw unit */
 283        usecs += (div / mult) >> 1;
 284
 285        /* Convert from usecs to device units */
 286        return (usecs * mult) / div;
 287}
 288
 289void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep);
 290void ionic_get_stats64(struct net_device *netdev,
 291                       struct rtnl_link_stats64 *ns);
 292void ionic_lif_deferred_enqueue(struct ionic_deferred *def,
 293                                struct ionic_deferred_work *work);
 294int ionic_lif_alloc(struct ionic *ionic);
 295int ionic_lif_init(struct ionic_lif *lif);
 296void ionic_lif_free(struct ionic_lif *lif);
 297void ionic_lif_deinit(struct ionic_lif *lif);
 298int ionic_lif_register(struct ionic_lif *lif);
 299void ionic_lif_unregister(struct ionic_lif *lif);
 300int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
 301                       union ionic_lif_identity *lif_ident);
 302int ionic_lif_size(struct ionic *ionic);
 303
 304#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)
 305void ionic_lif_hwstamp_replay(struct ionic_lif *lif);
 306int ionic_lif_hwstamp_set(struct ionic_lif *lif, struct ifreq *ifr);
 307int ionic_lif_hwstamp_get(struct ionic_lif *lif, struct ifreq *ifr);
 308ktime_t ionic_lif_phc_ktime(struct ionic_lif *lif, u64 counter);
 309void ionic_lif_register_phc(struct ionic_lif *lif);
 310void ionic_lif_unregister_phc(struct ionic_lif *lif);
 311void ionic_lif_alloc_phc(struct ionic_lif *lif);
 312void ionic_lif_free_phc(struct ionic_lif *lif);
 313#else
 314static inline void ionic_lif_hwstamp_replay(struct ionic_lif *lif) {}
 315
 316static inline int ionic_lif_hwstamp_set(struct ionic_lif *lif, struct ifreq *ifr)
 317{
 318        return -EOPNOTSUPP;
 319}
 320
 321static inline int ionic_lif_hwstamp_get(struct ionic_lif *lif, struct ifreq *ifr)
 322{
 323        return -EOPNOTSUPP;
 324}
 325
 326static inline ktime_t ionic_lif_phc_ktime(struct ionic_lif *lif, u64 counter)
 327{
 328        return ns_to_ktime(0);
 329}
 330
 331static inline void ionic_lif_register_phc(struct ionic_lif *lif) {}
 332static inline void ionic_lif_unregister_phc(struct ionic_lif *lif) {}
 333static inline void ionic_lif_alloc_phc(struct ionic_lif *lif) {}
 334static inline void ionic_lif_free_phc(struct ionic_lif *lif) {}
 335#endif
 336
 337int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif);
 338int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif);
 339int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all);
 340int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode);
 341int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class);
 342
 343int ionic_lif_rss_config(struct ionic_lif *lif, u16 types,
 344                         const u8 *key, const u32 *indir);
 345int ionic_reconfigure_queues(struct ionic_lif *lif,
 346                             struct ionic_queue_params *qparam);
 347
 348static inline void debug_stats_txq_post(struct ionic_queue *q, bool dbell)
 349{
 350        struct ionic_txq_desc *desc = &q->txq[q->head_idx];
 351        u8 num_sg_elems;
 352
 353        q->dbell_count += dbell;
 354
 355        num_sg_elems = ((le64_to_cpu(desc->cmd) >> IONIC_TXQ_DESC_NSGE_SHIFT)
 356                                                & IONIC_TXQ_DESC_NSGE_MASK);
 357        if (num_sg_elems > (IONIC_MAX_NUM_SG_CNTR - 1))
 358                num_sg_elems = IONIC_MAX_NUM_SG_CNTR - 1;
 359
 360        q->lif->txqstats[q->index].sg_cntr[num_sg_elems]++;
 361}
 362
 363static inline void debug_stats_napi_poll(struct ionic_qcq *qcq,
 364                                         unsigned int work_done)
 365{
 366        qcq->napi_stats.poll_count++;
 367
 368        if (work_done > (IONIC_MAX_NUM_NAPI_CNTR - 1))
 369                work_done = IONIC_MAX_NUM_NAPI_CNTR - 1;
 370
 371        qcq->napi_stats.work_done_cntr[work_done]++;
 372}
 373
 374#define DEBUG_STATS_CQE_CNT(cq)         ((cq)->compl_count++)
 375#define DEBUG_STATS_RX_BUFF_CNT(q)      ((q)->lif->rxqstats[q->index].buffers_posted++)
 376#define DEBUG_STATS_TXQ_POST(q, dbell)  debug_stats_txq_post(q, dbell)
 377#define DEBUG_STATS_NAPI_POLL(qcq, work_done) \
 378        debug_stats_napi_poll(qcq, work_done)
 379
 380#endif /* _IONIC_LIF_H_ */
 381