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7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/module.h>
11#include <linux/bitops.h>
12#include <linux/cdev.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmapool.h>
15#include <linux/fs.h>
16#include <linux/hdlc.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/platform_data/wan_ixp4xx_hss.h>
21#include <linux/poll.h>
22#include <linux/slab.h>
23#include <linux/soc/ixp4xx/npe.h>
24#include <linux/soc/ixp4xx/qmgr.h>
25#include <linux/soc/ixp4xx/cpu.h>
26
27#define DEBUG_DESC 0
28#define DEBUG_RX 0
29#define DEBUG_TX 0
30#define DEBUG_PKT_BYTES 0
31#define DEBUG_CLOSE 0
32
33#define DRV_NAME "ixp4xx_hss"
34
35#define PKT_EXTRA_FLAGS 0
36#define PKT_NUM_PIPES 1
37#define PKT_PIPE_FIFO_SIZEW 4
38
39#define RX_DESCS 16
40#define TX_DESCS 16
41
42#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
43#define RX_SIZE (HDLC_MAX_MRU + 4)
44#define MAX_CLOSE_WAIT 1000
45#define HSS_COUNT 2
46#define FRAME_SIZE 256
47#define FRAME_OFFSET 0
48#define MAX_CHANNELS (FRAME_SIZE / 8)
49
50#define NAPI_WEIGHT 16
51
52
53#define HSS0_CHL_RXTRIG_QUEUE 12
54#define HSS0_PKT_RX_QUEUE 13
55#define HSS0_PKT_TX0_QUEUE 14
56#define HSS0_PKT_TX1_QUEUE 15
57#define HSS0_PKT_TX2_QUEUE 16
58#define HSS0_PKT_TX3_QUEUE 17
59#define HSS0_PKT_RXFREE0_QUEUE 18
60#define HSS0_PKT_RXFREE1_QUEUE 19
61#define HSS0_PKT_RXFREE2_QUEUE 20
62#define HSS0_PKT_RXFREE3_QUEUE 21
63#define HSS0_PKT_TXDONE_QUEUE 22
64
65#define HSS1_CHL_RXTRIG_QUEUE 10
66#define HSS1_PKT_RX_QUEUE 0
67#define HSS1_PKT_TX0_QUEUE 5
68#define HSS1_PKT_TX1_QUEUE 6
69#define HSS1_PKT_TX2_QUEUE 7
70#define HSS1_PKT_TX3_QUEUE 8
71#define HSS1_PKT_RXFREE0_QUEUE 1
72#define HSS1_PKT_RXFREE1_QUEUE 2
73#define HSS1_PKT_RXFREE2_QUEUE 3
74#define HSS1_PKT_RXFREE3_QUEUE 4
75#define HSS1_PKT_TXDONE_QUEUE 9
76
77#define NPE_PKT_MODE_HDLC 0
78#define NPE_PKT_MODE_RAW 1
79#define NPE_PKT_MODE_56KMODE 2
80#define NPE_PKT_MODE_56KENDIAN_MSB 4
81
82
83#define PKT_HDLC_IDLE_ONES 0x1
84#define PKT_HDLC_CRC_32 0x2
85#define PKT_HDLC_MSB_ENDIAN 0x4
86
87
88
89#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
90#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
91#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
92
93
94#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
95#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
96
97
98#define PCR_FCLK_EDGE_RISING 0x08000000
99#define PCR_DCLK_EDGE_RISING 0x04000000
100
101
102#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
103
104
105#define PCR_FRM_PULSE_DISABLED 0x01000000
106
107
108#define PCR_HALF_CLK_RATE 0x00200000
109
110
111#define PCR_DATA_POLARITY_INVERT 0x00100000
112
113
114#define PCR_MSB_ENDIAN 0x00080000
115
116
117#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
118
119
120#define PCR_SOF_NO_FBIT 0x00020000
121
122
123#define PCR_TX_DATA_ENABLE 0x00010000
124
125
126#define PCR_TX_V56K_HIGH 0x00002000
127#define PCR_TX_V56K_HIGH_IMP 0x00004000
128
129
130#define PCR_TX_UNASS_HIGH 0x00000800
131#define PCR_TX_UNASS_HIGH_IMP 0x00001000
132
133
134#define PCR_TX_FB_HIGH_IMP 0x00000400
135
136
137#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
138
139
140#define PCR_TX_56KS_56K_DATA 0x00000100
141
142
143
144#define CCR_NPE_HFIFO_2_HDLC 0x04000000
145#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
146
147
148#define CCR_LOOPBACK 0x02000000
149
150
151#define CCR_SECOND_HSS 0x01000000
152
153
154#define CLK42X_SPEED_EXP ((0x3FF << 22) | (2 << 12) | 15)
155
156#define CLK42X_SPEED_512KHZ ((130 << 22) | (2 << 12) | 15)
157#define CLK42X_SPEED_1536KHZ ((43 << 22) | (18 << 12) | 47)
158#define CLK42X_SPEED_1544KHZ ((43 << 22) | (33 << 12) | 192)
159#define CLK42X_SPEED_2048KHZ ((32 << 22) | (34 << 12) | 63)
160#define CLK42X_SPEED_4096KHZ ((16 << 22) | (34 << 12) | 127)
161#define CLK42X_SPEED_8192KHZ ((8 << 22) | (34 << 12) | 255)
162
163#define CLK46X_SPEED_512KHZ ((130 << 22) | (24 << 12) | 127)
164#define CLK46X_SPEED_1536KHZ ((43 << 22) | (152 << 12) | 383)
165#define CLK46X_SPEED_1544KHZ ((43 << 22) | (66 << 12) | 385)
166#define CLK46X_SPEED_2048KHZ ((32 << 22) | (280 << 12) | 511)
167#define CLK46X_SPEED_4096KHZ ((16 << 22) | (280 << 12) | 1023)
168#define CLK46X_SPEED_8192KHZ ((8 << 22) | (280 << 12) | 2047)
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193
194#define TDMMAP_UNASSIGNED 0
195#define TDMMAP_HDLC 1
196#define TDMMAP_VOICE56K 2
197#define TDMMAP_VOICE64K 3
198
199
200#define HSS_CONFIG_TX_PCR 0x00
201#define HSS_CONFIG_RX_PCR 0x04
202#define HSS_CONFIG_CORE_CR 0x08
203#define HSS_CONFIG_CLOCK_CR 0x0C
204#define HSS_CONFIG_TX_FCR 0x10
205#define HSS_CONFIG_RX_FCR 0x14
206#define HSS_CONFIG_TX_LUT 0x18
207#define HSS_CONFIG_RX_LUT 0x38
208
209
210
211#define PORT_CONFIG_WRITE 0x40
212
213
214#define PORT_CONFIG_LOAD 0x41
215
216
217#define PORT_ERROR_READ 0x42
218
219
220
221
222#define PKT_PIPE_FLOW_ENABLE 0x50
223#define PKT_PIPE_FLOW_DISABLE 0x51
224#define PKT_NUM_PIPES_WRITE 0x52
225#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
226#define PKT_PIPE_HDLC_CFG_WRITE 0x54
227#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
228#define PKT_PIPE_RX_SIZE_WRITE 0x56
229#define PKT_PIPE_MODE_WRITE 0x57
230
231
232#define ERR_SHUTDOWN 1
233#define ERR_HDLC_ALIGN 2
234#define ERR_HDLC_FCS 3
235#define ERR_RXFREE_Q_EMPTY 4
236
237
238#define ERR_HDLC_TOO_LONG 5
239#define ERR_HDLC_ABORT 6
240#define ERR_DISCONNECTING 7
241
242#ifdef __ARMEB__
243typedef struct sk_buff buffer_t;
244#define free_buffer dev_kfree_skb
245#define free_buffer_irq dev_consume_skb_irq
246#else
247typedef void buffer_t;
248#define free_buffer kfree
249#define free_buffer_irq kfree
250#endif
251
252struct port {
253 struct device *dev;
254 struct npe *npe;
255 struct net_device *netdev;
256 struct napi_struct napi;
257 struct hss_plat_info *plat;
258 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
259 struct desc *desc_tab;
260 dma_addr_t desc_tab_phys;
261 unsigned int id;
262 unsigned int clock_type, clock_rate, loopback;
263 unsigned int initialized, carrier;
264 u8 hdlc_cfg;
265 u32 clock_reg;
266};
267
268
269struct msg {
270#ifdef __ARMEB__
271 u8 cmd, unused, hss_port, index;
272 union {
273 struct { u8 data8a, data8b, data8c, data8d; };
274 struct { u16 data16a, data16b; };
275 struct { u32 data32; };
276 };
277#else
278 u8 index, hss_port, unused, cmd;
279 union {
280 struct { u8 data8d, data8c, data8b, data8a; };
281 struct { u16 data16b, data16a; };
282 struct { u32 data32; };
283 };
284#endif
285};
286
287
288struct desc {
289 u32 next;
290
291#ifdef __ARMEB__
292 u16 buf_len;
293 u16 pkt_len;
294 u32 data;
295 u8 status;
296 u8 error_count;
297 u16 __reserved;
298#else
299 u16 pkt_len;
300 u16 buf_len;
301 u32 data;
302 u16 __reserved;
303 u8 error_count;
304 u8 status;
305#endif
306 u32 __reserved1[4];
307};
308
309#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
310 (n) * sizeof(struct desc))
311#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
312
313#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
314 ((n) + RX_DESCS) * sizeof(struct desc))
315#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
316
317
318
319
320
321static int ports_open;
322static struct dma_pool *dma_pool;
323static DEFINE_SPINLOCK(npe_lock);
324
325static const struct {
326 int tx, txdone, rx, rxfree;
327} queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
328 HSS0_PKT_RXFREE0_QUEUE},
329 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
330 HSS1_PKT_RXFREE0_QUEUE},
331};
332
333
334
335
336
337static inline struct port *dev_to_port(struct net_device *dev)
338{
339 return dev_to_hdlc(dev)->priv;
340}
341
342#ifndef __ARMEB__
343static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
344{
345 int i;
346
347 for (i = 0; i < cnt; i++)
348 dest[i] = swab32(src[i]);
349}
350#endif
351
352
353
354
355
356static void hss_npe_send(struct port *port, struct msg *msg, const char *what)
357{
358 u32 *val = (u32 *)msg;
359
360 if (npe_send_message(port->npe, msg, what)) {
361 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
362 port->id, val[0], val[1], npe_name(port->npe));
363 BUG();
364 }
365}
366
367static void hss_config_set_lut(struct port *port)
368{
369 struct msg msg;
370 int ch;
371
372 memset(&msg, 0, sizeof(msg));
373 msg.cmd = PORT_CONFIG_WRITE;
374 msg.hss_port = port->id;
375
376 for (ch = 0; ch < MAX_CHANNELS; ch++) {
377 msg.data32 >>= 2;
378 msg.data32 |= TDMMAP_HDLC << 30;
379
380 if (ch % 16 == 15) {
381 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
382 hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
383
384 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
385 hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
386 }
387 }
388}
389
390static void hss_config(struct port *port)
391{
392 struct msg msg;
393
394 memset(&msg, 0, sizeof(msg));
395 msg.cmd = PORT_CONFIG_WRITE;
396 msg.hss_port = port->id;
397 msg.index = HSS_CONFIG_TX_PCR;
398 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
399 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
400 if (port->clock_type == CLOCK_INT)
401 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
402 hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
403
404 msg.index = HSS_CONFIG_RX_PCR;
405 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
406 hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
407
408 memset(&msg, 0, sizeof(msg));
409 msg.cmd = PORT_CONFIG_WRITE;
410 msg.hss_port = port->id;
411 msg.index = HSS_CONFIG_CORE_CR;
412 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
413 (port->id ? CCR_SECOND_HSS : 0);
414 hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
415
416 memset(&msg, 0, sizeof(msg));
417 msg.cmd = PORT_CONFIG_WRITE;
418 msg.hss_port = port->id;
419 msg.index = HSS_CONFIG_CLOCK_CR;
420 msg.data32 = port->clock_reg;
421 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
422
423 memset(&msg, 0, sizeof(msg));
424 msg.cmd = PORT_CONFIG_WRITE;
425 msg.hss_port = port->id;
426 msg.index = HSS_CONFIG_TX_FCR;
427 msg.data16a = FRAME_OFFSET;
428 msg.data16b = FRAME_SIZE - 1;
429 hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
430
431 memset(&msg, 0, sizeof(msg));
432 msg.cmd = PORT_CONFIG_WRITE;
433 msg.hss_port = port->id;
434 msg.index = HSS_CONFIG_RX_FCR;
435 msg.data16a = FRAME_OFFSET;
436 msg.data16b = FRAME_SIZE - 1;
437 hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
438
439 hss_config_set_lut(port);
440
441 memset(&msg, 0, sizeof(msg));
442 msg.cmd = PORT_CONFIG_LOAD;
443 msg.hss_port = port->id;
444 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
445
446 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
447
448 msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
449 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id);
450 BUG();
451 }
452
453
454 npe_recv_message(port->npe, &msg, "FLUSH_IT");
455}
456
457static void hss_set_hdlc_cfg(struct port *port)
458{
459 struct msg msg;
460
461 memset(&msg, 0, sizeof(msg));
462 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
463 msg.hss_port = port->id;
464 msg.data8a = port->hdlc_cfg;
465 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3);
466 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
467}
468
469static u32 hss_get_status(struct port *port)
470{
471 struct msg msg;
472
473 memset(&msg, 0, sizeof(msg));
474 msg.cmd = PORT_ERROR_READ;
475 msg.hss_port = port->id;
476 hss_npe_send(port, &msg, "PORT_ERROR_READ");
477 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
478 pr_crit("HSS-%i: unable to read HSS status\n", port->id);
479 BUG();
480 }
481
482 return msg.data32;
483}
484
485static void hss_start_hdlc(struct port *port)
486{
487 struct msg msg;
488
489 memset(&msg, 0, sizeof(msg));
490 msg.cmd = PKT_PIPE_FLOW_ENABLE;
491 msg.hss_port = port->id;
492 msg.data32 = 0;
493 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
494}
495
496static void hss_stop_hdlc(struct port *port)
497{
498 struct msg msg;
499
500 memset(&msg, 0, sizeof(msg));
501 msg.cmd = PKT_PIPE_FLOW_DISABLE;
502 msg.hss_port = port->id;
503 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
504 hss_get_status(port);
505}
506
507static int hss_load_firmware(struct port *port)
508{
509 struct msg msg;
510 int err;
511
512 if (port->initialized)
513 return 0;
514
515 if (!npe_running(port->npe)) {
516 err = npe_load_firmware(port->npe, npe_name(port->npe),
517 port->dev);
518 if (err)
519 return err;
520 }
521
522
523 memset(&msg, 0, sizeof(msg));
524 msg.cmd = PKT_NUM_PIPES_WRITE;
525 msg.hss_port = port->id;
526 msg.data8a = PKT_NUM_PIPES;
527 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
528
529 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
530 msg.data8a = PKT_PIPE_FIFO_SIZEW;
531 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
532
533 msg.cmd = PKT_PIPE_MODE_WRITE;
534 msg.data8a = NPE_PKT_MODE_HDLC;
535
536
537 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
538
539 msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
540 msg.data16a = HDLC_MAX_MRU;
541 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
542
543 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
544 msg.data32 = 0x7F7F7F7F;
545 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
546
547 port->initialized = 1;
548 return 0;
549}
550
551
552
553
554
555static inline void debug_pkt(struct net_device *dev, const char *func,
556 u8 *data, int len)
557{
558#if DEBUG_PKT_BYTES
559 int i;
560
561 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
562 for (i = 0; i < len; i++) {
563 if (i >= DEBUG_PKT_BYTES)
564 break;
565 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
566 }
567 printk("\n");
568#endif
569}
570
571static inline void debug_desc(u32 phys, struct desc *desc)
572{
573#if DEBUG_DESC
574 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
575 phys, desc->next, desc->buf_len, desc->pkt_len,
576 desc->data, desc->status, desc->error_count);
577#endif
578}
579
580static inline int queue_get_desc(unsigned int queue, struct port *port,
581 int is_tx)
582{
583 u32 phys, tab_phys, n_desc;
584 struct desc *tab;
585
586 phys = qmgr_get_entry(queue);
587 if (!phys)
588 return -1;
589
590 BUG_ON(phys & 0x1F);
591 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
592 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
593 n_desc = (phys - tab_phys) / sizeof(struct desc);
594 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
595 debug_desc(phys, &tab[n_desc]);
596 BUG_ON(tab[n_desc].next);
597 return n_desc;
598}
599
600static inline void queue_put_desc(unsigned int queue, u32 phys,
601 struct desc *desc)
602{
603 debug_desc(phys, desc);
604 BUG_ON(phys & 0x1F);
605 qmgr_put_entry(queue, phys);
606
607
608
609}
610
611static inline void dma_unmap_tx(struct port *port, struct desc *desc)
612{
613#ifdef __ARMEB__
614 dma_unmap_single(&port->netdev->dev, desc->data,
615 desc->buf_len, DMA_TO_DEVICE);
616#else
617 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
618 ALIGN((desc->data & 3) + desc->buf_len, 4),
619 DMA_TO_DEVICE);
620#endif
621}
622
623static void hss_hdlc_set_carrier(void *pdev, int carrier)
624{
625 struct net_device *netdev = pdev;
626 struct port *port = dev_to_port(netdev);
627 unsigned long flags;
628
629 spin_lock_irqsave(&npe_lock, flags);
630 port->carrier = carrier;
631 if (!port->loopback) {
632 if (carrier)
633 netif_carrier_on(netdev);
634 else
635 netif_carrier_off(netdev);
636 }
637 spin_unlock_irqrestore(&npe_lock, flags);
638}
639
640static void hss_hdlc_rx_irq(void *pdev)
641{
642 struct net_device *dev = pdev;
643 struct port *port = dev_to_port(dev);
644
645#if DEBUG_RX
646 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
647#endif
648 qmgr_disable_irq(queue_ids[port->id].rx);
649 napi_schedule(&port->napi);
650}
651
652static int hss_hdlc_poll(struct napi_struct *napi, int budget)
653{
654 struct port *port = container_of(napi, struct port, napi);
655 struct net_device *dev = port->netdev;
656 unsigned int rxq = queue_ids[port->id].rx;
657 unsigned int rxfreeq = queue_ids[port->id].rxfree;
658 int received = 0;
659
660#if DEBUG_RX
661 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
662#endif
663
664 while (received < budget) {
665 struct sk_buff *skb;
666 struct desc *desc;
667 int n;
668#ifdef __ARMEB__
669 struct sk_buff *temp;
670 u32 phys;
671#endif
672
673 n = queue_get_desc(rxq, port, 0);
674 if (n < 0) {
675#if DEBUG_RX
676 printk(KERN_DEBUG "%s: hss_hdlc_poll"
677 " napi_complete\n", dev->name);
678#endif
679 napi_complete(napi);
680 qmgr_enable_irq(rxq);
681 if (!qmgr_stat_empty(rxq) &&
682 napi_reschedule(napi)) {
683#if DEBUG_RX
684 printk(KERN_DEBUG "%s: hss_hdlc_poll"
685 " napi_reschedule succeeded\n",
686 dev->name);
687#endif
688 qmgr_disable_irq(rxq);
689 continue;
690 }
691#if DEBUG_RX
692 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
693 dev->name);
694#endif
695 return received;
696 }
697
698 desc = rx_desc_ptr(port, n);
699#if 0
700 if (desc->error_count)
701 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
702 " errors %u\n", dev->name, desc->status,
703 desc->error_count);
704#endif
705 skb = NULL;
706 switch (desc->status) {
707 case 0:
708#ifdef __ARMEB__
709 skb = netdev_alloc_skb(dev, RX_SIZE);
710 if (skb) {
711 phys = dma_map_single(&dev->dev, skb->data,
712 RX_SIZE,
713 DMA_FROM_DEVICE);
714 if (dma_mapping_error(&dev->dev, phys)) {
715 dev_kfree_skb(skb);
716 skb = NULL;
717 }
718 }
719#else
720 skb = netdev_alloc_skb(dev, desc->pkt_len);
721#endif
722 if (!skb)
723 dev->stats.rx_dropped++;
724 break;
725 case ERR_HDLC_ALIGN:
726 case ERR_HDLC_ABORT:
727 dev->stats.rx_frame_errors++;
728 dev->stats.rx_errors++;
729 break;
730 case ERR_HDLC_FCS:
731 dev->stats.rx_crc_errors++;
732 dev->stats.rx_errors++;
733 break;
734 case ERR_HDLC_TOO_LONG:
735 dev->stats.rx_length_errors++;
736 dev->stats.rx_errors++;
737 break;
738 default:
739 netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n",
740 desc->status, desc->error_count);
741 dev->stats.rx_errors++;
742 }
743
744 if (!skb) {
745
746 desc->buf_len = RX_SIZE;
747 desc->pkt_len = desc->status = 0;
748 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
749 continue;
750 }
751
752
753#ifdef __ARMEB__
754 temp = skb;
755 skb = port->rx_buff_tab[n];
756 dma_unmap_single(&dev->dev, desc->data,
757 RX_SIZE, DMA_FROM_DEVICE);
758#else
759 dma_sync_single_for_cpu(&dev->dev, desc->data,
760 RX_SIZE, DMA_FROM_DEVICE);
761 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
762 ALIGN(desc->pkt_len, 4) / 4);
763#endif
764 skb_put(skb, desc->pkt_len);
765
766 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
767
768 skb->protocol = hdlc_type_trans(skb, dev);
769 dev->stats.rx_packets++;
770 dev->stats.rx_bytes += skb->len;
771 netif_receive_skb(skb);
772
773
774#ifdef __ARMEB__
775 port->rx_buff_tab[n] = temp;
776 desc->data = phys;
777#endif
778 desc->buf_len = RX_SIZE;
779 desc->pkt_len = 0;
780 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
781 received++;
782 }
783#if DEBUG_RX
784 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
785#endif
786 return received;
787}
788
789static void hss_hdlc_txdone_irq(void *pdev)
790{
791 struct net_device *dev = pdev;
792 struct port *port = dev_to_port(dev);
793 int n_desc;
794
795#if DEBUG_TX
796 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
797#endif
798 while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
799 port, 1)) >= 0) {
800 struct desc *desc;
801 int start;
802
803 desc = tx_desc_ptr(port, n_desc);
804
805 dev->stats.tx_packets++;
806 dev->stats.tx_bytes += desc->pkt_len;
807
808 dma_unmap_tx(port, desc);
809#if DEBUG_TX
810 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
811 dev->name, port->tx_buff_tab[n_desc]);
812#endif
813 free_buffer_irq(port->tx_buff_tab[n_desc]);
814 port->tx_buff_tab[n_desc] = NULL;
815
816 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
817 queue_put_desc(port->plat->txreadyq,
818 tx_desc_phys(port, n_desc), desc);
819 if (start) {
820#if DEBUG_TX
821 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
822 " ready\n", dev->name);
823#endif
824 netif_wake_queue(dev);
825 }
826 }
827}
828
829static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
830{
831 struct port *port = dev_to_port(dev);
832 unsigned int txreadyq = port->plat->txreadyq;
833 int len, offset, bytes, n;
834 void *mem;
835 u32 phys;
836 struct desc *desc;
837
838#if DEBUG_TX
839 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
840#endif
841
842 if (unlikely(skb->len > HDLC_MAX_MRU)) {
843 dev_kfree_skb(skb);
844 dev->stats.tx_errors++;
845 return NETDEV_TX_OK;
846 }
847
848 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
849
850 len = skb->len;
851#ifdef __ARMEB__
852 offset = 0;
853 bytes = len;
854 mem = skb->data;
855#else
856 offset = (int)skb->data & 3;
857 bytes = ALIGN(offset + len, 4);
858 mem = kmalloc(bytes, GFP_ATOMIC);
859 if (!mem) {
860 dev_kfree_skb(skb);
861 dev->stats.tx_dropped++;
862 return NETDEV_TX_OK;
863 }
864 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
865 dev_kfree_skb(skb);
866#endif
867
868 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
869 if (dma_mapping_error(&dev->dev, phys)) {
870#ifdef __ARMEB__
871 dev_kfree_skb(skb);
872#else
873 kfree(mem);
874#endif
875 dev->stats.tx_dropped++;
876 return NETDEV_TX_OK;
877 }
878
879 n = queue_get_desc(txreadyq, port, 1);
880 BUG_ON(n < 0);
881 desc = tx_desc_ptr(port, n);
882
883#ifdef __ARMEB__
884 port->tx_buff_tab[n] = skb;
885#else
886 port->tx_buff_tab[n] = mem;
887#endif
888 desc->data = phys + offset;
889 desc->buf_len = desc->pkt_len = len;
890
891 wmb();
892 queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
893
894 if (qmgr_stat_below_low_watermark(txreadyq)) {
895#if DEBUG_TX
896 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
897#endif
898 netif_stop_queue(dev);
899
900 if (!qmgr_stat_below_low_watermark(txreadyq)) {
901#if DEBUG_TX
902 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
903 dev->name);
904#endif
905 netif_wake_queue(dev);
906 }
907 }
908
909#if DEBUG_TX
910 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
911#endif
912 return NETDEV_TX_OK;
913}
914
915static int request_hdlc_queues(struct port *port)
916{
917 int err;
918
919 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
920 "%s:RX-free", port->netdev->name);
921 if (err)
922 return err;
923
924 err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0,
925 "%s:RX", port->netdev->name);
926 if (err)
927 goto rel_rxfree;
928
929 err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0,
930 "%s:TX", port->netdev->name);
931 if (err)
932 goto rel_rx;
933
934 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
935 "%s:TX-ready", port->netdev->name);
936 if (err)
937 goto rel_tx;
938
939 err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0,
940 "%s:TX-done", port->netdev->name);
941 if (err)
942 goto rel_txready;
943 return 0;
944
945rel_txready:
946 qmgr_release_queue(port->plat->txreadyq);
947rel_tx:
948 qmgr_release_queue(queue_ids[port->id].tx);
949rel_rx:
950 qmgr_release_queue(queue_ids[port->id].rx);
951rel_rxfree:
952 qmgr_release_queue(queue_ids[port->id].rxfree);
953 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
954 port->netdev->name);
955 return err;
956}
957
958static void release_hdlc_queues(struct port *port)
959{
960 qmgr_release_queue(queue_ids[port->id].rxfree);
961 qmgr_release_queue(queue_ids[port->id].rx);
962 qmgr_release_queue(queue_ids[port->id].txdone);
963 qmgr_release_queue(queue_ids[port->id].tx);
964 qmgr_release_queue(port->plat->txreadyq);
965}
966
967static int init_hdlc_queues(struct port *port)
968{
969 int i;
970
971 if (!ports_open) {
972 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
973 POOL_ALLOC_SIZE, 32, 0);
974 if (!dma_pool)
975 return -ENOMEM;
976 }
977
978 port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
979 &port->desc_tab_phys);
980 if (!port->desc_tab)
981 return -ENOMEM;
982 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
983 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab));
984 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
985
986
987 for (i = 0; i < RX_DESCS; i++) {
988 struct desc *desc = rx_desc_ptr(port, i);
989 buffer_t *buff;
990 void *data;
991#ifdef __ARMEB__
992 buff = netdev_alloc_skb(port->netdev, RX_SIZE);
993 if (!buff)
994 return -ENOMEM;
995 data = buff->data;
996#else
997 buff = kmalloc(RX_SIZE, GFP_KERNEL);
998 if (!buff)
999 return -ENOMEM;
1000 data = buff;
1001#endif
1002 desc->buf_len = RX_SIZE;
1003 desc->data = dma_map_single(&port->netdev->dev, data,
1004 RX_SIZE, DMA_FROM_DEVICE);
1005 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1006 free_buffer(buff);
1007 return -EIO;
1008 }
1009 port->rx_buff_tab[i] = buff;
1010 }
1011
1012 return 0;
1013}
1014
1015static void destroy_hdlc_queues(struct port *port)
1016{
1017 int i;
1018
1019 if (port->desc_tab) {
1020 for (i = 0; i < RX_DESCS; i++) {
1021 struct desc *desc = rx_desc_ptr(port, i);
1022 buffer_t *buff = port->rx_buff_tab[i];
1023
1024 if (buff) {
1025 dma_unmap_single(&port->netdev->dev,
1026 desc->data, RX_SIZE,
1027 DMA_FROM_DEVICE);
1028 free_buffer(buff);
1029 }
1030 }
1031 for (i = 0; i < TX_DESCS; i++) {
1032 struct desc *desc = tx_desc_ptr(port, i);
1033 buffer_t *buff = port->tx_buff_tab[i];
1034
1035 if (buff) {
1036 dma_unmap_tx(port, desc);
1037 free_buffer(buff);
1038 }
1039 }
1040 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1041 port->desc_tab = NULL;
1042 }
1043
1044 if (!ports_open && dma_pool) {
1045 dma_pool_destroy(dma_pool);
1046 dma_pool = NULL;
1047 }
1048}
1049
1050static int hss_hdlc_open(struct net_device *dev)
1051{
1052 struct port *port = dev_to_port(dev);
1053 unsigned long flags;
1054 int i, err = 0;
1055
1056 err = hdlc_open(dev);
1057 if (err)
1058 return err;
1059
1060 err = hss_load_firmware(port);
1061 if (err)
1062 goto err_hdlc_close;
1063
1064 err = request_hdlc_queues(port);
1065 if (err)
1066 goto err_hdlc_close;
1067
1068 err = init_hdlc_queues(port);
1069 if (err)
1070 goto err_destroy_queues;
1071
1072 spin_lock_irqsave(&npe_lock, flags);
1073 if (port->plat->open) {
1074 err = port->plat->open(port->id, dev, hss_hdlc_set_carrier);
1075 if (err)
1076 goto err_unlock;
1077 }
1078
1079 spin_unlock_irqrestore(&npe_lock, flags);
1080
1081
1082 for (i = 0; i < TX_DESCS; i++)
1083 queue_put_desc(port->plat->txreadyq,
1084 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1085
1086 for (i = 0; i < RX_DESCS; i++)
1087 queue_put_desc(queue_ids[port->id].rxfree,
1088 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1089
1090 napi_enable(&port->napi);
1091 netif_start_queue(dev);
1092
1093 qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1094 hss_hdlc_rx_irq, dev);
1095
1096 qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1097 hss_hdlc_txdone_irq, dev);
1098 qmgr_enable_irq(queue_ids[port->id].txdone);
1099
1100 ports_open++;
1101
1102 hss_set_hdlc_cfg(port);
1103 hss_config(port);
1104
1105 hss_start_hdlc(port);
1106
1107
1108 napi_schedule(&port->napi);
1109 return 0;
1110
1111err_unlock:
1112 spin_unlock_irqrestore(&npe_lock, flags);
1113err_destroy_queues:
1114 destroy_hdlc_queues(port);
1115 release_hdlc_queues(port);
1116err_hdlc_close:
1117 hdlc_close(dev);
1118 return err;
1119}
1120
1121static int hss_hdlc_close(struct net_device *dev)
1122{
1123 struct port *port = dev_to_port(dev);
1124 unsigned long flags;
1125 int i, buffs = RX_DESCS;
1126
1127 spin_lock_irqsave(&npe_lock, flags);
1128 ports_open--;
1129 qmgr_disable_irq(queue_ids[port->id].rx);
1130 netif_stop_queue(dev);
1131 napi_disable(&port->napi);
1132
1133 hss_stop_hdlc(port);
1134
1135 while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1136 buffs--;
1137 while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1138 buffs--;
1139
1140 if (buffs)
1141 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n",
1142 buffs);
1143
1144 buffs = TX_DESCS;
1145 while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1146 buffs--;
1147
1148 i = 0;
1149 do {
1150 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1151 buffs--;
1152 if (!buffs)
1153 break;
1154 } while (++i < MAX_CLOSE_WAIT);
1155
1156 if (buffs)
1157 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n",
1158 buffs);
1159#if DEBUG_CLOSE
1160 if (!buffs)
1161 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1162#endif
1163 qmgr_disable_irq(queue_ids[port->id].txdone);
1164
1165 if (port->plat->close)
1166 port->plat->close(port->id, dev);
1167 spin_unlock_irqrestore(&npe_lock, flags);
1168
1169 destroy_hdlc_queues(port);
1170 release_hdlc_queues(port);
1171 hdlc_close(dev);
1172 return 0;
1173}
1174
1175static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1176 unsigned short parity)
1177{
1178 struct port *port = dev_to_port(dev);
1179
1180 if (encoding != ENCODING_NRZ)
1181 return -EINVAL;
1182
1183 switch (parity) {
1184 case PARITY_CRC16_PR1_CCITT:
1185 port->hdlc_cfg = 0;
1186 return 0;
1187
1188 case PARITY_CRC32_PR1_CCITT:
1189 port->hdlc_cfg = PKT_HDLC_CRC_32;
1190 return 0;
1191
1192 default:
1193 return -EINVAL;
1194 }
1195}
1196
1197static u32 check_clock(u32 timer_freq, u32 rate, u32 a, u32 b, u32 c,
1198 u32 *best, u32 *best_diff, u32 *reg)
1199{
1200
1201 u64 new_rate;
1202 u32 new_diff;
1203
1204 new_rate = timer_freq * (u64)(c + 1);
1205 do_div(new_rate, a * (c + 1) + b + 1);
1206 new_diff = abs((u32)new_rate - rate);
1207
1208 if (new_diff < *best_diff) {
1209 *best = new_rate;
1210 *best_diff = new_diff;
1211 *reg = (a << 22) | (b << 12) | c;
1212 }
1213 return new_diff;
1214}
1215
1216static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg)
1217{
1218 u32 a, b, diff = 0xFFFFFFFF;
1219
1220 a = timer_freq / rate;
1221
1222 if (a > 0x3FF) {
1223 check_clock(timer_freq, rate, 0x3FF, 1, 1, best, &diff, reg);
1224 return;
1225 }
1226 if (a == 0) {
1227 a = 1;
1228 rate = timer_freq;
1229 }
1230
1231 if (rate * a == timer_freq) {
1232 check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg);
1233 return;
1234 }
1235
1236 for (b = 0; b < 0x400; b++) {
1237 u64 c = (b + 1) * (u64)rate;
1238
1239 do_div(c, timer_freq - rate * a);
1240 c--;
1241 if (c >= 0xFFF) {
1242 if (b == 0 &&
1243 !check_clock(timer_freq, rate, a - 1, 1, 1, best,
1244 &diff, reg))
1245 return;
1246 check_clock(timer_freq, rate, a, b, 0xFFF, best,
1247 &diff, reg);
1248 return;
1249 }
1250 if (!check_clock(timer_freq, rate, a, b, c, best, &diff, reg))
1251 return;
1252 if (!check_clock(timer_freq, rate, a, b, c + 1, best, &diff,
1253 reg))
1254 return;
1255 }
1256}
1257
1258static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1259{
1260 const size_t size = sizeof(sync_serial_settings);
1261 sync_serial_settings new_line;
1262 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1263 struct port *port = dev_to_port(dev);
1264 unsigned long flags;
1265 int clk;
1266
1267 if (cmd != SIOCWANDEV)
1268 return hdlc_ioctl(dev, ifr, cmd);
1269
1270 switch (ifr->ifr_settings.type) {
1271 case IF_GET_IFACE:
1272 ifr->ifr_settings.type = IF_IFACE_V35;
1273 if (ifr->ifr_settings.size < size) {
1274 ifr->ifr_settings.size = size;
1275 return -ENOBUFS;
1276 }
1277 memset(&new_line, 0, sizeof(new_line));
1278 new_line.clock_type = port->clock_type;
1279 new_line.clock_rate = port->clock_rate;
1280 new_line.loopback = port->loopback;
1281 if (copy_to_user(line, &new_line, size))
1282 return -EFAULT;
1283 return 0;
1284
1285 case IF_IFACE_SYNC_SERIAL:
1286 case IF_IFACE_V35:
1287 if (!capable(CAP_NET_ADMIN))
1288 return -EPERM;
1289 if (copy_from_user(&new_line, line, size))
1290 return -EFAULT;
1291
1292 clk = new_line.clock_type;
1293 if (port->plat->set_clock)
1294 clk = port->plat->set_clock(port->id, clk);
1295
1296 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1297 return -EINVAL;
1298
1299 if (new_line.loopback != 0 && new_line.loopback != 1)
1300 return -EINVAL;
1301
1302 port->clock_type = clk;
1303 if (clk == CLOCK_INT) {
1304 find_best_clock(port->plat->timer_freq,
1305 new_line.clock_rate,
1306 &port->clock_rate, &port->clock_reg);
1307 } else {
1308 port->clock_rate = 0;
1309 port->clock_reg = CLK42X_SPEED_2048KHZ;
1310 }
1311 port->loopback = new_line.loopback;
1312
1313 spin_lock_irqsave(&npe_lock, flags);
1314
1315 if (dev->flags & IFF_UP)
1316 hss_config(port);
1317
1318 if (port->loopback || port->carrier)
1319 netif_carrier_on(port->netdev);
1320 else
1321 netif_carrier_off(port->netdev);
1322 spin_unlock_irqrestore(&npe_lock, flags);
1323
1324 return 0;
1325
1326 default:
1327 return hdlc_ioctl(dev, ifr, cmd);
1328 }
1329}
1330
1331
1332
1333
1334
1335static const struct net_device_ops hss_hdlc_ops = {
1336 .ndo_open = hss_hdlc_open,
1337 .ndo_stop = hss_hdlc_close,
1338 .ndo_start_xmit = hdlc_start_xmit,
1339 .ndo_do_ioctl = hss_hdlc_ioctl,
1340};
1341
1342static int hss_init_one(struct platform_device *pdev)
1343{
1344 struct port *port;
1345 struct net_device *dev;
1346 hdlc_device *hdlc;
1347 int err;
1348
1349 port = kzalloc(sizeof(*port), GFP_KERNEL);
1350 if (!port)
1351 return -ENOMEM;
1352
1353 port->npe = npe_request(0);
1354 if (!port->npe) {
1355 err = -ENODEV;
1356 goto err_free;
1357 }
1358
1359 dev = alloc_hdlcdev(port);
1360 port->netdev = alloc_hdlcdev(port);
1361 if (!port->netdev) {
1362 err = -ENOMEM;
1363 goto err_plat;
1364 }
1365
1366 SET_NETDEV_DEV(dev, &pdev->dev);
1367 hdlc = dev_to_hdlc(dev);
1368 hdlc->attach = hss_hdlc_attach;
1369 hdlc->xmit = hss_hdlc_xmit;
1370 dev->netdev_ops = &hss_hdlc_ops;
1371 dev->tx_queue_len = 100;
1372 port->clock_type = CLOCK_EXT;
1373 port->clock_rate = 0;
1374 port->clock_reg = CLK42X_SPEED_2048KHZ;
1375 port->id = pdev->id;
1376 port->dev = &pdev->dev;
1377 port->plat = pdev->dev.platform_data;
1378 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1379
1380 err = register_hdlc_device(dev);
1381 if (err)
1382 goto err_free_netdev;
1383
1384 platform_set_drvdata(pdev, port);
1385
1386 netdev_info(dev, "initialized\n");
1387 return 0;
1388
1389err_free_netdev:
1390 free_netdev(dev);
1391err_plat:
1392 npe_release(port->npe);
1393err_free:
1394 kfree(port);
1395 return err;
1396}
1397
1398static int hss_remove_one(struct platform_device *pdev)
1399{
1400 struct port *port = platform_get_drvdata(pdev);
1401
1402 unregister_hdlc_device(port->netdev);
1403 free_netdev(port->netdev);
1404 npe_release(port->npe);
1405 kfree(port);
1406 return 0;
1407}
1408
1409static struct platform_driver ixp4xx_hss_driver = {
1410 .driver.name = DRV_NAME,
1411 .probe = hss_init_one,
1412 .remove = hss_remove_one,
1413};
1414
1415static int __init hss_init_module(void)
1416{
1417 if ((ixp4xx_read_feature_bits() &
1418 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1419 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
1420 return -ENODEV;
1421
1422 return platform_driver_register(&ixp4xx_hss_driver);
1423}
1424
1425static void __exit hss_cleanup_module(void)
1426{
1427 platform_driver_unregister(&ixp4xx_hss_driver);
1428}
1429
1430MODULE_AUTHOR("Krzysztof Halasa");
1431MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1432MODULE_LICENSE("GPL v2");
1433MODULE_ALIAS("platform:ixp4xx_hss");
1434module_init(hss_init_module);
1435module_exit(hss_cleanup_module);
1436