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5#ifndef ATH11K_RX_DESC_H
6#define ATH11K_RX_DESC_H
7
8enum rx_desc_rxpcu_filter {
9 RX_DESC_RXPCU_FILTER_PASS,
10 RX_DESC_RXPCU_FILTER_MONITOR_CLIENT,
11 RX_DESC_RXPCU_FILTER_MONITOR_OTHER,
12};
13
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27
28#define RX_DESC_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)
29#define RX_DESC_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2)
30
31enum rx_desc_sw_frame_grp_id {
32 RX_DESC_SW_FRAME_GRP_ID_NDP_FRAME,
33 RX_DESC_SW_FRAME_GRP_ID_MCAST_DATA,
34 RX_DESC_SW_FRAME_GRP_ID_UCAST_DATA,
35 RX_DESC_SW_FRAME_GRP_ID_NULL_DATA,
36 RX_DESC_SW_FRAME_GRP_ID_MGMT_0000,
37 RX_DESC_SW_FRAME_GRP_ID_MGMT_0001,
38 RX_DESC_SW_FRAME_GRP_ID_MGMT_0010,
39 RX_DESC_SW_FRAME_GRP_ID_MGMT_0011,
40 RX_DESC_SW_FRAME_GRP_ID_MGMT_0100,
41 RX_DESC_SW_FRAME_GRP_ID_MGMT_0101,
42 RX_DESC_SW_FRAME_GRP_ID_MGMT_0110,
43 RX_DESC_SW_FRAME_GRP_ID_MGMT_0111,
44 RX_DESC_SW_FRAME_GRP_ID_MGMT_1000,
45 RX_DESC_SW_FRAME_GRP_ID_MGMT_1001,
46 RX_DESC_SW_FRAME_GRP_ID_MGMT_1010,
47 RX_DESC_SW_FRAME_GRP_ID_MGMT_1011,
48 RX_DESC_SW_FRAME_GRP_ID_MGMT_1100,
49 RX_DESC_SW_FRAME_GRP_ID_MGMT_1101,
50 RX_DESC_SW_FRAME_GRP_ID_MGMT_1110,
51 RX_DESC_SW_FRAME_GRP_ID_MGMT_1111,
52 RX_DESC_SW_FRAME_GRP_ID_CTRL_0000,
53 RX_DESC_SW_FRAME_GRP_ID_CTRL_0001,
54 RX_DESC_SW_FRAME_GRP_ID_CTRL_0010,
55 RX_DESC_SW_FRAME_GRP_ID_CTRL_0011,
56 RX_DESC_SW_FRAME_GRP_ID_CTRL_0100,
57 RX_DESC_SW_FRAME_GRP_ID_CTRL_0101,
58 RX_DESC_SW_FRAME_GRP_ID_CTRL_0110,
59 RX_DESC_SW_FRAME_GRP_ID_CTRL_0111,
60 RX_DESC_SW_FRAME_GRP_ID_CTRL_1000,
61 RX_DESC_SW_FRAME_GRP_ID_CTRL_1001,
62 RX_DESC_SW_FRAME_GRP_ID_CTRL_1010,
63 RX_DESC_SW_FRAME_GRP_ID_CTRL_1011,
64 RX_DESC_SW_FRAME_GRP_ID_CTRL_1100,
65 RX_DESC_SW_FRAME_GRP_ID_CTRL_1101,
66 RX_DESC_SW_FRAME_GRP_ID_CTRL_1110,
67 RX_DESC_SW_FRAME_GRP_ID_CTRL_1111,
68 RX_DESC_SW_FRAME_GRP_ID_UNSUPPORTED,
69 RX_DESC_SW_FRAME_GRP_ID_PHY_ERR,
70};
71
72enum rx_desc_decap_type {
73 RX_DESC_DECAP_TYPE_RAW,
74 RX_DESC_DECAP_TYPE_NATIVE_WIFI,
75 RX_DESC_DECAP_TYPE_ETHERNET2_DIX,
76 RX_DESC_DECAP_TYPE_8023,
77};
78
79enum rx_desc_decrypt_status_code {
80 RX_DESC_DECRYPT_STATUS_CODE_OK,
81 RX_DESC_DECRYPT_STATUS_CODE_UNPROTECTED_FRAME,
82 RX_DESC_DECRYPT_STATUS_CODE_DATA_ERR,
83 RX_DESC_DECRYPT_STATUS_CODE_KEY_INVALID,
84 RX_DESC_DECRYPT_STATUS_CODE_PEER_ENTRY_INVALID,
85 RX_DESC_DECRYPT_STATUS_CODE_OTHER,
86};
87
88#define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0)
89#define RX_ATTENTION_INFO1_RSVD_1A BIT(1)
90#define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2)
91#define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3)
92#define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4)
93#define RX_ATTENTION_INFO1_POWER_MGMT BIT(5)
94#define RX_ATTENTION_INFO1_NON_QOS BIT(6)
95#define RX_ATTENTION_INFO1_NULL_DATA BIT(7)
96#define RX_ATTENTION_INFO1_MGMT_TYPE BIT(8)
97#define RX_ATTENTION_INFO1_CTRL_TYPE BIT(9)
98#define RX_ATTENTION_INFO1_MORE_DATA BIT(10)
99#define RX_ATTENTION_INFO1_EOSP BIT(11)
100#define RX_ATTENTION_INFO1_A_MSDU_ERROR BIT(12)
101#define RX_ATTENTION_INFO1_FRAGMENT BIT(13)
102#define RX_ATTENTION_INFO1_ORDER BIT(14)
103#define RX_ATTENTION_INFO1_CCE_MATCH BIT(15)
104#define RX_ATTENTION_INFO1_OVERFLOW_ERR BIT(16)
105#define RX_ATTENTION_INFO1_MSDU_LEN_ERR BIT(17)
106#define RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL BIT(18)
107#define RX_ATTENTION_INFO1_IP_CKSUM_FAIL BIT(19)
108#define RX_ATTENTION_INFO1_SA_IDX_INVALID BIT(20)
109#define RX_ATTENTION_INFO1_DA_IDX_INVALID BIT(21)
110#define RX_ATTENTION_INFO1_RSVD_1B BIT(22)
111#define RX_ATTENTION_INFO1_RX_IN_TX_DECRYPT_BYP BIT(23)
112#define RX_ATTENTION_INFO1_ENCRYPT_REQUIRED BIT(24)
113#define RX_ATTENTION_INFO1_DIRECTED BIT(25)
114#define RX_ATTENTION_INFO1_BUFFER_FRAGMENT BIT(26)
115#define RX_ATTENTION_INFO1_MPDU_LEN_ERR BIT(27)
116#define RX_ATTENTION_INFO1_TKIP_MIC_ERR BIT(28)
117#define RX_ATTENTION_INFO1_DECRYPT_ERR BIT(29)
118#define RX_ATTENTION_INFO1_UNDECRYPT_FRAME_ERR BIT(30)
119#define RX_ATTENTION_INFO1_FCS_ERR BIT(31)
120
121#define RX_ATTENTION_INFO2_FLOW_IDX_TIMEOUT BIT(0)
122#define RX_ATTENTION_INFO2_FLOW_IDX_INVALID BIT(1)
123#define RX_ATTENTION_INFO2_WIFI_PARSER_ERR BIT(2)
124#define RX_ATTENTION_INFO2_AMSDU_PARSER_ERR BIT(3)
125#define RX_ATTENTION_INFO2_SA_IDX_TIMEOUT BIT(4)
126#define RX_ATTENTION_INFO2_DA_IDX_TIMEOUT BIT(5)
127#define RX_ATTENTION_INFO2_MSDU_LIMIT_ERR BIT(6)
128#define RX_ATTENTION_INFO2_DA_IS_VALID BIT(7)
129#define RX_ATTENTION_INFO2_DA_IS_MCBC BIT(8)
130#define RX_ATTENTION_INFO2_SA_IS_VALID BIT(9)
131#define RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE GENMASK(12, 10)
132#define RX_ATTENTION_INFO2_RX_BITMAP_NOT_UPDED BIT(13)
133#define RX_ATTENTION_INFO2_MSDU_DONE BIT(31)
134
135struct rx_attention {
136 __le16 info0;
137 __le16 phy_ppdu_id;
138 __le32 info1;
139 __le32 info2;
140} __packed;
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339#define RX_MPDU_START_INFO0_NDP_FRAME BIT(9)
340#define RX_MPDU_START_INFO0_PHY_ERR BIT(10)
341#define RX_MPDU_START_INFO0_PHY_ERR_MPDU_HDR BIT(11)
342#define RX_MPDU_START_INFO0_PROTO_VER_ERR BIT(12)
343#define RX_MPDU_START_INFO0_AST_LOOKUP_VALID BIT(13)
344
345#define RX_MPDU_START_INFO1_MPDU_FCTRL_VALID BIT(0)
346#define RX_MPDU_START_INFO1_MPDU_DUR_VALID BIT(1)
347#define RX_MPDU_START_INFO1_MAC_ADDR1_VALID BIT(2)
348#define RX_MPDU_START_INFO1_MAC_ADDR2_VALID BIT(3)
349#define RX_MPDU_START_INFO1_MAC_ADDR3_VALID BIT(4)
350#define RX_MPDU_START_INFO1_MAC_ADDR4_VALID BIT(5)
351#define RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID BIT(6)
352#define RX_MPDU_START_INFO1_MPDU_QOS_CTRL_VALID BIT(7)
353#define RX_MPDU_START_INFO1_MPDU_HT_CTRL_VALID BIT(8)
354#define RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID BIT(9)
355#define RX_MPDU_START_INFO1_MPDU_FRAG_NUMBER GENMASK(13, 10)
356#define RX_MPDU_START_INFO1_MORE_FRAG_FLAG BIT(14)
357#define RX_MPDU_START_INFO1_FROM_DS BIT(16)
358#define RX_MPDU_START_INFO1_TO_DS BIT(17)
359#define RX_MPDU_START_INFO1_ENCRYPTED BIT(18)
360#define RX_MPDU_START_INFO1_MPDU_RETRY BIT(19)
361#define RX_MPDU_START_INFO1_MPDU_SEQ_NUM GENMASK(31, 20)
362
363#define RX_MPDU_START_INFO2_EPD_EN BIT(0)
364#define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD BIT(1)
365#define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2)
366#define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH GENMASK(7, 6)
367#define RX_MPDU_START_INFO2_MESH_STA BIT(8)
368#define RX_MPDU_START_INFO2_BSSID_HIT BIT(9)
369#define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(13, 10)
370#define RX_MPDU_START_INFO2_TID GENMASK(17, 14)
371#define RX_MPDU_START_INFO2_TID_WCN6855 GENMASK(18, 15)
372
373#define RX_MPDU_START_INFO3_REO_DEST_IND GENMASK(4, 0)
374#define RX_MPDU_START_INFO3_FLOW_ID_TOEPLITZ BIT(7)
375#define RX_MPDU_START_INFO3_PKT_SEL_FP_UCAST_DATA BIT(8)
376#define RX_MPDU_START_INFO3_PKT_SEL_FP_MCAST_DATA BIT(9)
377#define RX_MPDU_START_INFO3_PKT_SEL_FP_CTRL_BAR BIT(10)
378#define RX_MPDU_START_INFO3_RXDMA0_SRC_RING_SEL GENMASK(12, 11)
379#define RX_MPDU_START_INFO3_RXDMA0_DST_RING_SEL GENMASK(14, 13)
380
381#define RX_MPDU_START_INFO4_REO_QUEUE_DESC_HI GENMASK(7, 0)
382#define RX_MPDU_START_INFO4_RECV_QUEUE_NUM GENMASK(23, 8)
383#define RX_MPDU_START_INFO4_PRE_DELIM_ERR_WARN BIT(24)
384#define RX_MPDU_START_INFO4_FIRST_DELIM_ERR BIT(25)
385
386#define RX_MPDU_START_INFO5_KEY_ID GENMASK(7, 0)
387#define RX_MPDU_START_INFO5_NEW_PEER_ENTRY BIT(8)
388#define RX_MPDU_START_INFO5_DECRYPT_NEEDED BIT(9)
389#define RX_MPDU_START_INFO5_DECAP_TYPE GENMASK(11, 10)
390#define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING BIT(12)
391#define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING BIT(13)
392#define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C BIT(14)
393#define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S BIT(15)
394#define RX_MPDU_START_INFO5_PRE_DELIM_COUNT GENMASK(27, 16)
395#define RX_MPDU_START_INFO5_AMPDU_FLAG BIT(28)
396#define RX_MPDU_START_INFO5_BAR_FRAME BIT(29)
397
398#define RX_MPDU_START_INFO6_MPDU_LEN GENMASK(13, 0)
399#define RX_MPDU_START_INFO6_FIRST_MPDU BIT(14)
400#define RX_MPDU_START_INFO6_MCAST_BCAST BIT(15)
401#define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND BIT(16)
402#define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT BIT(17)
403#define RX_MPDU_START_INFO6_POWER_MGMT BIT(18)
404#define RX_MPDU_START_INFO6_NON_QOS BIT(19)
405#define RX_MPDU_START_INFO6_NULL_DATA BIT(20)
406#define RX_MPDU_START_INFO6_MGMT_TYPE BIT(21)
407#define RX_MPDU_START_INFO6_CTRL_TYPE BIT(22)
408#define RX_MPDU_START_INFO6_MORE_DATA BIT(23)
409#define RX_MPDU_START_INFO6_EOSP BIT(24)
410#define RX_MPDU_START_INFO6_FRAGMENT BIT(25)
411#define RX_MPDU_START_INFO6_ORDER BIT(26)
412#define RX_MPDU_START_INFO6_UAPSD_TRIGGER BIT(27)
413#define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED BIT(28)
414#define RX_MPDU_START_INFO6_DIRECTED BIT(29)
415
416#define RX_MPDU_START_RAW_MPDU BIT(0)
417
418struct rx_mpdu_start_ipq8074 {
419 __le16 info0;
420 __le16 phy_ppdu_id;
421 __le16 ast_index;
422 __le16 sw_peer_id;
423 __le32 info1;
424 __le32 info2;
425 __le32 pn[4];
426 __le32 peer_meta_data;
427 __le32 info3;
428 __le32 reo_queue_desc_lo;
429 __le32 info4;
430 __le32 info5;
431 __le32 info6;
432 __le16 frame_ctrl;
433 __le16 duration;
434 u8 addr1[ETH_ALEN];
435 u8 addr2[ETH_ALEN];
436 u8 addr3[ETH_ALEN];
437 __le16 seq_ctrl;
438 u8 addr4[ETH_ALEN];
439 __le16 qos_ctrl;
440 __le32 ht_ctrl;
441 __le32 raw;
442} __packed;
443
444#define RX_MPDU_START_INFO7_REO_DEST_IND GENMASK(4, 0)
445#define RX_MPDU_START_INFO7_LMAC_PEER_ID_MSB GENMASK(6, 5)
446#define RX_MPDU_START_INFO7_FLOW_ID_TOEPLITZ BIT(7)
447#define RX_MPDU_START_INFO7_PKT_SEL_FP_UCAST_DATA BIT(8)
448#define RX_MPDU_START_INFO7_PKT_SEL_FP_MCAST_DATA BIT(9)
449#define RX_MPDU_START_INFO7_PKT_SEL_FP_CTRL_BAR BIT(10)
450#define RX_MPDU_START_INFO7_RXDMA0_SRC_RING_SEL GENMASK(12, 11)
451#define RX_MPDU_START_INFO7_RXDMA0_DST_RING_SEL GENMASK(14, 13)
452
453#define RX_MPDU_START_INFO8_REO_QUEUE_DESC_HI GENMASK(7, 0)
454#define RX_MPDU_START_INFO8_RECV_QUEUE_NUM GENMASK(23, 8)
455#define RX_MPDU_START_INFO8_PRE_DELIM_ERR_WARN BIT(24)
456#define RX_MPDU_START_INFO8_FIRST_DELIM_ERR BIT(25)
457
458#define RX_MPDU_START_INFO9_EPD_EN BIT(0)
459#define RX_MPDU_START_INFO9_ALL_FRAME_ENCPD BIT(1)
460#define RX_MPDU_START_INFO9_ENC_TYPE GENMASK(5, 2)
461#define RX_MPDU_START_INFO9_VAR_WEP_KEY_WIDTH GENMASK(7, 6)
462#define RX_MPDU_START_INFO9_MESH_STA GENMASK(9, 8)
463#define RX_MPDU_START_INFO9_BSSID_HIT BIT(10)
464#define RX_MPDU_START_INFO9_BSSID_NUM GENMASK(14, 11)
465#define RX_MPDU_START_INFO9_TID GENMASK(18, 15)
466
467#define RX_MPDU_START_INFO10_RXPCU_MPDU_FLTR GENMASK(1, 0)
468#define RX_MPDU_START_INFO10_SW_FRAME_GRP_ID GENMASK(8, 2)
469#define RX_MPDU_START_INFO10_NDP_FRAME BIT(9)
470#define RX_MPDU_START_INFO10_PHY_ERR BIT(10)
471#define RX_MPDU_START_INFO10_PHY_ERR_MPDU_HDR BIT(11)
472#define RX_MPDU_START_INFO10_PROTO_VER_ERR BIT(12)
473#define RX_MPDU_START_INFO10_AST_LOOKUP_VALID BIT(13)
474
475#define RX_MPDU_START_INFO11_MPDU_FCTRL_VALID BIT(0)
476#define RX_MPDU_START_INFO11_MPDU_DUR_VALID BIT(1)
477#define RX_MPDU_START_INFO11_MAC_ADDR1_VALID BIT(2)
478#define RX_MPDU_START_INFO11_MAC_ADDR2_VALID BIT(3)
479#define RX_MPDU_START_INFO11_MAC_ADDR3_VALID BIT(4)
480#define RX_MPDU_START_INFO11_MAC_ADDR4_VALID BIT(5)
481#define RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID BIT(6)
482#define RX_MPDU_START_INFO11_MPDU_QOS_CTRL_VALID BIT(7)
483#define RX_MPDU_START_INFO11_MPDU_HT_CTRL_VALID BIT(8)
484#define RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID BIT(9)
485#define RX_MPDU_START_INFO11_MPDU_FRAG_NUMBER GENMASK(13, 10)
486#define RX_MPDU_START_INFO11_MORE_FRAG_FLAG BIT(14)
487#define RX_MPDU_START_INFO11_FROM_DS BIT(16)
488#define RX_MPDU_START_INFO11_TO_DS BIT(17)
489#define RX_MPDU_START_INFO11_ENCRYPTED BIT(18)
490#define RX_MPDU_START_INFO11_MPDU_RETRY BIT(19)
491#define RX_MPDU_START_INFO11_MPDU_SEQ_NUM GENMASK(31, 20)
492
493#define RX_MPDU_START_INFO12_KEY_ID GENMASK(7, 0)
494#define RX_MPDU_START_INFO12_NEW_PEER_ENTRY BIT(8)
495#define RX_MPDU_START_INFO12_DECRYPT_NEEDED BIT(9)
496#define RX_MPDU_START_INFO12_DECAP_TYPE GENMASK(11, 10)
497#define RX_MPDU_START_INFO12_VLAN_TAG_C_PADDING BIT(12)
498#define RX_MPDU_START_INFO12_VLAN_TAG_S_PADDING BIT(13)
499#define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_C BIT(14)
500#define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_S BIT(15)
501#define RX_MPDU_START_INFO12_PRE_DELIM_COUNT GENMASK(27, 16)
502#define RX_MPDU_START_INFO12_AMPDU_FLAG BIT(28)
503#define RX_MPDU_START_INFO12_BAR_FRAME BIT(29)
504#define RX_MPDU_START_INFO12_RAW_MPDU BIT(30)
505
506#define RX_MPDU_START_INFO13_MPDU_LEN GENMASK(13, 0)
507#define RX_MPDU_START_INFO13_FIRST_MPDU BIT(14)
508#define RX_MPDU_START_INFO13_MCAST_BCAST BIT(15)
509#define RX_MPDU_START_INFO13_AST_IDX_NOT_FOUND BIT(16)
510#define RX_MPDU_START_INFO13_AST_IDX_TIMEOUT BIT(17)
511#define RX_MPDU_START_INFO13_POWER_MGMT BIT(18)
512#define RX_MPDU_START_INFO13_NON_QOS BIT(19)
513#define RX_MPDU_START_INFO13_NULL_DATA BIT(20)
514#define RX_MPDU_START_INFO13_MGMT_TYPE BIT(21)
515#define RX_MPDU_START_INFO13_CTRL_TYPE BIT(22)
516#define RX_MPDU_START_INFO13_MORE_DATA BIT(23)
517#define RX_MPDU_START_INFO13_EOSP BIT(24)
518#define RX_MPDU_START_INFO13_FRAGMENT BIT(25)
519#define RX_MPDU_START_INFO13_ORDER BIT(26)
520#define RX_MPDU_START_INFO13_UAPSD_TRIGGER BIT(27)
521#define RX_MPDU_START_INFO13_ENCRYPT_REQUIRED BIT(28)
522#define RX_MPDU_START_INFO13_DIRECTED BIT(29)
523#define RX_MPDU_START_INFO13_AMSDU_PRESENT BIT(30)
524
525struct rx_mpdu_start_qcn9074 {
526 __le32 info7;
527 __le32 reo_queue_desc_lo;
528 __le32 info8;
529 __le32 pn[4];
530 __le32 info9;
531 __le32 peer_meta_data;
532 __le16 info10;
533 __le16 phy_ppdu_id;
534 __le16 ast_index;
535 __le16 sw_peer_id;
536 __le32 info11;
537 __le32 info12;
538 __le32 info13;
539 __le16 frame_ctrl;
540 __le16 duration;
541 u8 addr1[ETH_ALEN];
542 u8 addr2[ETH_ALEN];
543 u8 addr3[ETH_ALEN];
544 __le16 seq_ctrl;
545 u8 addr4[ETH_ALEN];
546 __le16 qos_ctrl;
547 __le32 ht_ctrl;
548} __packed;
549
550struct rx_mpdu_start_wcn6855 {
551 __le32 info3;
552 __le32 reo_queue_desc_lo;
553 __le32 info4;
554 __le32 pn[4];
555 __le32 info2;
556 __le32 peer_meta_data;
557 __le16 info0;
558 __le16 phy_ppdu_id;
559 __le16 ast_index;
560 __le16 sw_peer_id;
561 __le32 info1;
562 __le32 info5;
563 __le32 info6;
564 __le16 frame_ctrl;
565 __le16 duration;
566 u8 addr1[ETH_ALEN];
567 u8 addr2[ETH_ALEN];
568 u8 addr3[ETH_ALEN];
569 __le16 seq_ctrl;
570 u8 addr4[ETH_ALEN];
571 __le16 qos_ctrl;
572 __le32 ht_ctrl;
573} __packed;
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741enum rx_msdu_start_pkt_type {
742 RX_MSDU_START_PKT_TYPE_11A,
743 RX_MSDU_START_PKT_TYPE_11B,
744 RX_MSDU_START_PKT_TYPE_11N,
745 RX_MSDU_START_PKT_TYPE_11AC,
746 RX_MSDU_START_PKT_TYPE_11AX,
747};
748
749enum rx_msdu_start_sgi {
750 RX_MSDU_START_SGI_0_8_US,
751 RX_MSDU_START_SGI_0_4_US,
752 RX_MSDU_START_SGI_1_6_US,
753 RX_MSDU_START_SGI_3_2_US,
754};
755
756enum rx_msdu_start_recv_bw {
757 RX_MSDU_START_RECV_BW_20MHZ,
758 RX_MSDU_START_RECV_BW_40MHZ,
759 RX_MSDU_START_RECV_BW_80MHZ,
760 RX_MSDU_START_RECV_BW_160MHZ,
761};
762
763enum rx_msdu_start_reception_type {
764 RX_MSDU_START_RECEPTION_TYPE_SU,
765 RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO,
766 RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA,
767 RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO,
768 RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO,
769 RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA,
770 RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO,
771};
772
773#define RX_MSDU_START_INFO1_MSDU_LENGTH GENMASK(13, 0)
774#define RX_MSDU_START_INFO1_RSVD_1A BIT(14)
775#define RX_MSDU_START_INFO1_IPSEC_ESP BIT(15)
776#define RX_MSDU_START_INFO1_L3_OFFSET GENMASK(22, 16)
777#define RX_MSDU_START_INFO1_IPSEC_AH BIT(23)
778#define RX_MSDU_START_INFO1_L4_OFFSET GENMASK(31, 24)
779
780#define RX_MSDU_START_INFO2_MSDU_NUMBER GENMASK(7, 0)
781#define RX_MSDU_START_INFO2_DECAP_TYPE GENMASK(9, 8)
782#define RX_MSDU_START_INFO2_IPV4 BIT(10)
783#define RX_MSDU_START_INFO2_IPV6 BIT(11)
784#define RX_MSDU_START_INFO2_TCP BIT(12)
785#define RX_MSDU_START_INFO2_UDP BIT(13)
786#define RX_MSDU_START_INFO2_IP_FRAG BIT(14)
787#define RX_MSDU_START_INFO2_TCP_ONLY_ACK BIT(15)
788#define RX_MSDU_START_INFO2_DA_IS_BCAST_MCAST BIT(16)
789#define RX_MSDU_START_INFO2_SELECTED_TOEPLITZ_HASH GENMASK(18, 17)
790#define RX_MSDU_START_INFO2_IP_FIXED_HDR_VALID BIT(19)
791#define RX_MSDU_START_INFO2_IP_EXTN_HDR_VALID BIT(20)
792#define RX_MSDU_START_INFO2_IP_TCP_UDP_HDR_VALID BIT(21)
793#define RX_MSDU_START_INFO2_MESH_CTRL_PRESENT BIT(22)
794#define RX_MSDU_START_INFO2_LDPC BIT(23)
795#define RX_MSDU_START_INFO2_IP4_IP6_NXT_HDR GENMASK(31, 24)
796#define RX_MSDU_START_INFO2_DECAP_FORMAT GENMASK(9, 8)
797
798#define RX_MSDU_START_INFO3_USER_RSSI GENMASK(7, 0)
799#define RX_MSDU_START_INFO3_PKT_TYPE GENMASK(11, 8)
800#define RX_MSDU_START_INFO3_STBC BIT(12)
801#define RX_MSDU_START_INFO3_SGI GENMASK(14, 13)
802#define RX_MSDU_START_INFO3_RATE_MCS GENMASK(18, 15)
803#define RX_MSDU_START_INFO3_RECV_BW GENMASK(20, 19)
804#define RX_MSDU_START_INFO3_RECEPTION_TYPE GENMASK(23, 21)
805#define RX_MSDU_START_INFO3_MIMO_SS_BITMAP GENMASK(31, 24)
806
807struct rx_msdu_start_ipq8074 {
808 __le16 info0;
809 __le16 phy_ppdu_id;
810 __le32 info1;
811 __le32 info2;
812 __le32 toeplitz_hash;
813 __le32 flow_id_toeplitz;
814 __le32 info3;
815 __le32 ppdu_start_timestamp;
816 __le32 phy_meta_data;
817} __packed;
818
819struct rx_msdu_start_qcn9074 {
820 __le16 info0;
821 __le16 phy_ppdu_id;
822 __le32 info1;
823 __le32 info2;
824 __le32 toeplitz_hash;
825 __le32 flow_id_toeplitz;
826 __le32 info3;
827 __le32 ppdu_start_timestamp;
828 __le32 phy_meta_data;
829 __le16 vlan_ctag_c1;
830 __le16 vlan_stag_c1;
831} __packed;
832
833struct rx_msdu_start_wcn6855 {
834 __le16 info0;
835 __le16 phy_ppdu_id;
836 __le32 info1;
837 __le32 info2;
838 __le32 toeplitz_hash;
839 __le32 flow_id_toeplitz;
840 __le32 info3;
841 __le32 ppdu_start_timestamp;
842 __le32 phy_meta_data;
843 __le16 vlan_ctag_ci;
844 __le16 vlan_stag_ci;
845} __packed;
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1020#define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)
1021#define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2)
1022
1023#define RX_MSDU_END_INFO1_KEY_ID GENMASK(7, 0)
1024#define RX_MSDU_END_INFO1_CCE_SUPER_RULE GENMASK(13, 8)
1025#define RX_MSDU_END_INFO1_CCND_TRUNCATE BIT(14)
1026#define RX_MSDU_END_INFO1_CCND_CCE_DIS BIT(15)
1027#define RX_MSDU_END_INFO1_EXT_WAPI_PN GENMASK(31, 16)
1028
1029#define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN GENMASK(13, 0)
1030#define RX_MSDU_END_INFO2_FIRST_MSDU BIT(14)
1031#define RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855 BIT(28)
1032#define RX_MSDU_END_INFO2_LAST_MSDU BIT(15)
1033#define RX_MSDU_END_INFO2_LAST_MSDU_WCN6855 BIT(29)
1034#define RX_MSDU_END_INFO2_SA_IDX_TIMEOUT BIT(16)
1035#define RX_MSDU_END_INFO2_DA_IDX_TIMEOUT BIT(17)
1036#define RX_MSDU_END_INFO2_MSDU_LIMIT_ERR BIT(18)
1037#define RX_MSDU_END_INFO2_FLOW_IDX_TIMEOUT BIT(19)
1038#define RX_MSDU_END_INFO2_FLOW_IDX_INVALID BIT(20)
1039#define RX_MSDU_END_INFO2_WIFI_PARSER_ERR BIT(21)
1040#define RX_MSDU_END_INFO2_AMSDU_PARSET_ERR BIT(22)
1041#define RX_MSDU_END_INFO2_SA_IS_VALID BIT(23)
1042#define RX_MSDU_END_INFO2_DA_IS_VALID BIT(24)
1043#define RX_MSDU_END_INFO2_DA_IS_MCBC BIT(25)
1044#define RX_MSDU_END_INFO2_L3_HDR_PADDING GENMASK(27, 26)
1045
1046#define RX_MSDU_END_INFO3_TCP_FLAG GENMASK(8, 0)
1047#define RX_MSDU_END_INFO3_LRO_ELIGIBLE BIT(9)
1048
1049#define RX_MSDU_END_INFO4_DA_OFFSET GENMASK(5, 0)
1050#define RX_MSDU_END_INFO4_SA_OFFSET GENMASK(11, 6)
1051#define RX_MSDU_END_INFO4_DA_OFFSET_VALID BIT(12)
1052#define RX_MSDU_END_INFO4_SA_OFFSET_VALID BIT(13)
1053#define RX_MSDU_END_INFO4_L3_TYPE GENMASK(31, 16)
1054
1055#define RX_MSDU_END_INFO5_MSDU_DROP BIT(0)
1056#define RX_MSDU_END_INFO5_REO_DEST_IND GENMASK(5, 1)
1057#define RX_MSDU_END_INFO5_FLOW_IDX GENMASK(25, 6)
1058
1059struct rx_msdu_end_ipq8074 {
1060 __le16 info0;
1061 __le16 phy_ppdu_id;
1062 __le16 ip_hdr_cksum;
1063 __le16 tcp_udp_cksum;
1064 __le32 info1;
1065 __le32 ext_wapi_pn[2];
1066 __le32 info2;
1067 __le32 ipv6_options_crc;
1068 __le32 tcp_seq_num;
1069 __le32 tcp_ack_num;
1070 __le16 info3;
1071 __le16 window_size;
1072 __le32 info4;
1073 __le32 rule_indication[2];
1074 __le16 sa_idx;
1075 __le16 da_idx;
1076 __le32 info5;
1077 __le32 fse_metadata;
1078 __le16 cce_metadata;
1079 __le16 sa_sw_peer_id;
1080} __packed;
1081
1082struct rx_msdu_end_wcn6855 {
1083 __le16 info0;
1084 __le16 phy_ppdu_id;
1085 __le16 ip_hdr_cksum;
1086 __le16 reported_mpdu_len;
1087 __le32 info1;
1088 __le32 ext_wapi_pn[2];
1089 __le32 info4;
1090 __le32 ipv6_options_crc;
1091 __le32 tcp_seq_num;
1092 __le32 tcp_ack_num;
1093 __le16 info3;
1094 __le16 window_size;
1095 __le32 info2;
1096 __le16 sa_idx;
1097 __le16 da_idx;
1098 __le32 info5;
1099 __le32 fse_metadata;
1100 __le16 cce_metadata;
1101 __le16 sa_sw_peer_id;
1102 __le32 rule_indication[2];
1103 __le32 info6;
1104 __le32 info7;
1105} __packed;
1106
1107#define RX_MSDU_END_MPDU_LENGTH_INFO GENMASK(13, 0)
1108
1109#define RX_MSDU_END_INFO2_DA_OFFSET GENMASK(5, 0)
1110#define RX_MSDU_END_INFO2_SA_OFFSET GENMASK(11, 6)
1111#define RX_MSDU_END_INFO2_DA_OFFSET_VALID BIT(12)
1112#define RX_MSDU_END_INFO2_SA_OFFSET_VALID BIT(13)
1113#define RX_MSDU_END_INFO2_L3_TYPE GENMASK(31, 16)
1114
1115#define RX_MSDU_END_INFO4_SA_IDX_TIMEOUT BIT(0)
1116#define RX_MSDU_END_INFO4_DA_IDX_TIMEOUT BIT(1)
1117#define RX_MSDU_END_INFO4_MSDU_LIMIT_ERR BIT(2)
1118#define RX_MSDU_END_INFO4_FLOW_IDX_TIMEOUT BIT(3)
1119#define RX_MSDU_END_INFO4_FLOW_IDX_INVALID BIT(4)
1120#define RX_MSDU_END_INFO4_WIFI_PARSER_ERR BIT(5)
1121#define RX_MSDU_END_INFO4_AMSDU_PARSER_ERR BIT(6)
1122#define RX_MSDU_END_INFO4_SA_IS_VALID BIT(7)
1123#define RX_MSDU_END_INFO4_DA_IS_VALID BIT(8)
1124#define RX_MSDU_END_INFO4_DA_IS_MCBC BIT(9)
1125#define RX_MSDU_END_INFO4_L3_HDR_PADDING GENMASK(11, 10)
1126#define RX_MSDU_END_INFO4_FIRST_MSDU BIT(12)
1127#define RX_MSDU_END_INFO4_LAST_MSDU BIT(13)
1128
1129#define RX_MSDU_END_INFO6_AGGR_COUNT GENMASK(7, 0)
1130#define RX_MSDU_END_INFO6_FLOW_AGGR_CONTN BIT(8)
1131#define RX_MSDU_END_INFO6_FISA_TIMEOUT BIT(9)
1132
1133struct rx_msdu_end_qcn9074 {
1134 __le16 info0;
1135 __le16 phy_ppdu_id;
1136 __le16 ip_hdr_cksum;
1137 __le16 mpdu_length_info;
1138 __le32 info1;
1139 __le32 rule_indication[2];
1140 __le32 info2;
1141 __le32 ipv6_options_crc;
1142 __le32 tcp_seq_num;
1143 __le32 tcp_ack_num;
1144 __le16 info3;
1145 __le16 window_size;
1146 __le16 tcp_udp_cksum;
1147 __le16 info4;
1148 __le16 sa_idx;
1149 __le16 da_idx;
1150 __le32 info5;
1151 __le32 fse_metadata;
1152 __le16 cce_metadata;
1153 __le16 sa_sw_peer_id;
1154 __le32 info6;
1155 __le16 cum_l4_cksum;
1156 __le16 cum_ip_length;
1157} __packed;
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1321enum rx_mpdu_end_rxdma_dest_ring {
1322 RX_MPDU_END_RXDMA_DEST_RING_RELEASE,
1323 RX_MPDU_END_RXDMA_DEST_RING_FW,
1324 RX_MPDU_END_RXDMA_DEST_RING_SW,
1325 RX_MPDU_END_RXDMA_DEST_RING_REO,
1326};
1327
1328#define RX_MPDU_END_INFO1_UNSUP_KTYPE_SHORT_FRAME BIT(11)
1329#define RX_MPDU_END_INFO1_RX_IN_TX_DECRYPT_BYT BIT(12)
1330#define RX_MPDU_END_INFO1_OVERFLOW_ERR BIT(13)
1331#define RX_MPDU_END_INFO1_MPDU_LEN_ERR BIT(14)
1332#define RX_MPDU_END_INFO1_TKIP_MIC_ERR BIT(15)
1333#define RX_MPDU_END_INFO1_DECRYPT_ERR BIT(16)
1334#define RX_MPDU_END_INFO1_UNENCRYPTED_FRAME_ERR BIT(17)
1335#define RX_MPDU_END_INFO1_PN_FIELDS_VALID BIT(18)
1336#define RX_MPDU_END_INFO1_FCS_ERR BIT(19)
1337#define RX_MPDU_END_INFO1_MSDU_LEN_ERR BIT(20)
1338#define RX_MPDU_END_INFO1_RXDMA0_DEST_RING GENMASK(22, 21)
1339#define RX_MPDU_END_INFO1_RXDMA1_DEST_RING GENMASK(24, 23)
1340#define RX_MPDU_END_INFO1_DECRYPT_STATUS_CODE GENMASK(27, 25)
1341#define RX_MPDU_END_INFO1_RX_BITMAP_NOT_UPD BIT(28)
1342
1343struct rx_mpdu_end {
1344 __le16 info0;
1345 __le16 phy_ppdu_id;
1346 __le32 info1;
1347} __packed;
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1427#define HAL_RX_DESC_PADDING0_BYTES 4
1428#define HAL_RX_DESC_PADDING1_BYTES 16
1429
1430#define HAL_RX_DESC_HDR_STATUS_LEN 120
1431
1432struct hal_rx_desc_ipq8074 {
1433 __le32 msdu_end_tag;
1434 struct rx_msdu_end_ipq8074 msdu_end;
1435 __le32 rx_attn_tag;
1436 struct rx_attention attention;
1437 __le32 msdu_start_tag;
1438 struct rx_msdu_start_ipq8074 msdu_start;
1439 u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
1440 __le32 mpdu_start_tag;
1441 struct rx_mpdu_start_ipq8074 mpdu_start;
1442 __le32 mpdu_end_tag;
1443 struct rx_mpdu_end mpdu_end;
1444 u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
1445 __le32 hdr_status_tag;
1446 __le32 phy_ppdu_id;
1447 u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
1448 u8 msdu_payload[0];
1449} __packed;
1450
1451struct hal_rx_desc_qcn9074 {
1452 __le32 msdu_end_tag;
1453 struct rx_msdu_end_qcn9074 msdu_end;
1454 __le32 rx_attn_tag;
1455 struct rx_attention attention;
1456 __le32 msdu_start_tag;
1457 struct rx_msdu_start_qcn9074 msdu_start;
1458 u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
1459 __le32 mpdu_start_tag;
1460 struct rx_mpdu_start_qcn9074 mpdu_start;
1461 __le32 mpdu_end_tag;
1462 struct rx_mpdu_end mpdu_end;
1463 u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
1464 __le32 hdr_status_tag;
1465 __le32 phy_ppdu_id;
1466 u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
1467 u8 msdu_payload[0];
1468} __packed;
1469
1470struct hal_rx_desc_wcn6855 {
1471 __le32 msdu_end_tag;
1472 struct rx_msdu_end_wcn6855 msdu_end;
1473 __le32 rx_attn_tag;
1474 struct rx_attention attention;
1475 __le32 msdu_start_tag;
1476 struct rx_msdu_start_wcn6855 msdu_start;
1477 u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
1478 __le32 mpdu_start_tag;
1479 struct rx_mpdu_start_wcn6855 mpdu_start;
1480 __le32 mpdu_end_tag;
1481 struct rx_mpdu_end mpdu_end;
1482 u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
1483 __le32 hdr_status_tag;
1484 __le32 phy_ppdu_id;
1485 u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
1486 u8 msdu_payload[0];
1487} __packed;
1488
1489struct hal_rx_desc {
1490 union {
1491 struct hal_rx_desc_ipq8074 ipq8074;
1492 struct hal_rx_desc_qcn9074 qcn9074;
1493 struct hal_rx_desc_wcn6855 wcn6855;
1494 } u;
1495} __packed;
1496
1497#define HAL_RX_RU_ALLOC_TYPE_MAX 6
1498#define RU_26 1
1499#define RU_52 2
1500#define RU_106 4
1501#define RU_242 9
1502#define RU_484 18
1503#define RU_996 37
1504
1505#endif
1506