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7#include <linux/types.h>
8#include <linux/slab.h>
9#include <linux/export.h>
10#include <linux/etherdevice.h>
11#include <linux/pci.h>
12#include <linux/firmware.h>
13
14#include "iwl-drv.h"
15#include "iwl-modparams.h"
16#include "iwl-nvm-parse.h"
17#include "iwl-prph.h"
18#include "iwl-io.h"
19#include "iwl-csr.h"
20#include "fw/acpi.h"
21#include "fw/api/nvm-reg.h"
22#include "fw/api/commands.h"
23#include "fw/api/cmdhdr.h"
24#include "fw/img.h"
25
26
27enum nvm_offsets {
28
29 SUBSYSTEM_ID = 0x0A,
30 HW_ADDR = 0x15,
31
32
33 NVM_SW_SECTION = 0x1C0,
34 NVM_VERSION = 0,
35 RADIO_CFG = 1,
36 SKU = 2,
37 N_HW_ADDRS = 3,
38 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
39
40
41 NVM_CALIB_SECTION = 0x2B8,
42 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
43
44
45 NVM_CHANNELS_SDP = 0,
46};
47
48enum ext_nvm_offsets {
49
50 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
51
52
53 NVM_VERSION_EXT_NVM = 0,
54 N_HW_ADDRS_FAMILY_8000 = 3,
55
56
57 RADIO_CFG_FAMILY_EXT_NVM = 0,
58 SKU_FAMILY_8000 = 2,
59
60
61 NVM_CHANNELS_EXTENDED = 0,
62 NVM_LAR_OFFSET_OLD = 0x4C7,
63 NVM_LAR_OFFSET = 0x507,
64 NVM_LAR_ENABLED = 0x7,
65};
66
67
68enum nvm_sku_bits {
69 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
70 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
71 NVM_SKU_CAP_11N_ENABLE = BIT(2),
72 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
73 NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
74};
75
76
77
78
79static const u16 iwl_nvm_channels[] = {
80
81 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
82
83 36, 40, 44 , 48, 52, 56, 60, 64,
84 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
85 149, 153, 157, 161, 165
86};
87
88static const u16 iwl_ext_nvm_channels[] = {
89
90 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
91
92 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
93 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
94 149, 153, 157, 161, 165, 169, 173, 177, 181
95};
96
97static const u16 iwl_uhb_nvm_channels[] = {
98
99 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
100
101 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
102 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
103 149, 153, 157, 161, 165, 169, 173, 177, 181,
104
105 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,
106 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129,
107 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185,
108 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233
109};
110
111#define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
112#define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels)
113#define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels)
114#define NUM_2GHZ_CHANNELS 14
115#define NUM_5GHZ_CHANNELS 37
116#define FIRST_2GHZ_HT_MINUS 5
117#define LAST_2GHZ_HT_PLUS 9
118#define N_HW_ADDR_MASK 0xF
119
120
121static struct ieee80211_rate iwl_cfg80211_rates[] = {
122 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
123 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
124 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
125 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
126 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
127 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
128 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
129 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
130 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
131 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
132 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
133 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
134 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
135 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
136 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
137};
138#define RATES_24_OFFS 0
139#define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
140#define RATES_52_OFFS 4
141#define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
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159enum iwl_nvm_channel_flags {
160 NVM_CHANNEL_VALID = BIT(0),
161 NVM_CHANNEL_IBSS = BIT(1),
162 NVM_CHANNEL_ACTIVE = BIT(3),
163 NVM_CHANNEL_RADAR = BIT(4),
164 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
165 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
166 NVM_CHANNEL_UNIFORM = BIT(7),
167 NVM_CHANNEL_20MHZ = BIT(8),
168 NVM_CHANNEL_40MHZ = BIT(9),
169 NVM_CHANNEL_80MHZ = BIT(10),
170 NVM_CHANNEL_160MHZ = BIT(11),
171 NVM_CHANNEL_DC_HIGH = BIT(12),
172};
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191
192enum iwl_reg_capa_flags {
193 REG_CAPA_BF_CCD_LOW_BAND = BIT(0),
194 REG_CAPA_BF_CCD_HIGH_BAND = BIT(1),
195 REG_CAPA_160MHZ_ALLOWED = BIT(2),
196 REG_CAPA_80MHZ_ALLOWED = BIT(3),
197 REG_CAPA_MCS_8_ALLOWED = BIT(4),
198 REG_CAPA_MCS_9_ALLOWED = BIT(5),
199 REG_CAPA_40MHZ_FORBIDDEN = BIT(7),
200 REG_CAPA_DC_HIGH_ENABLED = BIT(9),
201 REG_CAPA_11AX_DISABLED = BIT(10),
202};
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225enum iwl_reg_capa_flags_v2 {
226 REG_CAPA_V2_STRADDLE_DISABLED = BIT(0),
227 REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1),
228 REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2),
229 REG_CAPA_V2_160MHZ_ALLOWED = BIT(3),
230 REG_CAPA_V2_80MHZ_ALLOWED = BIT(4),
231 REG_CAPA_V2_MCS_8_ALLOWED = BIT(5),
232 REG_CAPA_V2_MCS_9_ALLOWED = BIT(6),
233 REG_CAPA_V2_WEATHER_DISABLED = BIT(7),
234 REG_CAPA_V2_40MHZ_ALLOWED = BIT(8),
235 REG_CAPA_V2_11AX_DISABLED = BIT(10),
236};
237
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240
241
242#define REG_CAPA_V2_RESP_VER 6
243
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255
256struct iwl_reg_capa {
257 u16 allow_40mhz;
258 u16 allow_80mhz;
259 u16 allow_160mhz;
260 u16 disable_11ax;
261};
262
263static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
264 int chan, u32 flags)
265{
266#define CHECK_AND_PRINT_I(x) \
267 ((flags & NVM_CHANNEL_##x) ? " " #x : "")
268
269 if (!(flags & NVM_CHANNEL_VALID)) {
270 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
271 chan, flags);
272 return;
273 }
274
275
276 IWL_DEBUG_DEV(dev, level,
277 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n",
278 chan, flags,
279 CHECK_AND_PRINT_I(VALID),
280 CHECK_AND_PRINT_I(IBSS),
281 CHECK_AND_PRINT_I(ACTIVE),
282 CHECK_AND_PRINT_I(RADAR),
283 CHECK_AND_PRINT_I(INDOOR_ONLY),
284 CHECK_AND_PRINT_I(GO_CONCURRENT),
285 CHECK_AND_PRINT_I(UNIFORM),
286 CHECK_AND_PRINT_I(20MHZ),
287 CHECK_AND_PRINT_I(40MHZ),
288 CHECK_AND_PRINT_I(80MHZ),
289 CHECK_AND_PRINT_I(160MHZ),
290 CHECK_AND_PRINT_I(DC_HIGH));
291#undef CHECK_AND_PRINT_I
292}
293
294static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band,
295 u32 nvm_flags, const struct iwl_cfg *cfg)
296{
297 u32 flags = IEEE80211_CHAN_NO_HT40;
298
299 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) {
300 if (ch_num <= LAST_2GHZ_HT_PLUS)
301 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
302 if (ch_num >= FIRST_2GHZ_HT_MINUS)
303 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
304 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
305 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
306 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
307 else
308 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
309 }
310 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
311 flags |= IEEE80211_CHAN_NO_80MHZ;
312 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
313 flags |= IEEE80211_CHAN_NO_160MHZ;
314
315 if (!(nvm_flags & NVM_CHANNEL_IBSS))
316 flags |= IEEE80211_CHAN_NO_IR;
317
318 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
319 flags |= IEEE80211_CHAN_NO_IR;
320
321 if (nvm_flags & NVM_CHANNEL_RADAR)
322 flags |= IEEE80211_CHAN_RADAR;
323
324 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
325 flags |= IEEE80211_CHAN_INDOOR_ONLY;
326
327
328
329
330 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
331 (flags & IEEE80211_CHAN_NO_IR))
332 flags |= IEEE80211_CHAN_IR_CONCURRENT;
333
334 return flags;
335}
336
337static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx)
338{
339 if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) {
340 return NL80211_BAND_6GHZ;
341 }
342
343 if (ch_idx >= NUM_2GHZ_CHANNELS)
344 return NL80211_BAND_5GHZ;
345 return NL80211_BAND_2GHZ;
346}
347
348static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
349 struct iwl_nvm_data *data,
350 const void * const nvm_ch_flags,
351 u32 sbands_flags, bool v4)
352{
353 int ch_idx;
354 int n_channels = 0;
355 struct ieee80211_channel *channel;
356 u32 ch_flags;
357 int num_of_ch;
358 const u16 *nvm_chan;
359
360 if (cfg->uhb_supported) {
361 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB;
362 nvm_chan = iwl_uhb_nvm_channels;
363 } else if (cfg->nvm_type == IWL_NVM_EXT) {
364 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
365 nvm_chan = iwl_ext_nvm_channels;
366 } else {
367 num_of_ch = IWL_NVM_NUM_CHANNELS;
368 nvm_chan = iwl_nvm_channels;
369 }
370
371 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
372 enum nl80211_band band =
373 iwl_nl80211_band_from_channel_idx(ch_idx);
374
375 if (v4)
376 ch_flags =
377 __le32_to_cpup((__le32 *)nvm_ch_flags + ch_idx);
378 else
379 ch_flags =
380 __le16_to_cpup((__le16 *)nvm_ch_flags + ch_idx);
381
382 if (band == NL80211_BAND_5GHZ &&
383 !data->sku_cap_band_52ghz_enable)
384 continue;
385
386
387 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
388 band == NL80211_BAND_5GHZ) {
389 ch_flags &= ~(NVM_CHANNEL_40MHZ |
390 NVM_CHANNEL_80MHZ |
391 NVM_CHANNEL_160MHZ);
392 }
393
394 if (ch_flags & NVM_CHANNEL_160MHZ)
395 data->vht160_supported = true;
396
397 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
398 !(ch_flags & NVM_CHANNEL_VALID)) {
399
400
401
402
403
404 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
405 nvm_chan[ch_idx], ch_flags);
406 continue;
407 }
408
409 channel = &data->channels[n_channels];
410 n_channels++;
411
412 channel->hw_value = nvm_chan[ch_idx];
413 channel->band = band;
414 channel->center_freq =
415 ieee80211_channel_to_frequency(
416 channel->hw_value, channel->band);
417
418
419
420
421
422
423
424 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
425
426
427 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
428 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
429 ch_idx, band,
430 ch_flags, cfg);
431 else
432 channel->flags = 0;
433
434
435
436
437 if (cfg->uhb_supported)
438 channel->flags = 0;
439 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
440 channel->hw_value, ch_flags);
441 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
442 channel->hw_value, channel->max_power);
443 }
444
445 return n_channels;
446}
447
448static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
449 struct iwl_nvm_data *data,
450 struct ieee80211_sta_vht_cap *vht_cap,
451 u8 tx_chains, u8 rx_chains)
452{
453 const struct iwl_cfg *cfg = trans->cfg;
454 int num_rx_ants = num_of_ant(rx_chains);
455 int num_tx_ants = num_of_ant(tx_chains);
456
457 vht_cap->vht_supported = true;
458
459 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
460 IEEE80211_VHT_CAP_RXSTBC_1 |
461 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
462 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
463 IEEE80211_VHT_MAX_AMPDU_1024K <<
464 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
465
466 if (data->vht160_supported)
467 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
468 IEEE80211_VHT_CAP_SHORT_GI_160;
469
470 if (cfg->vht_mu_mimo_supported)
471 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
472
473 if (cfg->ht_params->ldpc)
474 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
475
476 if (data->sku_cap_mimo_disabled) {
477 num_rx_ants = 1;
478 num_tx_ants = 1;
479 }
480
481 if (num_tx_ants > 1)
482 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
483 else
484 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
485
486 switch (iwlwifi_mod_params.amsdu_size) {
487 case IWL_AMSDU_DEF:
488 if (trans->trans_cfg->mq_rx_supported)
489 vht_cap->cap |=
490 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
491 else
492 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
493 break;
494 case IWL_AMSDU_2K:
495 if (trans->trans_cfg->mq_rx_supported)
496 vht_cap->cap |=
497 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
498 else
499 WARN(1, "RB size of 2K is not supported by this device\n");
500 break;
501 case IWL_AMSDU_4K:
502 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
503 break;
504 case IWL_AMSDU_8K:
505 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
506 break;
507 case IWL_AMSDU_12K:
508 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
509 break;
510 default:
511 break;
512 }
513
514 vht_cap->vht_mcs.rx_mcs_map =
515 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
516 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
517 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
518 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
519 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
520 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
521 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
522 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
523
524 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
525 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
526
527 vht_cap->vht_mcs.rx_mcs_map |=
528 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
529 }
530
531 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
532
533 vht_cap->vht_mcs.tx_highest |=
534 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
535}
536
537static const struct ieee80211_sband_iftype_data iwl_he_capa[] = {
538 {
539 .types_mask = BIT(NL80211_IFTYPE_STATION),
540 .he_cap = {
541 .has_he = true,
542 .he_cap_elem = {
543 .mac_cap_info[0] =
544 IEEE80211_HE_MAC_CAP0_HTC_HE |
545 IEEE80211_HE_MAC_CAP0_TWT_REQ,
546 .mac_cap_info[1] =
547 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
548 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
549 .mac_cap_info[2] =
550 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP,
551 .mac_cap_info[3] =
552 IEEE80211_HE_MAC_CAP3_OMI_CONTROL,
553 .mac_cap_info[4] =
554 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU |
555 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
556 .mac_cap_info[5] =
557 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
558 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
559 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
560 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
561 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
562 .phy_cap_info[0] =
563 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
564 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
565 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
566 .phy_cap_info[1] =
567 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
568 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
569 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
570 .phy_cap_info[2] =
571 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
572 .phy_cap_info[3] =
573 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
574 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
575 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
576 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
577 .phy_cap_info[4] =
578 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
579 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
580 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
581 .phy_cap_info[6] =
582 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
583 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB |
584 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
585 .phy_cap_info[7] =
586 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
587 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI,
588 .phy_cap_info[8] =
589 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
590 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
591 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
592 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
593 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242,
594 .phy_cap_info[9] =
595 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
596 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
597 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
598 },
599
600
601
602
603
604 .he_mcs_nss_supp = {
605 .rx_mcs_80 = cpu_to_le16(0xfffa),
606 .tx_mcs_80 = cpu_to_le16(0xfffa),
607 .rx_mcs_160 = cpu_to_le16(0xfffa),
608 .tx_mcs_160 = cpu_to_le16(0xfffa),
609 .rx_mcs_80p80 = cpu_to_le16(0xffff),
610 .tx_mcs_80p80 = cpu_to_le16(0xffff),
611 },
612
613
614
615
616 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
617 },
618 },
619 {
620 .types_mask = BIT(NL80211_IFTYPE_AP),
621 .he_cap = {
622 .has_he = true,
623 .he_cap_elem = {
624 .mac_cap_info[0] =
625 IEEE80211_HE_MAC_CAP0_HTC_HE,
626 .mac_cap_info[1] =
627 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
628 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
629 .mac_cap_info[3] =
630 IEEE80211_HE_MAC_CAP3_OMI_CONTROL,
631 .phy_cap_info[0] =
632 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
633 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G,
634 .phy_cap_info[1] =
635 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
636 .phy_cap_info[2] =
637 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
638 .phy_cap_info[3] =
639 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
640 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
641 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
642 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
643 .phy_cap_info[6] =
644 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
645 .phy_cap_info[7] =
646 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI,
647 .phy_cap_info[8] =
648 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
649 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242,
650 .phy_cap_info[9] =
651 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
652 },
653
654
655
656
657
658 .he_mcs_nss_supp = {
659 .rx_mcs_80 = cpu_to_le16(0xfffa),
660 .tx_mcs_80 = cpu_to_le16(0xfffa),
661 .rx_mcs_160 = cpu_to_le16(0xfffa),
662 .tx_mcs_160 = cpu_to_le16(0xfffa),
663 .rx_mcs_80p80 = cpu_to_le16(0xffff),
664 .tx_mcs_80p80 = cpu_to_le16(0xffff),
665 },
666
667
668
669
670 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
671 },
672 },
673};
674
675static void iwl_init_he_6ghz_capa(struct iwl_trans *trans,
676 struct iwl_nvm_data *data,
677 struct ieee80211_supported_band *sband,
678 u8 tx_chains, u8 rx_chains)
679{
680 struct ieee80211_sta_ht_cap ht_cap;
681 struct ieee80211_sta_vht_cap vht_cap = {};
682 struct ieee80211_sband_iftype_data *iftype_data;
683 u16 he_6ghz_capa = 0;
684 u32 exp;
685 int i;
686
687 if (sband->band != NL80211_BAND_6GHZ)
688 return;
689
690
691 iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ,
692 tx_chains, rx_chains);
693 WARN_ON(!ht_cap.ht_supported);
694 iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains);
695 WARN_ON(!vht_cap.vht_supported);
696
697 he_6ghz_capa |=
698 u16_encode_bits(ht_cap.ampdu_density,
699 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START);
700 exp = u32_get_bits(vht_cap.cap,
701 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK);
702 he_6ghz_capa |=
703 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP);
704 exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK);
705 he_6ghz_capa |=
706 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
707
708 if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN)
709 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS;
710 if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN)
711 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
712
713 IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa);
714
715
716 iftype_data = (void *)sband->iftype_data;
717 for (i = 0; i < sband->n_iftype_data; i++)
718 iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa);
719}
720
721static void
722iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans,
723 struct ieee80211_supported_band *sband,
724 struct ieee80211_sband_iftype_data *iftype_data,
725 u8 tx_chains, u8 rx_chains,
726 const struct iwl_fw *fw)
727{
728 bool is_ap = iftype_data->types_mask & BIT(NL80211_IFTYPE_AP);
729
730
731
732
733 if (sband->band != NL80211_BAND_2GHZ)
734 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
735 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1;
736 else
737 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
738 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
739
740 if (is_ap && iwlwifi_mod_params.nvm_file)
741 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |=
742 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
743
744 if ((tx_chains & rx_chains) == ANT_AB) {
745 iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |=
746 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
747 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2;
748 if (!is_ap)
749 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |=
750 IEEE80211_HE_PHY_CAP7_MAX_NC_2;
751 } else if (!is_ap) {
752
753
754
755 iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &=
756 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
757 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &=
758 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
759 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |=
760 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
761 }
762
763 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
764 case IWL_CFG_RF_TYPE_GF:
765 case IWL_CFG_RF_TYPE_MR:
766 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |=
767 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
768 if (!is_ap)
769 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |=
770 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
771 break;
772 }
773
774 if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT))
775 iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |=
776 IEEE80211_HE_MAC_CAP2_BCAST_TWT;
777}
778
779static void iwl_init_he_hw_capab(struct iwl_trans *trans,
780 struct iwl_nvm_data *data,
781 struct ieee80211_supported_band *sband,
782 u8 tx_chains, u8 rx_chains,
783 const struct iwl_fw *fw)
784{
785 struct ieee80211_sband_iftype_data *iftype_data;
786 int i;
787
788
789 if (WARN_ON(sband->iftype_data))
790 return;
791
792 BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_capa));
793 BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_capa));
794
795 switch (sband->band) {
796 case NL80211_BAND_2GHZ:
797 iftype_data = data->iftd.low;
798 break;
799 case NL80211_BAND_5GHZ:
800 case NL80211_BAND_6GHZ:
801 iftype_data = data->iftd.high;
802 break;
803 default:
804 WARN_ON(1);
805 return;
806 }
807
808 memcpy(iftype_data, iwl_he_capa, sizeof(iwl_he_capa));
809
810 sband->iftype_data = iftype_data;
811 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa);
812
813 for (i = 0; i < sband->n_iftype_data; i++)
814 iwl_nvm_fixup_sband_iftd(trans, sband, &iftype_data[i],
815 tx_chains, rx_chains, fw);
816
817 iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains);
818}
819
820static void iwl_init_sbands(struct iwl_trans *trans,
821 struct iwl_nvm_data *data,
822 const void *nvm_ch_flags, u8 tx_chains,
823 u8 rx_chains, u32 sbands_flags, bool v4,
824 const struct iwl_fw *fw)
825{
826 struct device *dev = trans->dev;
827 const struct iwl_cfg *cfg = trans->cfg;
828 int n_channels;
829 int n_used = 0;
830 struct ieee80211_supported_band *sband;
831
832 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
833 sbands_flags, v4);
834 sband = &data->bands[NL80211_BAND_2GHZ];
835 sband->band = NL80211_BAND_2GHZ;
836 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
837 sband->n_bitrates = N_RATES_24;
838 n_used += iwl_init_sband_channels(data, sband, n_channels,
839 NL80211_BAND_2GHZ);
840 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
841 tx_chains, rx_chains);
842
843 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
844 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
845 fw);
846
847 sband = &data->bands[NL80211_BAND_5GHZ];
848 sband->band = NL80211_BAND_5GHZ;
849 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
850 sband->n_bitrates = N_RATES_52;
851 n_used += iwl_init_sband_channels(data, sband, n_channels,
852 NL80211_BAND_5GHZ);
853 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
854 tx_chains, rx_chains);
855 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
856 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
857 tx_chains, rx_chains);
858
859 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
860 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
861 fw);
862
863
864 sband = &data->bands[NL80211_BAND_6GHZ];
865 sband->band = NL80211_BAND_6GHZ;
866
867 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
868 sband->n_bitrates = N_RATES_52;
869 n_used += iwl_init_sband_channels(data, sband, n_channels,
870 NL80211_BAND_6GHZ);
871
872 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
873 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
874 fw);
875 else
876 sband->n_channels = 0;
877 if (n_channels != n_used)
878 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
879 n_used, n_channels);
880}
881
882static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
883 const __le16 *phy_sku)
884{
885 if (cfg->nvm_type != IWL_NVM_EXT)
886 return le16_to_cpup(nvm_sw + SKU);
887
888 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
889}
890
891static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
892{
893 if (cfg->nvm_type != IWL_NVM_EXT)
894 return le16_to_cpup(nvm_sw + NVM_VERSION);
895 else
896 return le32_to_cpup((__le32 *)(nvm_sw +
897 NVM_VERSION_EXT_NVM));
898}
899
900static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
901 const __le16 *phy_sku)
902{
903 if (cfg->nvm_type != IWL_NVM_EXT)
904 return le16_to_cpup(nvm_sw + RADIO_CFG);
905
906 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
907
908}
909
910static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
911{
912 int n_hw_addr;
913
914 if (cfg->nvm_type != IWL_NVM_EXT)
915 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
916
917 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
918
919 return n_hw_addr & N_HW_ADDR_MASK;
920}
921
922static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
923 struct iwl_nvm_data *data,
924 u32 radio_cfg)
925{
926 if (cfg->nvm_type != IWL_NVM_EXT) {
927 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
928 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
929 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
930 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
931 return;
932 }
933
934
935 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
936 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
937 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
938 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
939 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
940 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
941}
942
943static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
944{
945 const u8 *hw_addr;
946
947 hw_addr = (const u8 *)&mac_addr0;
948 dest[0] = hw_addr[3];
949 dest[1] = hw_addr[2];
950 dest[2] = hw_addr[1];
951 dest[3] = hw_addr[0];
952
953 hw_addr = (const u8 *)&mac_addr1;
954 dest[4] = hw_addr[1];
955 dest[5] = hw_addr[0];
956}
957
958static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
959 struct iwl_nvm_data *data)
960{
961 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_STRAP));
962 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_STRAP));
963
964 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
965
966
967
968
969 if (is_valid_ether_addr(data->hw_addr))
970 return;
971
972 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP));
973 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP));
974
975 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
976}
977
978static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
979 const struct iwl_cfg *cfg,
980 struct iwl_nvm_data *data,
981 const __le16 *mac_override,
982 const __be16 *nvm_hw)
983{
984 const u8 *hw_addr;
985
986 if (mac_override) {
987 static const u8 reserved_mac[] = {
988 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
989 };
990
991 hw_addr = (const u8 *)(mac_override +
992 MAC_ADDRESS_OVERRIDE_EXT_NVM);
993
994
995
996
997
998 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
999
1000
1001
1002
1003
1004 if (is_valid_ether_addr(data->hw_addr) &&
1005 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
1006 return;
1007
1008 IWL_ERR(trans,
1009 "mac address from nvm override section is not valid\n");
1010 }
1011
1012 if (nvm_hw) {
1013
1014 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
1015 WFMP_MAC_ADDR_0));
1016 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
1017 WFMP_MAC_ADDR_1));
1018
1019 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
1020
1021 return;
1022 }
1023
1024 IWL_ERR(trans, "mac address is not found\n");
1025}
1026
1027static int iwl_set_hw_address(struct iwl_trans *trans,
1028 const struct iwl_cfg *cfg,
1029 struct iwl_nvm_data *data, const __be16 *nvm_hw,
1030 const __le16 *mac_override)
1031{
1032 if (cfg->mac_addr_from_csr) {
1033 iwl_set_hw_address_from_csr(trans, data);
1034 } else if (cfg->nvm_type != IWL_NVM_EXT) {
1035 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
1036
1037
1038 data->hw_addr[0] = hw_addr[1];
1039 data->hw_addr[1] = hw_addr[0];
1040 data->hw_addr[2] = hw_addr[3];
1041 data->hw_addr[3] = hw_addr[2];
1042 data->hw_addr[4] = hw_addr[5];
1043 data->hw_addr[5] = hw_addr[4];
1044 } else {
1045 iwl_set_hw_address_family_8000(trans, cfg, data,
1046 mac_override, nvm_hw);
1047 }
1048
1049 if (!is_valid_ether_addr(data->hw_addr)) {
1050 IWL_ERR(trans, "no valid mac address was found\n");
1051 return -EINVAL;
1052 }
1053
1054 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr);
1055
1056 return 0;
1057}
1058
1059static bool
1060iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1061 const __be16 *nvm_hw)
1062{
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1073
1074
1075
1076
1077 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
1078 u8 sku = (subsystem_id & 0x1e) >> 1;
1079
1080 if (sku == 5 || sku == 9) {
1081 IWL_DEBUG_EEPROM(trans->dev,
1082 "disabling wide channels in 5GHz (0x%0x %d)\n",
1083 subsystem_id, sku);
1084 return true;
1085 }
1086 }
1087
1088 return false;
1089}
1090
1091struct iwl_nvm_data *
1092iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1093 const struct iwl_fw *fw,
1094 const __be16 *nvm_hw, const __le16 *nvm_sw,
1095 const __le16 *nvm_calib, const __le16 *regulatory,
1096 const __le16 *mac_override, const __le16 *phy_sku,
1097 u8 tx_chains, u8 rx_chains)
1098{
1099 struct iwl_nvm_data *data;
1100 bool lar_enabled;
1101 u32 sku, radio_cfg;
1102 u32 sbands_flags = 0;
1103 u16 lar_config;
1104 const __le16 *ch_section;
1105
1106 if (cfg->uhb_supported)
1107 data = kzalloc(struct_size(data, channels,
1108 IWL_NVM_NUM_CHANNELS_UHB),
1109 GFP_KERNEL);
1110 else if (cfg->nvm_type != IWL_NVM_EXT)
1111 data = kzalloc(struct_size(data, channels,
1112 IWL_NVM_NUM_CHANNELS),
1113 GFP_KERNEL);
1114 else
1115 data = kzalloc(struct_size(data, channels,
1116 IWL_NVM_NUM_CHANNELS_EXT),
1117 GFP_KERNEL);
1118 if (!data)
1119 return NULL;
1120
1121 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
1122
1123 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
1124 iwl_set_radio_cfg(cfg, data, radio_cfg);
1125 if (data->valid_tx_ant)
1126 tx_chains &= data->valid_tx_ant;
1127 if (data->valid_rx_ant)
1128 rx_chains &= data->valid_rx_ant;
1129
1130 sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
1131 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
1132 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
1133 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
1134 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
1135 data->sku_cap_11n_enable = false;
1136 data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
1137 (sku & NVM_SKU_CAP_11AC_ENABLE);
1138 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
1139
1140 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
1141
1142 if (cfg->nvm_type != IWL_NVM_EXT) {
1143
1144 if (!nvm_calib) {
1145 IWL_ERR(trans,
1146 "Can't parse empty Calib NVM sections\n");
1147 kfree(data);
1148 return NULL;
1149 }
1150
1151 ch_section = cfg->nvm_type == IWL_NVM_SDP ?
1152 ®ulatory[NVM_CHANNELS_SDP] :
1153 &nvm_sw[NVM_CHANNELS];
1154
1155
1156 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
1157 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
1158 lar_enabled = true;
1159 } else {
1160 u16 lar_offset = data->nvm_version < 0xE39 ?
1161 NVM_LAR_OFFSET_OLD :
1162 NVM_LAR_OFFSET;
1163
1164 lar_config = le16_to_cpup(regulatory + lar_offset);
1165 data->lar_enabled = !!(lar_config &
1166 NVM_LAR_ENABLED);
1167 lar_enabled = data->lar_enabled;
1168 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED];
1169 }
1170
1171
1172 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
1173 kfree(data);
1174 return NULL;
1175 }
1176
1177 if (lar_enabled &&
1178 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1179 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1180
1181 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw))
1182 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1183
1184 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains,
1185 sbands_flags, false, fw);
1186 data->calib_version = 255;
1187
1188 return data;
1189}
1190IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1191
1192static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
1193 int ch_idx, u16 nvm_flags,
1194 struct iwl_reg_capa reg_capa,
1195 const struct iwl_cfg *cfg)
1196{
1197 u32 flags = NL80211_RRF_NO_HT40;
1198
1199 if (ch_idx < NUM_2GHZ_CHANNELS &&
1200 (nvm_flags & NVM_CHANNEL_40MHZ)) {
1201 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1202 flags &= ~NL80211_RRF_NO_HT40PLUS;
1203 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1204 flags &= ~NL80211_RRF_NO_HT40MINUS;
1205 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
1206 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1207 flags &= ~NL80211_RRF_NO_HT40PLUS;
1208 else
1209 flags &= ~NL80211_RRF_NO_HT40MINUS;
1210 }
1211
1212 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1213 flags |= NL80211_RRF_NO_80MHZ;
1214 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1215 flags |= NL80211_RRF_NO_160MHZ;
1216
1217 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1218 flags |= NL80211_RRF_NO_IR;
1219
1220 if (nvm_flags & NVM_CHANNEL_RADAR)
1221 flags |= NL80211_RRF_DFS;
1222
1223 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1224 flags |= NL80211_RRF_NO_OUTDOOR;
1225
1226
1227
1228
1229 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
1230 (flags & NL80211_RRF_NO_IR))
1231 flags |= NL80211_RRF_GO_CONCURRENT;
1232
1233
1234
1235
1236 if (ch_idx >= NUM_2GHZ_CHANNELS) {
1237 if (!reg_capa.allow_40mhz)
1238 flags |= NL80211_RRF_NO_HT40;
1239
1240 if (!reg_capa.allow_80mhz)
1241 flags |= NL80211_RRF_NO_80MHZ;
1242
1243 if (!reg_capa.allow_160mhz)
1244 flags |= NL80211_RRF_NO_160MHZ;
1245 }
1246 if (reg_capa.disable_11ax)
1247 flags |= NL80211_RRF_NO_HE;
1248
1249 return flags;
1250}
1251
1252static struct iwl_reg_capa iwl_get_reg_capa(u16 flags, u8 resp_ver)
1253{
1254 struct iwl_reg_capa reg_capa;
1255
1256 if (resp_ver >= REG_CAPA_V2_RESP_VER) {
1257 reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED;
1258 reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED;
1259 reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED;
1260 reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED;
1261 } else {
1262 reg_capa.allow_40mhz = !(flags & REG_CAPA_40MHZ_FORBIDDEN);
1263 reg_capa.allow_80mhz = flags & REG_CAPA_80MHZ_ALLOWED;
1264 reg_capa.allow_160mhz = flags & REG_CAPA_160MHZ_ALLOWED;
1265 reg_capa.disable_11ax = flags & REG_CAPA_11AX_DISABLED;
1266 }
1267 return reg_capa;
1268}
1269
1270struct ieee80211_regdomain *
1271iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1272 int num_of_ch, __le32 *channels, u16 fw_mcc,
1273 u16 geo_info, u16 cap, u8 resp_ver)
1274{
1275 int ch_idx;
1276 u16 ch_flags;
1277 u32 reg_rule_flags, prev_reg_rule_flags = 0;
1278 const u16 *nvm_chan;
1279 struct ieee80211_regdomain *regd, *copy_rd;
1280 struct ieee80211_reg_rule *rule;
1281 enum nl80211_band band;
1282 int center_freq, prev_center_freq = 0;
1283 int valid_rules = 0;
1284 bool new_rule;
1285 int max_num_ch;
1286 struct iwl_reg_capa reg_capa;
1287
1288 if (cfg->uhb_supported) {
1289 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB;
1290 nvm_chan = iwl_uhb_nvm_channels;
1291 } else if (cfg->nvm_type == IWL_NVM_EXT) {
1292 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT;
1293 nvm_chan = iwl_ext_nvm_channels;
1294 } else {
1295 max_num_ch = IWL_NVM_NUM_CHANNELS;
1296 nvm_chan = iwl_nvm_channels;
1297 }
1298
1299 if (WARN_ON(num_of_ch > max_num_ch))
1300 num_of_ch = max_num_ch;
1301
1302 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1303 return ERR_PTR(-EINVAL);
1304
1305 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1306 num_of_ch);
1307
1308
1309 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL);
1310 if (!regd)
1311 return ERR_PTR(-ENOMEM);
1312
1313
1314 regd->alpha2[0] = fw_mcc >> 8;
1315 regd->alpha2[1] = fw_mcc & 0xff;
1316
1317
1318 reg_capa = iwl_get_reg_capa(cap, resp_ver);
1319
1320 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1321 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1322 band = iwl_nl80211_band_from_channel_idx(ch_idx);
1323 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1324 band);
1325 new_rule = false;
1326
1327 if (!(ch_flags & NVM_CHANNEL_VALID)) {
1328 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1329 nvm_chan[ch_idx], ch_flags);
1330 continue;
1331 }
1332
1333 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1334 ch_flags, reg_capa,
1335 cfg);
1336
1337
1338 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1339 center_freq - prev_center_freq > 20) {
1340 valid_rules++;
1341 new_rule = true;
1342 }
1343
1344 rule = ®d->reg_rules[valid_rules - 1];
1345
1346 if (new_rule)
1347 rule->freq_range.start_freq_khz =
1348 MHZ_TO_KHZ(center_freq - 10);
1349
1350 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1351
1352
1353 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1354 rule->power_rule.max_eirp =
1355 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1356
1357 rule->flags = reg_rule_flags;
1358
1359
1360 rule->flags |= NL80211_RRF_AUTO_BW;
1361 rule->freq_range.max_bandwidth_khz = 0;
1362
1363 prev_center_freq = center_freq;
1364 prev_reg_rule_flags = reg_rule_flags;
1365
1366 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1367 nvm_chan[ch_idx], ch_flags);
1368
1369 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1370 band == NL80211_BAND_2GHZ)
1371 continue;
1372
1373 reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1374 }
1375
1376 regd->n_reg_rules = valid_rules;
1377
1378
1379
1380
1381
1382 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules),
1383 GFP_KERNEL);
1384 if (!copy_rd)
1385 copy_rd = ERR_PTR(-ENOMEM);
1386
1387 kfree(regd);
1388 return copy_rd;
1389}
1390IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1391
1392#define IWL_MAX_NVM_SECTION_SIZE 0x1b58
1393#define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc
1394#define MAX_NVM_FILE_LEN 16384
1395
1396void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1397 unsigned int len)
1398{
1399#define IWL_4165_DEVICE_ID 0x5501
1400#define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1401
1402 if (section == NVM_SECTION_TYPE_PHY_SKU &&
1403 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1404 (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1405
1406 data[3] = ANT_B | (ANT_B << 4);
1407}
1408IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431int iwl_read_external_nvm(struct iwl_trans *trans,
1432 const char *nvm_file_name,
1433 struct iwl_nvm_section *nvm_sections)
1434{
1435 int ret, section_size;
1436 u16 section_id;
1437 const struct firmware *fw_entry;
1438 const struct {
1439 __le16 word1;
1440 __le16 word2;
1441 u8 data[];
1442 } *file_sec;
1443 const u8 *eof;
1444 u8 *temp;
1445 int max_section_size;
1446 const __le32 *dword_buff;
1447
1448#define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1449#define NVM_WORD2_ID(x) (x >> 12)
1450#define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1451#define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1452#define NVM_HEADER_0 (0x2A504C54)
1453#define NVM_HEADER_1 (0x4E564D2A)
1454#define NVM_HEADER_SIZE (4 * sizeof(u32))
1455
1456 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1457
1458
1459 if (trans->cfg->nvm_type != IWL_NVM_EXT)
1460 max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1461 else
1462 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1463
1464
1465
1466
1467
1468
1469
1470 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1471 if (ret) {
1472 IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1473 nvm_file_name, ret);
1474 return ret;
1475 }
1476
1477 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1478 nvm_file_name, fw_entry->size);
1479
1480 if (fw_entry->size > MAX_NVM_FILE_LEN) {
1481 IWL_ERR(trans, "NVM file too large\n");
1482 ret = -EINVAL;
1483 goto out;
1484 }
1485
1486 eof = fw_entry->data + fw_entry->size;
1487 dword_buff = (__le32 *)fw_entry->data;
1488
1489
1490
1491
1492
1493
1494
1495
1496 if (fw_entry->size > NVM_HEADER_SIZE &&
1497 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1498 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1499 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
1500 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1501 IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1502 le32_to_cpu(dword_buff[3]));
1503
1504
1505 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1506 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP &&
1507 le32_to_cpu(dword_buff[2]) < 0xE4A) {
1508 ret = -EFAULT;
1509 goto out;
1510 }
1511 } else {
1512 file_sec = (void *)fw_entry->data;
1513 }
1514
1515 while (true) {
1516 if (file_sec->data > eof) {
1517 IWL_ERR(trans,
1518 "ERROR - NVM file too short for section header\n");
1519 ret = -EINVAL;
1520 break;
1521 }
1522
1523
1524 if (!file_sec->word1 && !file_sec->word2) {
1525 ret = 0;
1526 break;
1527 }
1528
1529 if (trans->cfg->nvm_type != IWL_NVM_EXT) {
1530 section_size =
1531 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
1532 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
1533 } else {
1534 section_size = 2 * EXT_NVM_WORD2_LEN(
1535 le16_to_cpu(file_sec->word2));
1536 section_id = EXT_NVM_WORD1_ID(
1537 le16_to_cpu(file_sec->word1));
1538 }
1539
1540 if (section_size > max_section_size) {
1541 IWL_ERR(trans, "ERROR - section too large (%d)\n",
1542 section_size);
1543 ret = -EINVAL;
1544 break;
1545 }
1546
1547 if (!section_size) {
1548 IWL_ERR(trans, "ERROR - section empty\n");
1549 ret = -EINVAL;
1550 break;
1551 }
1552
1553 if (file_sec->data + section_size > eof) {
1554 IWL_ERR(trans,
1555 "ERROR - NVM file too short for section (%d bytes)\n",
1556 section_size);
1557 ret = -EINVAL;
1558 break;
1559 }
1560
1561 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
1562 "Invalid NVM section ID %d\n", section_id)) {
1563 ret = -EINVAL;
1564 break;
1565 }
1566
1567 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
1568 if (!temp) {
1569 ret = -ENOMEM;
1570 break;
1571 }
1572
1573 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
1574
1575 kfree(nvm_sections[section_id].data);
1576 nvm_sections[section_id].data = temp;
1577 nvm_sections[section_id].length = section_size;
1578
1579
1580 file_sec = (void *)(file_sec->data + section_size);
1581 }
1582out:
1583 release_firmware(fw_entry);
1584 return ret;
1585}
1586IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
1587
1588struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
1589 const struct iwl_fw *fw)
1590{
1591 struct iwl_nvm_get_info cmd = {};
1592 struct iwl_nvm_data *nvm;
1593 struct iwl_host_cmd hcmd = {
1594 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
1595 .data = { &cmd, },
1596 .len = { sizeof(cmd) },
1597 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
1598 };
1599 int ret;
1600 bool empty_otp;
1601 u32 mac_flags;
1602 u32 sbands_flags = 0;
1603
1604
1605
1606
1607
1608
1609 struct iwl_nvm_get_info_rsp *rsp;
1610 struct iwl_nvm_get_info_rsp_v3 *rsp_v3;
1611 bool v4 = fw_has_api(&fw->ucode_capa,
1612 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO);
1613 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);
1614 void *channel_profile;
1615
1616 ret = iwl_trans_send_cmd(trans, &hcmd);
1617 if (ret)
1618 return ERR_PTR(ret);
1619
1620 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size,
1621 "Invalid payload len in NVM response from FW %d",
1622 iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
1623 ret = -EINVAL;
1624 goto out;
1625 }
1626
1627 rsp = (void *)hcmd.resp_pkt->data;
1628 empty_otp = !!(le32_to_cpu(rsp->general.flags) &
1629 NVM_GENERAL_FLAGS_EMPTY_OTP);
1630 if (empty_otp)
1631 IWL_INFO(trans, "OTP is empty\n");
1632
1633 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
1634 if (!nvm) {
1635 ret = -ENOMEM;
1636 goto out;
1637 }
1638
1639 iwl_set_hw_address_from_csr(trans, nvm);
1640
1641
1642 if (!is_valid_ether_addr(nvm->hw_addr)) {
1643 IWL_ERR(trans, "no valid mac address was found\n");
1644 ret = -EINVAL;
1645 goto err_free;
1646 }
1647
1648 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
1649
1650
1651 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
1652 nvm->n_hw_addrs = rsp->general.n_hw_addrs;
1653 if (nvm->n_hw_addrs == 0)
1654 IWL_WARN(trans,
1655 "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
1656 empty_otp);
1657
1658
1659 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
1660 nvm->sku_cap_11ac_enable =
1661 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
1662 nvm->sku_cap_11n_enable =
1663 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
1664 nvm->sku_cap_11ax_enable =
1665 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
1666 nvm->sku_cap_band_24ghz_enable =
1667 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
1668 nvm->sku_cap_band_52ghz_enable =
1669 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
1670 nvm->sku_cap_mimo_disabled =
1671 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
1672
1673
1674 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
1675 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
1676
1677 if (le32_to_cpu(rsp->regulatory.lar_enabled) &&
1678 fw_has_capa(&fw->ucode_capa,
1679 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) {
1680 nvm->lar_enabled = true;
1681 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1682 }
1683
1684 rsp_v3 = (void *)rsp;
1685 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile :
1686 (void *)rsp_v3->regulatory.channel_profile;
1687
1688 iwl_init_sbands(trans, nvm,
1689 channel_profile,
1690 nvm->valid_tx_ant & fw->valid_tx_ant,
1691 nvm->valid_rx_ant & fw->valid_rx_ant,
1692 sbands_flags, v4, fw);
1693
1694 iwl_free_resp(&hcmd);
1695 return nvm;
1696
1697err_free:
1698 kfree(nvm);
1699out:
1700 iwl_free_resp(&hcmd);
1701 return ERR_PTR(ret);
1702}
1703IWL_EXPORT_SYMBOL(iwl_get_nvm);
1704