1
2
3#ifndef __MT7603_EEPROM_H
4#define __MT7603_EEPROM_H
5
6#include "mt7603.h"
7
8enum mt7603_eeprom_field {
9 MT_EE_CHIP_ID = 0x000,
10 MT_EE_VERSION = 0x002,
11 MT_EE_MAC_ADDR = 0x004,
12 MT_EE_NIC_CONF_0 = 0x034,
13 MT_EE_NIC_CONF_1 = 0x036,
14 MT_EE_NIC_CONF_2 = 0x042,
15
16 MT_EE_XTAL_TRIM_1 = 0x03a,
17
18 MT_EE_RSSI_OFFSET_2G = 0x046,
19 MT_EE_WIFI_RF_SETTING = 0x048,
20 MT_EE_RSSI_OFFSET_5G = 0x04a,
21
22 MT_EE_TX_POWER_DELTA_BW40 = 0x050,
23 MT_EE_TX_POWER_DELTA_BW80 = 0x052,
24
25 MT_EE_TX_POWER_EXT_PA_5G = 0x054,
26
27 MT_EE_TEMP_SENSOR_CAL = 0x055,
28
29 MT_EE_TX_POWER_0_START_2G = 0x056,
30 MT_EE_TX_POWER_1_START_2G = 0x05c,
31
32
33#define MT_TX_POWER_GROUP_SIZE_5G 5
34#define MT_TX_POWER_GROUPS_5G 6
35 MT_EE_TX_POWER_0_START_5G = 0x062,
36
37 MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA = 0x074,
38 MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE = 0x076,
39
40 MT_EE_TX_POWER_1_START_5G = 0x080,
41
42 MT_EE_TX_POWER_CCK = 0x0a0,
43 MT_EE_TX_POWER_OFDM_2G_6M = 0x0a2,
44 MT_EE_TX_POWER_OFDM_2G_24M = 0x0a4,
45 MT_EE_TX_POWER_OFDM_2G_54M = 0x0a6,
46 MT_EE_TX_POWER_HT_BPSK_QPSK = 0x0a8,
47 MT_EE_TX_POWER_HT_16_64_QAM = 0x0aa,
48 MT_EE_TX_POWER_HT_64_QAM = 0x0ac,
49
50 MT_EE_ELAN_RX_MODE_GAIN = 0x0c0,
51 MT_EE_ELAN_RX_MODE_NF = 0x0c1,
52 MT_EE_ELAN_RX_MODE_P1DB = 0x0c2,
53
54 MT_EE_ELAN_BYPASS_MODE_GAIN = 0x0c3,
55 MT_EE_ELAN_BYPASS_MODE_NF = 0x0c4,
56 MT_EE_ELAN_BYPASS_MODE_P1DB = 0x0c5,
57
58 MT_EE_STEP_NUM_NEG_6_7 = 0x0c6,
59 MT_EE_STEP_NUM_NEG_4_5 = 0x0c8,
60 MT_EE_STEP_NUM_NEG_2_3 = 0x0ca,
61 MT_EE_STEP_NUM_NEG_0_1 = 0x0cc,
62
63 MT_EE_REF_STEP_24G = 0x0ce,
64
65 MT_EE_STEP_NUM_PLUS_1_2 = 0x0d0,
66 MT_EE_STEP_NUM_PLUS_3_4 = 0x0d2,
67 MT_EE_STEP_NUM_PLUS_5_6 = 0x0d4,
68 MT_EE_STEP_NUM_PLUS_7 = 0x0d6,
69
70 MT_EE_CP_FT_VERSION = 0x0f0,
71
72 MT_EE_TX_POWER_TSSI_OFF = 0x0f2,
73
74 MT_EE_XTAL_FREQ_OFFSET = 0x0f4,
75 MT_EE_XTAL_TRIM_2_COMP = 0x0f5,
76 MT_EE_XTAL_TRIM_3_COMP = 0x0f6,
77 MT_EE_XTAL_WF_RFCAL = 0x0f7,
78
79 __MT_EE_MAX
80};
81
82enum mt7603_eeprom_source {
83 MT_EE_SRC_PROM,
84 MT_EE_SRC_EFUSE,
85 MT_EE_SRC_FLASH,
86};
87
88#define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0)
89#define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4)
90
91#endif
92
