1
2
3
4#ifndef __MT7915_REGS_H
5#define __MT7915_REGS_H
6
7
8#define MT_MCU_WFDMA0_BASE 0x2000
9#define MT_MCU_WFDMA0(ofs) (MT_MCU_WFDMA0_BASE + (ofs))
10#define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
11
12
13#define MT_MCU_WFDMA1_BASE 0x3000
14#define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs))
15
16#define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
17#define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
18#define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
19#define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
20#define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
21
22#define MT_PLE_BASE 0x8000
23#define MT_PLE(ofs) (MT_PLE_BASE + (ofs))
24
25#define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0)
26#define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4)
27#define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8)
28#define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc)
29
30#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \
31 ((n) << 2))
32#define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
33
34#define MT_MDP_BASE 0xf000
35#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
36
37#define MT_MDP_DCR0 MT_MDP(0x000)
38#define MT_MDP_DCR0_DAMSDU_EN BIT(15)
39
40#define MT_MDP_DCR1 MT_MDP(0x004)
41#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)
42
43#define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8))
44#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)
45#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)
46#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)
47
48#define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8))
49#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)
50#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)
51#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)
52#define MT_MDP_TO_HIF 0
53#define MT_MDP_TO_WM 1
54
55
56#define MT_WF_TMAC_BASE(_band) ((_band) ? 0xa1000 : 0x21000)
57#define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))
58
59#define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)
60#define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25)
61
62#define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x090)
63#define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x094)
64#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
65#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
66
67#define MT_TMAC_ATCR(_band) MT_WF_TMAC(_band, 0x098)
68#define MT_TMAC_ATCR_TXV_TOUT GENMASK(7, 0)
69
70#define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, 0x09c)
71#define MT_TMAC_TRCR0_TR2T_CHK GENMASK(8, 0)
72#define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16)
73
74#define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4)
75#define MT_IFS_EIFS GENMASK(8, 0)
76#define MT_IFS_RIFS GENMASK(14, 10)
77#define MT_IFS_SIFS GENMASK(22, 16)
78#define MT_IFS_SLOT GENMASK(30, 24)
79
80#define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4)
81#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
82#define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
83#define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18)
84
85#define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, 0x1e0)
86
87#define MT_WF_DMA_BASE(_band) ((_band) ? 0xa1e00 : 0x21e00)
88#define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
89
90#define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)
91#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
92#define MT_DMA_DCR0_RXD_G5_EN BIT(23)
93
94
95#define MT_WF_ETBF_BASE(_band) ((_band) ? 0xa4000 : 0x24000)
96#define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs))
97
98#define MT_ETBF_TX_NDP_BFRP(_band) MT_WF_ETBF(_band, 0x040)
99#define MT_ETBF_TX_FB_CPL GENMASK(31, 16)
100#define MT_ETBF_TX_FB_TRI GENMASK(15, 0)
101
102#define MT_ETBF_RX_FB_CONT(_band) MT_WF_ETBF(_band, 0x068)
103#define MT_ETBF_RX_FB_BW GENMASK(7, 6)
104#define MT_ETBF_RX_FB_NC GENMASK(5, 3)
105#define MT_ETBF_RX_FB_NR GENMASK(2, 0)
106
107#define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x0f0)
108#define MT_ETBF_TX_IBF_CNT GENMASK(31, 16)
109#define MT_ETBF_TX_EBF_CNT GENMASK(15, 0)
110
111#define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x0f8)
112#define MT_ETBF_RX_FB_ALL GENMASK(31, 24)
113#define MT_ETBF_RX_FB_HE GENMASK(23, 16)
114#define MT_ETBF_RX_FB_VHT GENMASK(15, 8)
115#define MT_ETBF_RX_FB_HT GENMASK(7, 0)
116
117
118#define MT_WF_LPON_BASE(_band) ((_band) ? 0xa4200 : 0x24200)
119#define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs))
120
121#define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x080)
122#define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x084)
123
124#define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (n) * 4)
125#define MT_LPON_TCR_SW_MODE GENMASK(1, 0)
126#define MT_LPON_TCR_SW_WRITE BIT(0)
127#define MT_LPON_TCR_SW_ADJUST BIT(1)
128#define MT_LPON_TCR_SW_READ GENMASK(1, 0)
129
130
131#define MT_WF_MIB_BASE(_band) ((_band) ? 0xa4800 : 0x24800)
132#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs))
133
134#define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014)
135#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
136
137#define MT_MIB_SDR34(_band) MT_WF_MIB(_band, 0x090)
138#define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0)
139
140#define MT_MIB_DR8(_band) MT_WF_MIB(_band, 0x0c0)
141#define MT_MIB_DR9(_band) MT_WF_MIB(_band, 0x0c4)
142#define MT_MIB_DR11(_band) MT_WF_MIB(_band, 0x0cc)
143
144#define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4))
145#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
146#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
147
148#define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, 0x104 + ((n) << 4))
149#define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)
150#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
151
152#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0x0a8 + ((n) << 2))
153#define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, 0x164 + ((n) << 2))
154#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x4b8 + ((n) << 2))
155#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
156
157#define MT_WTBLON_TOP_BASE 0x34000
158#define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
159#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x0)
160#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
161
162#define MT_WTBL_UPDATE MT_WTBLON_TOP(0x030)
163#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0)
164#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
165#define MT_WTBL_UPDATE_BUSY BIT(31)
166
167#define MT_WTBL_BASE 0x38000
168#define MT_WTBL_LMAC_ID GENMASK(14, 8)
169#define MT_WTBL_LMAC_DW GENMASK(7, 2)
170#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \
171 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
172 FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
173
174
175#define MT_WF_AGG_BASE(_band) ((_band) ? 0xa0800 : 0x20800)
176#define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
177
178#define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, 0x05c + (_n) * 4)
179#define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, 0x06c + (_n) * 4)
180#define MT_AGG_PCR0_MM_PROT BIT(0)
181#define MT_AGG_PCR0_GF_PROT BIT(1)
182#define MT_AGG_PCR0_BW20_PROT BIT(2)
183#define MT_AGG_PCR0_BW40_PROT BIT(4)
184#define MT_AGG_PCR0_BW80_PROT BIT(6)
185#define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8)
186#define MT_AGG_PCR0_VHT_PROT BIT(13)
187#define MT_AGG_PCR0_PTA_WIN_DIS BIT(15)
188
189#define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23)
190#define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0)
191
192#define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x084)
193#define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
194#define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)
195
196#define MT_AGG_MRCR(_band) MT_WF_AGG(_band, 0x098)
197#define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12)
198#define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6)
199#define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7)
200#define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24)
201
202#define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, 0x0f0)
203#define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, 0x0f4)
204
205
206#define MT_WF_ARB_BASE(_band) ((_band) ? 0xa0c00 : 0x20c00)
207#define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs))
208
209#define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080)
210#define MT_ARB_SCR_TX_DISABLE BIT(8)
211#define MT_ARB_SCR_RX_DISABLE BIT(9)
212
213#define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, 0x194 + (_n) * 4)
214
215
216#define MT_WF_RMAC_BASE(_band) ((_band) ? 0xa1400 : 0x21400)
217#define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs))
218
219#define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
220#define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
221#define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
222#define MT_WF_RFCR_DROP_VERSION BIT(3)
223#define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
224#define MT_WF_RFCR_DROP_MCAST BIT(5)
225#define MT_WF_RFCR_DROP_BCAST BIT(6)
226#define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
227#define MT_WF_RFCR_DROP_A3_MAC BIT(8)
228#define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
229#define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
230#define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
231#define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
232#define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
233#define MT_WF_RFCR_DROP_CTS BIT(14)
234#define MT_WF_RFCR_DROP_RTS BIT(15)
235#define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
236#define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
237#define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
238#define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
239#define MT_WF_RFCR_DROP_NDPA BIT(20)
240#define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
241
242#define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)
243#define MT_WF_RFCR1_DROP_ACK BIT(4)
244#define MT_WF_RFCR1_DROP_BF_POLL BIT(5)
245#define MT_WF_RFCR1_DROP_BA BIT(6)
246#define MT_WF_RFCR1_DROP_CFEND BIT(7)
247#define MT_WF_RFCR1_DROP_CFACK BIT(8)
248
249#define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
250#define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)
251#define MT_WF_RMAC_MIB_RXTIME_EN BIT(30)
252
253
254#define MT_WFDMA0_BASE 0xd4000
255#define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs))
256
257#define MT_WFDMA0_RST MT_WFDMA0(0x100)
258#define MT_WFDMA0_RST_LOGIC_RST BIT(4)
259#define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5)
260
261#define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
262#define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
263#define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1)
264#define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2)
265
266#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
267#define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
268#define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
269
270#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
271#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
272
273#define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500)
274
275#define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680)
276#define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684)
277#define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688)
278
279
280#define MT_WFDMA1_BASE 0xd5000
281#define MT_WFDMA1(ofs) (MT_WFDMA1_BASE + (ofs))
282
283#define MT_WFDMA1_RST MT_WFDMA1(0x100)
284#define MT_WFDMA1_RST_LOGIC_RST BIT(4)
285#define MT_WFDMA1_RST_DMASHDL_ALL_RST BIT(5)
286
287#define MT_WFDMA1_BUSY_ENA MT_WFDMA1(0x13c)
288#define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0)
289#define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1)
290#define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2)
291
292#define MT_MCU_CMD MT_WFDMA1(0x1f0)
293#define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1)
294#define MT_MCU_CMD_STOP_DMA BIT(2)
295#define MT_MCU_CMD_RESET_DONE BIT(3)
296#define MT_MCU_CMD_RECOVERY_DONE BIT(4)
297#define MT_MCU_CMD_NORMAL_STATE BIT(5)
298#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)
299
300#define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208)
301#define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
302#define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
303#define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28)
304#define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27)
305
306#define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c)
307#define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0)
308
309#define MT_TX_RING_BASE MT_WFDMA1(0x300)
310#define MT_RX_EVENT_RING_BASE MT_WFDMA1(0x500)
311
312#define MT_WFDMA1_TX_RING0_EXT_CTRL MT_WFDMA1(0x600)
313#define MT_WFDMA1_TX_RING1_EXT_CTRL MT_WFDMA1(0x604)
314#define MT_WFDMA1_TX_RING2_EXT_CTRL MT_WFDMA1(0x608)
315#define MT_WFDMA1_TX_RING3_EXT_CTRL MT_WFDMA1(0x60c)
316#define MT_WFDMA1_TX_RING4_EXT_CTRL MT_WFDMA1(0x610)
317#define MT_WFDMA1_TX_RING5_EXT_CTRL MT_WFDMA1(0x614)
318#define MT_WFDMA1_TX_RING6_EXT_CTRL MT_WFDMA1(0x618)
319#define MT_WFDMA1_TX_RING7_EXT_CTRL MT_WFDMA1(0x61c)
320
321#define MT_WFDMA1_TX_RING16_EXT_CTRL MT_WFDMA1(0x640)
322#define MT_WFDMA1_TX_RING17_EXT_CTRL MT_WFDMA1(0x644)
323#define MT_WFDMA1_TX_RING18_EXT_CTRL MT_WFDMA1(0x648)
324#define MT_WFDMA1_TX_RING19_EXT_CTRL MT_WFDMA1(0x64c)
325#define MT_WFDMA1_TX_RING20_EXT_CTRL MT_WFDMA1(0x650)
326#define MT_WFDMA1_TX_RING21_EXT_CTRL MT_WFDMA1(0x654)
327#define MT_WFDMA1_TX_RING22_EXT_CTRL MT_WFDMA1(0x658)
328#define MT_WFDMA1_TX_RING23_EXT_CTRL MT_WFDMA1(0x65c)
329
330#define MT_WFDMA1_RX_RING0_EXT_CTRL MT_WFDMA1(0x680)
331#define MT_WFDMA1_RX_RING1_EXT_CTRL MT_WFDMA1(0x684)
332#define MT_WFDMA1_RX_RING2_EXT_CTRL MT_WFDMA1(0x688)
333#define MT_WFDMA1_RX_RING3_EXT_CTRL MT_WFDMA1(0x68c)
334
335
336#define MT_WFDMA_EXT_CSR_BASE 0xd7000
337#define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs))
338
339#define MT_INT_SOURCE_CSR MT_WFDMA_EXT_CSR(0x10)
340#define MT_INT_MASK_CSR MT_WFDMA_EXT_CSR(0x14)
341#define MT_INT_RX_DONE_DATA0 BIT(16)
342#define MT_INT_RX_DONE_DATA1 BIT(17)
343#define MT_INT_RX_DONE_WM BIT(0)
344#define MT_INT_RX_DONE_WA BIT(1)
345#define MT_INT_RX_DONE_WA_EXT BIT(2)
346#define MT_INT_RX_DONE_ALL (GENMASK(2, 0) | GENMASK(17, 16))
347#define MT_INT_TX_DONE_MCU_WA BIT(15)
348#define MT_INT_TX_DONE_FWDL BIT(26)
349#define MT_INT_TX_DONE_MCU_WM BIT(27)
350#define MT_INT_TX_DONE_BAND0 BIT(30)
351#define MT_INT_TX_DONE_BAND1 BIT(31)
352
353#define MT_INT_BAND1_MASK (MT_INT_RX_DONE_WA_EXT | \
354 MT_INT_TX_DONE_BAND1)
355
356#define MT_INT_MCU_CMD BIT(29)
357
358#define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WA | \
359 MT_INT_TX_DONE_MCU_WM | \
360 MT_INT_TX_DONE_FWDL)
361
362#define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30)
363#define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0)
364
365#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)
366#define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
367
368#define MT_INT1_SOURCE_CSR MT_WFDMA_EXT_CSR(0x88)
369#define MT_INT1_MASK_CSR MT_WFDMA_EXT_CSR(0x8c)
370
371#define MT_PCIE_RECOG_ID MT_WFDMA_EXT_CSR(0x90)
372#define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)
373#define MT_PCIE_RECOG_ID_SEM BIT(31)
374
375
376#define MT_WFDMA0_PCIE1_BASE 0xd8000
377#define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
378
379#define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
380#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
381#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
382#define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
383
384
385#define MT_WFDMA1_PCIE1_BASE 0xd9000
386#define MT_WFDMA1_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
387
388#define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c)
389#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
390#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
391#define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
392
393#define MT_TOP_RGU_BASE 0xf0000
394#define MT_TOP_PWR_CTRL (MT_TOP_RGU_BASE + (0x0))
395#define MT_TOP_PWR_KEY (0x5746 << 16)
396#define MT_TOP_PWR_SW_RST BIT(0)
397#define MT_TOP_PWR_SW_PWR_ON GENMASK(3, 2)
398#define MT_TOP_PWR_HW_CTRL BIT(4)
399#define MT_TOP_PWR_PWR_ON BIT(7)
400
401#define MT_INFRA_CFG_BASE 0xf1000
402#define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs))
403
404#define MT_HIF_REMAP_L1 MT_INFRA(0x1ac)
405#define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)
406#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
407#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
408#define MT_HIF_REMAP_BASE_L1 0xe0000
409
410#define MT_HIF_REMAP_L2 MT_INFRA(0x1b0)
411#define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)
412#define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)
413#define MT_HIF_REMAP_L2_BASE GENMASK(31, 12)
414#define MT_HIF_REMAP_BASE_L2 0x00000
415
416#define MT_SWDEF_BASE 0x41f200
417#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs))
418#define MT_SWDEF_MODE MT_SWDEF(0x3c)
419#define MT_SWDEF_NORMAL_MODE 0
420#define MT_SWDEF_ICAP_MODE 1
421#define MT_SWDEF_SPECTRUM_MODE 2
422
423#define MT_TOP_BASE 0x18060000
424#define MT_TOP(ofs) (MT_TOP_BASE + (ofs))
425
426#define MT_TOP_LPCR_HOST_BAND0 MT_TOP(0x10)
427#define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
428#define MT_TOP_LPCR_HOST_DRV_OWN BIT(1)
429
430#define MT_TOP_MISC MT_TOP(0xf0)
431#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
432
433#define MT_HW_BOUND 0x70010020
434#define MT_HW_CHIPID 0x70010200
435#define MT_HW_REV 0x70010204
436
437#define MT_PCIE1_MAC_BASE 0x74020000
438#define MT_PCIE1_MAC(ofs) (MT_PCIE1_MAC_BASE + (ofs))
439#define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188)
440
441#define MT_PCIE_MAC_BASE 0x74030000
442#define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs))
443#define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
444
445#define MT_WF_IRPI_BASE 0x83006000
446#define MT_WF_IRPI(ofs) (MT_WF_IRPI_BASE + ((ofs) << 16))
447
448
449#define MT_WF_PHY_BASE 0x83080000
450#define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs))
451
452#define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16))
453#define MT_WF_PHY_RX_CTRL1_IPI_EN GENMASK(2, 0)
454#define MT_WF_PHY_RX_CTRL1_STSCNT_EN GENMASK(11, 9)
455
456#define MT_WF_PHY_RXTD12(_phy) MT_WF_PHY(0x8230 + ((_phy) << 16))
457#define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18)
458#define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29)
459
460#endif
461
