1
2
3
4
5#include <linux/devcoredump.h>
6
7#include "main.h"
8#include "regd.h"
9#include "fw.h"
10#include "ps.h"
11#include "sec.h"
12#include "mac.h"
13#include "coex.h"
14#include "phy.h"
15#include "reg.h"
16#include "efuse.h"
17#include "tx.h"
18#include "debug.h"
19#include "bf.h"
20
21bool rtw_disable_lps_deep_mode;
22EXPORT_SYMBOL(rtw_disable_lps_deep_mode);
23bool rtw_bf_support = true;
24unsigned int rtw_debug_mask;
25EXPORT_SYMBOL(rtw_debug_mask);
26
27module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644);
28module_param_named(support_bf, rtw_bf_support, bool, 0644);
29module_param_named(debug_mask, rtw_debug_mask, uint, 0644);
30
31MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS");
32MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support");
33MODULE_PARM_DESC(debug_mask, "Debugging mask");
34
35static struct ieee80211_channel rtw_channeltable_2g[] = {
36 {.center_freq = 2412, .hw_value = 1,},
37 {.center_freq = 2417, .hw_value = 2,},
38 {.center_freq = 2422, .hw_value = 3,},
39 {.center_freq = 2427, .hw_value = 4,},
40 {.center_freq = 2432, .hw_value = 5,},
41 {.center_freq = 2437, .hw_value = 6,},
42 {.center_freq = 2442, .hw_value = 7,},
43 {.center_freq = 2447, .hw_value = 8,},
44 {.center_freq = 2452, .hw_value = 9,},
45 {.center_freq = 2457, .hw_value = 10,},
46 {.center_freq = 2462, .hw_value = 11,},
47 {.center_freq = 2467, .hw_value = 12,},
48 {.center_freq = 2472, .hw_value = 13,},
49 {.center_freq = 2484, .hw_value = 14,},
50};
51
52static struct ieee80211_channel rtw_channeltable_5g[] = {
53 {.center_freq = 5180, .hw_value = 36,},
54 {.center_freq = 5200, .hw_value = 40,},
55 {.center_freq = 5220, .hw_value = 44,},
56 {.center_freq = 5240, .hw_value = 48,},
57 {.center_freq = 5260, .hw_value = 52,},
58 {.center_freq = 5280, .hw_value = 56,},
59 {.center_freq = 5300, .hw_value = 60,},
60 {.center_freq = 5320, .hw_value = 64,},
61 {.center_freq = 5500, .hw_value = 100,},
62 {.center_freq = 5520, .hw_value = 104,},
63 {.center_freq = 5540, .hw_value = 108,},
64 {.center_freq = 5560, .hw_value = 112,},
65 {.center_freq = 5580, .hw_value = 116,},
66 {.center_freq = 5600, .hw_value = 120,},
67 {.center_freq = 5620, .hw_value = 124,},
68 {.center_freq = 5640, .hw_value = 128,},
69 {.center_freq = 5660, .hw_value = 132,},
70 {.center_freq = 5680, .hw_value = 136,},
71 {.center_freq = 5700, .hw_value = 140,},
72 {.center_freq = 5720, .hw_value = 144,},
73 {.center_freq = 5745, .hw_value = 149,},
74 {.center_freq = 5765, .hw_value = 153,},
75 {.center_freq = 5785, .hw_value = 157,},
76 {.center_freq = 5805, .hw_value = 161,},
77 {.center_freq = 5825, .hw_value = 165,
78 .flags = IEEE80211_CHAN_NO_HT40MINUS},
79};
80
81static struct ieee80211_rate rtw_ratetable[] = {
82 {.bitrate = 10, .hw_value = 0x00,},
83 {.bitrate = 20, .hw_value = 0x01,},
84 {.bitrate = 55, .hw_value = 0x02,},
85 {.bitrate = 110, .hw_value = 0x03,},
86 {.bitrate = 60, .hw_value = 0x04,},
87 {.bitrate = 90, .hw_value = 0x05,},
88 {.bitrate = 120, .hw_value = 0x06,},
89 {.bitrate = 180, .hw_value = 0x07,},
90 {.bitrate = 240, .hw_value = 0x08,},
91 {.bitrate = 360, .hw_value = 0x09,},
92 {.bitrate = 480, .hw_value = 0x0a,},
93 {.bitrate = 540, .hw_value = 0x0b,},
94};
95
96u16 rtw_desc_to_bitrate(u8 desc_rate)
97{
98 struct ieee80211_rate rate;
99
100 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n"))
101 return 0;
102
103 rate = rtw_ratetable[desc_rate];
104
105 return rate.bitrate;
106}
107
108static struct ieee80211_supported_band rtw_band_2ghz = {
109 .band = NL80211_BAND_2GHZ,
110
111 .channels = rtw_channeltable_2g,
112 .n_channels = ARRAY_SIZE(rtw_channeltable_2g),
113
114 .bitrates = rtw_ratetable,
115 .n_bitrates = ARRAY_SIZE(rtw_ratetable),
116
117 .ht_cap = {0},
118 .vht_cap = {0},
119};
120
121static struct ieee80211_supported_band rtw_band_5ghz = {
122 .band = NL80211_BAND_5GHZ,
123
124 .channels = rtw_channeltable_5g,
125 .n_channels = ARRAY_SIZE(rtw_channeltable_5g),
126
127
128 .bitrates = rtw_ratetable + 4,
129 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
130
131 .ht_cap = {0},
132 .vht_cap = {0},
133};
134
135struct rtw_watch_dog_iter_data {
136 struct rtw_dev *rtwdev;
137 struct rtw_vif *rtwvif;
138};
139
140static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
141{
142 struct rtw_bf_info *bf_info = &rtwdev->bf_info;
143 u8 fix_rate_enable = 0;
144 u8 new_csi_rate_idx;
145
146 if (rtwvif->bfee.role != RTW_BFEE_SU &&
147 rtwvif->bfee.role != RTW_BFEE_MU)
148 return;
149
150 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
151 bf_info->cur_csi_rpt_rate,
152 fix_rate_enable, &new_csi_rate_idx);
153
154 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
155 bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
156}
157
158static void rtw_vif_watch_dog_iter(void *data, u8 *mac,
159 struct ieee80211_vif *vif)
160{
161 struct rtw_watch_dog_iter_data *iter_data = data;
162 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
163
164 if (vif->type == NL80211_IFTYPE_STATION)
165 if (vif->bss_conf.assoc)
166 iter_data->rtwvif = rtwvif;
167
168 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
169
170 rtwvif->stats.tx_unicast = 0;
171 rtwvif->stats.rx_unicast = 0;
172 rtwvif->stats.tx_cnt = 0;
173 rtwvif->stats.rx_cnt = 0;
174}
175
176
177
178
179static void rtw_watch_dog_work(struct work_struct *work)
180{
181 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
182 watch_dog_work.work);
183 struct rtw_traffic_stats *stats = &rtwdev->stats;
184 struct rtw_watch_dog_iter_data data = {};
185 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
186 bool ps_active;
187
188 mutex_lock(&rtwdev->mutex);
189
190 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
191 goto unlock;
192
193 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
194 RTW_WATCH_DOG_DELAY_TIME);
195
196 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
197 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
198 else
199 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
200
201 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
202 rtw_coex_wl_status_change_notify(rtwdev, 0);
203
204 if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
205 stats->rx_cnt > RTW_LPS_THRESHOLD)
206 ps_active = true;
207 else
208 ps_active = false;
209
210 ewma_tp_add(&stats->tx_ewma_tp,
211 (u32)(stats->tx_unicast >> RTW_TP_SHIFT));
212 ewma_tp_add(&stats->rx_ewma_tp,
213 (u32)(stats->rx_unicast >> RTW_TP_SHIFT));
214 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
215 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
216
217
218 stats->tx_unicast = 0;
219 stats->rx_unicast = 0;
220 stats->tx_cnt = 0;
221 stats->rx_cnt = 0;
222
223 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
224 goto unlock;
225
226
227 rtw_leave_lps(rtwdev);
228
229 rtw_phy_dynamic_mechanism(rtwdev);
230
231 data.rtwdev = rtwdev;
232
233 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data);
234
235
236
237
238
239
240
241
242
243
244 if (rtwdev->ps_enabled && data.rtwvif && !ps_active &&
245 !rtwdev->beacon_loss)
246 rtw_enter_lps(rtwdev, data.rtwvif->port);
247
248 rtwdev->watch_dog_cnt++;
249
250unlock:
251 mutex_unlock(&rtwdev->mutex);
252}
253
254static void rtw_c2h_work(struct work_struct *work)
255{
256 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work);
257 struct sk_buff *skb, *tmp;
258
259 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
260 skb_unlink(skb, &rtwdev->c2h_queue);
261 rtw_fw_c2h_cmd_handle(rtwdev, skb);
262 dev_kfree_skb_any(skb);
263 }
264}
265
266static u8 rtw_acquire_macid(struct rtw_dev *rtwdev)
267{
268 unsigned long mac_id;
269
270 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM);
271 if (mac_id < RTW_MAX_MAC_ID_NUM)
272 set_bit(mac_id, rtwdev->mac_id_map);
273
274 return mac_id;
275}
276
277int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
278 struct ieee80211_vif *vif)
279{
280 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
281 int i;
282
283 si->mac_id = rtw_acquire_macid(rtwdev);
284 if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
285 return -ENOSPC;
286
287 si->sta = sta;
288 si->vif = vif;
289 si->init_ra_lv = 1;
290 ewma_rssi_init(&si->avg_rssi);
291 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
292 rtw_txq_init(rtwdev, sta->txq[i]);
293
294 rtw_update_sta_info(rtwdev, si);
295 rtw_fw_media_status_report(rtwdev, si->mac_id, true);
296
297 rtwdev->sta_cnt++;
298 rtwdev->beacon_loss = false;
299 rtw_info(rtwdev, "sta %pM joined with macid %d\n",
300 sta->addr, si->mac_id);
301
302 return 0;
303}
304
305void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
306 bool fw_exist)
307{
308 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
309 int i;
310
311 rtw_release_macid(rtwdev, si->mac_id);
312 if (fw_exist)
313 rtw_fw_media_status_report(rtwdev, si->mac_id, false);
314
315 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
316 rtw_txq_cleanup(rtwdev, sta->txq[i]);
317
318 kfree(si->mask);
319
320 rtwdev->sta_cnt--;
321 rtw_info(rtwdev, "sta %pM with macid %d left\n",
322 sta->addr, si->mac_id);
323}
324
325struct rtw_fwcd_hdr {
326 u32 item;
327 u32 size;
328 u32 padding1;
329 u32 padding2;
330} __packed;
331
332static int rtw_fwcd_prep(struct rtw_dev *rtwdev)
333{
334 struct rtw_chip_info *chip = rtwdev->chip;
335 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
336 const struct rtw_fwcd_segs *segs = chip->fwcd_segs;
337 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr);
338 u8 i;
339
340 if (segs) {
341 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr);
342
343 for (i = 0; i < segs->num; i++)
344 prep_size += segs->segs[i];
345 }
346
347 desc->data = vmalloc(prep_size);
348 if (!desc->data)
349 return -ENOMEM;
350
351 desc->size = prep_size;
352 desc->next = desc->data;
353
354 return 0;
355}
356
357static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size)
358{
359 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
360 struct rtw_fwcd_hdr *hdr;
361 u8 *next;
362
363 if (!desc->data) {
364 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n");
365 return NULL;
366 }
367
368 next = desc->next + sizeof(struct rtw_fwcd_hdr);
369 if (next - desc->data + size > desc->size) {
370 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n");
371 return NULL;
372 }
373
374 hdr = (struct rtw_fwcd_hdr *)(desc->next);
375 hdr->item = item;
376 hdr->size = size;
377 hdr->padding1 = 0x01234567;
378 hdr->padding2 = 0x89abcdef;
379 desc->next = next + size;
380
381 return next;
382}
383
384static void rtw_fwcd_dump(struct rtw_dev *rtwdev)
385{
386 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
387
388 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n");
389
390
391
392
393
394
395 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL);
396}
397
398static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self)
399{
400 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
401
402 if (free_self) {
403 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n");
404 vfree(desc->data);
405 }
406
407 desc->data = NULL;
408 desc->next = NULL;
409}
410
411static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev)
412{
413 u32 size = rtwdev->chip->fw_rxff_size;
414 u32 *buf;
415 u8 seq;
416
417 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size);
418 if (!buf)
419 return -ENOMEM;
420
421 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
422 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n");
423 return -EINVAL;
424 }
425
426 if (GET_FW_DUMP_LEN(buf) == 0) {
427 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");
428 return -EINVAL;
429 }
430
431 seq = GET_FW_DUMP_SEQ(buf);
432 if (seq > 0) {
433 rtw_dbg(rtwdev, RTW_DBG_FW,
434 "fw crash dump's seq is wrong: %d\n", seq);
435 return -EINVAL;
436 }
437
438 return 0;
439}
440
441int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
442 u32 fwcd_item)
443{
444 u32 rxff = rtwdev->chip->fw_rxff_size;
445 u32 dump_size, done_size = 0;
446 u8 *buf;
447 int ret;
448
449 buf = rtw_fwcd_next(rtwdev, fwcd_item, size);
450 if (!buf)
451 return -ENOMEM;
452
453 while (size) {
454 dump_size = size > rxff ? rxff : size;
455
456 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size,
457 dump_size);
458 if (ret) {
459 rtw_err(rtwdev,
460 "ddma fw 0x%x [+0x%x] to fw fifo fail\n",
461 ocp_src, done_size);
462 return ret;
463 }
464
465 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0,
466 dump_size, (u32 *)(buf + done_size));
467 if (ret) {
468 rtw_err(rtwdev,
469 "dump fw 0x%x [+0x%x] from fw fifo fail\n",
470 ocp_src, done_size);
471 return ret;
472 }
473
474 size -= dump_size;
475 done_size += dump_size;
476 }
477
478 return 0;
479}
480EXPORT_SYMBOL(rtw_dump_fw);
481
482int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size)
483{
484 u8 *buf;
485 u32 i;
486
487 if (addr & 0x3) {
488 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr);
489 return -EINVAL;
490 }
491
492 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size);
493 if (!buf)
494 return -ENOMEM;
495
496 for (i = 0; i < size; i += 4)
497 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i);
498
499 return 0;
500}
501EXPORT_SYMBOL(rtw_dump_reg);
502
503void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
504 struct ieee80211_bss_conf *conf)
505{
506 if (conf && conf->assoc) {
507 rtwvif->aid = conf->aid;
508 rtwvif->net_type = RTW_NET_MGD_LINKED;
509 } else {
510 rtwvif->aid = 0;
511 rtwvif->net_type = RTW_NET_NO_LINK;
512 }
513}
514
515static void rtw_reset_key_iter(struct ieee80211_hw *hw,
516 struct ieee80211_vif *vif,
517 struct ieee80211_sta *sta,
518 struct ieee80211_key_conf *key,
519 void *data)
520{
521 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
522 struct rtw_sec_desc *sec = &rtwdev->sec;
523
524 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
525}
526
527static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta)
528{
529 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
530
531 if (rtwdev->sta_cnt == 0) {
532 rtw_warn(rtwdev, "sta count before reset should not be 0\n");
533 return;
534 }
535 rtw_sta_remove(rtwdev, sta, false);
536}
537
538static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
539{
540 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
541 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
542
543 rtw_bf_disassoc(rtwdev, vif, NULL);
544 rtw_vif_assoc_changed(rtwvif, NULL);
545 rtw_txq_cleanup(rtwdev, vif->txq);
546}
547
548void rtw_fw_recovery(struct rtw_dev *rtwdev)
549{
550 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
551 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
552}
553
554static void __fw_recovery_work(struct rtw_dev *rtwdev)
555{
556 int ret = 0;
557
558 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
559
560 ret = rtw_fwcd_prep(rtwdev);
561 if (ret)
562 goto free;
563 ret = rtw_fw_dump_crash_log(rtwdev);
564 if (ret)
565 goto free;
566 ret = rtw_chip_dump_fw_crash(rtwdev);
567 if (ret)
568 goto free;
569
570 rtw_fwcd_dump(rtwdev);
571free:
572 rtw_fwcd_free(rtwdev, !!ret);
573 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);
574
575 WARN(1, "firmware crash, start reset and recover\n");
576
577 rcu_read_lock();
578 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev);
579 rcu_read_unlock();
580 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev);
581 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev);
582 rtw_enter_ips(rtwdev);
583}
584
585static void rtw_fw_recovery_work(struct work_struct *work)
586{
587 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
588 fw_recovery_work);
589
590 mutex_lock(&rtwdev->mutex);
591 __fw_recovery_work(rtwdev);
592 mutex_unlock(&rtwdev->mutex);
593
594 ieee80211_restart_hw(rtwdev->hw);
595}
596
597struct rtw_txq_ba_iter_data {
598};
599
600static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta)
601{
602 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
603 int ret;
604 u8 tid;
605
606 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
607 while (tid != IEEE80211_NUM_TIDS) {
608 clear_bit(tid, si->tid_ba);
609 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
610 if (ret == -EINVAL) {
611 struct ieee80211_txq *txq;
612 struct rtw_txq *rtwtxq;
613
614 txq = sta->txq[tid];
615 rtwtxq = (struct rtw_txq *)txq->drv_priv;
616 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
617 }
618
619 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
620 }
621}
622
623static void rtw_txq_ba_work(struct work_struct *work)
624{
625 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work);
626 struct rtw_txq_ba_iter_data data;
627
628 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data);
629}
630
631void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
632 struct rtw_channel_params *chan_params)
633{
634 struct ieee80211_channel *channel = chandef->chan;
635 enum nl80211_chan_width width = chandef->width;
636 u8 *cch_by_bw = chan_params->cch_by_bw;
637 u32 primary_freq, center_freq;
638 u8 center_chan;
639 u8 bandwidth = RTW_CHANNEL_WIDTH_20;
640 u8 primary_chan_idx = 0;
641 u8 i;
642
643 center_chan = channel->hw_value;
644 primary_freq = channel->center_freq;
645 center_freq = chandef->center_freq1;
646
647
648 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value;
649
650 switch (width) {
651 case NL80211_CHAN_WIDTH_20_NOHT:
652 case NL80211_CHAN_WIDTH_20:
653 bandwidth = RTW_CHANNEL_WIDTH_20;
654 primary_chan_idx = RTW_SC_DONT_CARE;
655 break;
656 case NL80211_CHAN_WIDTH_40:
657 bandwidth = RTW_CHANNEL_WIDTH_40;
658 if (primary_freq > center_freq) {
659 primary_chan_idx = RTW_SC_20_UPPER;
660 center_chan -= 2;
661 } else {
662 primary_chan_idx = RTW_SC_20_LOWER;
663 center_chan += 2;
664 }
665 break;
666 case NL80211_CHAN_WIDTH_80:
667 bandwidth = RTW_CHANNEL_WIDTH_80;
668 if (primary_freq > center_freq) {
669 if (primary_freq - center_freq == 10) {
670 primary_chan_idx = RTW_SC_20_UPPER;
671 center_chan -= 2;
672 } else {
673 primary_chan_idx = RTW_SC_20_UPMOST;
674 center_chan -= 6;
675 }
676
677
678
679 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4;
680 } else {
681 if (center_freq - primary_freq == 10) {
682 primary_chan_idx = RTW_SC_20_LOWER;
683 center_chan += 2;
684 } else {
685 primary_chan_idx = RTW_SC_20_LOWEST;
686 center_chan += 6;
687 }
688
689
690
691 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4;
692 }
693 break;
694 default:
695 center_chan = 0;
696 break;
697 }
698
699 chan_params->center_chan = center_chan;
700 chan_params->bandwidth = bandwidth;
701 chan_params->primary_chan_idx = primary_chan_idx;
702
703
704 cch_by_bw[bandwidth] = center_chan;
705
706 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++)
707 cch_by_bw[i] = 0;
708}
709
710void rtw_set_channel(struct rtw_dev *rtwdev)
711{
712 struct ieee80211_hw *hw = rtwdev->hw;
713 struct rtw_hal *hal = &rtwdev->hal;
714 struct rtw_chip_info *chip = rtwdev->chip;
715 struct rtw_channel_params ch_param;
716 u8 center_chan, bandwidth, primary_chan_idx;
717 u8 i;
718
719 rtw_get_channel_params(&hw->conf.chandef, &ch_param);
720 if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))
721 return;
722
723 center_chan = ch_param.center_chan;
724 bandwidth = ch_param.bandwidth;
725 primary_chan_idx = ch_param.primary_chan_idx;
726
727 hal->current_band_width = bandwidth;
728 hal->current_channel = center_chan;
729 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G;
730
731 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++)
732 hal->cch_by_bw[i] = ch_param.cch_by_bw[i];
733
734 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx);
735
736 if (hal->current_band_type == RTW_BAND_5G) {
737 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
738 } else {
739 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
740 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
741 else
742 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
743 }
744
745 rtw_phy_set_tx_power_level(rtwdev, center_chan);
746
747
748
749
750
751 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
752 rtwdev->need_rfk = true;
753}
754
755void rtw_chip_prepare_tx(struct rtw_dev *rtwdev)
756{
757 struct rtw_chip_info *chip = rtwdev->chip;
758
759 if (rtwdev->need_rfk) {
760 rtwdev->need_rfk = false;
761 chip->ops->phy_calibration(rtwdev);
762 }
763}
764
765static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr)
766{
767 int i;
768
769 for (i = 0; i < ETH_ALEN; i++)
770 rtw_write8(rtwdev, start + i, addr[i]);
771}
772
773void rtw_vif_port_config(struct rtw_dev *rtwdev,
774 struct rtw_vif *rtwvif,
775 u32 config)
776{
777 u32 addr, mask;
778
779 if (config & PORT_SET_MAC_ADDR) {
780 addr = rtwvif->conf->mac_addr.addr;
781 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
782 }
783 if (config & PORT_SET_BSSID) {
784 addr = rtwvif->conf->bssid.addr;
785 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
786 }
787 if (config & PORT_SET_NET_TYPE) {
788 addr = rtwvif->conf->net_type.addr;
789 mask = rtwvif->conf->net_type.mask;
790 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
791 }
792 if (config & PORT_SET_AID) {
793 addr = rtwvif->conf->aid.addr;
794 mask = rtwvif->conf->aid.mask;
795 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
796 }
797 if (config & PORT_SET_BCN_CTRL) {
798 addr = rtwvif->conf->bcn_ctrl.addr;
799 mask = rtwvif->conf->bcn_ctrl.mask;
800 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
801 }
802}
803
804static u8 hw_bw_cap_to_bitamp(u8 bw_cap)
805{
806 u8 bw = 0;
807
808 switch (bw_cap) {
809 case EFUSE_HW_CAP_IGNORE:
810 case EFUSE_HW_CAP_SUPP_BW80:
811 bw |= BIT(RTW_CHANNEL_WIDTH_80);
812 fallthrough;
813 case EFUSE_HW_CAP_SUPP_BW40:
814 bw |= BIT(RTW_CHANNEL_WIDTH_40);
815 fallthrough;
816 default:
817 bw |= BIT(RTW_CHANNEL_WIDTH_20);
818 break;
819 }
820
821 return bw;
822}
823
824static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num)
825{
826 struct rtw_hal *hal = &rtwdev->hal;
827 struct rtw_chip_info *chip = rtwdev->chip;
828
829 if (hw_ant_num == EFUSE_HW_CAP_IGNORE ||
830 hw_ant_num >= hal->rf_path_num)
831 return;
832
833 switch (hw_ant_num) {
834 case 1:
835 hal->rf_type = RF_1T1R;
836 hal->rf_path_num = 1;
837 if (!chip->fix_rf_phy_num)
838 hal->rf_phy_num = hal->rf_path_num;
839 hal->antenna_tx = BB_PATH_A;
840 hal->antenna_rx = BB_PATH_A;
841 break;
842 default:
843 WARN(1, "invalid hw configuration from efuse\n");
844 break;
845 }
846}
847
848static u64 get_vht_ra_mask(struct ieee80211_sta *sta)
849{
850 u64 ra_mask = 0;
851 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map);
852 u8 vht_mcs_cap;
853 int i, nss;
854
855
856 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {
857 vht_mcs_cap = mcs_map & 0x3;
858 switch (vht_mcs_cap) {
859 case 2:
860 ra_mask |= 0x3ffULL << nss;
861 break;
862 case 1:
863 ra_mask |= 0x1ffULL << nss;
864 break;
865 case 0:
866 ra_mask |= 0x0ffULL << nss;
867 break;
868 default:
869 break;
870 }
871 }
872
873 return ra_mask;
874}
875
876static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num)
877{
878 u8 rate_id = 0;
879
880 switch (wireless_set) {
881 case WIRELESS_CCK:
882 rate_id = RTW_RATEID_B_20M;
883 break;
884 case WIRELESS_OFDM:
885 rate_id = RTW_RATEID_G;
886 break;
887 case WIRELESS_CCK | WIRELESS_OFDM:
888 rate_id = RTW_RATEID_BG;
889 break;
890 case WIRELESS_OFDM | WIRELESS_HT:
891 if (tx_num == 1)
892 rate_id = RTW_RATEID_GN_N1SS;
893 else if (tx_num == 2)
894 rate_id = RTW_RATEID_GN_N2SS;
895 else if (tx_num == 3)
896 rate_id = RTW_RATEID_ARFR5_N_3SS;
897 break;
898 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT:
899 if (bw_mode == RTW_CHANNEL_WIDTH_40) {
900 if (tx_num == 1)
901 rate_id = RTW_RATEID_BGN_40M_1SS;
902 else if (tx_num == 2)
903 rate_id = RTW_RATEID_BGN_40M_2SS;
904 else if (tx_num == 3)
905 rate_id = RTW_RATEID_ARFR5_N_3SS;
906 else if (tx_num == 4)
907 rate_id = RTW_RATEID_ARFR7_N_4SS;
908 } else {
909 if (tx_num == 1)
910 rate_id = RTW_RATEID_BGN_20M_1SS;
911 else if (tx_num == 2)
912 rate_id = RTW_RATEID_BGN_20M_2SS;
913 else if (tx_num == 3)
914 rate_id = RTW_RATEID_ARFR5_N_3SS;
915 else if (tx_num == 4)
916 rate_id = RTW_RATEID_ARFR7_N_4SS;
917 }
918 break;
919 case WIRELESS_OFDM | WIRELESS_VHT:
920 if (tx_num == 1)
921 rate_id = RTW_RATEID_ARFR1_AC_1SS;
922 else if (tx_num == 2)
923 rate_id = RTW_RATEID_ARFR0_AC_2SS;
924 else if (tx_num == 3)
925 rate_id = RTW_RATEID_ARFR4_AC_3SS;
926 else if (tx_num == 4)
927 rate_id = RTW_RATEID_ARFR6_AC_4SS;
928 break;
929 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT:
930 if (bw_mode >= RTW_CHANNEL_WIDTH_80) {
931 if (tx_num == 1)
932 rate_id = RTW_RATEID_ARFR1_AC_1SS;
933 else if (tx_num == 2)
934 rate_id = RTW_RATEID_ARFR0_AC_2SS;
935 else if (tx_num == 3)
936 rate_id = RTW_RATEID_ARFR4_AC_3SS;
937 else if (tx_num == 4)
938 rate_id = RTW_RATEID_ARFR6_AC_4SS;
939 } else {
940 if (tx_num == 1)
941 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS;
942 else if (tx_num == 2)
943 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS;
944 else if (tx_num == 3)
945 rate_id = RTW_RATEID_ARFR4_AC_3SS;
946 else if (tx_num == 4)
947 rate_id = RTW_RATEID_ARFR6_AC_4SS;
948 }
949 break;
950 default:
951 break;
952 }
953
954 return rate_id;
955}
956
957#define RA_MASK_CCK_RATES 0x0000f
958#define RA_MASK_OFDM_RATES 0x00ff0
959#define RA_MASK_HT_RATES_1SS (0xff000ULL << 0)
960#define RA_MASK_HT_RATES_2SS (0xff000ULL << 8)
961#define RA_MASK_HT_RATES_3SS (0xff000ULL << 16)
962#define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \
963 RA_MASK_HT_RATES_2SS | \
964 RA_MASK_HT_RATES_3SS)
965#define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0)
966#define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10)
967#define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20)
968#define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \
969 RA_MASK_VHT_RATES_2SS | \
970 RA_MASK_VHT_RATES_3SS)
971#define RA_MASK_CCK_IN_HT 0x00005
972#define RA_MASK_CCK_IN_VHT 0x00005
973#define RA_MASK_OFDM_IN_VHT 0x00010
974#define RA_MASK_OFDM_IN_HT_2G 0x00010
975#define RA_MASK_OFDM_IN_HT_5G 0x00030
976
977static u64 rtw_update_rate_mask(struct rtw_dev *rtwdev,
978 struct rtw_sta_info *si,
979 u64 ra_mask, bool is_vht_enable,
980 u8 wireless_set)
981{
982 struct rtw_hal *hal = &rtwdev->hal;
983 const struct cfg80211_bitrate_mask *mask = si->mask;
984 u64 cfg_mask = GENMASK_ULL(63, 0);
985 u8 rssi_level, band;
986
987 if (wireless_set != WIRELESS_CCK) {
988 rssi_level = si->rssi_level;
989 if (rssi_level == 0)
990 ra_mask &= 0xffffffffffffffffULL;
991 else if (rssi_level == 1)
992 ra_mask &= 0xfffffffffffffff0ULL;
993 else if (rssi_level == 2)
994 ra_mask &= 0xffffffffffffefe0ULL;
995 else if (rssi_level == 3)
996 ra_mask &= 0xffffffffffffcfc0ULL;
997 else if (rssi_level == 4)
998 ra_mask &= 0xffffffffffff8f80ULL;
999 else if (rssi_level >= 5)
1000 ra_mask &= 0xffffffffffff0f00ULL;
1001 }
1002
1003 if (!si->use_cfg_mask)
1004 return ra_mask;
1005
1006 band = hal->current_band_type;
1007 if (band == RTW_BAND_2G) {
1008 band = NL80211_BAND_2GHZ;
1009 cfg_mask = mask->control[band].legacy;
1010 } else if (band == RTW_BAND_5G) {
1011 band = NL80211_BAND_5GHZ;
1012 cfg_mask = u64_encode_bits(mask->control[band].legacy,
1013 RA_MASK_OFDM_RATES);
1014 }
1015
1016 if (!is_vht_enable) {
1017 if (ra_mask & RA_MASK_HT_RATES_1SS)
1018 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
1019 RA_MASK_HT_RATES_1SS);
1020 if (ra_mask & RA_MASK_HT_RATES_2SS)
1021 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
1022 RA_MASK_HT_RATES_2SS);
1023 } else {
1024 if (ra_mask & RA_MASK_VHT_RATES_1SS)
1025 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
1026 RA_MASK_VHT_RATES_1SS);
1027 if (ra_mask & RA_MASK_VHT_RATES_2SS)
1028 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
1029 RA_MASK_VHT_RATES_2SS);
1030 }
1031
1032 ra_mask &= cfg_mask;
1033
1034 return ra_mask;
1035}
1036
1037void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si)
1038{
1039 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1040 struct ieee80211_sta *sta = si->sta;
1041 struct rtw_efuse *efuse = &rtwdev->efuse;
1042 struct rtw_hal *hal = &rtwdev->hal;
1043 u8 wireless_set;
1044 u8 bw_mode;
1045 u8 rate_id;
1046 u8 rf_type = RF_1T1R;
1047 u8 stbc_en = 0;
1048 u8 ldpc_en = 0;
1049 u8 tx_num = 1;
1050 u64 ra_mask = 0;
1051 bool is_vht_enable = false;
1052 bool is_support_sgi = false;
1053
1054 if (sta->vht_cap.vht_supported) {
1055 is_vht_enable = true;
1056 ra_mask |= get_vht_ra_mask(sta);
1057 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
1058 stbc_en = VHT_STBC_EN;
1059 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
1060 ldpc_en = VHT_LDPC_EN;
1061 } else if (sta->ht_cap.ht_supported) {
1062 ra_mask |= (sta->ht_cap.mcs.rx_mask[1] << 20) |
1063 (sta->ht_cap.mcs.rx_mask[0] << 12);
1064 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
1065 stbc_en = HT_STBC_EN;
1066 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
1067 ldpc_en = HT_LDPC_EN;
1068 }
1069
1070 if (efuse->hw_cap.nss == 1)
1071 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
1072
1073 if (hal->current_band_type == RTW_BAND_5G) {
1074 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4;
1075 if (sta->vht_cap.vht_supported) {
1076 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT;
1077 wireless_set = WIRELESS_OFDM | WIRELESS_VHT;
1078 } else if (sta->ht_cap.ht_supported) {
1079 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G;
1080 wireless_set = WIRELESS_OFDM | WIRELESS_HT;
1081 } else {
1082 wireless_set = WIRELESS_OFDM;
1083 }
1084 dm_info->rrsr_val_init = RRSR_INIT_5G;
1085 } else if (hal->current_band_type == RTW_BAND_2G) {
1086 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ];
1087 if (sta->vht_cap.vht_supported) {
1088 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT |
1089 RA_MASK_OFDM_IN_VHT;
1090 wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
1091 WIRELESS_HT | WIRELESS_VHT;
1092 } else if (sta->ht_cap.ht_supported) {
1093 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT |
1094 RA_MASK_OFDM_IN_HT_2G;
1095 wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
1096 WIRELESS_HT;
1097 } else if (sta->supp_rates[0] <= 0xf) {
1098 wireless_set = WIRELESS_CCK;
1099 } else {
1100 wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
1101 }
1102 dm_info->rrsr_val_init = RRSR_INIT_2G;
1103 } else {
1104 rtw_err(rtwdev, "Unknown band type\n");
1105 wireless_set = 0;
1106 }
1107
1108 switch (sta->bandwidth) {
1109 case IEEE80211_STA_RX_BW_80:
1110 bw_mode = RTW_CHANNEL_WIDTH_80;
1111 is_support_sgi = sta->vht_cap.vht_supported &&
1112 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
1113 break;
1114 case IEEE80211_STA_RX_BW_40:
1115 bw_mode = RTW_CHANNEL_WIDTH_40;
1116 is_support_sgi = sta->ht_cap.ht_supported &&
1117 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
1118 break;
1119 default:
1120 bw_mode = RTW_CHANNEL_WIDTH_20;
1121 is_support_sgi = sta->ht_cap.ht_supported &&
1122 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
1123 break;
1124 }
1125
1126 if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) {
1127 tx_num = 2;
1128 rf_type = RF_2T2R;
1129 } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) {
1130 tx_num = 2;
1131 rf_type = RF_2T2R;
1132 }
1133
1134 rate_id = get_rate_id(wireless_set, bw_mode, tx_num);
1135
1136 ra_mask = rtw_update_rate_mask(rtwdev, si, ra_mask, is_vht_enable,
1137 wireless_set);
1138
1139 si->bw_mode = bw_mode;
1140 si->stbc_en = stbc_en;
1141 si->ldpc_en = ldpc_en;
1142 si->rf_type = rf_type;
1143 si->wireless_set = wireless_set;
1144 si->sgi_enable = is_support_sgi;
1145 si->vht_enable = is_vht_enable;
1146 si->ra_mask = ra_mask;
1147 si->rate_id = rate_id;
1148
1149 rtw_fw_send_ra_info(rtwdev, si);
1150}
1151
1152static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev)
1153{
1154 struct rtw_chip_info *chip = rtwdev->chip;
1155 struct rtw_fw_state *fw;
1156
1157 fw = &rtwdev->fw;
1158 wait_for_completion(&fw->completion);
1159 if (!fw->firmware)
1160 return -EINVAL;
1161
1162 if (chip->wow_fw_name) {
1163 fw = &rtwdev->wow_fw;
1164 wait_for_completion(&fw->completion);
1165 if (!fw->firmware)
1166 return -EINVAL;
1167 }
1168
1169 return 0;
1170}
1171
1172static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev,
1173 struct rtw_fw_state *fw)
1174{
1175 struct rtw_chip_info *chip = rtwdev->chip;
1176
1177 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported ||
1178 !fw->feature)
1179 return LPS_DEEP_MODE_NONE;
1180
1181 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) &&
1182 rtw_fw_feature_check(fw, FW_FEATURE_PG))
1183 return LPS_DEEP_MODE_PG;
1184
1185 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) &&
1186 rtw_fw_feature_check(fw, FW_FEATURE_LCLK))
1187 return LPS_DEEP_MODE_LCLK;
1188
1189 return LPS_DEEP_MODE_NONE;
1190}
1191
1192static int rtw_power_on(struct rtw_dev *rtwdev)
1193{
1194 struct rtw_chip_info *chip = rtwdev->chip;
1195 struct rtw_fw_state *fw = &rtwdev->fw;
1196 bool wifi_only;
1197 int ret;
1198
1199 ret = rtw_hci_setup(rtwdev);
1200 if (ret) {
1201 rtw_err(rtwdev, "failed to setup hci\n");
1202 goto err;
1203 }
1204
1205
1206 ret = rtw_mac_power_on(rtwdev);
1207 if (ret) {
1208 rtw_err(rtwdev, "failed to power on mac\n");
1209 goto err;
1210 }
1211
1212 ret = rtw_wait_firmware_completion(rtwdev);
1213 if (ret) {
1214 rtw_err(rtwdev, "failed to wait firmware completion\n");
1215 goto err_off;
1216 }
1217
1218 ret = rtw_download_firmware(rtwdev, fw);
1219 if (ret) {
1220 rtw_err(rtwdev, "failed to download firmware\n");
1221 goto err_off;
1222 }
1223
1224
1225 ret = rtw_mac_init(rtwdev);
1226 if (ret) {
1227 rtw_err(rtwdev, "failed to configure mac\n");
1228 goto err_off;
1229 }
1230
1231 chip->ops->phy_set_param(rtwdev);
1232
1233 ret = rtw_hci_start(rtwdev);
1234 if (ret) {
1235 rtw_err(rtwdev, "failed to start hci\n");
1236 goto err_off;
1237 }
1238
1239
1240 rtw_fw_send_general_info(rtwdev);
1241 rtw_fw_send_phydm_info(rtwdev);
1242
1243 wifi_only = !rtwdev->efuse.btcoex;
1244 rtw_coex_power_on_setting(rtwdev);
1245 rtw_coex_init_hw_config(rtwdev, wifi_only);
1246
1247 return 0;
1248
1249err_off:
1250 rtw_mac_power_off(rtwdev);
1251
1252err:
1253 return ret;
1254}
1255
1256void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start)
1257{
1258 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN))
1259 return;
1260
1261 if (start) {
1262 rtw_fw_scan_notify(rtwdev, true);
1263 } else {
1264 reinit_completion(&rtwdev->fw_scan_density);
1265 rtw_fw_scan_notify(rtwdev, false);
1266 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density,
1267 SCAN_NOTIFY_TIMEOUT))
1268 rtw_warn(rtwdev, "firmware failed to report density after scan\n");
1269 }
1270}
1271
1272int rtw_core_start(struct rtw_dev *rtwdev)
1273{
1274 int ret;
1275
1276 ret = rtw_power_on(rtwdev);
1277 if (ret)
1278 return ret;
1279
1280 rtw_sec_enable_sec_engine(rtwdev);
1281
1282 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw);
1283 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw);
1284
1285
1286 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
1287
1288 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
1289 RTW_WATCH_DOG_DELAY_TIME);
1290
1291 set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1292
1293 return 0;
1294}
1295
1296static void rtw_power_off(struct rtw_dev *rtwdev)
1297{
1298 rtw_hci_stop(rtwdev);
1299 rtw_coex_power_off_setting(rtwdev);
1300 rtw_mac_power_off(rtwdev);
1301}
1302
1303void rtw_core_stop(struct rtw_dev *rtwdev)
1304{
1305 struct rtw_coex *coex = &rtwdev->coex;
1306
1307 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1308 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
1309
1310 mutex_unlock(&rtwdev->mutex);
1311
1312 cancel_work_sync(&rtwdev->c2h_work);
1313 cancel_delayed_work_sync(&rtwdev->watch_dog_work);
1314 cancel_delayed_work_sync(&coex->bt_relink_work);
1315 cancel_delayed_work_sync(&coex->bt_reenable_work);
1316 cancel_delayed_work_sync(&coex->defreeze_work);
1317 cancel_delayed_work_sync(&coex->wl_remain_work);
1318 cancel_delayed_work_sync(&coex->bt_remain_work);
1319 cancel_delayed_work_sync(&coex->wl_connecting_work);
1320 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work);
1321 cancel_delayed_work_sync(&coex->wl_ccklock_work);
1322
1323 mutex_lock(&rtwdev->mutex);
1324
1325 rtw_power_off(rtwdev);
1326}
1327
1328static void rtw_init_ht_cap(struct rtw_dev *rtwdev,
1329 struct ieee80211_sta_ht_cap *ht_cap)
1330{
1331 struct rtw_efuse *efuse = &rtwdev->efuse;
1332
1333 ht_cap->ht_supported = true;
1334 ht_cap->cap = 0;
1335 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
1336 IEEE80211_HT_CAP_MAX_AMSDU |
1337 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
1338
1339 if (rtw_chip_has_rx_ldpc(rtwdev))
1340 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
1341
1342 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
1343 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1344 IEEE80211_HT_CAP_DSSSCCK40 |
1345 IEEE80211_HT_CAP_SGI_40;
1346 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1347 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
1348 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1349 if (efuse->hw_cap.nss > 1) {
1350 ht_cap->mcs.rx_mask[0] = 0xFF;
1351 ht_cap->mcs.rx_mask[1] = 0xFF;
1352 ht_cap->mcs.rx_mask[4] = 0x01;
1353 ht_cap->mcs.rx_highest = cpu_to_le16(300);
1354 } else {
1355 ht_cap->mcs.rx_mask[0] = 0xFF;
1356 ht_cap->mcs.rx_mask[1] = 0x00;
1357 ht_cap->mcs.rx_mask[4] = 0x01;
1358 ht_cap->mcs.rx_highest = cpu_to_le16(150);
1359 }
1360}
1361
1362static void rtw_init_vht_cap(struct rtw_dev *rtwdev,
1363 struct ieee80211_sta_vht_cap *vht_cap)
1364{
1365 struct rtw_efuse *efuse = &rtwdev->efuse;
1366 u16 mcs_map;
1367 __le16 highest;
1368
1369 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
1370 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
1371 return;
1372
1373 vht_cap->vht_supported = true;
1374 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
1375 IEEE80211_VHT_CAP_SHORT_GI_80 |
1376 IEEE80211_VHT_CAP_RXSTBC_1 |
1377 IEEE80211_VHT_CAP_HTC_VHT |
1378 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
1379 0;
1380 if (rtwdev->hal.rf_path_num > 1)
1381 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
1382 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
1383 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
1384 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
1385 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
1386
1387 if (rtw_chip_has_rx_ldpc(rtwdev))
1388 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
1389
1390 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
1391 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
1392 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
1393 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
1394 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
1395 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
1396 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14;
1397 if (efuse->hw_cap.nss > 1) {
1398 highest = cpu_to_le16(780);
1399 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2;
1400 } else {
1401 highest = cpu_to_le16(390);
1402 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2;
1403 }
1404
1405 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
1406 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
1407 vht_cap->vht_mcs.rx_highest = highest;
1408 vht_cap->vht_mcs.tx_highest = highest;
1409}
1410
1411static void rtw_set_supported_band(struct ieee80211_hw *hw,
1412 struct rtw_chip_info *chip)
1413{
1414 struct rtw_dev *rtwdev = hw->priv;
1415 struct ieee80211_supported_band *sband;
1416
1417 if (chip->band & RTW_BAND_2G) {
1418 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL);
1419 if (!sband)
1420 goto err_out;
1421 if (chip->ht_supported)
1422 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1423 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
1424 }
1425
1426 if (chip->band & RTW_BAND_5G) {
1427 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL);
1428 if (!sband)
1429 goto err_out;
1430 if (chip->ht_supported)
1431 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1432 if (chip->vht_supported)
1433 rtw_init_vht_cap(rtwdev, &sband->vht_cap);
1434 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
1435 }
1436
1437 return;
1438
1439err_out:
1440 rtw_err(rtwdev, "failed to set supported band\n");
1441}
1442
1443static void rtw_unset_supported_band(struct ieee80211_hw *hw,
1444 struct rtw_chip_info *chip)
1445{
1446 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
1447 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
1448}
1449
1450static void __update_firmware_feature(struct rtw_dev *rtwdev,
1451 struct rtw_fw_state *fw)
1452{
1453 u32 feature;
1454 const struct rtw_fw_hdr *fw_hdr =
1455 (const struct rtw_fw_hdr *)fw->firmware->data;
1456
1457 feature = le32_to_cpu(fw_hdr->feature);
1458 fw->feature = feature & FW_FEATURE_SIG ? feature : 0;
1459}
1460
1461static void __update_firmware_info(struct rtw_dev *rtwdev,
1462 struct rtw_fw_state *fw)
1463{
1464 const struct rtw_fw_hdr *fw_hdr =
1465 (const struct rtw_fw_hdr *)fw->firmware->data;
1466
1467 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
1468 fw->version = le16_to_cpu(fw_hdr->version);
1469 fw->sub_version = fw_hdr->subversion;
1470 fw->sub_index = fw_hdr->subindex;
1471
1472 __update_firmware_feature(rtwdev, fw);
1473}
1474
1475static void __update_firmware_info_legacy(struct rtw_dev *rtwdev,
1476 struct rtw_fw_state *fw)
1477{
1478 struct rtw_fw_hdr_legacy *legacy =
1479 (struct rtw_fw_hdr_legacy *)fw->firmware->data;
1480
1481 fw->h2c_version = 0;
1482 fw->version = le16_to_cpu(legacy->version);
1483 fw->sub_version = legacy->subversion1;
1484 fw->sub_index = legacy->subversion2;
1485}
1486
1487static void update_firmware_info(struct rtw_dev *rtwdev,
1488 struct rtw_fw_state *fw)
1489{
1490 if (rtw_chip_wcpu_11n(rtwdev))
1491 __update_firmware_info_legacy(rtwdev, fw);
1492 else
1493 __update_firmware_info(rtwdev, fw);
1494}
1495
1496static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
1497{
1498 struct rtw_fw_state *fw = context;
1499 struct rtw_dev *rtwdev = fw->rtwdev;
1500
1501 if (!firmware || !firmware->data) {
1502 rtw_err(rtwdev, "failed to request firmware\n");
1503 complete_all(&fw->completion);
1504 return;
1505 }
1506
1507 fw->firmware = firmware;
1508 update_firmware_info(rtwdev, fw);
1509 complete_all(&fw->completion);
1510
1511 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n",
1512 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
1513}
1514
1515static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
1516{
1517 const char *fw_name;
1518 struct rtw_fw_state *fw;
1519 int ret;
1520
1521 switch (type) {
1522 case RTW_WOWLAN_FW:
1523 fw = &rtwdev->wow_fw;
1524 fw_name = rtwdev->chip->wow_fw_name;
1525 break;
1526
1527 case RTW_NORMAL_FW:
1528 fw = &rtwdev->fw;
1529 fw_name = rtwdev->chip->fw_name;
1530 break;
1531
1532 default:
1533 rtw_warn(rtwdev, "unsupported firmware type\n");
1534 return -ENOENT;
1535 }
1536
1537 fw->rtwdev = rtwdev;
1538 init_completion(&fw->completion);
1539
1540 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
1541 GFP_KERNEL, fw, rtw_load_firmware_cb);
1542 if (ret) {
1543 rtw_err(rtwdev, "failed to async firmware request\n");
1544 return ret;
1545 }
1546
1547 return 0;
1548}
1549
1550static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
1551{
1552 struct rtw_chip_info *chip = rtwdev->chip;
1553 struct rtw_hal *hal = &rtwdev->hal;
1554 struct rtw_efuse *efuse = &rtwdev->efuse;
1555
1556 switch (rtw_hci_type(rtwdev)) {
1557 case RTW_HCI_TYPE_PCIE:
1558 rtwdev->hci.rpwm_addr = 0x03d9;
1559 rtwdev->hci.cpwm_addr = 0x03da;
1560 break;
1561 default:
1562 rtw_err(rtwdev, "unsupported hci type\n");
1563 return -EINVAL;
1564 }
1565
1566 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
1567 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
1568 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
1569 if (hal->chip_version & BIT_RF_TYPE_ID) {
1570 hal->rf_type = RF_2T2R;
1571 hal->rf_path_num = 2;
1572 hal->antenna_tx = BB_PATH_AB;
1573 hal->antenna_rx = BB_PATH_AB;
1574 } else {
1575 hal->rf_type = RF_1T1R;
1576 hal->rf_path_num = 1;
1577 hal->antenna_tx = BB_PATH_A;
1578 hal->antenna_rx = BB_PATH_A;
1579 }
1580 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
1581 hal->rf_path_num;
1582
1583 efuse->physical_size = chip->phy_efuse_size;
1584 efuse->logical_size = chip->log_efuse_size;
1585 efuse->protect_size = chip->ptct_efuse_size;
1586
1587
1588 rtwdev->hal.rcr |= BIT_VHT_DACK;
1589
1590 hal->bfee_sts_cap = 3;
1591
1592 return 0;
1593}
1594
1595static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev)
1596{
1597 struct rtw_fw_state *fw = &rtwdev->fw;
1598 int ret;
1599
1600 ret = rtw_hci_setup(rtwdev);
1601 if (ret) {
1602 rtw_err(rtwdev, "failed to setup hci\n");
1603 goto err;
1604 }
1605
1606 ret = rtw_mac_power_on(rtwdev);
1607 if (ret) {
1608 rtw_err(rtwdev, "failed to power on mac\n");
1609 goto err;
1610 }
1611
1612 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP);
1613
1614 wait_for_completion(&fw->completion);
1615 if (!fw->firmware) {
1616 ret = -EINVAL;
1617 rtw_err(rtwdev, "failed to load firmware\n");
1618 goto err;
1619 }
1620
1621 ret = rtw_download_firmware(rtwdev, fw);
1622 if (ret) {
1623 rtw_err(rtwdev, "failed to download firmware\n");
1624 goto err_off;
1625 }
1626
1627 return 0;
1628
1629err_off:
1630 rtw_mac_power_off(rtwdev);
1631
1632err:
1633 return ret;
1634}
1635
1636static int rtw_dump_hw_feature(struct rtw_dev *rtwdev)
1637{
1638 struct rtw_efuse *efuse = &rtwdev->efuse;
1639 u8 hw_feature[HW_FEATURE_LEN];
1640 u8 id;
1641 u8 bw;
1642 int i;
1643
1644 id = rtw_read8(rtwdev, REG_C2HEVT);
1645 if (id != C2H_HW_FEATURE_REPORT) {
1646 rtw_err(rtwdev, "failed to read hw feature report\n");
1647 return -EBUSY;
1648 }
1649
1650 for (i = 0; i < HW_FEATURE_LEN; i++)
1651 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
1652
1653 rtw_write8(rtwdev, REG_C2HEVT, 0);
1654
1655 bw = GET_EFUSE_HW_CAP_BW(hw_feature);
1656 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
1657 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
1658 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
1659 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
1660 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
1661
1662 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
1663
1664 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
1665 efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
1666 efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
1667
1668 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
1669 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
1670 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
1671 efuse->hw_cap.ant_num, efuse->hw_cap.nss);
1672
1673 return 0;
1674}
1675
1676static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev)
1677{
1678 rtw_hci_stop(rtwdev);
1679 rtw_mac_power_off(rtwdev);
1680}
1681
1682static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
1683{
1684 struct rtw_efuse *efuse = &rtwdev->efuse;
1685 int ret;
1686
1687 mutex_lock(&rtwdev->mutex);
1688
1689
1690 ret = rtw_chip_efuse_enable(rtwdev);
1691 if (ret)
1692 goto out_unlock;
1693
1694 ret = rtw_parse_efuse_map(rtwdev);
1695 if (ret)
1696 goto out_disable;
1697
1698 ret = rtw_dump_hw_feature(rtwdev);
1699 if (ret)
1700 goto out_disable;
1701
1702 ret = rtw_check_supported_rfe(rtwdev);
1703 if (ret)
1704 goto out_disable;
1705
1706 if (efuse->crystal_cap == 0xff)
1707 efuse->crystal_cap = 0;
1708 if (efuse->pa_type_2g == 0xff)
1709 efuse->pa_type_2g = 0;
1710 if (efuse->pa_type_5g == 0xff)
1711 efuse->pa_type_5g = 0;
1712 if (efuse->lna_type_2g == 0xff)
1713 efuse->lna_type_2g = 0;
1714 if (efuse->lna_type_5g == 0xff)
1715 efuse->lna_type_5g = 0;
1716 if (efuse->channel_plan == 0xff)
1717 efuse->channel_plan = 0x7f;
1718 if (efuse->rf_board_option == 0xff)
1719 efuse->rf_board_option = 0;
1720 if (efuse->bt_setting & BIT(0))
1721 efuse->share_ant = true;
1722 if (efuse->regd == 0xff)
1723 efuse->regd = 0;
1724 if (efuse->tx_bb_swing_setting_2g == 0xff)
1725 efuse->tx_bb_swing_setting_2g = 0;
1726 if (efuse->tx_bb_swing_setting_5g == 0xff)
1727 efuse->tx_bb_swing_setting_5g = 0;
1728
1729 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
1730 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
1731 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
1732 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
1733 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
1734
1735out_disable:
1736 rtw_chip_efuse_disable(rtwdev);
1737
1738out_unlock:
1739 mutex_unlock(&rtwdev->mutex);
1740 return ret;
1741}
1742
1743static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev)
1744{
1745 struct rtw_hal *hal = &rtwdev->hal;
1746 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
1747
1748 if (!rfe_def)
1749 return -ENODEV;
1750
1751 rtw_phy_setup_phy_cond(rtwdev, 0);
1752
1753 rtw_phy_init_tx_power(rtwdev);
1754 if (rfe_def->agc_btg_tbl)
1755 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl);
1756 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
1757 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
1758 rtw_phy_tx_power_by_rate_config(hal);
1759 rtw_phy_tx_power_limit_config(hal);
1760
1761 return 0;
1762}
1763
1764int rtw_chip_info_setup(struct rtw_dev *rtwdev)
1765{
1766 int ret;
1767
1768 ret = rtw_chip_parameter_setup(rtwdev);
1769 if (ret) {
1770 rtw_err(rtwdev, "failed to setup chip parameters\n");
1771 goto err_out;
1772 }
1773
1774 ret = rtw_chip_efuse_info_setup(rtwdev);
1775 if (ret) {
1776 rtw_err(rtwdev, "failed to setup chip efuse info\n");
1777 goto err_out;
1778 }
1779
1780 ret = rtw_chip_board_info_setup(rtwdev);
1781 if (ret) {
1782 rtw_err(rtwdev, "failed to setup chip board info\n");
1783 goto err_out;
1784 }
1785
1786 return 0;
1787
1788err_out:
1789 return ret;
1790}
1791EXPORT_SYMBOL(rtw_chip_info_setup);
1792
1793static void rtw_stats_init(struct rtw_dev *rtwdev)
1794{
1795 struct rtw_traffic_stats *stats = &rtwdev->stats;
1796 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1797 int i;
1798
1799 ewma_tp_init(&stats->tx_ewma_tp);
1800 ewma_tp_init(&stats->rx_ewma_tp);
1801
1802 for (i = 0; i < RTW_EVM_NUM; i++)
1803 ewma_evm_init(&dm_info->ewma_evm[i]);
1804 for (i = 0; i < RTW_SNR_NUM; i++)
1805 ewma_snr_init(&dm_info->ewma_snr[i]);
1806}
1807
1808int rtw_core_init(struct rtw_dev *rtwdev)
1809{
1810 struct rtw_chip_info *chip = rtwdev->chip;
1811 struct rtw_coex *coex = &rtwdev->coex;
1812 int ret;
1813
1814 INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
1815 INIT_LIST_HEAD(&rtwdev->txqs);
1816
1817 timer_setup(&rtwdev->tx_report.purge_timer,
1818 rtw_tx_report_purge_timer, 0);
1819 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
1820
1821 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
1822 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
1823 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
1824 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
1825 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
1826 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
1827 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work);
1828 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work,
1829 rtw_coex_bt_multi_link_remain_work);
1830 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work);
1831 INIT_WORK(&rtwdev->tx_work, rtw_tx_work);
1832 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
1833 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
1834 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
1835 skb_queue_head_init(&rtwdev->c2h_queue);
1836 skb_queue_head_init(&rtwdev->coex.queue);
1837 skb_queue_head_init(&rtwdev->tx_report.queue);
1838
1839 spin_lock_init(&rtwdev->rf_lock);
1840 spin_lock_init(&rtwdev->h2c.lock);
1841 spin_lock_init(&rtwdev->txq_lock);
1842 spin_lock_init(&rtwdev->tx_report.q_lock);
1843
1844 mutex_init(&rtwdev->mutex);
1845 mutex_init(&rtwdev->coex.mutex);
1846 mutex_init(&rtwdev->hal.tx_power_mutex);
1847
1848 init_waitqueue_head(&rtwdev->coex.wait);
1849 init_completion(&rtwdev->lps_leave_check);
1850 init_completion(&rtwdev->fw_scan_density);
1851
1852 rtwdev->sec.total_cam_num = 32;
1853 rtwdev->hal.current_channel = 1;
1854 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map);
1855
1856 rtw_stats_init(rtwdev);
1857
1858
1859 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
1860 BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS |
1861 BIT_AB | BIT_AM | BIT_APM;
1862
1863 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
1864 if (ret) {
1865 rtw_warn(rtwdev, "no firmware loaded\n");
1866 return ret;
1867 }
1868
1869 if (chip->wow_fw_name) {
1870 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW);
1871 if (ret) {
1872 rtw_warn(rtwdev, "no wow firmware loaded\n");
1873 wait_for_completion(&rtwdev->fw.completion);
1874 if (rtwdev->fw.firmware)
1875 release_firmware(rtwdev->fw.firmware);
1876 return ret;
1877 }
1878 }
1879
1880 return 0;
1881}
1882EXPORT_SYMBOL(rtw_core_init);
1883
1884void rtw_core_deinit(struct rtw_dev *rtwdev)
1885{
1886 struct rtw_fw_state *fw = &rtwdev->fw;
1887 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
1888 struct rtw_rsvd_page *rsvd_pkt, *tmp;
1889 unsigned long flags;
1890
1891 rtw_wait_firmware_completion(rtwdev);
1892
1893 if (fw->firmware)
1894 release_firmware(fw->firmware);
1895
1896 if (wow_fw->firmware)
1897 release_firmware(wow_fw->firmware);
1898
1899 destroy_workqueue(rtwdev->tx_wq);
1900 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
1901 skb_queue_purge(&rtwdev->tx_report.queue);
1902 skb_queue_purge(&rtwdev->coex.queue);
1903 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
1904
1905 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
1906 build_list) {
1907 list_del(&rsvd_pkt->build_list);
1908 kfree(rsvd_pkt);
1909 }
1910
1911 mutex_destroy(&rtwdev->mutex);
1912 mutex_destroy(&rtwdev->coex.mutex);
1913 mutex_destroy(&rtwdev->hal.tx_power_mutex);
1914}
1915EXPORT_SYMBOL(rtw_core_deinit);
1916
1917int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
1918{
1919 struct rtw_hal *hal = &rtwdev->hal;
1920 int max_tx_headroom = 0;
1921 int ret;
1922
1923
1924 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
1925
1926 hw->extra_tx_headroom = max_tx_headroom;
1927 hw->queues = IEEE80211_NUM_ACS;
1928 hw->txq_data_size = sizeof(struct rtw_txq);
1929 hw->sta_data_size = sizeof(struct rtw_sta_info);
1930 hw->vif_data_size = sizeof(struct rtw_vif);
1931
1932 ieee80211_hw_set(hw, SIGNAL_DBM);
1933 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
1934 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
1935 ieee80211_hw_set(hw, MFP_CAPABLE);
1936 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
1937 ieee80211_hw_set(hw, SUPPORTS_PS);
1938 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
1939 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
1940 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
1941 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
1942 ieee80211_hw_set(hw, TX_AMSDU);
1943
1944 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1945 BIT(NL80211_IFTYPE_AP) |
1946 BIT(NL80211_IFTYPE_ADHOC) |
1947 BIT(NL80211_IFTYPE_MESH_POINT);
1948 hw->wiphy->available_antennas_tx = hal->antenna_tx;
1949 hw->wiphy->available_antennas_rx = hal->antenna_rx;
1950
1951 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
1952 WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
1953
1954 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
1955
1956 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
1957
1958#ifdef CONFIG_PM
1959 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
1960 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
1961#endif
1962 rtw_set_supported_band(hw, rtwdev->chip);
1963 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
1964
1965 rtw_regd_init(rtwdev, rtw_regd_notifier);
1966
1967 ret = ieee80211_register_hw(hw);
1968 if (ret) {
1969 rtw_err(rtwdev, "failed to register hw\n");
1970 return ret;
1971 }
1972
1973 if (regulatory_hint(hw->wiphy, rtwdev->regd.alpha2))
1974 rtw_err(rtwdev, "regulatory_hint fail\n");
1975
1976 rtw_debugfs_init(rtwdev);
1977
1978 rtwdev->bf_info.bfer_mu_cnt = 0;
1979 rtwdev->bf_info.bfer_su_cnt = 0;
1980
1981 return 0;
1982}
1983EXPORT_SYMBOL(rtw_register_hw);
1984
1985void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
1986{
1987 struct rtw_chip_info *chip = rtwdev->chip;
1988
1989 ieee80211_unregister_hw(hw);
1990 rtw_unset_supported_band(hw, chip);
1991}
1992EXPORT_SYMBOL(rtw_unregister_hw);
1993
1994MODULE_AUTHOR("Realtek Corporation");
1995MODULE_DESCRIPTION("Realtek 802.11ac wireless core module");
1996MODULE_LICENSE("Dual BSD/GPL");
1997
