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8
9
10#ifndef __CONF_H__
11#define __CONF_H__
12
13enum {
14 CONF_HW_BIT_RATE_1MBPS = BIT(0),
15 CONF_HW_BIT_RATE_2MBPS = BIT(1),
16 CONF_HW_BIT_RATE_5_5MBPS = BIT(2),
17 CONF_HW_BIT_RATE_6MBPS = BIT(3),
18 CONF_HW_BIT_RATE_9MBPS = BIT(4),
19 CONF_HW_BIT_RATE_11MBPS = BIT(5),
20 CONF_HW_BIT_RATE_12MBPS = BIT(6),
21 CONF_HW_BIT_RATE_18MBPS = BIT(7),
22 CONF_HW_BIT_RATE_22MBPS = BIT(8),
23 CONF_HW_BIT_RATE_24MBPS = BIT(9),
24 CONF_HW_BIT_RATE_36MBPS = BIT(10),
25 CONF_HW_BIT_RATE_48MBPS = BIT(11),
26 CONF_HW_BIT_RATE_54MBPS = BIT(12),
27 CONF_HW_BIT_RATE_MCS_0 = BIT(13),
28 CONF_HW_BIT_RATE_MCS_1 = BIT(14),
29 CONF_HW_BIT_RATE_MCS_2 = BIT(15),
30 CONF_HW_BIT_RATE_MCS_3 = BIT(16),
31 CONF_HW_BIT_RATE_MCS_4 = BIT(17),
32 CONF_HW_BIT_RATE_MCS_5 = BIT(18),
33 CONF_HW_BIT_RATE_MCS_6 = BIT(19),
34 CONF_HW_BIT_RATE_MCS_7 = BIT(20),
35 CONF_HW_BIT_RATE_MCS_8 = BIT(21),
36 CONF_HW_BIT_RATE_MCS_9 = BIT(22),
37 CONF_HW_BIT_RATE_MCS_10 = BIT(23),
38 CONF_HW_BIT_RATE_MCS_11 = BIT(24),
39 CONF_HW_BIT_RATE_MCS_12 = BIT(25),
40 CONF_HW_BIT_RATE_MCS_13 = BIT(26),
41 CONF_HW_BIT_RATE_MCS_14 = BIT(27),
42 CONF_HW_BIT_RATE_MCS_15 = BIT(28),
43};
44
45enum {
46 CONF_HW_RATE_INDEX_1MBPS = 0,
47 CONF_HW_RATE_INDEX_2MBPS = 1,
48 CONF_HW_RATE_INDEX_5_5MBPS = 2,
49 CONF_HW_RATE_INDEX_11MBPS = 3,
50 CONF_HW_RATE_INDEX_6MBPS = 4,
51 CONF_HW_RATE_INDEX_9MBPS = 5,
52 CONF_HW_RATE_INDEX_12MBPS = 6,
53 CONF_HW_RATE_INDEX_18MBPS = 7,
54 CONF_HW_RATE_INDEX_24MBPS = 8,
55 CONF_HW_RATE_INDEX_36MBPS = 9,
56 CONF_HW_RATE_INDEX_48MBPS = 10,
57 CONF_HW_RATE_INDEX_54MBPS = 11,
58 CONF_HW_RATE_INDEX_MCS0 = 12,
59 CONF_HW_RATE_INDEX_MCS1 = 13,
60 CONF_HW_RATE_INDEX_MCS2 = 14,
61 CONF_HW_RATE_INDEX_MCS3 = 15,
62 CONF_HW_RATE_INDEX_MCS4 = 16,
63 CONF_HW_RATE_INDEX_MCS5 = 17,
64 CONF_HW_RATE_INDEX_MCS6 = 18,
65 CONF_HW_RATE_INDEX_MCS7 = 19,
66 CONF_HW_RATE_INDEX_MCS7_SGI = 20,
67 CONF_HW_RATE_INDEX_MCS0_40MHZ = 21,
68 CONF_HW_RATE_INDEX_MCS1_40MHZ = 22,
69 CONF_HW_RATE_INDEX_MCS2_40MHZ = 23,
70 CONF_HW_RATE_INDEX_MCS3_40MHZ = 24,
71 CONF_HW_RATE_INDEX_MCS4_40MHZ = 25,
72 CONF_HW_RATE_INDEX_MCS5_40MHZ = 26,
73 CONF_HW_RATE_INDEX_MCS6_40MHZ = 27,
74 CONF_HW_RATE_INDEX_MCS7_40MHZ = 28,
75 CONF_HW_RATE_INDEX_MCS7_40MHZ_SGI = 29,
76
77
78 CONF_HW_RATE_INDEX_MCS8 = 21,
79 CONF_HW_RATE_INDEX_MCS9 = 22,
80 CONF_HW_RATE_INDEX_MCS10 = 23,
81 CONF_HW_RATE_INDEX_MCS11 = 24,
82 CONF_HW_RATE_INDEX_MCS12 = 25,
83 CONF_HW_RATE_INDEX_MCS13 = 26,
84 CONF_HW_RATE_INDEX_MCS14 = 27,
85 CONF_HW_RATE_INDEX_MCS15 = 28,
86 CONF_HW_RATE_INDEX_MCS15_SGI = 29,
87
88 CONF_HW_RATE_INDEX_MAX = CONF_HW_RATE_INDEX_MCS7_40MHZ_SGI,
89};
90
91#define CONF_HW_RXTX_RATE_UNSUPPORTED 0xff
92
93enum {
94 CONF_SG_DISABLE = 0,
95 CONF_SG_PROTECTIVE,
96 CONF_SG_OPPORTUNISTIC
97};
98
99#define WLCORE_CONF_SG_PARAMS_MAX 67
100#define WLCORE_CONF_SG_PARAMS_ALL 0xff
101
102struct conf_sg_settings {
103 u32 params[WLCORE_CONF_SG_PARAMS_MAX];
104 u8 state;
105} __packed;
106
107enum conf_rx_queue_type {
108 CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
109 CONF_RX_QUEUE_TYPE_HIGH_PRIORITY,
110};
111
112struct conf_rx_settings {
113
114
115
116
117
118
119 u32 rx_msdu_life_time;
120
121
122
123
124
125
126 u32 packet_detection_threshold;
127
128
129
130
131
132
133
134 u16 ps_poll_timeout;
135
136
137
138
139
140
141 u16 upsd_timeout;
142
143
144
145
146
147
148
149 u16 rts_threshold;
150
151
152
153
154
155
156
157
158 u16 rx_cca_threshold;
159
160
161
162
163
164
165
166 u16 irq_blk_threshold;
167
168
169
170
171
172
173
174 u16 irq_pkt_threshold;
175
176
177
178
179
180
181 u16 irq_timeout;
182
183
184
185
186
187
188 u8 queue_type;
189} __packed;
190
191#define CONF_TX_MAX_RATE_CLASSES 10
192
193#define CONF_TX_RATE_MASK_UNSPECIFIED 0
194#define CONF_TX_RATE_MASK_BASIC (CONF_HW_BIT_RATE_1MBPS | \
195 CONF_HW_BIT_RATE_2MBPS)
196#define CONF_TX_RATE_RETRY_LIMIT 10
197
198
199#define CONF_TX_RATE_MASK_BASIC_P2P CONF_HW_BIT_RATE_6MBPS
200
201
202
203
204
205
206#define CONF_TX_ENABLED_RATES (CONF_HW_BIT_RATE_1MBPS | \
207 CONF_HW_BIT_RATE_2MBPS | CONF_HW_BIT_RATE_5_5MBPS | \
208 CONF_HW_BIT_RATE_6MBPS | CONF_HW_BIT_RATE_9MBPS | \
209 CONF_HW_BIT_RATE_11MBPS | CONF_HW_BIT_RATE_12MBPS | \
210 CONF_HW_BIT_RATE_18MBPS | CONF_HW_BIT_RATE_24MBPS | \
211 CONF_HW_BIT_RATE_36MBPS | CONF_HW_BIT_RATE_48MBPS | \
212 CONF_HW_BIT_RATE_54MBPS)
213
214#define CONF_TX_CCK_RATES (CONF_HW_BIT_RATE_1MBPS | \
215 CONF_HW_BIT_RATE_2MBPS | CONF_HW_BIT_RATE_5_5MBPS | \
216 CONF_HW_BIT_RATE_11MBPS)
217
218#define CONF_TX_OFDM_RATES (CONF_HW_BIT_RATE_6MBPS | \
219 CONF_HW_BIT_RATE_12MBPS | CONF_HW_BIT_RATE_24MBPS | \
220 CONF_HW_BIT_RATE_36MBPS | CONF_HW_BIT_RATE_48MBPS | \
221 CONF_HW_BIT_RATE_54MBPS)
222
223#define CONF_TX_MCS_RATES (CONF_HW_BIT_RATE_MCS_0 | \
224 CONF_HW_BIT_RATE_MCS_1 | CONF_HW_BIT_RATE_MCS_2 | \
225 CONF_HW_BIT_RATE_MCS_3 | CONF_HW_BIT_RATE_MCS_4 | \
226 CONF_HW_BIT_RATE_MCS_5 | CONF_HW_BIT_RATE_MCS_6 | \
227 CONF_HW_BIT_RATE_MCS_7)
228
229#define CONF_TX_MIMO_RATES (CONF_HW_BIT_RATE_MCS_8 | \
230 CONF_HW_BIT_RATE_MCS_9 | CONF_HW_BIT_RATE_MCS_10 | \
231 CONF_HW_BIT_RATE_MCS_11 | CONF_HW_BIT_RATE_MCS_12 | \
232 CONF_HW_BIT_RATE_MCS_13 | CONF_HW_BIT_RATE_MCS_14 | \
233 CONF_HW_BIT_RATE_MCS_15)
234
235
236
237
238
239#define CONF_TX_AP_DEFAULT_MGMT_RATES (CONF_HW_BIT_RATE_1MBPS | \
240 CONF_HW_BIT_RATE_2MBPS | CONF_HW_BIT_RATE_5_5MBPS)
241
242
243#define CONF_TX_IBSS_DEFAULT_RATES (CONF_HW_BIT_RATE_1MBPS | \
244 CONF_HW_BIT_RATE_2MBPS | CONF_HW_BIT_RATE_5_5MBPS | \
245 CONF_HW_BIT_RATE_11MBPS | CONF_TX_OFDM_RATES);
246
247struct conf_tx_rate_class {
248
249
250
251
252
253
254 u32 enabled_rates;
255
256
257
258
259
260
261 u8 short_retry_limit;
262
263
264
265
266
267
268 u8 long_retry_limit;
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286 u8 aflags;
287} __packed;
288
289#define CONF_TX_MAX_AC_COUNT 4
290
291
292#define CONF_TX_AIFS_PIFS 1
293
294
295#define CONF_TX_AIFS_DIFS 2
296
297
298enum conf_tx_ac {
299 CONF_TX_AC_BE = 0,
300 CONF_TX_AC_BK = 1,
301 CONF_TX_AC_VI = 2,
302 CONF_TX_AC_VO = 3,
303 CONF_TX_AC_CTS2SELF = 4,
304 CONF_TX_AC_ANY_TID = 0xff
305};
306
307struct conf_tx_ac_category {
308
309
310
311
312
313 u8 ac;
314
315
316
317
318
319
320
321 u8 cw_min;
322
323
324
325
326
327
328
329 u16 cw_max;
330
331
332
333
334
335
336 u8 aifsn;
337
338
339
340
341
342
343 u16 tx_op_limit;
344} __packed;
345
346#define CONF_TX_MAX_TID_COUNT 8
347
348
349#define CONF_TX_BA_ENABLED_TID_BITMAP 0x3F
350
351enum {
352 CONF_CHANNEL_TYPE_DCF = 0,
353 CONF_CHANNEL_TYPE_EDCF = 1,
354 CONF_CHANNEL_TYPE_HCCA = 2,
355};
356
357enum {
358 CONF_PS_SCHEME_LEGACY = 0,
359 CONF_PS_SCHEME_UPSD_TRIGGER = 1,
360 CONF_PS_SCHEME_LEGACY_PSPOLL = 2,
361 CONF_PS_SCHEME_SAPSD = 3,
362};
363
364enum {
365 CONF_ACK_POLICY_LEGACY = 0,
366 CONF_ACK_POLICY_NO_ACK = 1,
367 CONF_ACK_POLICY_BLOCK = 2,
368};
369
370
371struct conf_tx_tid {
372 u8 queue_id;
373 u8 channel_type;
374 u8 tsid;
375 u8 ps_scheme;
376 u8 ack_policy;
377 u32 apsd_conf[2];
378} __packed;
379
380struct conf_tx_settings {
381
382
383
384
385
386 u8 tx_energy_detection;
387
388
389
390
391
392 struct conf_tx_rate_class sta_rc_conf;
393
394
395
396
397 u8 ac_conf_count;
398 struct conf_tx_ac_category ac_conf[CONF_TX_MAX_AC_COUNT];
399
400
401
402
403
404
405
406 u8 max_tx_retries;
407
408
409
410
411
412 u16 ap_aging_period;
413
414
415
416
417 u8 tid_conf_count;
418 struct conf_tx_tid tid_conf[CONF_TX_MAX_TID_COUNT];
419
420
421
422
423
424
425 u16 frag_threshold;
426
427
428
429
430
431
432 u16 tx_compl_timeout;
433
434
435
436
437
438
439
440 u16 tx_compl_threshold;
441
442
443
444
445
446
447 u32 basic_rate;
448
449
450
451
452
453
454 u32 basic_rate_5;
455
456
457
458
459 u8 tmpl_short_retry_limit;
460 u8 tmpl_long_retry_limit;
461
462
463 u32 tx_watchdog_timeout;
464
465
466
467
468
469 u8 slow_link_thold;
470
471
472
473
474
475 u8 fast_link_thold;
476} __packed;
477
478enum {
479 CONF_WAKE_UP_EVENT_BEACON = 0x01,
480 CONF_WAKE_UP_EVENT_DTIM = 0x02,
481 CONF_WAKE_UP_EVENT_N_DTIM = 0x04,
482 CONF_WAKE_UP_EVENT_N_BEACONS = 0x08,
483 CONF_WAKE_UP_EVENT_BITS_MASK = 0x0F
484};
485
486#define CONF_MAX_BCN_FILT_IE_COUNT 32
487
488#define CONF_BCN_RULE_PASS_ON_CHANGE BIT(0)
489#define CONF_BCN_RULE_PASS_ON_APPEARANCE BIT(1)
490
491#define CONF_BCN_IE_OUI_LEN 3
492#define CONF_BCN_IE_VER_LEN 2
493
494struct conf_bcn_filt_rule {
495
496
497
498
499
500 u8 ie;
501
502
503
504
505
506
507 u8 rule;
508
509
510
511
512 u8 oui[CONF_BCN_IE_OUI_LEN];
513
514
515
516
517 u8 type;
518
519
520
521
522 u8 version[CONF_BCN_IE_VER_LEN];
523} __packed;
524
525#define CONF_MAX_RSSI_SNR_TRIGGERS 8
526
527enum {
528 CONF_TRIG_METRIC_RSSI_BEACON = 0,
529 CONF_TRIG_METRIC_RSSI_DATA,
530 CONF_TRIG_METRIC_SNR_BEACON,
531 CONF_TRIG_METRIC_SNR_DATA
532};
533
534enum {
535 CONF_TRIG_EVENT_TYPE_LEVEL = 0,
536 CONF_TRIG_EVENT_TYPE_EDGE
537};
538
539enum {
540 CONF_TRIG_EVENT_DIR_LOW = 0,
541 CONF_TRIG_EVENT_DIR_HIGH,
542 CONF_TRIG_EVENT_DIR_BIDIR
543};
544
545struct conf_sig_weights {
546
547
548
549
550
551
552 u8 rssi_bcn_avg_weight;
553
554
555
556
557
558
559 u8 rssi_pkt_avg_weight;
560
561
562
563
564
565
566 u8 snr_bcn_avg_weight;
567
568
569
570
571
572
573 u8 snr_pkt_avg_weight;
574} __packed;
575
576enum conf_bcn_filt_mode {
577 CONF_BCN_FILT_MODE_DISABLED = 0,
578 CONF_BCN_FILT_MODE_ENABLED = 1
579};
580
581enum conf_bet_mode {
582 CONF_BET_MODE_DISABLE = 0,
583 CONF_BET_MODE_ENABLE = 1,
584};
585
586struct conf_conn_settings {
587
588
589
590
591
592
593 u8 wake_up_event;
594
595
596
597
598
599
600
601
602 u8 listen_interval;
603
604
605
606
607
608 u8 suspend_wake_up_event;
609
610
611
612
613
614
615 u8 suspend_listen_interval;
616
617
618
619
620
621
622 u8 bcn_filt_mode;
623
624
625
626
627 u8 bcn_filt_ie_count;
628 struct conf_bcn_filt_rule bcn_filt_ie[CONF_MAX_BCN_FILT_IE_COUNT];
629
630
631
632
633
634
635
636 u32 synch_fail_thold;
637
638
639
640
641
642
643
644
645 u32 bss_lose_timeout;
646
647
648
649
650
651
652 u32 beacon_rx_timeout;
653
654
655
656
657
658
659 u32 broadcast_timeout;
660
661
662
663
664
665
666 u8 rx_broadcast_in_ps;
667
668
669
670
671
672
673 u8 ps_poll_threshold;
674
675
676
677
678 struct conf_sig_weights sig_weights;
679
680
681
682
683
684
685
686 u8 bet_enable;
687
688
689
690
691
692
693
694
695
696 u8 bet_max_consecutive;
697
698
699
700
701
702
703
704 u8 psm_entry_retries;
705
706
707
708
709
710
711
712 u8 psm_exit_retries;
713
714
715
716
717
718
719
720 u8 psm_entry_nullfunc_retries;
721
722
723
724
725
726 u16 dynamic_ps_timeout;
727
728
729
730
731
732 u8 forced_ps;
733
734
735
736
737
738
739
740
741 u32 keep_alive_interval;
742
743
744
745
746
747
748 u8 max_listen_interval;
749
750
751
752
753
754 u8 sta_sleep_auth;
755
756
757
758
759 u8 suspend_rx_ba_activity;
760} __packed;
761
762enum {
763 CONF_REF_CLK_19_2_E,
764 CONF_REF_CLK_26_E,
765 CONF_REF_CLK_38_4_E,
766 CONF_REF_CLK_52_E,
767 CONF_REF_CLK_38_4_M_XTAL,
768 CONF_REF_CLK_26_M_XTAL,
769};
770
771enum single_dual_band_enum {
772 CONF_SINGLE_BAND,
773 CONF_DUAL_BAND
774};
775
776#define CONF_RSSI_AND_PROCESS_COMPENSATION_SIZE 15
777#define CONF_NUMBER_OF_SUB_BANDS_5 7
778#define CONF_NUMBER_OF_RATE_GROUPS 6
779#define CONF_NUMBER_OF_CHANNELS_2_4 14
780#define CONF_NUMBER_OF_CHANNELS_5 35
781
782struct conf_itrim_settings {
783
784 u8 enable;
785
786
787 u32 timeout;
788} __packed;
789
790enum conf_fast_wakeup {
791 CONF_FAST_WAKEUP_ENABLE,
792 CONF_FAST_WAKEUP_DISABLE,
793};
794
795struct conf_pm_config_settings {
796
797
798
799
800
801 u32 host_clk_settling_time;
802
803
804
805
806
807
808 u8 host_fast_wakeup_support;
809} __packed;
810
811struct conf_roam_trigger_settings {
812
813
814
815
816
817 u16 trigger_pacing;
818
819
820
821
822
823
824 u8 avg_weight_rssi_beacon;
825
826
827
828
829
830
831 u8 avg_weight_rssi_data;
832
833
834
835
836
837
838 u8 avg_weight_snr_beacon;
839
840
841
842
843
844
845 u8 avg_weight_snr_data;
846} __packed;
847
848struct conf_scan_settings {
849
850
851
852
853
854
855 u32 min_dwell_time_active;
856
857
858
859
860
861
862
863
864
865 u32 max_dwell_time_active;
866
867
868
869
870
871
872
873
874
875 u32 min_dwell_time_active_long;
876
877
878
879
880
881
882
883 u32 max_dwell_time_active_long;
884
885
886 u32 dwell_time_passive;
887
888
889 u32 dwell_time_dfs;
890
891
892
893
894
895
896 u16 num_probe_reqs;
897
898
899
900
901
902
903
904
905 u32 split_scan_timeout;
906} __packed;
907
908struct conf_sched_scan_settings {
909
910
911
912
913
914
915
916 u32 base_dwell_time;
917
918
919
920
921
922 u32 max_dwell_time_delta;
923
924
925 u32 dwell_time_delta_per_probe;
926
927
928 u32 dwell_time_delta_per_probe_5;
929
930
931 u32 dwell_time_passive;
932
933
934 u32 dwell_time_dfs;
935
936
937 u8 num_probe_reqs;
938
939
940 s8 rssi_threshold;
941
942
943 s8 snr_threshold;
944
945
946
947
948
949 u8 num_short_intervals;
950
951
952 u16 long_interval;
953} __packed;
954
955struct conf_ht_setting {
956 u8 rx_ba_win_size;
957 u8 tx_ba_win_size;
958 u16 inactivity_timeout;
959
960
961 u8 tx_ba_tid_bitmap;
962} __packed;
963
964struct conf_memory_settings {
965
966 u8 num_stations;
967
968
969 u8 ssid_profiles;
970
971
972 u8 rx_block_num;
973
974
975 u8 tx_min_block_num;
976
977
978 u8 dynamic_memory;
979
980
981
982
983
984
985
986 u8 min_req_tx_blocks;
987
988
989
990
991
992
993
994 u8 min_req_rx_blocks;
995
996
997
998
999
1000
1001 u8 tx_min;
1002} __packed;
1003
1004struct conf_fm_coex {
1005 u8 enable;
1006 u8 swallow_period;
1007 u8 n_divider_fref_set_1;
1008 u8 n_divider_fref_set_2;
1009 u16 m_divider_fref_set_1;
1010 u16 m_divider_fref_set_2;
1011 u32 coex_pll_stabilization_time;
1012 u16 ldo_stabilization_time;
1013 u8 fm_disturbed_band_margin;
1014 u8 swallow_clk_diff;
1015} __packed;
1016
1017struct conf_rx_streaming_settings {
1018
1019
1020
1021
1022
1023 u32 duration;
1024
1025
1026
1027
1028
1029
1030
1031 u8 queues;
1032
1033
1034
1035
1036
1037
1038 u8 interval;
1039
1040
1041
1042
1043 u8 always;
1044} __packed;
1045
1046#define CONF_FWLOG_MIN_MEM_BLOCKS 2
1047#define CONF_FWLOG_MAX_MEM_BLOCKS 16
1048
1049struct conf_fwlog {
1050
1051 u8 mode;
1052
1053
1054
1055
1056
1057
1058 u8 mem_blocks;
1059
1060
1061 u8 severity;
1062
1063
1064 u8 timestamp;
1065
1066
1067 u8 output;
1068
1069
1070 u8 threshold;
1071} __packed;
1072
1073#define ACX_RATE_MGMT_NUM_OF_RATES 13
1074struct conf_rate_policy_settings {
1075 u16 rate_retry_score;
1076 u16 per_add;
1077 u16 per_th1;
1078 u16 per_th2;
1079 u16 max_per;
1080 u8 inverse_curiosity_factor;
1081 u8 tx_fail_low_th;
1082 u8 tx_fail_high_th;
1083 u8 per_alpha_shift;
1084 u8 per_add_shift;
1085 u8 per_beta1_shift;
1086 u8 per_beta2_shift;
1087 u8 rate_check_up;
1088 u8 rate_check_down;
1089 u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES];
1090} __packed;
1091
1092struct conf_hangover_settings {
1093 u32 recover_time;
1094 u8 hangover_period;
1095 u8 dynamic_mode;
1096 u8 early_termination_mode;
1097 u8 max_period;
1098 u8 min_period;
1099 u8 increase_delta;
1100 u8 decrease_delta;
1101 u8 quiet_time;
1102 u8 increase_time;
1103 u8 window_size;
1104} __packed;
1105
1106struct conf_recovery_settings {
1107
1108 u8 bug_on_recovery;
1109
1110
1111 u8 no_recovery;
1112} __packed;
1113
1114
1115
1116
1117
1118
1119#define WLCORE_CONF_VERSION (0x0007 << 16)
1120#define WLCORE_CONF_MASK 0xffff0000
1121#define WLCORE_CONF_SIZE (sizeof(struct wlcore_conf_header) + \
1122 sizeof(struct wlcore_conf))
1123
1124struct wlcore_conf_header {
1125 __le32 magic;
1126 __le32 version;
1127 __le32 checksum;
1128} __packed;
1129
1130struct wlcore_conf {
1131 struct conf_sg_settings sg;
1132 struct conf_rx_settings rx;
1133 struct conf_tx_settings tx;
1134 struct conf_conn_settings conn;
1135 struct conf_itrim_settings itrim;
1136 struct conf_pm_config_settings pm_config;
1137 struct conf_roam_trigger_settings roam_trigger;
1138 struct conf_scan_settings scan;
1139 struct conf_sched_scan_settings sched_scan;
1140 struct conf_ht_setting ht;
1141 struct conf_memory_settings mem;
1142 struct conf_fm_coex fm_coex;
1143 struct conf_rx_streaming_settings rx_streaming;
1144 struct conf_fwlog fwlog;
1145 struct conf_rate_policy_settings rate;
1146 struct conf_hangover_settings hangover;
1147 struct conf_recovery_settings recovery;
1148} __packed;
1149
1150struct wlcore_conf_file {
1151 struct wlcore_conf_header header;
1152 struct wlcore_conf core;
1153 u8 priv[];
1154} __packed;
1155
1156#endif
1157