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19#ifndef _AACRAID_H_
20#define _AACRAID_H_
21#ifndef dprintk
22# define dprintk(x)
23#endif
24
25#define _nblank(x) #x
26#define nblank(x) _nblank(x)[0]
27
28#include <linux/interrupt.h>
29#include <linux/completion.h>
30#include <linux/pci.h>
31#include <scsi/scsi_host.h>
32
33
34
35
36
37#define AAC_MAX_MSIX 32
38#define AAC_PCI_MSI_ENABLE 0x8000
39
40enum {
41 AAC_ENABLE_INTERRUPT = 0x0,
42 AAC_DISABLE_INTERRUPT,
43 AAC_ENABLE_MSIX,
44 AAC_DISABLE_MSIX,
45 AAC_CLEAR_AIF_BIT,
46 AAC_CLEAR_SYNC_BIT,
47 AAC_ENABLE_INTX
48};
49
50#define AAC_INT_MODE_INTX (1<<0)
51#define AAC_INT_MODE_MSI (1<<1)
52#define AAC_INT_MODE_AIF (1<<2)
53#define AAC_INT_MODE_SYNC (1<<3)
54#define AAC_INT_MODE_MSIX (1<<16)
55
56#define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb
57#define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa
58#define AAC_INT_DISABLE_ALL 0xffffffff
59
60
61#define PMC_TRANSITION_TO_OPERATIONAL (1<<31)
62#define PMC_IOARCB_TRANSFER_FAILED (1<<28)
63#define PMC_IOA_UNIT_CHECK (1<<27)
64#define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
65#define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
66#define PMC_IOARRIN_LOST (1<<4)
67#define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3)
68#define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
69#define PMC_HOST_RRQ_VALID (1<<1)
70#define PMC_OPERATIONAL_STATUS (1<<31)
71#define PMC_ALLOW_MSIX_VECTOR0 (1<<0)
72
73#define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \
74 PMC_IOA_UNIT_CHECK | \
75 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \
76 PMC_IOARRIN_LOST | \
77 PMC_SYSTEM_BUS_MMIO_ERROR | \
78 PMC_IOA_PROCESSOR_IN_ERROR_STATE)
79
80#define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \
81 PMC_HOST_RRQ_VALID | \
82 PMC_TRANSITION_TO_OPERATIONAL | \
83 PMC_ALLOW_MSIX_VECTOR0)
84#define PMC_GLOBAL_INT_BIT2 0x00000004
85#define PMC_GLOBAL_INT_BIT0 0x00000001
86
87#ifndef AAC_DRIVER_BUILD
88# define AAC_DRIVER_BUILD 50983
89# define AAC_DRIVER_BRANCH "-custom"
90#endif
91#define MAXIMUM_NUM_CONTAINERS 32
92
93#define AAC_NUM_MGT_FIB 8
94#define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
95#define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
96
97#define AAC_MAX_LUN 256
98
99#define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
100#define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256)
101
102#define AAC_DEBUG_INSTRUMENT_AIF_DELETE
103
104#define AAC_MAX_NATIVE_TARGETS 1024
105
106#define AAC_MAX_BUSES 5
107#define AAC_MAX_TARGETS 256
108#define AAC_BUS_TARGET_LOOP (AAC_MAX_BUSES * AAC_MAX_TARGETS)
109#define AAC_MAX_NATIVE_SIZE 2048
110#define FW_ERROR_BUFFER_SIZE 512
111#define AAC_SA_TIMEOUT 180
112#define AAC_ARC_TIMEOUT 60
113
114#define get_bus_number(x) (x/AAC_MAX_TARGETS)
115#define get_target_number(x) (x%AAC_MAX_TARGETS)
116
117
118#define SA_AIF_HOTPLUG (1<<1)
119#define SA_AIF_HARDWARE (1<<2)
120#define SA_AIF_PDEV_CHANGE (1<<4)
121#define SA_AIF_LDEV_CHANGE (1<<5)
122#define SA_AIF_BPSTAT_CHANGE (1<<30)
123#define SA_AIF_BPCFG_CHANGE (1<<31)
124
125#define HBA_MAX_SG_EMBEDDED 28
126#define HBA_MAX_SG_SEPARATE 90
127#define HBA_SENSE_DATA_LEN_MAX 32
128#define HBA_REQUEST_TAG_ERROR_FLAG 0x00000002
129#define HBA_SGL_FLAGS_EXT 0x80000000UL
130
131struct aac_hba_sgl {
132 u32 addr_lo;
133 u32 addr_hi;
134 u32 len;
135 u32 flags;
136};
137
138enum {
139 HBA_IU_TYPE_SCSI_CMD_REQ = 0x40,
140 HBA_IU_TYPE_SCSI_TM_REQ = 0x41,
141 HBA_IU_TYPE_SATA_REQ = 0x42,
142 HBA_IU_TYPE_RESP = 0x60,
143 HBA_IU_TYPE_COALESCED_RESP = 0x61,
144 HBA_IU_TYPE_INT_COALESCING_CFG_REQ = 0x70
145};
146
147enum {
148 HBA_CMD_BYTE1_DATA_DIR_IN = 0x1,
149 HBA_CMD_BYTE1_DATA_DIR_OUT = 0x2,
150 HBA_CMD_BYTE1_DATA_TYPE_DDR = 0x4,
151 HBA_CMD_BYTE1_CRYPTO_ENABLE = 0x8
152};
153
154enum {
155 HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN = 0x0,
156 HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT,
157 HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR,
158 HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE
159};
160
161enum {
162 HBA_RESP_DATAPRES_NO_DATA = 0x0,
163 HBA_RESP_DATAPRES_RESPONSE_DATA,
164 HBA_RESP_DATAPRES_SENSE_DATA
165};
166
167enum {
168 HBA_RESP_SVCRES_TASK_COMPLETE = 0x0,
169 HBA_RESP_SVCRES_FAILURE,
170 HBA_RESP_SVCRES_TMF_COMPLETE,
171 HBA_RESP_SVCRES_TMF_SUCCEEDED,
172 HBA_RESP_SVCRES_TMF_REJECTED,
173 HBA_RESP_SVCRES_TMF_LUN_INVALID
174};
175
176enum {
177 HBA_RESP_STAT_IO_ERROR = 0x1,
178 HBA_RESP_STAT_IO_ABORTED,
179 HBA_RESP_STAT_NO_PATH_TO_DEVICE,
180 HBA_RESP_STAT_INVALID_DEVICE,
181 HBA_RESP_STAT_HBAMODE_DISABLED = 0xE,
182 HBA_RESP_STAT_UNDERRUN = 0x51,
183 HBA_RESP_STAT_OVERRUN = 0x75
184};
185
186struct aac_hba_cmd_req {
187 u8 iu_type;
188
189
190
191
192
193
194 u8 byte1;
195 u8 reply_qid;
196 u8 reserved1;
197 __le32 it_nexus;
198 __le32 request_id;
199
200 __le32 tweak_value_lo;
201 u8 cdb[16];
202 u8 lun[8];
203
204
205 __le32 data_length;
206
207
208 u8 attr_prio;
209
210
211 u8 emb_data_desc_count;
212
213 __le16 dek_index;
214
215
216 __le32 error_ptr_lo;
217
218
219 __le32 error_ptr_hi;
220
221
222 __le32 error_length;
223
224
225 __le32 tweak_value_hi;
226
227 struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2];
228
229
230
231
232
233};
234
235
236#define HBA_TMF_ABORT_TASK 0x01
237#define HBA_TMF_LUN_RESET 0x08
238
239struct aac_hba_tm_req {
240 u8 iu_type;
241 u8 reply_qid;
242 u8 tmf;
243 u8 reserved1;
244
245 __le32 it_nexus;
246
247 u8 lun[8];
248
249
250 __le32 request_id;
251 __le32 reserved2;
252
253
254 __le32 managed_request_id;
255 __le32 reserved3;
256
257
258 __le32 error_ptr_lo;
259
260 __le32 error_ptr_hi;
261
262 __le32 error_length;
263};
264
265struct aac_hba_reset_req {
266 u8 iu_type;
267
268 u8 reset_type;
269 u8 reply_qid;
270 u8 reserved1;
271
272 __le32 it_nexus;
273 __le32 request_id;
274
275 __le32 error_ptr_lo;
276
277 __le32 error_ptr_hi;
278
279 __le32 error_length;
280};
281
282struct aac_hba_resp {
283 u8 iu_type;
284 u8 reserved1[3];
285 __le32 request_identifier;
286 __le32 reserved2;
287 u8 service_response;
288 u8 status;
289 u8 datapres;
290 u8 sense_response_data_len;
291 __le32 residual_count;
292
293 u8 sense_response_buf[HBA_SENSE_DATA_LEN_MAX];
294};
295
296struct aac_native_hba {
297 union {
298 struct aac_hba_cmd_req cmd;
299 struct aac_hba_tm_req tmr;
300 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE];
301 } cmd;
302 union {
303 struct aac_hba_resp err;
304 u8 resp_bytes[FW_ERROR_BUFFER_SIZE];
305 } resp;
306};
307
308#define CISS_REPORT_PHYSICAL_LUNS 0xc3
309#define WRITE_HOST_WELLNESS 0xa5
310#define CISS_IDENTIFY_PHYSICAL_DEVICE 0x15
311#define BMIC_IN 0x26
312#define BMIC_OUT 0x27
313
314struct aac_ciss_phys_luns_resp {
315 u8 list_length[4];
316 u8 resp_flag;
317 u8 reserved[3];
318 struct _ciss_lun {
319 u8 tid[3];
320 u8 bus;
321 u8 level3[2];
322 u8 level2[2];
323 u8 node_ident[16];
324 } lun[1];
325};
326
327
328
329
330#define AAC_MAX_HRRQ 64
331
332struct aac_ciss_identify_pd {
333 u8 scsi_bus;
334 u8 scsi_id;
335 u16 block_size;
336 u32 total_blocks;
337 u32 reserved_blocks;
338 u8 model[40];
339 u8 serial_number[40];
340 u8 firmware_revision[8];
341 u8 scsi_inquiry_bits;
342 u8 compaq_drive_stamp;
343 u8 last_failure_reason;
344
345 u8 flags;
346 u8 more_flags;
347 u8 scsi_lun;
348 u8 yet_more_flags;
349 u8 even_more_flags;
350 u32 spi_speed_rules;
351 u8 phys_connector[2];
352 u8 phys_box_on_bus;
353 u8 phys_bay_in_box;
354 u32 rpm;
355 u8 device_type;
356 u8 sata_version;
357 u64 big_total_block_count;
358 u64 ris_starting_lba;
359 u32 ris_size;
360 u8 wwid[20];
361 u8 controller_phy_map[32];
362 u16 phy_count;
363 u8 phy_connected_dev_type[256];
364 u8 phy_to_drive_bay_num[256];
365 u16 phy_to_attached_dev_index[256];
366 u8 box_index;
367 u8 spitfire_support;
368 u16 extra_physical_drive_flags;
369 u8 negotiated_link_rate[256];
370 u8 phy_to_phy_map[256];
371 u8 redundant_path_present_map;
372 u8 redundant_path_failure_map;
373 u8 active_path_number;
374 u16 alternate_paths_phys_connector[8];
375 u8 alternate_paths_phys_box_on_port[8];
376 u8 multi_lun_device_lun_count;
377 u8 minimum_good_fw_revision[8];
378 u8 unique_inquiry_bytes[20];
379 u8 current_temperature_degreesC;
380 u8 temperature_threshold_degreesC;
381 u8 max_temperature_degreesC;
382 u8 logical_blocks_per_phys_block_exp;
383 u16 current_queue_depth_limit;
384 u8 switch_name[10];
385 u16 switch_port;
386 u8 alternate_paths_switch_name[40];
387 u8 alternate_paths_switch_port[8];
388 u16 power_on_hours;
389 u16 percent_endurance_used;
390 u8 drive_authentication;
391 u8 smart_carrier_authentication;
392 u8 smart_carrier_app_fw_version;
393 u8 smart_carrier_bootloader_fw_version;
394 u8 SanitizeSecureEraseSupport;
395 u8 DriveKeyFlags;
396 u8 encryption_key_name[64];
397 u32 misc_drive_flags;
398 u16 dek_index;
399 u16 drive_encryption_flags;
400 u8 sanitize_maximum_time[6];
401 u8 connector_info_mode;
402 u8 connector_info_number[4];
403 u8 long_connector_name[64];
404 u8 device_unique_identifier[16];
405 u8 padto_2K[17];
406} __packed;
407
408
409
410
411#define CONTAINER_CHANNEL (0)
412#define NATIVE_CHANNEL (1)
413#define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL)
414#define CONTAINER_TO_ID(cont) (cont)
415#define CONTAINER_TO_LUN(cont) (0)
416#define ENCLOSURE_CHANNEL (3)
417
418#define PMC_DEVICE_S6 0x28b
419#define PMC_DEVICE_S7 0x28c
420#define PMC_DEVICE_S8 0x28d
421
422#define aac_phys_to_logical(x) ((x)+1)
423#define aac_logical_to_phys(x) ((x)?(x)-1:0)
424
425
426
427
428
429#define AAC_CHARDEV_UNREGISTERED (-1)
430#define AAC_CHARDEV_NEEDS_REINIT (-2)
431
432
433
434struct diskparm
435{
436 int heads;
437 int sectors;
438 int cylinders;
439};
440
441
442
443
444
445
446#define CT_NONE 0
447#define CT_OK 218
448#define FT_FILESYS 8
449#define FT_DRIVE 9
450
451
452
453
454
455
456
457struct sgentry {
458 __le32 addr;
459 __le32 count;
460};
461
462struct user_sgentry {
463 u32 addr;
464 u32 count;
465};
466
467struct sgentry64 {
468 __le32 addr[2];
469 __le32 count;
470};
471
472struct user_sgentry64 {
473 u32 addr[2];
474 u32 count;
475};
476
477struct sgentryraw {
478 __le32 next;
479 __le32 prev;
480 __le32 addr[2];
481 __le32 count;
482 __le32 flags;
483};
484
485struct user_sgentryraw {
486 u32 next;
487 u32 prev;
488 u32 addr[2];
489 u32 count;
490 u32 flags;
491};
492
493struct sge_ieee1212 {
494 u32 addrLow;
495 u32 addrHigh;
496 u32 length;
497 u32 flags;
498};
499
500
501
502
503
504
505
506
507struct sgmap {
508 __le32 count;
509 struct sgentry sg[1];
510};
511
512struct user_sgmap {
513 u32 count;
514 struct user_sgentry sg[1];
515};
516
517struct sgmap64 {
518 __le32 count;
519 struct sgentry64 sg[1];
520};
521
522struct user_sgmap64 {
523 u32 count;
524 struct user_sgentry64 sg[1];
525};
526
527struct sgmapraw {
528 __le32 count;
529 struct sgentryraw sg[1];
530};
531
532struct user_sgmapraw {
533 u32 count;
534 struct user_sgentryraw sg[1];
535};
536
537struct creation_info
538{
539 u8 buildnum;
540 u8 usec;
541 u8 via;
542
543
544 u8 year;
545 __le32 date;
546
547
548
549
550
551
552 __le32 serial[2];
553};
554
555
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565
566
567
568#define NUMBER_OF_COMM_QUEUES 8
569#define HOST_HIGH_CMD_ENTRIES 4
570#define HOST_NORM_CMD_ENTRIES 8
571#define ADAP_HIGH_CMD_ENTRIES 4
572#define ADAP_NORM_CMD_ENTRIES 512
573#define HOST_HIGH_RESP_ENTRIES 4
574#define HOST_NORM_RESP_ENTRIES 512
575#define ADAP_HIGH_RESP_ENTRIES 4
576#define ADAP_NORM_RESP_ENTRIES 8
577
578#define TOTAL_QUEUE_ENTRIES \
579 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
580 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
581
582
583
584
585
586
587#define QUEUE_ALIGNMENT 16
588
589
590
591
592
593
594
595
596struct aac_entry {
597 __le32 size;
598 __le32 addr;
599};
600
601
602
603
604
605
606struct aac_qhdr {
607 __le64 header_addr;
608
609 __le32 *producer;
610 __le32 *consumer;
611};
612
613
614
615
616
617
618#define HostNormCmdQue 1
619#define HostHighCmdQue 2
620#define HostNormRespQue 3
621#define HostHighRespQue 4
622#define AdapNormRespNotFull 5
623#define AdapHighRespNotFull 6
624#define AdapNormCmdNotFull 7
625#define AdapHighCmdNotFull 8
626#define SynchCommandComplete 9
627#define AdapInternalError 0xfe
628
629
630
631
632
633
634
635#define AdapNormCmdQue 2
636#define AdapHighCmdQue 3
637#define AdapNormRespQue 6
638#define AdapHighRespQue 7
639#define HostShutdown 8
640#define HostPowerFail 9
641#define FatalCommError 10
642#define HostNormRespNotFull 11
643#define HostHighRespNotFull 12
644#define HostNormCmdNotFull 13
645#define HostHighCmdNotFull 14
646#define FastIo 15
647#define AdapPrintfDone 16
648
649
650
651
652
653
654enum aac_queue_types {
655 HostNormCmdQueue = 0,
656 HostHighCmdQueue,
657 AdapNormCmdQueue,
658 AdapHighCmdQueue,
659 HostNormRespQueue,
660 HostHighRespQueue,
661 AdapNormRespQueue,
662 AdapHighRespQueue
663};
664
665
666
667
668
669#define FIB_MAGIC 0x0001
670#define FIB_MAGIC2 0x0004
671#define FIB_MAGIC2_64 0x0005
672
673
674
675
676
677#define FsaNormal 1
678
679
680struct aac_fib_xporthdr {
681 __le64 HostAddress;
682 __le32 Size;
683 __le32 Handle;
684 __le64 Reserved[2];
685};
686
687#define ALIGN32 32
688
689
690
691
692
693
694struct aac_fibhdr {
695 __le32 XferState;
696 __le16 Command;
697 u8 StructType;
698 u8 Unused;
699 __le16 Size;
700 __le16 SenderSize;
701
702 __le32 SenderFibAddress;
703 union {
704 __le32 ReceiverFibAddress;
705
706 __le32 SenderFibAddressHigh;
707 __le32 TimeStamp;
708 } u;
709 __le32 Handle;
710 u32 Previous;
711 u32 Next;
712};
713
714struct hw_fib {
715 struct aac_fibhdr header;
716 u8 data[512-sizeof(struct aac_fibhdr)];
717};
718
719
720
721
722
723#define TestCommandResponse 1
724#define TestAdapterCommand 2
725
726
727
728#define LastTestCommand 100
729#define ReinitHostNormCommandQueue 101
730#define ReinitHostHighCommandQueue 102
731#define ReinitHostHighRespQueue 103
732#define ReinitHostNormRespQueue 104
733#define ReinitAdapNormCommandQueue 105
734#define ReinitAdapHighCommandQueue 107
735#define ReinitAdapHighRespQueue 108
736#define ReinitAdapNormRespQueue 109
737#define InterfaceShutdown 110
738#define DmaCommandFib 120
739#define StartProfile 121
740#define TermProfile 122
741#define SpeedTest 123
742#define TakeABreakPt 124
743#define RequestPerfData 125
744#define SetInterruptDefTimer 126
745#define SetInterruptDefCount 127
746#define GetInterruptDefStatus 128
747#define LastCommCommand 129
748
749
750
751#define NuFileSystem 300
752#define UFS 301
753#define HostFileSystem 302
754#define LastFileSystemCommand 303
755
756
757
758#define ContainerCommand 500
759#define ContainerCommand64 501
760#define ContainerRawIo 502
761#define ContainerRawIo2 503
762
763
764
765#define ScsiPortCommand 600
766#define ScsiPortCommand64 601
767
768
769
770#define AifRequest 700
771#define CheckRevision 701
772#define FsaHostShutdown 702
773#define RequestAdapterInfo 703
774#define IsAdapterPaused 704
775#define SendHostTime 705
776#define RequestSupplementAdapterInfo 706
777#define LastMiscCommand 707
778
779
780
781
782
783enum fib_xfer_state {
784 HostOwned = (1<<0),
785 AdapterOwned = (1<<1),
786 FibInitialized = (1<<2),
787 FibEmpty = (1<<3),
788 AllocatedFromPool = (1<<4),
789 SentFromHost = (1<<5),
790 SentFromAdapter = (1<<6),
791 ResponseExpected = (1<<7),
792 NoResponseExpected = (1<<8),
793 AdapterProcessed = (1<<9),
794 HostProcessed = (1<<10),
795 HighPriority = (1<<11),
796 NormalPriority = (1<<12),
797 Async = (1<<13),
798 AsyncIo = (1<<13),
799 PageFileIo = (1<<14),
800 ShutdownRequest = (1<<15),
801 LazyWrite = (1<<16),
802 AdapterMicroFib = (1<<17),
803 BIOSFibPath = (1<<18),
804 FastResponseCapable = (1<<19),
805 ApiFib = (1<<20),
806
807 NoMoreAifDataAvailable = (1<<21)
808};
809
810
811
812
813
814
815#define ADAPTER_INIT_STRUCT_REVISION 3
816#define ADAPTER_INIT_STRUCT_REVISION_4 4
817#define ADAPTER_INIT_STRUCT_REVISION_6 6
818#define ADAPTER_INIT_STRUCT_REVISION_7 7
819#define ADAPTER_INIT_STRUCT_REVISION_8 8
820
821union aac_init
822{
823 struct _r7 {
824 __le32 init_struct_revision;
825 __le32 no_of_msix_vectors;
826 __le32 fsrev;
827 __le32 comm_header_address;
828 __le32 fast_io_comm_area_address;
829 __le32 adapter_fibs_physical_address;
830 __le32 adapter_fibs_virtual_address;
831 __le32 adapter_fibs_size;
832 __le32 adapter_fib_align;
833 __le32 printfbuf;
834 __le32 printfbufsiz;
835
836 __le32 host_phys_mem_pages;
837
838 __le32 host_elapsed_seconds;
839
840 __le32 init_flags;
841#define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001
842#define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010
843#define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020
844#define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040
845#define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080
846#define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100
847#define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400
848 __le32 max_io_commands;
849 __le32 max_io_size;
850 __le32 max_fib_size;
851
852 __le32 max_num_aif;
853
854
855 __le32 host_rrq_addr_low;
856 __le32 host_rrq_addr_high;
857 } r7;
858 struct _r8 {
859
860 __le32 init_struct_revision;
861 __le32 rr_queue_count;
862 __le32 host_elapsed_seconds;
863 __le32 init_flags;
864 __le32 max_io_size;
865 __le32 max_num_aif;
866 __le32 reserved1;
867 __le32 reserved2;
868 struct _rrq {
869 __le32 host_addr_low;
870 __le32 host_addr_high;
871 __le16 msix_id;
872 __le16 element_count;
873 __le16 comp_thresh;
874 __le16 unused;
875 } rrq[1];
876 } r8;
877};
878
879enum aac_log_level {
880 LOG_AAC_INIT = 10,
881 LOG_AAC_INFORMATIONAL = 20,
882 LOG_AAC_WARNING = 30,
883 LOG_AAC_LOW_ERROR = 40,
884 LOG_AAC_MEDIUM_ERROR = 50,
885 LOG_AAC_HIGH_ERROR = 60,
886 LOG_AAC_PANIC = 70,
887 LOG_AAC_DEBUG = 80,
888 LOG_AAC_WINDBG_PRINT = 90
889};
890
891#define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b
892#define FSAFS_NTC_FIB_CONTEXT 0x030c
893
894struct aac_dev;
895struct fib;
896struct scsi_cmnd;
897
898struct adapter_ops
899{
900
901 void (*adapter_interrupt)(struct aac_dev *dev);
902 void (*adapter_notify)(struct aac_dev *dev, u32 event);
903 void (*adapter_disable_int)(struct aac_dev *dev);
904 void (*adapter_enable_int)(struct aac_dev *dev);
905 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
906 int (*adapter_check_health)(struct aac_dev *dev);
907 int (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type);
908 void (*adapter_start)(struct aac_dev *dev);
909
910 int (*adapter_ioremap)(struct aac_dev * dev, u32 size);
911 irq_handler_t adapter_intr;
912
913 int (*adapter_deliver)(struct fib * fib);
914 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
915 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
916 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
917 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
918
919 int (*adapter_comm)(struct aac_dev * dev, int comm);
920};
921
922
923
924
925
926struct aac_driver_ident
927{
928 int (*init)(struct aac_dev *dev);
929 char * name;
930 char * vname;
931 char * model;
932 u16 channels;
933 int quirks;
934};
935
936
937
938
939
940
941#define AAC_QUIRK_31BIT 0x0001
942
943
944
945
946
947
948#define AAC_QUIRK_34SG 0x0002
949
950
951
952
953#define AAC_QUIRK_SLAVE 0x0004
954
955
956
957
958#define AAC_QUIRK_MASTER 0x0008
959
960
961
962
963
964
965#define AAC_QUIRK_17SG 0x0010
966
967
968
969
970
971#define AAC_QUIRK_SCSI_32 0x0020
972
973
974
975
976#define AAC_QUIRK_SRC 0x0040
977
978
979
980
981
982
983
984
985
986
987
988struct aac_queue {
989 u64 logical;
990 struct aac_entry *base;
991 struct aac_qhdr headers;
992 u32 entries;
993 wait_queue_head_t qfull;
994 wait_queue_head_t cmdready;
995
996 spinlock_t *lock;
997 spinlock_t lockdata;
998 struct list_head cmdq;
999
1000
1001 atomic_t numpending;
1002 struct aac_dev * dev;
1003};
1004
1005
1006
1007
1008
1009
1010struct aac_queue_block
1011{
1012 struct aac_queue queue[8];
1013};
1014
1015
1016
1017
1018
1019struct sa_drawbridge_CSR {
1020
1021 __le32 reserved[10];
1022 u8 LUT_Offset;
1023 u8 reserved1[3];
1024 __le32 LUT_Data;
1025 __le32 reserved2[26];
1026 __le16 PRICLEARIRQ;
1027 __le16 SECCLEARIRQ;
1028 __le16 PRISETIRQ;
1029 __le16 SECSETIRQ;
1030 __le16 PRICLEARIRQMASK;
1031 __le16 SECCLEARIRQMASK;
1032 __le16 PRISETIRQMASK;
1033 __le16 SECSETIRQMASK;
1034 __le32 MAILBOX0;
1035 __le32 MAILBOX1;
1036 __le32 MAILBOX2;
1037 __le32 MAILBOX3;
1038 __le32 MAILBOX4;
1039 __le32 MAILBOX5;
1040 __le32 MAILBOX6;
1041 __le32 MAILBOX7;
1042 __le32 ROM_Setup_Data;
1043 __le32 ROM_Control_Addr;
1044 __le32 reserved3[12];
1045 __le32 LUT[64];
1046};
1047
1048#define Mailbox0 SaDbCSR.MAILBOX0
1049#define Mailbox1 SaDbCSR.MAILBOX1
1050#define Mailbox2 SaDbCSR.MAILBOX2
1051#define Mailbox3 SaDbCSR.MAILBOX3
1052#define Mailbox4 SaDbCSR.MAILBOX4
1053#define Mailbox5 SaDbCSR.MAILBOX5
1054#define Mailbox6 SaDbCSR.MAILBOX6
1055#define Mailbox7 SaDbCSR.MAILBOX7
1056
1057#define DoorbellReg_p SaDbCSR.PRISETIRQ
1058#define DoorbellReg_s SaDbCSR.SECSETIRQ
1059#define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
1060
1061
1062#define DOORBELL_0 0x0001
1063#define DOORBELL_1 0x0002
1064#define DOORBELL_2 0x0004
1065#define DOORBELL_3 0x0008
1066#define DOORBELL_4 0x0010
1067#define DOORBELL_5 0x0020
1068#define DOORBELL_6 0x0040
1069
1070
1071#define PrintfReady DOORBELL_5
1072#define PrintfDone DOORBELL_5
1073
1074struct sa_registers {
1075 struct sa_drawbridge_CSR SaDbCSR;
1076};
1077
1078
1079#define SA_INIT_NUM_MSIXVECTORS 1
1080#define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS
1081
1082#define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1083#define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1084#define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
1085#define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
1086
1087
1088
1089
1090
1091struct rx_mu_registers {
1092
1093 __le32 ARSR;
1094 __le32 reserved0;
1095 __le32 AWR;
1096 __le32 reserved1;
1097 __le32 IMRx[2];
1098 __le32 OMRx[2];
1099 __le32 IDR;
1100 __le32 IISR;
1101
1102 __le32 IIMR;
1103
1104 __le32 ODR;
1105 __le32 OISR;
1106
1107 __le32 OIMR;
1108
1109 __le32 reserved2;
1110 __le32 reserved3;
1111 __le32 InboundQueue;
1112 __le32 OutboundQueue;
1113
1114
1115};
1116
1117struct rx_inbound {
1118 __le32 Mailbox[8];
1119};
1120
1121#define INBOUNDDOORBELL_0 0x00000001
1122#define INBOUNDDOORBELL_1 0x00000002
1123#define INBOUNDDOORBELL_2 0x00000004
1124#define INBOUNDDOORBELL_3 0x00000008
1125#define INBOUNDDOORBELL_4 0x00000010
1126#define INBOUNDDOORBELL_5 0x00000020
1127#define INBOUNDDOORBELL_6 0x00000040
1128
1129#define OUTBOUNDDOORBELL_0 0x00000001
1130#define OUTBOUNDDOORBELL_1 0x00000002
1131#define OUTBOUNDDOORBELL_2 0x00000004
1132#define OUTBOUNDDOORBELL_3 0x00000008
1133#define OUTBOUNDDOORBELL_4 0x00000010
1134
1135#define InboundDoorbellReg MUnit.IDR
1136#define OutboundDoorbellReg MUnit.ODR
1137
1138struct rx_registers {
1139 struct rx_mu_registers MUnit;
1140 __le32 reserved1[2];
1141 struct rx_inbound IndexRegs;
1142};
1143
1144#define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
1145#define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
1146#define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
1147#define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
1148
1149
1150
1151
1152
1153#define rkt_mu_registers rx_mu_registers
1154#define rkt_inbound rx_inbound
1155
1156struct rkt_registers {
1157 struct rkt_mu_registers MUnit;
1158 __le32 reserved1[1006];
1159 struct rkt_inbound IndexRegs;
1160};
1161
1162#define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
1163#define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
1164#define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
1165#define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
1166
1167
1168
1169
1170
1171#define src_inbound rx_inbound
1172
1173struct src_mu_registers {
1174
1175 __le32 reserved0[6];
1176 __le32 IOAR[2];
1177 __le32 IDR;
1178 __le32 IISR;
1179 __le32 reserved1[3];
1180 __le32 OIMR;
1181 __le32 reserved2[25];
1182 __le32 ODR_R;
1183 __le32 ODR_C;
1184 __le32 reserved3[3];
1185 __le32 SCR0;
1186 __le32 reserved4[2];
1187 __le32 OMR;
1188 __le32 IQ_L;
1189 __le32 IQ_H;
1190 __le32 ODR_MSI;
1191 __le32 reserved5;
1192 __le32 IQN_L;
1193 __le32 IQN_H;
1194};
1195
1196struct src_registers {
1197 struct src_mu_registers MUnit;
1198 union {
1199 struct {
1200 __le32 reserved1[130786];
1201 struct src_inbound IndexRegs;
1202 } tupelo;
1203 struct {
1204 __le32 reserved1[970];
1205 struct src_inbound IndexRegs;
1206 } denali;
1207 } u;
1208};
1209
1210#define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
1211#define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
1212#define src_writeb(AEP, CSR, value) writeb(value, \
1213 &((AEP)->regs.src.bar0->CSR))
1214#define src_writel(AEP, CSR, value) writel(value, \
1215 &((AEP)->regs.src.bar0->CSR))
1216#if defined(writeq)
1217#define src_writeq(AEP, CSR, value) writeq(value, \
1218 &((AEP)->regs.src.bar0->CSR))
1219#endif
1220
1221#define SRC_ODR_SHIFT 12
1222#define SRC_IDR_SHIFT 9
1223#define SRC_MSI_READ_MASK 0x1000
1224
1225typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
1226
1227struct aac_fib_context {
1228 s16 type;
1229 s16 size;
1230 u32 unique;
1231 ulong jiffies;
1232 struct list_head next;
1233 struct completion completion;
1234 int wait;
1235 unsigned long count;
1236 struct list_head fib_list;
1237};
1238
1239struct sense_data {
1240 u8 error_code;
1241 u8 valid:1;
1242
1243
1244
1245 u8 segment_number;
1246 u8 sense_key:4;
1247 u8 reserved:1;
1248 u8 ILI:1;
1249 u8 EOM:1;
1250 u8 filemark:1;
1251
1252 u8 information[4];
1253
1254
1255
1256 u8 add_sense_len;
1257 u8 cmnd_info[4];
1258 u8 ASC;
1259 u8 ASCQ;
1260 u8 FRUC;
1261 u8 bit_ptr:3;
1262
1263
1264 u8 BPV:1;
1265
1266
1267 u8 reserved2:2;
1268 u8 CD:1;
1269
1270
1271 u8 SKSV:1;
1272 u8 field_ptr[2];
1273};
1274
1275struct fsa_dev_info {
1276 u64 last;
1277 u64 size;
1278 u32 type;
1279 u32 config_waiting_on;
1280 unsigned long config_waiting_stamp;
1281 u16 queue_depth;
1282 u8 config_needed;
1283 u8 valid;
1284 u8 ro;
1285 u8 locked;
1286 u8 deleted;
1287 char devname[8];
1288 struct sense_data sense_data;
1289 u32 block_size;
1290 u8 identifier[16];
1291};
1292
1293struct fib {
1294 void *next;
1295 s16 type;
1296 s16 size;
1297
1298
1299
1300 struct aac_dev *dev;
1301
1302
1303
1304
1305 struct completion event_wait;
1306 spinlock_t event_lock;
1307
1308 u32 done;
1309 fib_callback callback;
1310 void *callback_data;
1311 u32 flags;
1312
1313
1314
1315
1316 struct list_head fiblink;
1317 void *data;
1318 u32 vector_no;
1319 struct hw_fib *hw_fib_va;
1320 dma_addr_t hw_fib_pa;
1321 dma_addr_t hw_sgl_pa;
1322 dma_addr_t hw_error_pa;
1323 u32 hbacmd_size;
1324};
1325
1326#define AAC_INIT 0
1327#define AAC_RESCAN 1
1328
1329#define AAC_DEVTYPE_RAID_MEMBER 1
1330#define AAC_DEVTYPE_ARC_RAW 2
1331#define AAC_DEVTYPE_NATIVE_RAW 3
1332
1333#define AAC_RESCAN_DELAY (10 * HZ)
1334
1335struct aac_hba_map_info {
1336 __le32 rmw_nexus;
1337 u8 devtype;
1338 s8 reset_state;
1339
1340 u16 qd_limit;
1341 u32 scan_counter;
1342 struct aac_ciss_identify_pd *safw_identify_resp;
1343};
1344
1345
1346
1347
1348
1349
1350
1351struct aac_adapter_info
1352{
1353 __le32 platform;
1354 __le32 cpu;
1355 __le32 subcpu;
1356 __le32 clock;
1357 __le32 execmem;
1358 __le32 buffermem;
1359 __le32 totalmem;
1360 __le32 kernelrev;
1361 __le32 kernelbuild;
1362 __le32 monitorrev;
1363 __le32 monitorbuild;
1364 __le32 hwrev;
1365 __le32 hwbuild;
1366 __le32 biosrev;
1367 __le32 biosbuild;
1368 __le32 cluster;
1369 __le32 clusterchannelmask;
1370 __le32 serial[2];
1371 __le32 battery;
1372 __le32 options;
1373 __le32 OEM;
1374};
1375
1376struct aac_supplement_adapter_info
1377{
1378 u8 adapter_type_text[17+1];
1379 u8 pad[2];
1380 __le32 flash_memory_byte_size;
1381 __le32 flash_image_id;
1382 __le32 max_number_ports;
1383 __le32 version;
1384 __le32 feature_bits;
1385 u8 slot_number;
1386 u8 reserved_pad0[3];
1387 u8 build_date[12];
1388 __le32 current_number_ports;
1389 struct {
1390 u8 assembly_pn[8];
1391 u8 fru_pn[8];
1392 u8 battery_fru_pn[8];
1393 u8 ec_version_string[8];
1394 u8 tsid[12];
1395 } vpd_info;
1396 __le32 flash_firmware_revision;
1397 __le32 flash_firmware_build;
1398 __le32 raid_type_morph_options;
1399 __le32 flash_firmware_boot_revision;
1400 __le32 flash_firmware_boot_build;
1401 u8 mfg_pcba_serial_no[12];
1402 u8 mfg_wwn_name[8];
1403 __le32 supported_options2;
1404 __le32 struct_expansion;
1405
1406 __le32 feature_bits3;
1407 __le32 supported_performance_modes;
1408 u8 host_bus_type;
1409 u8 host_bus_width;
1410 u16 host_bus_speed;
1411 u8 max_rrc_drives;
1412 u8 max_disk_xtasks;
1413
1414 u8 cpld_ver_loaded;
1415 u8 cpld_ver_in_flash;
1416
1417 __le64 max_rrc_capacity;
1418 __le32 compiled_max_hist_log_level;
1419 u8 custom_board_name[12];
1420 u16 supported_cntlr_mode;
1421 u16 reserved_for_future16;
1422 __le32 supported_options3;
1423
1424 __le16 virt_device_bus;
1425 __le16 virt_device_target;
1426 __le16 virt_device_lun;
1427 __le16 unused;
1428 __le32 reserved_for_future_growth[68];
1429
1430};
1431#define AAC_FEATURE_FALCON cpu_to_le32(0x00000010)
1432#define AAC_FEATURE_JBOD cpu_to_le32(0x08000000)
1433
1434#define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001)
1435#define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002)
1436#define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004)
1437#define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000)
1438
1439#define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000)
1440
1441#define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000)
1442
1443
1444
1445#define AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP cpu_to_le32(0x00004000)
1446#define AAC_SIS_VERSION_V3 3
1447#define AAC_SIS_SLOT_UNKNOWN 0xFF
1448
1449#define GetBusInfo 0x00000009
1450struct aac_bus_info {
1451 __le32 Command;
1452 __le32 ObjType;
1453 __le32 MethodId;
1454 __le32 ObjectId;
1455 __le32 CtlCmd;
1456};
1457
1458struct aac_bus_info_response {
1459 __le32 Status;
1460 __le32 ObjType;
1461 __le32 MethodId;
1462 __le32 ObjectId;
1463 __le32 CtlCmd;
1464 __le32 ProbeComplete;
1465 __le32 BusCount;
1466 __le32 TargetsPerBus;
1467 u8 InitiatorBusId[10];
1468 u8 BusValid[10];
1469};
1470
1471
1472
1473
1474#define AAC_BAT_REQ_PRESENT (1)
1475#define AAC_BAT_REQ_NOTPRESENT (2)
1476#define AAC_BAT_OPT_PRESENT (3)
1477#define AAC_BAT_OPT_NOTPRESENT (4)
1478#define AAC_BAT_NOT_SUPPORTED (5)
1479
1480
1481
1482#define AAC_CPU_SIMULATOR (1)
1483#define AAC_CPU_I960 (2)
1484#define AAC_CPU_STRONGARM (3)
1485
1486
1487
1488
1489#define AAC_OPT_SNAPSHOT cpu_to_le32(1)
1490#define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
1491#define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
1492#define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
1493#define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
1494#define AAC_OPT_RAID50 cpu_to_le32(1<<5)
1495#define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
1496#define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
1497#define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
1498#define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
1499#define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
1500#define AAC_OPT_ALARM cpu_to_le32(1<<11)
1501#define AAC_OPT_NONDASD cpu_to_le32(1<<12)
1502#define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13)
1503#define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14)
1504#define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1505#define AAC_OPT_NEW_COMM cpu_to_le32(1<<17)
1506#define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18)
1507#define AAC_OPT_EXTENDED cpu_to_le32(1<<23)
1508#define AAC_OPT_NATIVE_HBA cpu_to_le32(1<<25)
1509#define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28)
1510#define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29)
1511#define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30)
1512#define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31)
1513
1514#define AAC_COMM_PRODUCER 0
1515#define AAC_COMM_MESSAGE 1
1516#define AAC_COMM_MESSAGE_TYPE1 3
1517#define AAC_COMM_MESSAGE_TYPE2 4
1518#define AAC_COMM_MESSAGE_TYPE3 5
1519
1520#define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1)
1521#define AAC_EXTOPT_SOFT_RESET cpu_to_le32(1<<16)
1522
1523
1524struct aac_msix_ctx {
1525 int vector_no;
1526 struct aac_dev *dev;
1527};
1528
1529struct aac_dev
1530{
1531 struct list_head entry;
1532 const char *name;
1533 int id;
1534
1535
1536
1537
1538 unsigned int max_fib_size;
1539 unsigned int sg_tablesize;
1540 unsigned int max_num_aif;
1541
1542 unsigned int max_cmd_size;
1543
1544
1545
1546
1547 dma_addr_t hw_fib_pa;
1548 struct hw_fib *hw_fib_va;
1549 struct hw_fib *aif_base_va;
1550
1551
1552
1553 struct fib *fibs;
1554
1555 struct fib *free_fib;
1556 spinlock_t fib_lock;
1557
1558 struct mutex ioctl_mutex;
1559 struct mutex scan_mutex;
1560 struct aac_queue_block *queues;
1561
1562
1563
1564
1565
1566
1567
1568 struct list_head fib_list;
1569
1570 struct adapter_ops a_ops;
1571 unsigned long fsrev;
1572
1573 resource_size_t base_start;
1574 resource_size_t dbg_base;
1575
1576
1577 resource_size_t base_size, dbg_size;
1578
1579
1580
1581
1582
1583 union aac_init *init;
1584 dma_addr_t init_pa;
1585
1586 __le32 *host_rrq;
1587 dma_addr_t host_rrq_pa;
1588
1589 u32 host_rrq_idx[AAC_MAX_MSIX];
1590 atomic_t rrq_outstanding[AAC_MAX_MSIX];
1591 u32 fibs_pushed_no;
1592 struct pci_dev *pdev;
1593
1594 void *printfbuf;
1595 void *comm_addr;
1596 dma_addr_t comm_phys;
1597 size_t comm_size;
1598
1599 struct Scsi_Host *scsi_host_ptr;
1600 int maximum_num_containers;
1601 int maximum_num_physicals;
1602 int maximum_num_channels;
1603 struct fsa_dev_info *fsa_dev;
1604 struct task_struct *thread;
1605 struct delayed_work safw_rescan_work;
1606 struct delayed_work src_reinit_aif_worker;
1607 int cardtype;
1608
1609
1610
1611
1612 spinlock_t iq_lock;
1613
1614
1615
1616
1617#ifndef AAC_MIN_FOOTPRINT_SIZE
1618# define AAC_MIN_FOOTPRINT_SIZE 8192
1619# define AAC_MIN_SRC_BAR0_SIZE 0x400000
1620# define AAC_MIN_SRC_BAR1_SIZE 0x800
1621# define AAC_MIN_SRCV_BAR0_SIZE 0x100000
1622# define AAC_MIN_SRCV_BAR1_SIZE 0x400
1623#endif
1624 union
1625 {
1626 struct sa_registers __iomem *sa;
1627 struct rx_registers __iomem *rx;
1628 struct rkt_registers __iomem *rkt;
1629 struct {
1630 struct src_registers __iomem *bar0;
1631 char __iomem *bar1;
1632 } src;
1633 } regs;
1634 volatile void __iomem *base, *dbg_base_mapped;
1635 volatile struct rx_inbound __iomem *IndexRegs;
1636 u32 OIMR;
1637
1638
1639
1640 u32 aif_thread;
1641 struct aac_adapter_info adapter_info;
1642 struct aac_supplement_adapter_info supplement_adapter_info;
1643
1644
1645
1646 u8 nondasd_support;
1647 u8 jbod;
1648 u8 cache_protected;
1649 u8 dac_support;
1650 u8 needs_dac;
1651 u8 raid_scsi_mode;
1652 u8 comm_interface;
1653 u8 raw_io_interface;
1654 u8 raw_io_64;
1655 u8 printf_enabled;
1656 u8 in_reset;
1657 u8 in_soft_reset;
1658 u8 msi;
1659 u8 sa_firmware;
1660 int management_fib_count;
1661 spinlock_t manage_lock;
1662 spinlock_t sync_lock;
1663 int sync_mode;
1664 struct fib *sync_fib;
1665 struct list_head sync_fib_list;
1666 u32 doorbell_mask;
1667 u32 max_msix;
1668 u32 vector_cap;
1669 int msi_enabled;
1670 atomic_t msix_counter;
1671 u32 scan_counter;
1672 struct msix_entry msixentry[AAC_MAX_MSIX];
1673 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX];
1674 struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS];
1675 struct aac_ciss_phys_luns_resp *safw_phys_luns;
1676 u8 adapter_shutdown;
1677 u32 handle_pci_error;
1678 bool init_reset;
1679 u8 soft_reset_support;
1680};
1681
1682#define aac_adapter_interrupt(dev) \
1683 (dev)->a_ops.adapter_interrupt(dev)
1684
1685#define aac_adapter_notify(dev, event) \
1686 (dev)->a_ops.adapter_notify(dev, event)
1687
1688#define aac_adapter_disable_int(dev) \
1689 (dev)->a_ops.adapter_disable_int(dev)
1690
1691#define aac_adapter_enable_int(dev) \
1692 (dev)->a_ops.adapter_enable_int(dev)
1693
1694#define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
1695 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1696
1697#define aac_adapter_restart(dev, bled, reset_type) \
1698 ((dev)->a_ops.adapter_restart(dev, bled, reset_type))
1699
1700#define aac_adapter_start(dev) \
1701 ((dev)->a_ops.adapter_start(dev))
1702
1703#define aac_adapter_ioremap(dev, size) \
1704 (dev)->a_ops.adapter_ioremap(dev, size)
1705
1706#define aac_adapter_deliver(fib) \
1707 ((fib)->dev)->a_ops.adapter_deliver(fib)
1708
1709#define aac_adapter_bounds(dev,cmd,lba) \
1710 dev->a_ops.adapter_bounds(dev,cmd,lba)
1711
1712#define aac_adapter_read(fib,cmd,lba,count) \
1713 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1714
1715#define aac_adapter_write(fib,cmd,lba,count,fua) \
1716 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1717
1718#define aac_adapter_scsi(fib,cmd) \
1719 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1720
1721#define aac_adapter_comm(dev,comm) \
1722 (dev)->a_ops.adapter_comm(dev, comm)
1723
1724#define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001)
1725#define FIB_CONTEXT_FLAG (0x00000002)
1726#define FIB_CONTEXT_FLAG_WAIT (0x00000004)
1727#define FIB_CONTEXT_FLAG_FASTRESP (0x00000008)
1728#define FIB_CONTEXT_FLAG_NATIVE_HBA (0x00000010)
1729#define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020)
1730#define FIB_CONTEXT_FLAG_SCSI_CMD (0x00000040)
1731#define FIB_CONTEXT_FLAG_EH_RESET (0x00000080)
1732
1733
1734
1735
1736
1737#define Null 0
1738#define GetAttributes 1
1739#define SetAttributes 2
1740#define Lookup 3
1741#define ReadLink 4
1742#define Read 5
1743#define Write 6
1744#define Create 7
1745#define MakeDirectory 8
1746#define SymbolicLink 9
1747#define MakeNode 10
1748#define Removex 11
1749#define RemoveDirectoryx 12
1750#define Rename 13
1751#define Link 14
1752#define ReadDirectory 15
1753#define ReadDirectoryPlus 16
1754#define FileSystemStatus 17
1755#define FileSystemInfo 18
1756#define PathConfigure 19
1757#define Commit 20
1758#define Mount 21
1759#define UnMount 22
1760#define Newfs 23
1761#define FsCheck 24
1762#define FsSync 25
1763#define SimReadWrite 26
1764#define SetFileSystemStatus 27
1765#define BlockRead 28
1766#define BlockWrite 29
1767#define NvramIoctl 30
1768#define FsSyncWait 31
1769#define ClearArchiveBit 32
1770#define SetAcl 33
1771#define GetAcl 34
1772#define AssignAcl 35
1773#define FaultInsertion 36
1774#define CrazyCache 37
1775
1776#define MAX_FSACOMMAND_NUM 38
1777
1778
1779
1780
1781
1782
1783
1784#define ST_OK 0
1785#define ST_PERM 1
1786#define ST_NOENT 2
1787#define ST_IO 5
1788#define ST_NXIO 6
1789#define ST_E2BIG 7
1790#define ST_MEDERR 8
1791#define ST_ACCES 13
1792#define ST_EXIST 17
1793#define ST_XDEV 18
1794#define ST_NODEV 19
1795#define ST_NOTDIR 20
1796#define ST_ISDIR 21
1797#define ST_INVAL 22
1798#define ST_FBIG 27
1799#define ST_NOSPC 28
1800#define ST_ROFS 30
1801#define ST_MLINK 31
1802#define ST_WOULDBLOCK 35
1803#define ST_NAMETOOLONG 63
1804#define ST_NOTEMPTY 66
1805#define ST_DQUOT 69
1806#define ST_STALE 70
1807#define ST_REMOTE 71
1808#define ST_NOT_READY 72
1809#define ST_BADHANDLE 10001
1810#define ST_NOT_SYNC 10002
1811#define ST_BAD_COOKIE 10003
1812#define ST_NOTSUPP 10004
1813#define ST_TOOSMALL 10005
1814#define ST_SERVERFAULT 10006
1815#define ST_BADTYPE 10007
1816#define ST_JUKEBOX 10008
1817#define ST_NOTMOUNTED 10009
1818#define ST_MAINTMODE 10010
1819#define ST_STALEACL 10011
1820
1821
1822
1823
1824
1825#define CACHE_CSTABLE 1
1826#define CACHE_UNSTABLE 2
1827
1828
1829
1830
1831
1832
1833#define CMFILE_SYNCH_NVRAM 1
1834#define CMDATA_SYNCH_NVRAM 2
1835#define CMFILE_SYNCH 3
1836#define CMDATA_SYNCH 4
1837#define CMUNSTABLE 5
1838
1839#define RIO_TYPE_WRITE 0x0000
1840#define RIO_TYPE_READ 0x0001
1841#define RIO_SUREWRITE 0x0008
1842
1843#define RIO2_IO_TYPE 0x0003
1844#define RIO2_IO_TYPE_WRITE 0x0000
1845#define RIO2_IO_TYPE_READ 0x0001
1846#define RIO2_IO_TYPE_VERIFY 0x0002
1847#define RIO2_IO_ERROR 0x0004
1848#define RIO2_IO_SUREWRITE 0x0008
1849#define RIO2_SGL_CONFORMANT 0x0010
1850#define RIO2_SG_FORMAT 0xF000
1851#define RIO2_SG_FORMAT_ARC 0x0000
1852#define RIO2_SG_FORMAT_SRL 0x1000
1853#define RIO2_SG_FORMAT_IEEE1212 0x2000
1854
1855struct aac_read
1856{
1857 __le32 command;
1858 __le32 cid;
1859 __le32 block;
1860 __le32 count;
1861 struct sgmap sg;
1862};
1863
1864struct aac_read64
1865{
1866 __le32 command;
1867 __le16 cid;
1868 __le16 sector_count;
1869 __le32 block;
1870 __le16 pad;
1871 __le16 flags;
1872 struct sgmap64 sg;
1873};
1874
1875struct aac_read_reply
1876{
1877 __le32 status;
1878 __le32 count;
1879};
1880
1881struct aac_write
1882{
1883 __le32 command;
1884 __le32 cid;
1885 __le32 block;
1886 __le32 count;
1887 __le32 stable;
1888 struct sgmap sg;
1889};
1890
1891struct aac_write64
1892{
1893 __le32 command;
1894 __le16 cid;
1895 __le16 sector_count;
1896 __le32 block;
1897 __le16 pad;
1898 __le16 flags;
1899 struct sgmap64 sg;
1900};
1901struct aac_write_reply
1902{
1903 __le32 status;
1904 __le32 count;
1905 __le32 committed;
1906};
1907
1908struct aac_raw_io
1909{
1910 __le32 block[2];
1911 __le32 count;
1912 __le16 cid;
1913 __le16 flags;
1914 __le16 bpTotal;
1915 __le16 bpComplete;
1916 struct sgmapraw sg;
1917};
1918
1919struct aac_raw_io2 {
1920 __le32 blockLow;
1921 __le32 blockHigh;
1922 __le32 byteCount;
1923 __le16 cid;
1924 __le16 flags;
1925 __le32 sgeFirstSize;
1926 __le32 sgeNominalSize;
1927 u8 sgeCnt;
1928 u8 bpTotal;
1929 u8 bpComplete;
1930 u8 sgeFirstIndex;
1931 u8 unused[4];
1932 struct sge_ieee1212 sge[];
1933};
1934
1935#define CT_FLUSH_CACHE 129
1936struct aac_synchronize {
1937 __le32 command;
1938 __le32 type;
1939 __le32 cid;
1940 __le32 parm1;
1941 __le32 parm2;
1942 __le32 parm3;
1943 __le32 parm4;
1944 __le32 count;
1945};
1946
1947struct aac_synchronize_reply {
1948 __le32 dummy0;
1949 __le32 dummy1;
1950 __le32 status;
1951 __le32 parm1;
1952 __le32 parm2;
1953 __le32 parm3;
1954 __le32 parm4;
1955 __le32 parm5;
1956 u8 data[16];
1957};
1958
1959#define CT_POWER_MANAGEMENT 245
1960#define CT_PM_START_UNIT 2
1961#define CT_PM_STOP_UNIT 3
1962#define CT_PM_UNIT_IMMEDIATE 1
1963struct aac_power_management {
1964 __le32 command;
1965 __le32 type;
1966 __le32 sub;
1967 __le32 cid;
1968 __le32 parm;
1969};
1970
1971#define CT_PAUSE_IO 65
1972#define CT_RELEASE_IO 66
1973struct aac_pause {
1974 __le32 command;
1975 __le32 type;
1976 __le32 timeout;
1977 __le32 min;
1978 __le32 noRescan;
1979 __le32 parm3;
1980 __le32 parm4;
1981 __le32 count;
1982};
1983
1984struct aac_srb
1985{
1986 __le32 function;
1987 __le32 channel;
1988 __le32 id;
1989 __le32 lun;
1990 __le32 timeout;
1991 __le32 flags;
1992 __le32 count;
1993 __le32 retry_limit;
1994 __le32 cdb_size;
1995 u8 cdb[16];
1996 struct sgmap sg;
1997};
1998
1999
2000
2001
2002
2003struct user_aac_srb
2004{
2005 u32 function;
2006 u32 channel;
2007 u32 id;
2008 u32 lun;
2009 u32 timeout;
2010 u32 flags;
2011 u32 count;
2012 u32 retry_limit;
2013 u32 cdb_size;
2014 u8 cdb[16];
2015 struct user_sgmap sg;
2016};
2017
2018#define AAC_SENSE_BUFFERSIZE 30
2019
2020struct aac_srb_reply
2021{
2022 __le32 status;
2023 __le32 srb_status;
2024 __le32 scsi_status;
2025 __le32 data_xfer_length;
2026 __le32 sense_data_size;
2027 u8 sense_data[AAC_SENSE_BUFFERSIZE];
2028};
2029
2030struct aac_srb_unit {
2031 struct aac_srb srb;
2032 struct aac_srb_reply srb_reply;
2033};
2034
2035
2036
2037
2038#define SRB_NoDataXfer 0x0000
2039#define SRB_DisableDisconnect 0x0004
2040#define SRB_DisableSynchTransfer 0x0008
2041#define SRB_BypassFrozenQueue 0x0010
2042#define SRB_DisableAutosense 0x0020
2043#define SRB_DataIn 0x0040
2044#define SRB_DataOut 0x0080
2045
2046
2047
2048
2049#define SRBF_ExecuteScsi 0x0000
2050#define SRBF_ClaimDevice 0x0001
2051#define SRBF_IO_Control 0x0002
2052#define SRBF_ReceiveEvent 0x0003
2053#define SRBF_ReleaseQueue 0x0004
2054#define SRBF_AttachDevice 0x0005
2055#define SRBF_ReleaseDevice 0x0006
2056#define SRBF_Shutdown 0x0007
2057#define SRBF_Flush 0x0008
2058#define SRBF_AbortCommand 0x0010
2059#define SRBF_ReleaseRecovery 0x0011
2060#define SRBF_ResetBus 0x0012
2061#define SRBF_ResetDevice 0x0013
2062#define SRBF_TerminateIO 0x0014
2063#define SRBF_FlushQueue 0x0015
2064#define SRBF_RemoveDevice 0x0016
2065#define SRBF_DomainValidation 0x0017
2066
2067
2068
2069
2070#define SRB_STATUS_PENDING 0x00
2071#define SRB_STATUS_SUCCESS 0x01
2072#define SRB_STATUS_ABORTED 0x02
2073#define SRB_STATUS_ABORT_FAILED 0x03
2074#define SRB_STATUS_ERROR 0x04
2075#define SRB_STATUS_BUSY 0x05
2076#define SRB_STATUS_INVALID_REQUEST 0x06
2077#define SRB_STATUS_INVALID_PATH_ID 0x07
2078#define SRB_STATUS_NO_DEVICE 0x08
2079#define SRB_STATUS_TIMEOUT 0x09
2080#define SRB_STATUS_SELECTION_TIMEOUT 0x0A
2081#define SRB_STATUS_COMMAND_TIMEOUT 0x0B
2082#define SRB_STATUS_MESSAGE_REJECTED 0x0D
2083#define SRB_STATUS_BUS_RESET 0x0E
2084#define SRB_STATUS_PARITY_ERROR 0x0F
2085#define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
2086#define SRB_STATUS_NO_HBA 0x11
2087#define SRB_STATUS_DATA_OVERRUN 0x12
2088#define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
2089#define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14
2090#define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
2091#define SRB_STATUS_REQUEST_FLUSHED 0x16
2092#define SRB_STATUS_DELAYED_RETRY 0x17
2093#define SRB_STATUS_INVALID_LUN 0x20
2094#define SRB_STATUS_INVALID_TARGET_ID 0x21
2095#define SRB_STATUS_BAD_FUNCTION 0x22
2096#define SRB_STATUS_ERROR_RECOVERY 0x23
2097#define SRB_STATUS_NOT_STARTED 0x24
2098#define SRB_STATUS_NOT_IN_USE 0x30
2099#define SRB_STATUS_FORCE_ABORT 0x31
2100#define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32
2101
2102
2103
2104
2105
2106#define VM_Null 0
2107#define VM_NameServe 1
2108#define VM_ContainerConfig 2
2109#define VM_Ioctl 3
2110#define VM_FilesystemIoctl 4
2111#define VM_CloseAll 5
2112#define VM_CtBlockRead 6
2113#define VM_CtBlockWrite 7
2114#define VM_SliceBlockRead 8
2115#define VM_SliceBlockWrite 9
2116#define VM_DriveBlockRead 10
2117#define VM_DriveBlockWrite 11
2118#define VM_EnclosureMgt 12
2119#define VM_Unused 13
2120#define VM_CtBlockVerify 14
2121#define VM_CtPerf 15
2122#define VM_CtBlockRead64 16
2123#define VM_CtBlockWrite64 17
2124#define VM_CtBlockVerify64 18
2125#define VM_CtHostRead64 19
2126#define VM_CtHostWrite64 20
2127#define VM_DrvErrTblLog 21
2128#define VM_NameServe64 22
2129#define VM_NameServeAllBlk 30
2130
2131#define MAX_VMCOMMAND_NUM 23
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141struct aac_fsinfo {
2142 __le32 fsTotalSize;
2143 __le32 fsBlockSize;
2144 __le32 fsFragSize;
2145 __le32 fsMaxExtendSize;
2146 __le32 fsSpaceUnits;
2147 __le32 fsMaxNumFiles;
2148 __le32 fsNumFreeFiles;
2149 __le32 fsInodeDensity;
2150};
2151
2152struct aac_blockdevinfo {
2153 __le32 block_size;
2154 __le32 logical_phys_map;
2155 u8 identifier[16];
2156};
2157
2158union aac_contentinfo {
2159 struct aac_fsinfo filesys;
2160 struct aac_blockdevinfo bdevinfo;
2161};
2162
2163
2164
2165
2166
2167#define CT_GET_CONFIG_STATUS 147
2168struct aac_get_config_status {
2169 __le32 command;
2170 __le32 type;
2171 __le32 parm1;
2172 __le32 parm2;
2173 __le32 parm3;
2174 __le32 parm4;
2175 __le32 parm5;
2176 __le32 count;
2177};
2178
2179#define CFACT_CONTINUE 0
2180#define CFACT_PAUSE 1
2181#define CFACT_ABORT 2
2182struct aac_get_config_status_resp {
2183 __le32 response;
2184 __le32 dummy0;
2185 __le32 status;
2186 __le32 parm1;
2187 __le32 parm2;
2188 __le32 parm3;
2189 __le32 parm4;
2190 __le32 parm5;
2191 struct {
2192 __le32 action;
2193 __le16 flags;
2194 __le16 count;
2195 } data;
2196};
2197
2198
2199
2200
2201
2202#define CT_COMMIT_CONFIG 152
2203
2204struct aac_commit_config {
2205 __le32 command;
2206 __le32 type;
2207};
2208
2209
2210
2211
2212
2213#define CT_GET_CONTAINER_COUNT 4
2214struct aac_get_container_count {
2215 __le32 command;
2216 __le32 type;
2217};
2218
2219struct aac_get_container_count_resp {
2220 __le32 response;
2221 __le32 dummy0;
2222 __le32 MaxContainers;
2223 __le32 ContainerSwitchEntries;
2224 __le32 MaxPartitions;
2225 __le32 MaxSimpleVolumes;
2226};
2227
2228
2229
2230
2231
2232
2233
2234struct aac_mntent {
2235 __le32 oid;
2236 u8 name[16];
2237 struct creation_info create_info;
2238 __le32 capacity;
2239 __le32 vol;
2240 __le32 obj;
2241 __le32 state;
2242
2243 union aac_contentinfo fileinfo;
2244
2245 __le32 altoid;
2246
2247 __le32 capacityhigh;
2248};
2249
2250#define FSCS_NOTCLEAN 0x0001
2251#define FSCS_READONLY 0x0002
2252#define FSCS_HIDDEN 0x0004
2253#define FSCS_NOT_READY 0x0008
2254
2255struct aac_query_mount {
2256 __le32 command;
2257 __le32 type;
2258 __le32 count;
2259};
2260
2261struct aac_mount {
2262 __le32 status;
2263 __le32 type;
2264 __le32 count;
2265 struct aac_mntent mnt[1];
2266};
2267
2268#define CT_READ_NAME 130
2269struct aac_get_name {
2270 __le32 command;
2271 __le32 type;
2272 __le32 cid;
2273 __le32 parm1;
2274 __le32 parm2;
2275 __le32 parm3;
2276 __le32 parm4;
2277 __le32 count;
2278};
2279
2280struct aac_get_name_resp {
2281 __le32 dummy0;
2282 __le32 dummy1;
2283 __le32 status;
2284 __le32 parm1;
2285 __le32 parm2;
2286 __le32 parm3;
2287 __le32 parm4;
2288 __le32 parm5;
2289 u8 data[17];
2290};
2291
2292#define CT_CID_TO_32BITS_UID 165
2293struct aac_get_serial {
2294 __le32 command;
2295 __le32 type;
2296 __le32 cid;
2297};
2298
2299struct aac_get_serial_resp {
2300 __le32 dummy0;
2301 __le32 dummy1;
2302 __le32 status;
2303 __le32 uid;
2304};
2305
2306
2307
2308
2309
2310struct aac_close {
2311 __le32 command;
2312 __le32 cid;
2313};
2314
2315struct aac_query_disk
2316{
2317 s32 cnum;
2318 s32 bus;
2319 s32 id;
2320 s32 lun;
2321 u32 valid;
2322 u32 locked;
2323 u32 deleted;
2324 s32 instance;
2325 s8 name[10];
2326 u32 unmapped;
2327};
2328
2329struct aac_delete_disk {
2330 u32 disknum;
2331 u32 cnum;
2332};
2333
2334struct fib_ioctl
2335{
2336 u32 fibctx;
2337 s32 wait;
2338 char __user *fib;
2339};
2340
2341struct revision
2342{
2343 u32 compat;
2344 __le32 version;
2345 __le32 build;
2346};
2347
2348
2349
2350
2351
2352
2353#define CTL_CODE(function, method) ( \
2354 (4<< 16) | ((function) << 2) | (method) \
2355)
2356
2357
2358
2359
2360
2361
2362#define METHOD_BUFFERED 0
2363#define METHOD_NEITHER 3
2364
2365
2366
2367
2368
2369#define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED)
2370#define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED)
2371#define FSACTL_DELETE_DISK 0x163
2372#define FSACTL_QUERY_DISK 0x173
2373#define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED)
2374#define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED)
2375#define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED)
2376#define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED)
2377#define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED)
2378#define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER)
2379#define FSACTL_GET_CONTAINERS 2131
2380#define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED)
2381#define FSACTL_RESET_IOP CTL_CODE(2140, METHOD_BUFFERED)
2382#define FSACTL_GET_HBA_INFO CTL_CODE(2150, METHOD_BUFFERED)
2383
2384#define HW_IOP_RESET 0x01
2385#define HW_SOFT_RESET 0x02
2386#define IOP_HWSOFT_RESET (HW_IOP_RESET | HW_SOFT_RESET)
2387
2388#define IBW_SWR_OFFSET 0x4000
2389#define SOFT_RESET_TIME 60
2390
2391
2392
2393struct aac_common
2394{
2395
2396
2397
2398
2399 u32 irq_mod;
2400 u32 peak_fibs;
2401 u32 zero_fibs;
2402 u32 fib_timeouts;
2403
2404
2405
2406#ifdef DBG
2407 u32 FibsSent;
2408 u32 FibRecved;
2409 u32 NativeSent;
2410 u32 NativeRecved;
2411 u32 NoResponseSent;
2412 u32 NoResponseRecved;
2413 u32 AsyncSent;
2414 u32 AsyncRecved;
2415 u32 NormalSent;
2416 u32 NormalRecved;
2417#endif
2418};
2419
2420extern struct aac_common aac_config;
2421
2422
2423
2424
2425struct aac_hba_info {
2426
2427 u8 driver_name[50];
2428 u8 adapter_number;
2429 u8 system_io_bus_number;
2430 u8 device_number;
2431 u32 function_number;
2432 u32 vendor_id;
2433 u32 device_id;
2434 u32 sub_vendor_id;
2435 u32 sub_system_id;
2436 u32 mapped_base_address_size;
2437 u32 base_physical_address_high_part;
2438 u32 base_physical_address_low_part;
2439
2440 u32 max_command_size;
2441 u32 max_fib_size;
2442 u32 max_scatter_gather_from_os;
2443 u32 max_scatter_gather_to_fw;
2444 u32 max_outstanding_fibs;
2445
2446 u32 queue_start_threshold;
2447 u32 queue_dump_threshold;
2448 u32 max_io_size_queued;
2449 u32 outstanding_io;
2450
2451 u32 firmware_build_number;
2452 u32 bios_build_number;
2453 u32 driver_build_number;
2454 u32 serial_number_high_part;
2455 u32 serial_number_low_part;
2456 u32 supported_options;
2457 u32 feature_bits;
2458 u32 currentnumber_ports;
2459
2460 u8 new_comm_interface:1;
2461 u8 new_commands_supported:1;
2462 u8 disable_passthrough:1;
2463 u8 expose_non_dasd:1;
2464 u8 queue_allowed:1;
2465 u8 bled_check_enabled:1;
2466 u8 reserved1:1;
2467 u8 reserted2:1;
2468
2469 u32 reserved3[10];
2470
2471};
2472
2473
2474
2475
2476
2477
2478#ifdef DBG
2479#define FIB_COUNTER_INCREMENT(counter) (counter)++
2480#else
2481#define FIB_COUNTER_INCREMENT(counter)
2482#endif
2483
2484
2485
2486
2487
2488
2489#define BREAKPOINT_REQUEST 0x00000004
2490#define INIT_STRUCT_BASE_ADDRESS 0x00000005
2491#define READ_PERMANENT_PARAMETERS 0x0000000a
2492#define WRITE_PERMANENT_PARAMETERS 0x0000000b
2493#define HOST_CRASHING 0x0000000d
2494#define SEND_SYNCHRONOUS_FIB 0x0000000c
2495#define COMMAND_POST_RESULTS 0x00000014
2496#define GET_ADAPTER_PROPERTIES 0x00000019
2497#define GET_DRIVER_BUFFER_PROPERTIES 0x00000023
2498#define RCV_TEMP_READINGS 0x00000025
2499#define GET_COMM_PREFERRED_SETTINGS 0x00000026
2500#define IOP_RESET_FW_FIB_DUMP 0x00000034
2501#define DROP_IO 0x00000035
2502#define IOP_RESET 0x00001000
2503#define IOP_RESET_ALWAYS 0x00001001
2504#define RE_INIT_ADAPTER 0x000000ee
2505
2506#define IOP_SRC_RESET_MASK 0x00000100
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529#define SELF_TEST_FAILED 0x00000004
2530#define MONITOR_PANIC 0x00000020
2531#define KERNEL_BOOTING 0x00000040
2532#define KERNEL_UP_AND_RUNNING 0x00000080
2533#define KERNEL_PANIC 0x00000100
2534#define FLASH_UPD_PENDING 0x00002000
2535#define FLASH_UPD_SUCCESS 0x00004000
2536#define FLASH_UPD_FAILED 0x00008000
2537#define INVALID_OMR 0xffffffff
2538#define FWUPD_TIMEOUT (5 * 60)
2539
2540
2541
2542
2543
2544#define DoorBellSyncCmdAvailable (1<<0)
2545#define DoorBellPrintfDone (1<<5)
2546#define DoorBellAdapterNormCmdReady (1<<1)
2547#define DoorBellAdapterNormRespReady (1<<2)
2548#define DoorBellAdapterNormCmdNotFull (1<<3)
2549#define DoorBellAdapterNormRespNotFull (1<<4)
2550#define DoorBellPrintfReady (1<<5)
2551#define DoorBellAifPending (1<<6)
2552
2553
2554#define PmDoorBellResponseSent (1<<1)
2555
2556
2557
2558
2559
2560
2561#define AifCmdEventNotify 1
2562#define AifEnConfigChange 3
2563#define AifEnContainerChange 4
2564#define AifEnDeviceFailure 5
2565#define AifEnEnclosureManagement 13
2566#define EM_DRIVE_INSERTION 31
2567#define EM_DRIVE_REMOVAL 32
2568#define EM_SES_DRIVE_INSERTION 33
2569#define EM_SES_DRIVE_REMOVAL 26
2570#define AifEnBatteryEvent 14
2571#define AifEnAddContainer 15
2572#define AifEnDeleteContainer 16
2573#define AifEnExpEvent 23
2574#define AifExeFirmwarePanic 3
2575#define AifHighPriority 3
2576#define AifEnAddJBOD 30
2577#define AifEnDeleteJBOD 31
2578
2579#define AifBuManagerEvent 42
2580#define AifBuCacheDataLoss 10
2581#define AifBuCacheDataRecover 11
2582
2583#define AifCmdJobProgress 2
2584#define AifJobCtrZero 101
2585#define AifJobStsSuccess 1
2586#define AifJobStsRunning 102
2587#define AifCmdAPIReport 3
2588#define AifCmdDriverNotify 4
2589#define AifDenMorphComplete 200
2590#define AifDenVolumeExtendComplete 201
2591#define AifReqJobList 100
2592#define AifReqJobsForCtr 101
2593#define AifReqJobsForScsi 102
2594#define AifReqJobReport 103
2595#define AifReqTerminateJob 104
2596#define AifReqSuspendJob 105
2597#define AifReqResumeJob 106
2598#define AifReqSendAPIReport 107
2599#define AifReqAPIJobStart 108
2600#define AifReqAPIJobUpdate 109
2601#define AifReqAPIJobFinish 110
2602
2603
2604#define AifReqEvent 200
2605#define AifRawDeviceRemove 203
2606#define AifNativeDeviceAdd 204
2607#define AifNativeDeviceRemove 205
2608
2609
2610
2611
2612
2613
2614
2615
2616struct aac_aifcmd {
2617 __le32 command;
2618 __le32 seqnum;
2619 u8 data[1];
2620};
2621
2622
2623
2624
2625
2626
2627static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
2628{
2629 sector_div(capacity, divisor);
2630 return capacity;
2631}
2632
2633static inline int aac_pci_offline(struct aac_dev *dev)
2634{
2635 return pci_channel_offline(dev->pdev) || dev->handle_pci_error;
2636}
2637
2638static inline int aac_adapter_check_health(struct aac_dev *dev)
2639{
2640 if (unlikely(aac_pci_offline(dev)))
2641 return -1;
2642
2643 return (dev)->a_ops.adapter_check_health(dev);
2644}
2645
2646
2647int aac_scan_host(struct aac_dev *dev);
2648
2649static inline void aac_schedule_safw_scan_worker(struct aac_dev *dev)
2650{
2651 schedule_delayed_work(&dev->safw_rescan_work, AAC_RESCAN_DELAY);
2652}
2653
2654static inline void aac_schedule_src_reinit_aif_worker(struct aac_dev *dev)
2655{
2656 schedule_delayed_work(&dev->src_reinit_aif_worker, AAC_RESCAN_DELAY);
2657}
2658
2659static inline void aac_safw_rescan_worker(struct work_struct *work)
2660{
2661 struct aac_dev *dev = container_of(to_delayed_work(work),
2662 struct aac_dev, safw_rescan_work);
2663
2664 wait_event(dev->scsi_host_ptr->host_wait,
2665 !scsi_host_in_recovery(dev->scsi_host_ptr));
2666
2667 aac_scan_host(dev);
2668}
2669
2670static inline void aac_cancel_rescan_worker(struct aac_dev *dev)
2671{
2672 cancel_delayed_work_sync(&dev->safw_rescan_work);
2673 cancel_delayed_work_sync(&dev->src_reinit_aif_worker);
2674}
2675
2676
2677#define AAC_OWNER_MIDLEVEL 0x101
2678#define AAC_OWNER_LOWLEVEL 0x102
2679#define AAC_OWNER_ERROR_HANDLER 0x103
2680#define AAC_OWNER_FIRMWARE 0x106
2681
2682void aac_safw_rescan_worker(struct work_struct *work);
2683void aac_src_reinit_aif_worker(struct work_struct *work);
2684int aac_acquire_irq(struct aac_dev *dev);
2685void aac_free_irq(struct aac_dev *dev);
2686int aac_setup_safw_adapter(struct aac_dev *dev);
2687const char *aac_driverinfo(struct Scsi_Host *);
2688void aac_fib_vector_assign(struct aac_dev *dev);
2689struct fib *aac_fib_alloc(struct aac_dev *dev);
2690struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd);
2691int aac_fib_setup(struct aac_dev *dev);
2692void aac_fib_map_free(struct aac_dev *dev);
2693void aac_fib_free(struct fib * context);
2694void aac_fib_init(struct fib * context);
2695void aac_printf(struct aac_dev *dev, u32 val);
2696int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
2697int aac_hba_send(u8 command, struct fib *context,
2698 fib_callback callback, void *ctxt);
2699int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
2700void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
2701int aac_fib_complete(struct fib * context);
2702void aac_hba_callback(void *context, struct fib *fibptr);
2703#define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2704struct aac_dev *aac_init_adapter(struct aac_dev *dev);
2705void aac_src_access_devreg(struct aac_dev *dev, int mode);
2706void aac_set_intx_mode(struct aac_dev *dev);
2707int aac_get_config_status(struct aac_dev *dev, int commit_flag);
2708int aac_get_containers(struct aac_dev *dev);
2709int aac_scsi_cmd(struct scsi_cmnd *cmd);
2710int aac_dev_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg);
2711#ifndef shost_to_class
2712#define shost_to_class(shost) &shost->shost_dev
2713#endif
2714ssize_t aac_get_serial_number(struct device *dev, char *buf);
2715int aac_do_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg);
2716int aac_rx_init(struct aac_dev *dev);
2717int aac_rkt_init(struct aac_dev *dev);
2718int aac_nark_init(struct aac_dev *dev);
2719int aac_sa_init(struct aac_dev *dev);
2720int aac_src_init(struct aac_dev *dev);
2721int aac_srcv_init(struct aac_dev *dev);
2722int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
2723void aac_define_int_mode(struct aac_dev *dev);
2724unsigned int aac_response_normal(struct aac_queue * q);
2725unsigned int aac_command_normal(struct aac_queue * q);
2726unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
2727 int isAif, int isFastResponse,
2728 struct hw_fib *aif_fib);
2729int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type);
2730int aac_check_health(struct aac_dev * dev);
2731int aac_command_thread(void *data);
2732int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
2733int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
2734struct aac_driver_ident* aac_get_driver_ident(int devtype);
2735int aac_get_adapter_info(struct aac_dev* dev);
2736int aac_send_shutdown(struct aac_dev *dev);
2737int aac_probe_container(struct aac_dev *dev, int cid);
2738int _aac_rx_init(struct aac_dev *dev);
2739int aac_rx_select_comm(struct aac_dev *dev, int comm);
2740int aac_rx_deliver_producer(struct fib * fib);
2741void aac_reinit_aif(struct aac_dev *aac, unsigned int index);
2742
2743static inline int aac_is_src(struct aac_dev *dev)
2744{
2745 u16 device = dev->pdev->device;
2746
2747 if (device == PMC_DEVICE_S6 ||
2748 device == PMC_DEVICE_S7 ||
2749 device == PMC_DEVICE_S8)
2750 return 1;
2751 return 0;
2752}
2753
2754static inline int aac_supports_2T(struct aac_dev *dev)
2755{
2756 return (dev->adapter_info.options & AAC_OPT_NEW_COMM_64);
2757}
2758
2759char * get_container_type(unsigned type);
2760extern int numacb;
2761extern char aac_driver_version[];
2762extern int startup_timeout;
2763extern int aif_timeout;
2764extern int expose_physicals;
2765extern int aac_reset_devices;
2766extern int aac_msi;
2767extern int aac_commit;
2768extern int update_interval;
2769extern int check_interval;
2770extern int aac_check_reset;
2771extern int aac_fib_dump;
2772#endif
2773