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6#include "hisi_sas.h"
7#define DRV_NAME "hisi_sas_v3_hw"
8
9
10#define DLVRY_QUEUE_ENABLE 0x0
11#define IOST_BASE_ADDR_LO 0x8
12#define IOST_BASE_ADDR_HI 0xc
13#define ITCT_BASE_ADDR_LO 0x10
14#define ITCT_BASE_ADDR_HI 0x14
15#define IO_BROKEN_MSG_ADDR_LO 0x18
16#define IO_BROKEN_MSG_ADDR_HI 0x1c
17#define PHY_CONTEXT 0x20
18#define PHY_STATE 0x24
19#define PHY_PORT_NUM_MA 0x28
20#define PHY_CONN_RATE 0x30
21#define ITCT_CLR 0x44
22#define ITCT_CLR_EN_OFF 16
23#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
24#define ITCT_DEV_OFF 0
25#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
26#define SAS_AXI_USER3 0x50
27#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
28#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
29#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
30#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
31#define CFG_MAX_TAG 0x68
32#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
33#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
34#define HGC_GET_ITV_TIME 0x90
35#define DEVICE_MSG_WORK_MODE 0x94
36#define OPENA_WT_CONTI_TIME 0x9c
37#define I_T_NEXUS_LOSS_TIME 0xa0
38#define MAX_CON_TIME_LIMIT_TIME 0xa4
39#define BUS_INACTIVE_LIMIT_TIME 0xa8
40#define REJECT_TO_OPEN_LIMIT_TIME 0xac
41#define CQ_INT_CONVERGE_EN 0xb0
42#define CFG_AGING_TIME 0xbc
43#define HGC_DFX_CFG2 0xc0
44#define CFG_ABT_SET_QUERY_IPTT 0xd4
45#define CFG_SET_ABORTED_IPTT_OFF 0
46#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
47#define CFG_SET_ABORTED_EN_OFF 12
48#define CFG_ABT_SET_IPTT_DONE 0xd8
49#define CFG_ABT_SET_IPTT_DONE_OFF 0
50#define HGC_IOMB_PROC1_STATUS 0x104
51#define HGC_LM_DFX_STATUS2 0x128
52#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
53#define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
54 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
55#define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
56#define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
57 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
58#define HGC_CQE_ECC_ADDR 0x13c
59#define HGC_CQE_ECC_1B_ADDR_OFF 0
60#define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
61#define HGC_CQE_ECC_MB_ADDR_OFF 8
62#define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
63#define HGC_IOST_ECC_ADDR 0x140
64#define HGC_IOST_ECC_1B_ADDR_OFF 0
65#define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
66#define HGC_IOST_ECC_MB_ADDR_OFF 16
67#define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
68#define HGC_DQE_ECC_ADDR 0x144
69#define HGC_DQE_ECC_1B_ADDR_OFF 0
70#define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
71#define HGC_DQE_ECC_MB_ADDR_OFF 16
72#define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
73#define CHNL_INT_STATUS 0x148
74#define TAB_DFX 0x14c
75#define HGC_ITCT_ECC_ADDR 0x150
76#define HGC_ITCT_ECC_1B_ADDR_OFF 0
77#define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
78 HGC_ITCT_ECC_1B_ADDR_OFF)
79#define HGC_ITCT_ECC_MB_ADDR_OFF 16
80#define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
81 HGC_ITCT_ECC_MB_ADDR_OFF)
82#define HGC_AXI_FIFO_ERR_INFO 0x154
83#define AXI_ERR_INFO_OFF 0
84#define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
85#define FIFO_ERR_INFO_OFF 8
86#define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
87#define TAB_RD_TYPE 0x15c
88#define INT_COAL_EN 0x19c
89#define OQ_INT_COAL_TIME 0x1a0
90#define OQ_INT_COAL_CNT 0x1a4
91#define ENT_INT_COAL_TIME 0x1a8
92#define ENT_INT_COAL_CNT 0x1ac
93#define OQ_INT_SRC 0x1b0
94#define OQ_INT_SRC_MSK 0x1b4
95#define ENT_INT_SRC1 0x1b8
96#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
97#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
98#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
99#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
100#define ENT_INT_SRC2 0x1bc
101#define ENT_INT_SRC3 0x1c0
102#define ENT_INT_SRC3_WP_DEPTH_OFF 8
103#define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
104#define ENT_INT_SRC3_RP_DEPTH_OFF 10
105#define ENT_INT_SRC3_AXI_OFF 11
106#define ENT_INT_SRC3_FIFO_OFF 12
107#define ENT_INT_SRC3_LM_OFF 14
108#define ENT_INT_SRC3_ITC_INT_OFF 15
109#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
110#define ENT_INT_SRC3_ABT_OFF 16
111#define ENT_INT_SRC3_DQE_POISON_OFF 18
112#define ENT_INT_SRC3_IOST_POISON_OFF 19
113#define ENT_INT_SRC3_ITCT_POISON_OFF 20
114#define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF 21
115#define ENT_INT_SRC_MSK1 0x1c4
116#define ENT_INT_SRC_MSK2 0x1c8
117#define ENT_INT_SRC_MSK3 0x1cc
118#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
119#define CHNL_PHYUPDOWN_INT_MSK 0x1d0
120#define CHNL_ENT_INT_MSK 0x1d4
121#define HGC_COM_INT_MSK 0x1d8
122#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
123#define SAS_ECC_INTR 0x1e8
124#define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
125#define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
126#define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
127#define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
128#define SAS_ECC_INTR_ITCT_ECC_1B_OFF 4
129#define SAS_ECC_INTR_ITCT_ECC_MB_OFF 5
130#define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 6
131#define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 7
132#define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 8
133#define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 9
134#define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
135#define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
136#define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 12
137#define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 13
138#define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 14
139#define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 15
140#define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 16
141#define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 17
142#define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 18
143#define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 19
144#define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF 20
145#define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF 21
146#define SAS_ECC_INTR_MSK 0x1ec
147#define HGC_ERR_STAT_EN 0x238
148#define CQE_SEND_CNT 0x248
149#define DLVRY_Q_0_BASE_ADDR_LO 0x260
150#define DLVRY_Q_0_BASE_ADDR_HI 0x264
151#define DLVRY_Q_0_DEPTH 0x268
152#define DLVRY_Q_0_WR_PTR 0x26c
153#define DLVRY_Q_0_RD_PTR 0x270
154#define HYPER_STREAM_ID_EN_CFG 0xc80
155#define OQ0_INT_SRC_MSK 0xc90
156#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
157#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
158#define COMPL_Q_0_DEPTH 0x4e8
159#define COMPL_Q_0_WR_PTR 0x4ec
160#define COMPL_Q_0_RD_PTR 0x4f0
161#define HGC_RXM_DFX_STATUS14 0xae8
162#define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
163#define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
164 HGC_RXM_DFX_STATUS14_MEM0_OFF)
165#define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
166#define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
167 HGC_RXM_DFX_STATUS14_MEM1_OFF)
168#define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
169#define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
170 HGC_RXM_DFX_STATUS14_MEM2_OFF)
171#define HGC_RXM_DFX_STATUS15 0xaec
172#define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
173#define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
174 HGC_RXM_DFX_STATUS15_MEM3_OFF)
175#define AWQOS_AWCACHE_CFG 0xc84
176#define ARQOS_ARCACHE_CFG 0xc88
177#define HILINK_ERR_DFX 0xe04
178#define SAS_GPIO_CFG_0 0x1000
179#define SAS_GPIO_CFG_1 0x1004
180#define SAS_GPIO_TX_0_1 0x1040
181#define SAS_CFG_DRIVE_VLD 0x1070
182
183
184#define PORT_BASE (0x2000)
185#define PHY_CFG (PORT_BASE + 0x0)
186#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
187#define PHY_CFG_ENA_OFF 0
188#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
189#define PHY_CFG_DC_OPT_OFF 2
190#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
191#define PHY_CFG_PHY_RST_OFF 3
192#define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF)
193#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
194#define CFG_PROG_PHY_LINK_RATE_OFF 0
195#define CFG_PROG_PHY_LINK_RATE_MSK (0xff << CFG_PROG_PHY_LINK_RATE_OFF)
196#define CFG_PROG_OOB_PHY_LINK_RATE_OFF 8
197#define CFG_PROG_OOB_PHY_LINK_RATE_MSK (0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
198#define PHY_CTRL (PORT_BASE + 0x14)
199#define PHY_CTRL_RESET_OFF 0
200#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
201#define CMD_HDR_PIR_OFF 8
202#define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF)
203#define SERDES_CFG (PORT_BASE + 0x1c)
204#define CFG_ALOS_CHK_DISABLE_OFF 9
205#define CFG_ALOS_CHK_DISABLE_MSK (0x1 << CFG_ALOS_CHK_DISABLE_OFF)
206#define SAS_PHY_BIST_CTRL (PORT_BASE + 0x2c)
207#define CFG_BIST_MODE_SEL_OFF 0
208#define CFG_BIST_MODE_SEL_MSK (0xf << CFG_BIST_MODE_SEL_OFF)
209#define CFG_LOOP_TEST_MODE_OFF 14
210#define CFG_LOOP_TEST_MODE_MSK (0x3 << CFG_LOOP_TEST_MODE_OFF)
211#define CFG_RX_BIST_EN_OFF 16
212#define CFG_RX_BIST_EN_MSK (0x1 << CFG_RX_BIST_EN_OFF)
213#define CFG_TX_BIST_EN_OFF 17
214#define CFG_TX_BIST_EN_MSK (0x1 << CFG_TX_BIST_EN_OFF)
215#define CFG_BIST_TEST_OFF 18
216#define CFG_BIST_TEST_MSK (0x1 << CFG_BIST_TEST_OFF)
217#define SAS_PHY_BIST_CODE (PORT_BASE + 0x30)
218#define SAS_PHY_BIST_CODE1 (PORT_BASE + 0x34)
219#define SAS_BIST_ERR_CNT (PORT_BASE + 0x38)
220#define SL_CFG (PORT_BASE + 0x84)
221#define AIP_LIMIT (PORT_BASE + 0x90)
222#define SL_CONTROL (PORT_BASE + 0x94)
223#define SL_CONTROL_NOTIFY_EN_OFF 0
224#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
225#define SL_CTA_OFF 17
226#define SL_CTA_MSK (0x1 << SL_CTA_OFF)
227#define RX_PRIMS_STATUS (PORT_BASE + 0x98)
228#define RX_BCAST_CHG_OFF 1
229#define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
230#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
231#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
232#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
233#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
234#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
235#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
236#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
237#define TXID_AUTO (PORT_BASE + 0xb8)
238#define CT3_OFF 1
239#define CT3_MSK (0x1 << CT3_OFF)
240#define TX_HARDRST_OFF 2
241#define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
242#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
243#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
244#define STP_LINK_TIMER (PORT_BASE + 0x120)
245#define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
246#define CON_CFG_DRIVER (PORT_BASE + 0x130)
247#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
248#define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
249#define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
250#define CHL_INT0 (PORT_BASE + 0x1b4)
251#define CHL_INT0_HOTPLUG_TOUT_OFF 0
252#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
253#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
254#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
255#define CHL_INT0_SL_PHY_ENABLE_OFF 2
256#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
257#define CHL_INT0_NOT_RDY_OFF 4
258#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
259#define CHL_INT0_PHY_RDY_OFF 5
260#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
261#define CHL_INT1 (PORT_BASE + 0x1b8)
262#define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15
263#define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16
264#define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17
265#define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18
266#define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
267#define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
268#define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
269#define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
270#define CHL_INT1_DMAC_TX_FIFO_ERR_OFF 23
271#define CHL_INT1_DMAC_RX_FIFO_ERR_OFF 24
272#define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF 26
273#define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF 27
274#define CHL_INT2 (PORT_BASE + 0x1bc)
275#define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
276#define CHL_INT2_RX_DISP_ERR_OFF 28
277#define CHL_INT2_RX_CODE_ERR_OFF 29
278#define CHL_INT2_RX_INVLD_DW_OFF 30
279#define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
280#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
281#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
282#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
283#define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc)
284#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
285#define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
286#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
287#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
288#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
289#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
290#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
291#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
292#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
293#define DMA_TX_STATUS_BUSY_OFF 0
294#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
295#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
296#define DMA_RX_STATUS_BUSY_OFF 0
297#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
298
299#define COARSETUNE_TIME (PORT_BASE + 0x304)
300#define TXDEEMPH_G1 (PORT_BASE + 0x350)
301#define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
302#define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
303#define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
304#define ERR_CNT_CODE_ERR (PORT_BASE + 0x394)
305#define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
306#define DFX_FIFO_CTRL (PORT_BASE + 0x3a0)
307#define DFX_FIFO_CTRL_TRIGGER_MODE_OFF 0
308#define DFX_FIFO_CTRL_TRIGGER_MODE_MSK (0x7 << DFX_FIFO_CTRL_TRIGGER_MODE_OFF)
309#define DFX_FIFO_CTRL_DUMP_MODE_OFF 3
310#define DFX_FIFO_CTRL_DUMP_MODE_MSK (0x7 << DFX_FIFO_CTRL_DUMP_MODE_OFF)
311#define DFX_FIFO_CTRL_SIGNAL_SEL_OFF 6
312#define DFX_FIFO_CTRL_SIGNAL_SEL_MSK (0xF << DFX_FIFO_CTRL_SIGNAL_SEL_OFF)
313#define DFX_FIFO_CTRL_DUMP_DISABLE_OFF 10
314#define DFX_FIFO_CTRL_DUMP_DISABLE_MSK (0x1 << DFX_FIFO_CTRL_DUMP_DISABLE_OFF)
315#define DFX_FIFO_TRIGGER (PORT_BASE + 0x3a4)
316#define DFX_FIFO_TRIGGER_MSK (PORT_BASE + 0x3a8)
317#define DFX_FIFO_DUMP_MSK (PORT_BASE + 0x3aC)
318#define DFX_FIFO_RD_DATA (PORT_BASE + 0x3b0)
319
320#define DEFAULT_ITCT_HW 2048
321#if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
322#error Max ITCT exceeded
323#endif
324
325#define AXI_MASTER_CFG_BASE (0x5000)
326#define AM_CTRL_GLOBAL (0x0)
327#define AM_CTRL_SHUTDOWN_REQ_OFF 0
328#define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
329#define AM_CURR_TRANS_RETURN (0x150)
330
331#define AM_CFG_MAX_TRANS (0x5010)
332#define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
333#define AXI_CFG (0x5100)
334#define AM_ROB_ECC_ERR_ADDR (0x510c)
335#define AM_ROB_ECC_ERR_ADDR_OFF 0
336#define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff
337
338
339#define RAS_BASE (0x6000)
340#define SAS_RAS_INTR0 (RAS_BASE)
341#define SAS_RAS_INTR1 (RAS_BASE + 0x04)
342#define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
343#define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
344#define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
345#define SAS_RAS_INTR2 (RAS_BASE + 0x20)
346#define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
347
348
349
350
351#define CMD_HDR_ABORT_FLAG_OFF 0
352#define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
353#define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
354#define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
355#define CMD_HDR_RESP_REPORT_OFF 5
356#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
357#define CMD_HDR_TLR_CTRL_OFF 6
358#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
359#define CMD_HDR_PORT_OFF 18
360#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
361#define CMD_HDR_PRIORITY_OFF 27
362#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
363#define CMD_HDR_CMD_OFF 29
364#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
365
366#define CMD_HDR_UNCON_CMD_OFF 3
367#define CMD_HDR_DIR_OFF 5
368#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
369#define CMD_HDR_RESET_OFF 7
370#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
371#define CMD_HDR_VDTL_OFF 10
372#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
373#define CMD_HDR_FRAME_TYPE_OFF 11
374#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
375#define CMD_HDR_DEV_ID_OFF 16
376#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
377
378#define CMD_HDR_CFL_OFF 0
379#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
380#define CMD_HDR_NCQ_TAG_OFF 10
381#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
382#define CMD_HDR_MRFL_OFF 15
383#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
384#define CMD_HDR_SG_MOD_OFF 24
385#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
386
387#define CMD_HDR_IPTT_OFF 0
388#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
389
390#define CMD_HDR_DIF_SGL_LEN_OFF 0
391#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
392#define CMD_HDR_DATA_SGL_LEN_OFF 16
393#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
394
395#define CMD_HDR_ADDR_MODE_SEL_OFF 15
396#define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
397#define CMD_HDR_ABORT_IPTT_OFF 16
398#define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
399
400
401
402#define CMPLT_HDR_CMPLT_OFF 0
403#define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
404#define CMPLT_HDR_ERROR_PHASE_OFF 2
405#define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
406#define CMPLT_HDR_RSPNS_XFRD_OFF 10
407#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
408#define CMPLT_HDR_ERX_OFF 12
409#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
410#define CMPLT_HDR_ABORT_STAT_OFF 13
411#define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
412
413#define STAT_IO_NOT_VALID 0x1
414#define STAT_IO_NO_DEVICE 0x2
415#define STAT_IO_COMPLETE 0x3
416#define STAT_IO_ABORTED 0x4
417
418#define CMPLT_HDR_IPTT_OFF 0
419#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
420#define CMPLT_HDR_DEV_ID_OFF 16
421#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
422
423#define CMPLT_HDR_IO_IN_TARGET_OFF 17
424#define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
425
426
427
428#define ITCT_HDR_DEV_TYPE_OFF 0
429#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
430#define ITCT_HDR_VALID_OFF 2
431#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
432#define ITCT_HDR_MCR_OFF 5
433#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
434#define ITCT_HDR_VLN_OFF 9
435#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
436#define ITCT_HDR_SMP_TIMEOUT_OFF 16
437#define ITCT_HDR_AWT_CONTINUE_OFF 25
438#define ITCT_HDR_PORT_ID_OFF 28
439#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
440
441#define ITCT_HDR_INLT_OFF 0
442#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
443#define ITCT_HDR_RTOLT_OFF 48
444#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
445
446struct hisi_sas_protect_iu_v3_hw {
447 u32 dw0;
448 u32 lbrtcv;
449 u32 lbrtgv;
450 u32 dw3;
451 u32 dw4;
452 u32 dw5;
453 u32 rsv;
454};
455
456struct hisi_sas_complete_v3_hdr {
457 __le32 dw0;
458 __le32 dw1;
459 __le32 act;
460 __le32 dw3;
461};
462
463struct hisi_sas_err_record_v3 {
464
465 __le32 trans_tx_fail_type;
466
467
468 __le32 trans_rx_fail_type;
469
470
471 __le16 dma_tx_err_type;
472 __le16 sipc_rx_err_type;
473
474
475 __le32 dma_rx_err_type;
476};
477
478#define RX_DATA_LEN_UNDERFLOW_OFF 6
479#define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
480
481#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
482#define HISI_SAS_MSI_COUNT_V3_HW 32
483
484#define DIR_NO_DATA 0
485#define DIR_TO_INI 1
486#define DIR_TO_DEVICE 2
487#define DIR_RESERVED 3
488
489#define FIS_CMD_IS_UNCONSTRAINED(fis) \
490 ((fis.command == ATA_CMD_READ_LOG_EXT) || \
491 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
492 ((fis.command == ATA_CMD_DEV_RESET) && \
493 ((fis.control & ATA_SRST) != 0)))
494
495#define T10_INSRT_EN_OFF 0
496#define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF)
497#define T10_RMV_EN_OFF 1
498#define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF)
499#define T10_RPLC_EN_OFF 2
500#define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF)
501#define T10_CHK_EN_OFF 3
502#define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF)
503#define INCR_LBRT_OFF 5
504#define INCR_LBRT_MSK (1 << INCR_LBRT_OFF)
505#define USR_DATA_BLOCK_SZ_OFF 20
506#define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF)
507#define T10_CHK_MSK_OFF 16
508#define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
509#define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)
510
511#define BASE_VECTORS_V3_HW 16
512#define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1)
513
514#define CHNL_INT_STS_MSK 0xeeeeeeee
515#define CHNL_INT_STS_PHY_MSK 0xe
516#define CHNL_INT_STS_INT0_MSK BIT(1)
517#define CHNL_INT_STS_INT1_MSK BIT(2)
518#define CHNL_INT_STS_INT2_MSK BIT(3)
519#define CHNL_WIDTH 4
520
521enum {
522 DSM_FUNC_ERR_HANDLE_MSI = 0,
523};
524
525static bool hisi_sas_intr_conv;
526MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
527
528
529static int prot_mask;
530module_param(prot_mask, int, 0);
531MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
532
533static void debugfs_work_handler_v3_hw(struct work_struct *work);
534static void debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba);
535
536static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
537{
538 void __iomem *regs = hisi_hba->regs + off;
539
540 return readl(regs);
541}
542
543static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
544{
545 void __iomem *regs = hisi_hba->regs + off;
546
547 writel(val, regs);
548}
549
550static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
551 u32 off, u32 val)
552{
553 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
554
555 writel(val, regs);
556}
557
558static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
559 int phy_no, u32 off)
560{
561 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
562
563 return readl(regs);
564}
565
566#define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \
567 timeout_us) \
568({ \
569 void __iomem *regs = hisi_hba->regs + off; \
570 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \
571})
572
573#define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \
574 timeout_us) \
575({ \
576 void __iomem *regs = hisi_hba->regs + off; \
577 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
578})
579
580static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
581{
582 int i, j;
583
584
585 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
586 (u32)((1ULL << hisi_hba->queue_count) - 1));
587 hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);
588 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
589 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
590 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
591 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
592 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
593 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
594 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
595 hisi_sas_intr_conv);
596 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
597 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
598 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
599 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
600 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
601 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
602 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff);
603 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
604 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
605 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
606 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555);
607 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
608 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
609 for (i = 0; i < hisi_hba->queue_count; i++)
610 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);
611
612 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
613
614 for (i = 0; i < hisi_hba->n_phy; i++) {
615 enum sas_linkrate max;
616 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
617 struct asd_sas_phy *sas_phy = &phy->sas_phy;
618 u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, i,
619 PROG_PHY_LINK_RATE);
620
621 prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
622 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
623 SAS_LINK_RATE_1_5_GBPS))
624 max = SAS_LINK_RATE_12_0_GBPS;
625 else
626 max = sas_phy->phy->maximum_linkrate;
627 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
628 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
629 prog_phy_link_rate);
630 hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
631 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
632 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
633 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
634 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
635 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
636 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff);
637 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
638 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
639 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
640 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
641 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
642 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
643 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
644 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
645 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
646 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
647 hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
648 0x30f4240);
649
650 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
651 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
652
653
654 for (j = 0; j < FFE_CFG_MAX; j++) {
655 u32 val = hisi_sas_phy_read32(hisi_hba, i,
656 TXDEEMPH_G1 + (j * 0x4));
657 hisi_hba->debugfs_bist_ffe[i][j] = val;
658 }
659 }
660
661 for (i = 0; i < hisi_hba->queue_count; i++) {
662
663 hisi_sas_write32(hisi_hba,
664 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
665 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
666
667 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
668 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
669
670 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
671 HISI_SAS_QUEUE_SLOTS);
672
673
674 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
675 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
676
677 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
678 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
679
680 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
681 HISI_SAS_QUEUE_SLOTS);
682 }
683
684
685 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
686 lower_32_bits(hisi_hba->itct_dma));
687
688 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
689 upper_32_bits(hisi_hba->itct_dma));
690
691
692 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
693 lower_32_bits(hisi_hba->iost_dma));
694
695 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
696 upper_32_bits(hisi_hba->iost_dma));
697
698
699 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
700 lower_32_bits(hisi_hba->breakpoint_dma));
701
702 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
703 upper_32_bits(hisi_hba->breakpoint_dma));
704
705
706 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
707 lower_32_bits(hisi_hba->sata_breakpoint_dma));
708
709 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
710 upper_32_bits(hisi_hba->sata_breakpoint_dma));
711
712
713 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
714 lower_32_bits(hisi_hba->initial_fis_dma));
715
716 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
717 upper_32_bits(hisi_hba->initial_fis_dma));
718
719
720 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
721 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
722 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
723 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
724
725
726 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
727 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
728 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
729
730 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
731 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
732}
733
734static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
735{
736 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
737
738 cfg &= ~PHY_CFG_DC_OPT_MSK;
739 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
740 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
741}
742
743static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
744{
745 struct sas_identify_frame identify_frame;
746 u32 *identify_buffer;
747
748 memset(&identify_frame, 0, sizeof(identify_frame));
749 identify_frame.dev_type = SAS_END_DEVICE;
750 identify_frame.frame_type = 0;
751 identify_frame._un1 = 1;
752 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
753 identify_frame.target_bits = SAS_PROTOCOL_NONE;
754 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
755 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
756 identify_frame.phy_id = phy_no;
757 identify_buffer = (u32 *)(&identify_frame);
758
759 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
760 __swab32(identify_buffer[0]));
761 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
762 __swab32(identify_buffer[1]));
763 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
764 __swab32(identify_buffer[2]));
765 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
766 __swab32(identify_buffer[3]));
767 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
768 __swab32(identify_buffer[4]));
769 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
770 __swab32(identify_buffer[5]));
771}
772
773static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
774 struct hisi_sas_device *sas_dev)
775{
776 struct domain_device *device = sas_dev->sas_device;
777 struct device *dev = hisi_hba->dev;
778 u64 qw0, device_id = sas_dev->device_id;
779 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
780 struct domain_device *parent_dev = device->parent;
781 struct asd_sas_port *sas_port = device->port;
782 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
783 u64 sas_addr;
784
785 memset(itct, 0, sizeof(*itct));
786
787
788 qw0 = 0;
789 switch (sas_dev->dev_type) {
790 case SAS_END_DEVICE:
791 case SAS_EDGE_EXPANDER_DEVICE:
792 case SAS_FANOUT_EXPANDER_DEVICE:
793 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
794 break;
795 case SAS_SATA_DEV:
796 case SAS_SATA_PENDING:
797 if (parent_dev && dev_is_expander(parent_dev->dev_type))
798 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
799 else
800 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
801 break;
802 default:
803 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
804 sas_dev->dev_type);
805 }
806
807 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
808 (device->linkrate << ITCT_HDR_MCR_OFF) |
809 (1 << ITCT_HDR_VLN_OFF) |
810 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
811 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
812 (port->id << ITCT_HDR_PORT_ID_OFF));
813 itct->qw0 = cpu_to_le64(qw0);
814
815
816 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
817 itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
818
819
820 if (!dev_is_sata(device))
821 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
822 (0x1ULL << ITCT_HDR_RTOLT_OFF));
823}
824
825static int clear_itct_v3_hw(struct hisi_hba *hisi_hba,
826 struct hisi_sas_device *sas_dev)
827{
828 DECLARE_COMPLETION_ONSTACK(completion);
829 u64 dev_id = sas_dev->device_id;
830 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
831 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
832 struct device *dev = hisi_hba->dev;
833
834 sas_dev->completion = &completion;
835
836
837 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
838 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
839 ENT_INT_SRC3_ITC_INT_MSK);
840
841
842 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
843 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
844
845 if (!wait_for_completion_timeout(sas_dev->completion,
846 HISI_SAS_CLEAR_ITCT_TIMEOUT)) {
847 dev_warn(dev, "failed to clear ITCT\n");
848 return -ETIMEDOUT;
849 }
850
851 memset(itct, 0, sizeof(struct hisi_sas_itct));
852 return 0;
853}
854
855static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
856 struct domain_device *device)
857{
858 struct hisi_sas_slot *slot, *slot2;
859 struct hisi_sas_device *sas_dev = device->lldd_dev;
860 u32 cfg_abt_set_query_iptt;
861
862 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
863 CFG_ABT_SET_QUERY_IPTT);
864 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
865 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
866 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
867 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
868 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
869 cfg_abt_set_query_iptt);
870 }
871 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
872 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
873 cfg_abt_set_query_iptt);
874 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
875 1 << CFG_ABT_SET_IPTT_DONE_OFF);
876}
877
878static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
879{
880 struct device *dev = hisi_hba->dev;
881 int ret;
882 u32 val;
883
884 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
885
886
887 hisi_sas_stop_phys(hisi_hba);
888 udelay(50);
889
890
891 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
892 20000, 1000000);
893 if (ret) {
894 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
895 return -EIO;
896 }
897
898 if (ACPI_HANDLE(dev)) {
899 acpi_status s;
900
901 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
902 if (ACPI_FAILURE(s)) {
903 dev_err(dev, "Reset failed\n");
904 return -EIO;
905 }
906 } else {
907 dev_err(dev, "no reset method!\n");
908 return -EINVAL;
909 }
910
911 return 0;
912}
913
914static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
915{
916 struct device *dev = hisi_hba->dev;
917 struct acpi_device *acpi_dev;
918 union acpi_object *obj;
919 guid_t guid;
920 int rc;
921
922 rc = reset_hw_v3_hw(hisi_hba);
923 if (rc) {
924 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
925 return rc;
926 }
927
928 msleep(100);
929 init_reg_v3_hw(hisi_hba);
930
931 if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) {
932 dev_err(dev, "Parse GUID failed\n");
933 return -EINVAL;
934 }
935
936
937
938
939
940
941 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0,
942 DSM_FUNC_ERR_HANDLE_MSI, NULL);
943 if (!obj)
944 dev_warn(dev, "can not find DSM method, ignore\n");
945 else
946 ACPI_FREE(obj);
947
948 acpi_dev = ACPI_COMPANION(dev);
949 if (!acpi_device_power_manageable(acpi_dev))
950 dev_notice(dev, "neither _PS0 nor _PR0 is defined\n");
951 return 0;
952}
953
954static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
955{
956 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
957
958 cfg |= PHY_CFG_ENA_MSK;
959 cfg &= ~PHY_CFG_PHY_RST_MSK;
960 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
961}
962
963static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
964{
965 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
966 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
967 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
968 BIT(CHL_INT2_RX_CODE_ERR_OFF) |
969 BIT(CHL_INT2_RX_INVLD_DW_OFF);
970 u32 state;
971
972 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
973
974 cfg &= ~PHY_CFG_ENA_MSK;
975 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
976
977 mdelay(50);
978
979 state = hisi_sas_read32(hisi_hba, PHY_STATE);
980 if (state & BIT(phy_no)) {
981 cfg |= PHY_CFG_PHY_RST_MSK;
982 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
983 }
984
985 udelay(1);
986
987 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
988 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
989 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
990
991 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
992 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
993}
994
995static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
996{
997 config_id_frame_v3_hw(hisi_hba, phy_no);
998 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
999 enable_phy_v3_hw(hisi_hba, phy_no);
1000}
1001
1002static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1003{
1004 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1005 u32 txid_auto;
1006
1007 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
1008 if (phy->identify.device_type == SAS_END_DEVICE) {
1009 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1010 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1011 txid_auto | TX_HARDRST_MSK);
1012 }
1013 msleep(100);
1014 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
1015}
1016
1017static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
1018{
1019 return SAS_LINK_RATE_12_0_GBPS;
1020}
1021
1022static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
1023{
1024 int i;
1025
1026 for (i = 0; i < hisi_hba->n_phy; i++) {
1027 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1028 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1029
1030 if (!sas_phy->phy->enabled)
1031 continue;
1032
1033 hisi_sas_phy_enable(hisi_hba, i, 1);
1034 }
1035}
1036
1037static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1038{
1039 u32 sl_control;
1040
1041 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1042 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1043 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1044 msleep(1);
1045 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1046 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1047 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1048}
1049
1050static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
1051{
1052 int i, bitmap = 0;
1053 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1054 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1055
1056 for (i = 0; i < hisi_hba->n_phy; i++)
1057 if (phy_state & BIT(i))
1058 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1059 bitmap |= BIT(i);
1060
1061 return bitmap;
1062}
1063
1064static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
1065{
1066 struct hisi_hba *hisi_hba = dq->hisi_hba;
1067 struct hisi_sas_slot *s, *s1, *s2 = NULL;
1068 int dlvry_queue = dq->id;
1069 int wp;
1070
1071 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1072 if (!s->ready)
1073 break;
1074 s2 = s;
1075 list_del(&s->delivery);
1076 }
1077
1078 if (!s2)
1079 return;
1080
1081
1082
1083
1084 smp_rmb();
1085 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1086
1087 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1088}
1089
1090static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
1091 struct hisi_sas_slot *slot,
1092 struct hisi_sas_cmd_hdr *hdr,
1093 struct scatterlist *scatter,
1094 int n_elem)
1095{
1096 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1097 struct scatterlist *sg;
1098 int i;
1099
1100 for_each_sg(scatter, sg, n_elem, i) {
1101 struct hisi_sas_sge *entry = &sge_page->sge[i];
1102
1103 entry->addr = cpu_to_le64(sg_dma_address(sg));
1104 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1105 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1106 entry->data_off = 0;
1107 }
1108
1109 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1110
1111 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1112}
1113
1114static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
1115 struct hisi_sas_slot *slot,
1116 struct hisi_sas_cmd_hdr *hdr,
1117 struct scatterlist *scatter,
1118 int n_elem)
1119{
1120 struct hisi_sas_sge_dif_page *sge_dif_page;
1121 struct scatterlist *sg;
1122 int i;
1123
1124 sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);
1125
1126 for_each_sg(scatter, sg, n_elem, i) {
1127 struct hisi_sas_sge *entry = &sge_dif_page->sge[i];
1128
1129 entry->addr = cpu_to_le64(sg_dma_address(sg));
1130 entry->page_ctrl_0 = 0;
1131 entry->page_ctrl_1 = 0;
1132 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1133 entry->data_off = 0;
1134 }
1135
1136 hdr->dif_prd_table_addr =
1137 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));
1138
1139 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
1140}
1141
1142static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
1143{
1144 unsigned char prot_flags = scsi_cmnd->prot_flags;
1145
1146 if (prot_flags & SCSI_PROT_REF_CHECK)
1147 return T10_CHK_APP_TAG_MSK;
1148 return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
1149}
1150
1151static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
1152 struct hisi_sas_protect_iu_v3_hw *prot)
1153{
1154 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
1155 unsigned int interval = scsi_prot_interval(scsi_cmnd);
1156 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request);
1157
1158 switch (prot_op) {
1159 case SCSI_PROT_READ_INSERT:
1160 prot->dw0 |= T10_INSRT_EN_MSK;
1161 prot->lbrtgv = lbrt_chk_val;
1162 break;
1163 case SCSI_PROT_READ_STRIP:
1164 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1165 prot->lbrtcv = lbrt_chk_val;
1166 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1167 break;
1168 case SCSI_PROT_READ_PASS:
1169 prot->dw0 |= T10_CHK_EN_MSK;
1170 prot->lbrtcv = lbrt_chk_val;
1171 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1172 break;
1173 case SCSI_PROT_WRITE_INSERT:
1174 prot->dw0 |= T10_INSRT_EN_MSK;
1175 prot->lbrtgv = lbrt_chk_val;
1176 break;
1177 case SCSI_PROT_WRITE_STRIP:
1178 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1179 prot->lbrtcv = lbrt_chk_val;
1180 break;
1181 case SCSI_PROT_WRITE_PASS:
1182 prot->dw0 |= T10_CHK_EN_MSK;
1183 prot->lbrtcv = lbrt_chk_val;
1184 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1185 break;
1186 default:
1187 WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
1188 break;
1189 }
1190
1191 switch (interval) {
1192 case 512:
1193 break;
1194 case 4096:
1195 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
1196 break;
1197 case 520:
1198 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
1199 break;
1200 default:
1201 WARN(1, "protection interval (0x%x) invalid\n",
1202 interval);
1203 break;
1204 }
1205
1206 prot->dw0 |= INCR_LBRT_MSK;
1207}
1208
1209static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
1210 struct hisi_sas_slot *slot)
1211{
1212 struct sas_task *task = slot->task;
1213 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1214 struct domain_device *device = task->dev;
1215 struct hisi_sas_device *sas_dev = device->lldd_dev;
1216 struct hisi_sas_port *port = slot->port;
1217 struct sas_ssp_task *ssp_task = &task->ssp_task;
1218 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1219 struct hisi_sas_tmf_task *tmf = slot->tmf;
1220 int has_data = 0, priority = !!tmf;
1221 unsigned char prot_op;
1222 u8 *buf_cmd;
1223 u32 dw1 = 0, dw2 = 0, len = 0;
1224
1225 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1226 (2 << CMD_HDR_TLR_CTRL_OFF) |
1227 (port->id << CMD_HDR_PORT_OFF) |
1228 (priority << CMD_HDR_PRIORITY_OFF) |
1229 (1 << CMD_HDR_CMD_OFF));
1230
1231 dw1 = 1 << CMD_HDR_VDTL_OFF;
1232 if (tmf) {
1233 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1234 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1235 } else {
1236 prot_op = scsi_get_prot_op(scsi_cmnd);
1237 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1238 switch (scsi_cmnd->sc_data_direction) {
1239 case DMA_TO_DEVICE:
1240 has_data = 1;
1241 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1242 break;
1243 case DMA_FROM_DEVICE:
1244 has_data = 1;
1245 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1246 break;
1247 default:
1248 dw1 &= ~CMD_HDR_DIR_MSK;
1249 }
1250 }
1251
1252
1253 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1254
1255 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1256 + 3) / 4) << CMD_HDR_CFL_OFF) |
1257 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1258 (2 << CMD_HDR_SG_MOD_OFF);
1259 hdr->dw2 = cpu_to_le32(dw2);
1260 hdr->transfer_tags = cpu_to_le32(slot->idx);
1261
1262 if (has_data) {
1263 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1264 slot->n_elem);
1265
1266 if (scsi_prot_sg_count(scsi_cmnd))
1267 prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
1268 scsi_prot_sglist(scsi_cmnd),
1269 slot->n_elem_dif);
1270 }
1271
1272 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1273 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1274
1275 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1276 sizeof(struct ssp_frame_hdr);
1277
1278 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1279 if (!tmf) {
1280 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
1281 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
1282 } else {
1283 buf_cmd[10] = tmf->tmf;
1284 switch (tmf->tmf) {
1285 case TMF_ABORT_TASK:
1286 case TMF_QUERY_TASK:
1287 buf_cmd[12] =
1288 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1289 buf_cmd[13] =
1290 tmf->tag_of_task_to_be_managed & 0xff;
1291 break;
1292 default:
1293 break;
1294 }
1295 }
1296
1297 if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
1298 struct hisi_sas_protect_iu_v3_hw prot;
1299 u8 *buf_cmd_prot;
1300
1301 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
1302 dw1 |= CMD_HDR_PIR_MSK;
1303 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
1304 sizeof(struct ssp_frame_hdr) +
1305 sizeof(struct ssp_command_iu);
1306
1307 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
1308 fill_prot_v3_hw(scsi_cmnd, &prot);
1309 memcpy(buf_cmd_prot, &prot,
1310 sizeof(struct hisi_sas_protect_iu_v3_hw));
1311
1312
1313
1314
1315 if (prot_op == SCSI_PROT_WRITE_INSERT ||
1316 prot_op == SCSI_PROT_READ_INSERT ||
1317 prot_op == SCSI_PROT_WRITE_PASS ||
1318 prot_op == SCSI_PROT_READ_PASS) {
1319 unsigned int interval = scsi_prot_interval(scsi_cmnd);
1320 unsigned int ilog2_interval = ilog2(interval);
1321
1322 len = (task->total_xfer_len >> ilog2_interval) * 8;
1323 }
1324 }
1325
1326 hdr->dw1 = cpu_to_le32(dw1);
1327
1328 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
1329}
1330
1331static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1332 struct hisi_sas_slot *slot)
1333{
1334 struct sas_task *task = slot->task;
1335 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1336 struct domain_device *device = task->dev;
1337 struct hisi_sas_port *port = slot->port;
1338 struct scatterlist *sg_req;
1339 struct hisi_sas_device *sas_dev = device->lldd_dev;
1340 dma_addr_t req_dma_addr;
1341 unsigned int req_len;
1342
1343
1344 sg_req = &task->smp_task.smp_req;
1345 req_len = sg_dma_len(sg_req);
1346 req_dma_addr = sg_dma_address(sg_req);
1347
1348
1349
1350 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1351 (1 << CMD_HDR_PRIORITY_OFF) |
1352 (2 << CMD_HDR_CMD_OFF));
1353
1354
1355 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1356 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1357 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1358
1359
1360 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1361 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1362 CMD_HDR_MRFL_OFF));
1363
1364 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1365
1366 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1367 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1368}
1369
1370static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1371 struct hisi_sas_slot *slot)
1372{
1373 struct sas_task *task = slot->task;
1374 struct domain_device *device = task->dev;
1375 struct domain_device *parent_dev = device->parent;
1376 struct hisi_sas_device *sas_dev = device->lldd_dev;
1377 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1378 struct asd_sas_port *sas_port = device->port;
1379 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1380 u8 *buf_cmd;
1381 int has_data = 0, hdr_tag = 0;
1382 u32 dw1 = 0, dw2 = 0;
1383
1384 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1385 if (parent_dev && dev_is_expander(parent_dev->dev_type))
1386 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1387 else
1388 hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
1389
1390 switch (task->data_dir) {
1391 case DMA_TO_DEVICE:
1392 has_data = 1;
1393 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1394 break;
1395 case DMA_FROM_DEVICE:
1396 has_data = 1;
1397 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1398 break;
1399 default:
1400 dw1 &= ~CMD_HDR_DIR_MSK;
1401 }
1402
1403 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1404 (task->ata_task.fis.control & ATA_SRST))
1405 dw1 |= 1 << CMD_HDR_RESET_OFF;
1406
1407 dw1 |= (hisi_sas_get_ata_protocol(
1408 &task->ata_task.fis, task->data_dir))
1409 << CMD_HDR_FRAME_TYPE_OFF;
1410 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1411
1412 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1413 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1414
1415 hdr->dw1 = cpu_to_le32(dw1);
1416
1417
1418 if (task->ata_task.use_ncq) {
1419 struct ata_queued_cmd *qc = task->uldd_task;
1420
1421 hdr_tag = qc->tag;
1422 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1423 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1424 }
1425
1426 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1427 2 << CMD_HDR_SG_MOD_OFF;
1428 hdr->dw2 = cpu_to_le32(dw2);
1429
1430
1431 hdr->transfer_tags = cpu_to_le32(slot->idx);
1432
1433 if (has_data)
1434 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1435 slot->n_elem);
1436
1437 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1438 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1439 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1440
1441 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1442
1443 if (likely(!task->ata_task.device_control_reg_update))
1444 task->ata_task.fis.flags |= 0x80;
1445
1446 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1447}
1448
1449static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1450 struct hisi_sas_slot *slot,
1451 int device_id, int abort_flag, int tag_to_abort)
1452{
1453 struct sas_task *task = slot->task;
1454 struct domain_device *dev = task->dev;
1455 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1456 struct hisi_sas_port *port = slot->port;
1457
1458
1459 hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) |
1460 (port->id << CMD_HDR_PORT_OFF) |
1461 (dev_is_sata(dev)
1462 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1463 (abort_flag
1464 << CMD_HDR_ABORT_FLAG_OFF));
1465
1466
1467 hdr->dw1 = cpu_to_le32(device_id
1468 << CMD_HDR_DEV_ID_OFF);
1469
1470
1471 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1472 hdr->transfer_tags = cpu_to_le32(slot->idx);
1473}
1474
1475static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1476{
1477 int i;
1478 irqreturn_t res;
1479 u32 context, port_id, link_rate;
1480 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1481 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1482 struct device *dev = hisi_hba->dev;
1483 unsigned long flags;
1484
1485 del_timer(&phy->timer);
1486 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1487
1488 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1489 port_id = (port_id >> (4 * phy_no)) & 0xf;
1490 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1491 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1492
1493 if (port_id == 0xf) {
1494 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1495 res = IRQ_NONE;
1496 goto end;
1497 }
1498 sas_phy->linkrate = link_rate;
1499 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1500
1501
1502 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1503 if (context & (1 << phy_no)) {
1504 struct hisi_sas_initial_fis *initial_fis;
1505 struct dev_to_host_fis *fis;
1506 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1507 struct Scsi_Host *shost = hisi_hba->shost;
1508
1509 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1510 initial_fis = &hisi_hba->initial_fis[phy_no];
1511 fis = &initial_fis->fis;
1512
1513
1514 if (fis->status & ATA_ERR) {
1515 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1516 phy_no, fis->status);
1517 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1518 res = IRQ_NONE;
1519 goto end;
1520 }
1521
1522 sas_phy->oob_mode = SATA_OOB_MODE;
1523 attached_sas_addr[0] = 0x50;
1524 attached_sas_addr[6] = shost->host_no;
1525 attached_sas_addr[7] = phy_no;
1526 memcpy(sas_phy->attached_sas_addr,
1527 attached_sas_addr,
1528 SAS_ADDR_SIZE);
1529 memcpy(sas_phy->frame_rcvd, fis,
1530 sizeof(struct dev_to_host_fis));
1531 phy->phy_type |= PORT_TYPE_SATA;
1532 phy->identify.device_type = SAS_SATA_DEV;
1533 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1534 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1535 } else {
1536 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1537 struct sas_identify_frame *id =
1538 (struct sas_identify_frame *)frame_rcvd;
1539
1540 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1541 for (i = 0; i < 6; i++) {
1542 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1543 RX_IDAF_DWORD0 + (i * 4));
1544 frame_rcvd[i] = __swab32(idaf);
1545 }
1546 sas_phy->oob_mode = SAS_OOB_MODE;
1547 memcpy(sas_phy->attached_sas_addr,
1548 &id->sas_addr,
1549 SAS_ADDR_SIZE);
1550 phy->phy_type |= PORT_TYPE_SAS;
1551 phy->identify.device_type = id->dev_type;
1552 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1553 if (phy->identify.device_type == SAS_END_DEVICE)
1554 phy->identify.target_port_protocols =
1555 SAS_PROTOCOL_SSP;
1556 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1557 phy->identify.target_port_protocols =
1558 SAS_PROTOCOL_SMP;
1559 }
1560
1561 phy->port_id = port_id;
1562 phy->phy_attached = 1;
1563 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1564 res = IRQ_HANDLED;
1565 spin_lock_irqsave(&phy->lock, flags);
1566 if (phy->reset_completion) {
1567 phy->in_reset = 0;
1568 complete(phy->reset_completion);
1569 }
1570 spin_unlock_irqrestore(&phy->lock, flags);
1571end:
1572 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1573 CHL_INT0_SL_PHY_ENABLE_MSK);
1574 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1575
1576 return res;
1577}
1578
1579static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1580{
1581 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1582 u32 phy_state, sl_ctrl, txid_auto;
1583 struct device *dev = hisi_hba->dev;
1584
1585 atomic_inc(&phy->down_cnt);
1586
1587 del_timer(&phy->timer);
1588 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1589
1590 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1591 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1592 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0,
1593 GFP_ATOMIC);
1594
1595 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1596 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1597 sl_ctrl&(~SL_CTA_MSK));
1598
1599 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1600 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1601 txid_auto | CT3_MSK);
1602
1603 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1604 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1605
1606 return IRQ_HANDLED;
1607}
1608
1609static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1610{
1611 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1612 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1613 u32 bcast_status;
1614
1615 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1616 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1617 if ((bcast_status & RX_BCAST_CHG_MSK) &&
1618 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
1619 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
1620 GFP_ATOMIC);
1621 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1622 CHL_INT0_SL_RX_BCST_ACK_MSK);
1623 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1624
1625 return IRQ_HANDLED;
1626}
1627
1628static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1629{
1630 struct hisi_hba *hisi_hba = p;
1631 u32 irq_msk;
1632 int phy_no = 0;
1633 irqreturn_t res = IRQ_NONE;
1634
1635 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1636 & 0x11111111;
1637 while (irq_msk) {
1638 if (irq_msk & 1) {
1639 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1640 CHL_INT0);
1641 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1642 int rdy = phy_state & (1 << phy_no);
1643
1644 if (rdy) {
1645 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1646
1647 if (phy_up_v3_hw(phy_no, hisi_hba)
1648 == IRQ_HANDLED)
1649 res = IRQ_HANDLED;
1650 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1651
1652 if (phy_bcast_v3_hw(phy_no, hisi_hba)
1653 == IRQ_HANDLED)
1654 res = IRQ_HANDLED;
1655 } else {
1656 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1657
1658 if (phy_down_v3_hw(phy_no, hisi_hba)
1659 == IRQ_HANDLED)
1660 res = IRQ_HANDLED;
1661 }
1662 }
1663 irq_msk >>= 4;
1664 phy_no++;
1665 }
1666
1667 return res;
1668}
1669
1670static const struct hisi_sas_hw_error port_axi_error[] = {
1671 {
1672 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF),
1673 .msg = "dmac_tx_ecc_bad_err",
1674 },
1675 {
1676 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF),
1677 .msg = "dmac_rx_ecc_bad_err",
1678 },
1679 {
1680 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1681 .msg = "dma_tx_axi_wr_err",
1682 },
1683 {
1684 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1685 .msg = "dma_tx_axi_rd_err",
1686 },
1687 {
1688 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1689 .msg = "dma_rx_axi_wr_err",
1690 },
1691 {
1692 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1693 .msg = "dma_rx_axi_rd_err",
1694 },
1695 {
1696 .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF),
1697 .msg = "dma_tx_fifo_err",
1698 },
1699 {
1700 .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF),
1701 .msg = "dma_rx_fifo_err",
1702 },
1703 {
1704 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF),
1705 .msg = "dma_tx_axi_ruser_err",
1706 },
1707 {
1708 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF),
1709 .msg = "dma_rx_axi_ruser_err",
1710 },
1711};
1712
1713static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1714{
1715 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1716 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1717 struct device *dev = hisi_hba->dev;
1718 int i;
1719
1720 irq_value &= ~irq_msk;
1721 if (!irq_value) {
1722 dev_warn(dev, "phy%d channel int 1 received with status bits cleared\n",
1723 phy_no);
1724 return;
1725 }
1726
1727 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1728 const struct hisi_sas_hw_error *error = &port_axi_error[i];
1729
1730 if (!(irq_value & error->irq_msk))
1731 continue;
1732
1733 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1734 error->msg, phy_no, irq_value);
1735 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1736 }
1737
1738 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1739}
1740
1741static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1742{
1743 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1744 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1745 struct sas_phy *sphy = sas_phy->phy;
1746 unsigned long flags;
1747 u32 reg_value;
1748
1749 spin_lock_irqsave(&phy->lock, flags);
1750
1751
1752 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1753 sphy->loss_of_dword_sync_count += reg_value;
1754
1755
1756 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1757 sphy->phy_reset_problem_count += reg_value;
1758
1759
1760 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1761 sphy->invalid_dword_count += reg_value;
1762
1763
1764 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1765 sphy->running_disparity_error_count += reg_value;
1766
1767
1768 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1769 phy->code_violation_err_count += reg_value;
1770
1771 spin_unlock_irqrestore(&phy->lock, flags);
1772}
1773
1774static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1775{
1776 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1777 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1778 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1779 struct pci_dev *pci_dev = hisi_hba->pci_dev;
1780 struct device *dev = hisi_hba->dev;
1781 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1782 BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1783 BIT(CHL_INT2_RX_INVLD_DW_OFF);
1784
1785 irq_value &= ~irq_msk;
1786 if (!irq_value) {
1787 dev_warn(dev, "phy%d channel int 2 received with status bits cleared\n",
1788 phy_no);
1789 return;
1790 }
1791
1792 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1793 dev_warn(dev, "phy%d identify timeout\n", phy_no);
1794 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1795 }
1796
1797 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1798 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1799 STP_LINK_TIMEOUT_STATE);
1800
1801 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1802 phy_no, reg_value);
1803 if (reg_value & BIT(4))
1804 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1805 }
1806
1807 if (pci_dev->revision > 0x20 && (irq_value & msk)) {
1808 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1809 struct sas_phy *sphy = sas_phy->phy;
1810
1811 phy_get_events_v3_hw(hisi_hba, phy_no);
1812
1813 if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
1814 dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no,
1815 sphy->invalid_dword_count);
1816
1817 if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
1818 dev_info(dev, "phy%d code violation cnt: %u\n", phy_no,
1819 phy->code_violation_err_count);
1820
1821 if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
1822 dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
1823 sphy->running_disparity_error_count);
1824 }
1825
1826 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1827 (pci_dev->revision == 0x20)) {
1828 u32 reg_value;
1829 int rc;
1830
1831 rc = hisi_sas_read32_poll_timeout_atomic(
1832 HILINK_ERR_DFX, reg_value,
1833 !((reg_value >> 8) & BIT(phy_no)),
1834 1000, 10000);
1835 if (rc)
1836 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1837 }
1838
1839 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1840}
1841
1842static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1843{
1844 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1845
1846 if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
1847 hisi_sas_phy_oob_ready(hisi_hba, phy_no);
1848
1849 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1850 irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1851 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1852 & (~CHL_INT0_NOT_RDY_MSK));
1853}
1854
1855static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1856{
1857 struct hisi_hba *hisi_hba = p;
1858 u32 irq_msk;
1859 int phy_no = 0;
1860
1861 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1862 & CHNL_INT_STS_MSK;
1863
1864 while (irq_msk) {
1865 if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
1866 handle_chl_int0_v3_hw(hisi_hba, phy_no);
1867
1868 if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
1869 handle_chl_int1_v3_hw(hisi_hba, phy_no);
1870
1871 if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
1872 handle_chl_int2_v3_hw(hisi_hba, phy_no);
1873
1874 irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
1875 phy_no++;
1876 }
1877
1878 return IRQ_HANDLED;
1879}
1880
1881static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
1882 {
1883 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
1884 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
1885 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
1886 .msg = "hgc_dqe_eccbad_intr",
1887 .reg = HGC_DQE_ECC_ADDR,
1888 },
1889 {
1890 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
1891 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
1892 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
1893 .msg = "hgc_iost_eccbad_intr",
1894 .reg = HGC_IOST_ECC_ADDR,
1895 },
1896 {
1897 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
1898 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
1899 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
1900 .msg = "hgc_itct_eccbad_intr",
1901 .reg = HGC_ITCT_ECC_ADDR,
1902 },
1903 {
1904 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
1905 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
1906 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
1907 .msg = "hgc_iostl_eccbad_intr",
1908 .reg = HGC_LM_DFX_STATUS2,
1909 },
1910 {
1911 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
1912 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
1913 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
1914 .msg = "hgc_itctl_eccbad_intr",
1915 .reg = HGC_LM_DFX_STATUS2,
1916 },
1917 {
1918 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
1919 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
1920 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
1921 .msg = "hgc_cqe_eccbad_intr",
1922 .reg = HGC_CQE_ECC_ADDR,
1923 },
1924 {
1925 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
1926 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
1927 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
1928 .msg = "rxm_mem0_eccbad_intr",
1929 .reg = HGC_RXM_DFX_STATUS14,
1930 },
1931 {
1932 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
1933 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
1934 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
1935 .msg = "rxm_mem1_eccbad_intr",
1936 .reg = HGC_RXM_DFX_STATUS14,
1937 },
1938 {
1939 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
1940 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
1941 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
1942 .msg = "rxm_mem2_eccbad_intr",
1943 .reg = HGC_RXM_DFX_STATUS14,
1944 },
1945 {
1946 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
1947 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
1948 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
1949 .msg = "rxm_mem3_eccbad_intr",
1950 .reg = HGC_RXM_DFX_STATUS15,
1951 },
1952 {
1953 .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF),
1954 .msk = AM_ROB_ECC_ERR_ADDR_MSK,
1955 .shift = AM_ROB_ECC_ERR_ADDR_OFF,
1956 .msg = "ooo_ram_eccbad_intr",
1957 .reg = AM_ROB_ECC_ERR_ADDR,
1958 },
1959};
1960
1961static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
1962 u32 irq_value)
1963{
1964 struct device *dev = hisi_hba->dev;
1965 const struct hisi_sas_hw_error *ecc_error;
1966 u32 val;
1967 int i;
1968
1969 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
1970 ecc_error = &multi_bit_ecc_errors[i];
1971 if (irq_value & ecc_error->irq_msk) {
1972 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
1973 val &= ecc_error->msk;
1974 val >>= ecc_error->shift;
1975 dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
1976 ecc_error->msg, irq_value, val);
1977 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1978 }
1979 }
1980}
1981
1982static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba)
1983{
1984 u32 irq_value, irq_msk;
1985
1986 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
1987 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1988
1989 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
1990 if (irq_value)
1991 multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
1992
1993 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
1994 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
1995}
1996
1997static const struct hisi_sas_hw_error axi_error[] = {
1998 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1999 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
2000 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
2001 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
2002 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
2003 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
2004 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
2005 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
2006 {}
2007};
2008
2009static const struct hisi_sas_hw_error fifo_error[] = {
2010 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
2011 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
2012 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
2013 { .msk = BIT(11), .msg = "CMDP_FIFO" },
2014 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
2015 {}
2016};
2017
2018static const struct hisi_sas_hw_error fatal_axi_error[] = {
2019 {
2020 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
2021 .msg = "write pointer and depth",
2022 },
2023 {
2024 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
2025 .msg = "iptt no match slot",
2026 },
2027 {
2028 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2029 .msg = "read pointer and depth",
2030 },
2031 {
2032 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2033 .reg = HGC_AXI_FIFO_ERR_INFO,
2034 .sub = axi_error,
2035 },
2036 {
2037 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2038 .reg = HGC_AXI_FIFO_ERR_INFO,
2039 .sub = fifo_error,
2040 },
2041 {
2042 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2043 .msg = "LM add/fetch list",
2044 },
2045 {
2046 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2047 .msg = "SAS_HGC_ABT fetch LM list",
2048 },
2049 {
2050 .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF),
2051 .msg = "read dqe poison",
2052 },
2053 {
2054 .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF),
2055 .msg = "read iost poison",
2056 },
2057 {
2058 .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF),
2059 .msg = "read itct poison",
2060 },
2061 {
2062 .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF),
2063 .msg = "read itct ncq poison",
2064 },
2065
2066};
2067
2068static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
2069{
2070 u32 irq_value, irq_msk;
2071 struct hisi_hba *hisi_hba = p;
2072 struct device *dev = hisi_hba->dev;
2073 struct pci_dev *pdev = hisi_hba->pci_dev;
2074 int i;
2075
2076 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2077 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
2078
2079 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2080 irq_value &= ~irq_msk;
2081
2082 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
2083 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
2084
2085 if (!(irq_value & error->irq_msk))
2086 continue;
2087
2088 if (error->sub) {
2089 const struct hisi_sas_hw_error *sub = error->sub;
2090 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
2091
2092 for (; sub->msk || sub->msg; sub++) {
2093 if (!(err_value & sub->msk))
2094 continue;
2095
2096 dev_err(dev, "%s error (0x%x) found!\n",
2097 sub->msg, irq_value);
2098 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2099 }
2100 } else {
2101 dev_err(dev, "%s error (0x%x) found!\n",
2102 error->msg, irq_value);
2103 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2104 }
2105
2106 if (pdev->revision < 0x21) {
2107 u32 reg_val;
2108
2109 reg_val = hisi_sas_read32(hisi_hba,
2110 AXI_MASTER_CFG_BASE +
2111 AM_CTRL_GLOBAL);
2112 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2113 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2114 AM_CTRL_GLOBAL, reg_val);
2115 }
2116 }
2117
2118 fatal_ecc_int_v3_hw(hisi_hba);
2119
2120 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
2121 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
2122 u32 dev_id = reg_val & ITCT_DEV_MSK;
2123 struct hisi_sas_device *sas_dev =
2124 &hisi_hba->devices[dev_id];
2125
2126 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
2127 dev_dbg(dev, "clear ITCT ok\n");
2128 complete(sas_dev->completion);
2129 }
2130
2131 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
2132 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
2133
2134 return IRQ_HANDLED;
2135}
2136
2137static void
2138slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
2139 struct hisi_sas_slot *slot)
2140{
2141 struct task_status_struct *ts = &task->task_status;
2142 struct hisi_sas_complete_v3_hdr *complete_queue =
2143 hisi_hba->complete_hdr[slot->cmplt_queue];
2144 struct hisi_sas_complete_v3_hdr *complete_hdr =
2145 &complete_queue[slot->cmplt_queue_slot];
2146 struct hisi_sas_err_record_v3 *record =
2147 hisi_sas_status_buf_addr_mem(slot);
2148 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
2149 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
2150 u32 dw3 = le32_to_cpu(complete_hdr->dw3);
2151
2152 switch (task->task_proto) {
2153 case SAS_PROTOCOL_SSP:
2154 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2155 ts->residual = trans_tx_fail_type;
2156 ts->stat = SAS_DATA_UNDERRUN;
2157 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2158 ts->stat = SAS_QUEUE_FULL;
2159 slot->abort = 1;
2160 } else {
2161 ts->stat = SAS_OPEN_REJECT;
2162 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2163 }
2164 break;
2165 case SAS_PROTOCOL_SATA:
2166 case SAS_PROTOCOL_STP:
2167 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2168 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2169 ts->residual = trans_tx_fail_type;
2170 ts->stat = SAS_DATA_UNDERRUN;
2171 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2172 ts->stat = SAS_PHY_DOWN;
2173 slot->abort = 1;
2174 } else {
2175 ts->stat = SAS_OPEN_REJECT;
2176 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2177 }
2178 hisi_sas_sata_done(task, slot);
2179 break;
2180 case SAS_PROTOCOL_SMP:
2181 ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2182 break;
2183 default:
2184 break;
2185 }
2186}
2187
2188static void slot_complete_v3_hw(struct hisi_hba *hisi_hba,
2189 struct hisi_sas_slot *slot)
2190{
2191 struct sas_task *task = slot->task;
2192 struct hisi_sas_device *sas_dev;
2193 struct device *dev = hisi_hba->dev;
2194 struct task_status_struct *ts;
2195 struct domain_device *device;
2196 struct sas_ha_struct *ha;
2197 struct hisi_sas_complete_v3_hdr *complete_queue =
2198 hisi_hba->complete_hdr[slot->cmplt_queue];
2199 struct hisi_sas_complete_v3_hdr *complete_hdr =
2200 &complete_queue[slot->cmplt_queue_slot];
2201 unsigned long flags;
2202 bool is_internal = slot->is_internal;
2203 u32 dw0, dw1, dw3;
2204
2205 if (unlikely(!task || !task->lldd_task || !task->dev))
2206 return;
2207
2208 ts = &task->task_status;
2209 device = task->dev;
2210 ha = device->port->ha;
2211 sas_dev = device->lldd_dev;
2212
2213 spin_lock_irqsave(&task->task_state_lock, flags);
2214 task->task_state_flags &=
2215 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2216 spin_unlock_irqrestore(&task->task_state_lock, flags);
2217
2218 memset(ts, 0, sizeof(*ts));
2219 ts->resp = SAS_TASK_COMPLETE;
2220
2221 if (unlikely(!sas_dev)) {
2222 dev_dbg(dev, "slot complete: port has not device\n");
2223 ts->stat = SAS_PHY_DOWN;
2224 goto out;
2225 }
2226
2227 dw0 = le32_to_cpu(complete_hdr->dw0);
2228 dw1 = le32_to_cpu(complete_hdr->dw1);
2229 dw3 = le32_to_cpu(complete_hdr->dw3);
2230
2231
2232
2233
2234 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
2235 case STAT_IO_ABORTED:
2236
2237 ts->stat = SAS_ABORTED_TASK;
2238 goto out;
2239 case STAT_IO_COMPLETE:
2240
2241 ts->stat = TMF_RESP_FUNC_SUCC;
2242 goto out;
2243 case STAT_IO_NO_DEVICE:
2244 ts->stat = TMF_RESP_FUNC_COMPLETE;
2245 goto out;
2246 case STAT_IO_NOT_VALID:
2247
2248
2249
2250 ts->stat = TMF_RESP_FUNC_FAILED;
2251 goto out;
2252 default:
2253 break;
2254 }
2255
2256
2257 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
2258 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2259
2260 slot_err_v3_hw(hisi_hba, task, slot);
2261 if (ts->stat != SAS_DATA_UNDERRUN)
2262 dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d addr=%016llx CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2263 slot->idx, task, sas_dev->device_id,
2264 SAS_ADDR(device->sas_addr),
2265 dw0, dw1, complete_hdr->act, dw3,
2266 error_info[0], error_info[1],
2267 error_info[2], error_info[3]);
2268 if (unlikely(slot->abort)) {
2269 sas_task_abort(task);
2270 return;
2271 }
2272 goto out;
2273 }
2274
2275 switch (task->task_proto) {
2276 case SAS_PROTOCOL_SSP: {
2277 struct ssp_response_iu *iu =
2278 hisi_sas_status_buf_addr_mem(slot) +
2279 sizeof(struct hisi_sas_err_record);
2280
2281 sas_ssp_task_response(dev, task, iu);
2282 break;
2283 }
2284 case SAS_PROTOCOL_SMP: {
2285 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2286 void *to = page_address(sg_page(sg_resp));
2287
2288 ts->stat = SAS_SAM_STAT_GOOD;
2289
2290 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2291 DMA_TO_DEVICE);
2292 memcpy(to + sg_resp->offset,
2293 hisi_sas_status_buf_addr_mem(slot) +
2294 sizeof(struct hisi_sas_err_record),
2295 sg_resp->length);
2296 break;
2297 }
2298 case SAS_PROTOCOL_SATA:
2299 case SAS_PROTOCOL_STP:
2300 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2301 ts->stat = SAS_SAM_STAT_GOOD;
2302 hisi_sas_sata_done(task, slot);
2303 break;
2304 default:
2305 ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2306 break;
2307 }
2308
2309 if (!slot->port->port_attached) {
2310 dev_warn(dev, "slot complete: port %d has removed\n",
2311 slot->port->sas_port.id);
2312 ts->stat = SAS_PHY_DOWN;
2313 }
2314
2315out:
2316 spin_lock_irqsave(&task->task_state_lock, flags);
2317 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2318 spin_unlock_irqrestore(&task->task_state_lock, flags);
2319 dev_info(dev, "slot complete: task(%pK) aborted\n", task);
2320 return;
2321 }
2322 task->task_state_flags |= SAS_TASK_STATE_DONE;
2323 spin_unlock_irqrestore(&task->task_state_lock, flags);
2324 hisi_sas_slot_task_free(hisi_hba, task, slot);
2325
2326 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2327 spin_lock_irqsave(&device->done_lock, flags);
2328 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2329 spin_unlock_irqrestore(&device->done_lock, flags);
2330 dev_info(dev, "slot complete: task(%pK) ignored\n ",
2331 task);
2332 return;
2333 }
2334 spin_unlock_irqrestore(&device->done_lock, flags);
2335 }
2336
2337 if (task->task_done)
2338 task->task_done(task);
2339}
2340
2341static irqreturn_t cq_thread_v3_hw(int irq_no, void *p)
2342{
2343 struct hisi_sas_cq *cq = p;
2344 struct hisi_hba *hisi_hba = cq->hisi_hba;
2345 struct hisi_sas_slot *slot;
2346 struct hisi_sas_complete_v3_hdr *complete_queue;
2347 u32 rd_point = cq->rd_point, wr_point;
2348 int queue = cq->id;
2349
2350 complete_queue = hisi_hba->complete_hdr[queue];
2351
2352 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2353 (0x14 * queue));
2354
2355 while (rd_point != wr_point) {
2356 struct hisi_sas_complete_v3_hdr *complete_hdr;
2357 struct device *dev = hisi_hba->dev;
2358 u32 dw1;
2359 int iptt;
2360
2361 complete_hdr = &complete_queue[rd_point];
2362 dw1 = le32_to_cpu(complete_hdr->dw1);
2363
2364 iptt = dw1 & CMPLT_HDR_IPTT_MSK;
2365 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
2366 slot = &hisi_hba->slot_info[iptt];
2367 slot->cmplt_queue_slot = rd_point;
2368 slot->cmplt_queue = queue;
2369 slot_complete_v3_hw(hisi_hba, slot);
2370 } else
2371 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
2372
2373 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2374 rd_point = 0;
2375 }
2376
2377
2378 cq->rd_point = rd_point;
2379 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2380
2381 return IRQ_HANDLED;
2382}
2383
2384static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
2385{
2386 struct hisi_sas_cq *cq = p;
2387 struct hisi_hba *hisi_hba = cq->hisi_hba;
2388 int queue = cq->id;
2389
2390 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2391
2392 return IRQ_WAKE_THREAD;
2393}
2394
2395static int interrupt_preinit_v3_hw(struct hisi_hba *hisi_hba)
2396{
2397 int vectors;
2398 int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi;
2399 struct Scsi_Host *shost = hisi_hba->shost;
2400 struct irq_affinity desc = {
2401 .pre_vectors = BASE_VECTORS_V3_HW,
2402 };
2403
2404 min_msi = MIN_AFFINE_VECTORS_V3_HW;
2405 vectors = pci_alloc_irq_vectors_affinity(hisi_hba->pci_dev,
2406 min_msi, max_msi,
2407 PCI_IRQ_MSI |
2408 PCI_IRQ_AFFINITY,
2409 &desc);
2410 if (vectors < 0)
2411 return -ENOENT;
2412
2413
2414 hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW;
2415 shost->nr_hw_queues = hisi_hba->cq_nvecs;
2416
2417 return 0;
2418}
2419
2420static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
2421{
2422 struct device *dev = hisi_hba->dev;
2423 struct pci_dev *pdev = hisi_hba->pci_dev;
2424 int rc, i;
2425
2426 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
2427 int_phy_up_down_bcast_v3_hw, 0,
2428 DRV_NAME " phy", hisi_hba);
2429 if (rc) {
2430 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
2431 return -ENOENT;
2432 }
2433
2434 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
2435 int_chnl_int_v3_hw, 0,
2436 DRV_NAME " channel", hisi_hba);
2437 if (rc) {
2438 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
2439 return -ENOENT;
2440 }
2441
2442 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
2443 fatal_axi_int_v3_hw, 0,
2444 DRV_NAME " fatal", hisi_hba);
2445 if (rc) {
2446 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
2447 return -ENOENT;
2448 }
2449
2450 if (hisi_sas_intr_conv)
2451 dev_info(dev, "Enable interrupt converge\n");
2452
2453 for (i = 0; i < hisi_hba->cq_nvecs; i++) {
2454 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2455 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2456 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
2457 IRQF_ONESHOT;
2458
2459 cq->irq_no = pci_irq_vector(pdev, nr);
2460 rc = devm_request_threaded_irq(dev, cq->irq_no,
2461 cq_interrupt_v3_hw,
2462 cq_thread_v3_hw,
2463 irqflags,
2464 DRV_NAME " cq", cq);
2465 if (rc) {
2466 dev_err(dev, "could not request cq%d interrupt, rc=%d\n",
2467 i, rc);
2468 return -ENOENT;
2469 }
2470 cq->irq_mask = pci_irq_get_affinity(pdev, i + BASE_VECTORS_V3_HW);
2471 if (!cq->irq_mask) {
2472 dev_err(dev, "could not get cq%d irq affinity!\n", i);
2473 return -ENOENT;
2474 }
2475 }
2476
2477 return 0;
2478}
2479
2480static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
2481{
2482 int rc;
2483
2484 rc = hw_init_v3_hw(hisi_hba);
2485 if (rc)
2486 return rc;
2487
2488 rc = interrupt_init_v3_hw(hisi_hba);
2489 if (rc)
2490 return rc;
2491
2492 return 0;
2493}
2494
2495static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
2496 struct sas_phy_linkrates *r)
2497{
2498 enum sas_linkrate max = r->maximum_linkrate;
2499 u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no,
2500 PROG_PHY_LINK_RATE);
2501
2502 prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
2503 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
2504 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
2505 prog_phy_link_rate);
2506}
2507
2508static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
2509{
2510 struct pci_dev *pdev = hisi_hba->pci_dev;
2511 int i;
2512
2513 synchronize_irq(pci_irq_vector(pdev, 1));
2514 synchronize_irq(pci_irq_vector(pdev, 2));
2515 synchronize_irq(pci_irq_vector(pdev, 11));
2516 for (i = 0; i < hisi_hba->queue_count; i++)
2517 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
2518
2519 for (i = 0; i < hisi_hba->cq_nvecs; i++)
2520 synchronize_irq(pci_irq_vector(pdev, i + 16));
2521
2522 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
2523 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
2524 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
2525 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2526
2527 for (i = 0; i < hisi_hba->n_phy; i++) {
2528 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
2529 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
2530 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
2531 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
2532 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
2533 }
2534}
2535
2536static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
2537{
2538 return hisi_sas_read32(hisi_hba, PHY_STATE);
2539}
2540
2541static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2542{
2543 struct device *dev = hisi_hba->dev;
2544 u32 status, reg_val;
2545 int rc;
2546
2547 interrupt_disable_v3_hw(hisi_hba);
2548 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2549
2550 hisi_sas_stop_phys(hisi_hba);
2551
2552 mdelay(10);
2553
2554 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2555 AM_CTRL_GLOBAL);
2556 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2557 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2558 AM_CTRL_GLOBAL, reg_val);
2559
2560
2561 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2562 AM_CURR_TRANS_RETURN, status,
2563 status == 0x3, 10, 100);
2564 if (rc) {
2565 dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2566 return rc;
2567 }
2568
2569 return 0;
2570}
2571
2572static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2573{
2574 struct device *dev = hisi_hba->dev;
2575 int rc;
2576
2577 rc = disable_host_v3_hw(hisi_hba);
2578 if (rc) {
2579 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2580 return rc;
2581 }
2582
2583 hisi_sas_init_mem(hisi_hba);
2584
2585 return hw_init_v3_hw(hisi_hba);
2586}
2587
2588static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2589 u8 reg_index, u8 reg_count, u8 *write_data)
2590{
2591 struct device *dev = hisi_hba->dev;
2592 u32 *data = (u32 *)write_data;
2593 int i;
2594
2595 switch (reg_type) {
2596 case SAS_GPIO_REG_TX:
2597 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2598 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2599 reg_index, reg_index + reg_count - 1);
2600 return -EINVAL;
2601 }
2602
2603 for (i = 0; i < reg_count; i++)
2604 hisi_sas_write32(hisi_hba,
2605 SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2606 data[i]);
2607 break;
2608 default:
2609 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2610 reg_type);
2611 return -EINVAL;
2612 }
2613
2614 return 0;
2615}
2616
2617static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2618 int delay_ms, int timeout_ms)
2619{
2620 struct device *dev = hisi_hba->dev;
2621 int entries, entries_old = 0, time;
2622
2623 for (time = 0; time < timeout_ms; time += delay_ms) {
2624 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2625 if (entries == entries_old)
2626 break;
2627
2628 entries_old = entries;
2629 msleep(delay_ms);
2630 }
2631
2632 if (time >= timeout_ms) {
2633 dev_dbg(dev, "Wait commands complete timeout!\n");
2634 return;
2635 }
2636
2637 dev_dbg(dev, "wait commands complete %dms\n", time);
2638}
2639
2640static ssize_t intr_conv_v3_hw_show(struct device *dev,
2641 struct device_attribute *attr, char *buf)
2642{
2643 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
2644}
2645static DEVICE_ATTR_RO(intr_conv_v3_hw);
2646
2647static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
2648{
2649
2650 hisi_sas_stop_phys(hisi_hba);
2651
2652 if (hisi_hba->intr_coal_ticks == 0 ||
2653 hisi_hba->intr_coal_count == 0) {
2654 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
2655 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
2656 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
2657 } else {
2658 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
2659 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
2660 hisi_hba->intr_coal_ticks);
2661 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
2662 hisi_hba->intr_coal_count);
2663 }
2664 phys_init_v3_hw(hisi_hba);
2665}
2666
2667static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
2668 struct device_attribute *attr,
2669 char *buf)
2670{
2671 struct Scsi_Host *shost = class_to_shost(dev);
2672 struct hisi_hba *hisi_hba = shost_priv(shost);
2673
2674 return scnprintf(buf, PAGE_SIZE, "%u\n",
2675 hisi_hba->intr_coal_ticks);
2676}
2677
2678static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
2679 struct device_attribute *attr,
2680 const char *buf, size_t count)
2681{
2682 struct Scsi_Host *shost = class_to_shost(dev);
2683 struct hisi_hba *hisi_hba = shost_priv(shost);
2684 u32 intr_coal_ticks;
2685 int ret;
2686
2687 ret = kstrtou32(buf, 10, &intr_coal_ticks);
2688 if (ret) {
2689 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2690 return -EINVAL;
2691 }
2692
2693 if (intr_coal_ticks >= BIT(24)) {
2694 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
2695 return -EINVAL;
2696 }
2697
2698 hisi_hba->intr_coal_ticks = intr_coal_ticks;
2699
2700 config_intr_coal_v3_hw(hisi_hba);
2701
2702 return count;
2703}
2704static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
2705
2706static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
2707 struct device_attribute
2708 *attr, char *buf)
2709{
2710 struct Scsi_Host *shost = class_to_shost(dev);
2711 struct hisi_hba *hisi_hba = shost_priv(shost);
2712
2713 return scnprintf(buf, PAGE_SIZE, "%u\n",
2714 hisi_hba->intr_coal_count);
2715}
2716
2717static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
2718 struct device_attribute
2719 *attr, const char *buf, size_t count)
2720{
2721 struct Scsi_Host *shost = class_to_shost(dev);
2722 struct hisi_hba *hisi_hba = shost_priv(shost);
2723 u32 intr_coal_count;
2724 int ret;
2725
2726 ret = kstrtou32(buf, 10, &intr_coal_count);
2727 if (ret) {
2728 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2729 return -EINVAL;
2730 }
2731
2732 if (intr_coal_count >= BIT(8)) {
2733 dev_err(dev, "intr_coal_count must be less than 2^8!\n");
2734 return -EINVAL;
2735 }
2736
2737 hisi_hba->intr_coal_count = intr_coal_count;
2738
2739 config_intr_coal_v3_hw(hisi_hba);
2740
2741 return count;
2742}
2743static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
2744
2745static int slave_configure_v3_hw(struct scsi_device *sdev)
2746{
2747 struct Scsi_Host *shost = dev_to_shost(&sdev->sdev_gendev);
2748 struct domain_device *ddev = sdev_to_domain_dev(sdev);
2749 struct hisi_hba *hisi_hba = shost_priv(shost);
2750 struct device *dev = hisi_hba->dev;
2751 int ret = sas_slave_configure(sdev);
2752
2753 if (ret)
2754 return ret;
2755 if (!dev_is_sata(ddev))
2756 sas_change_queue_depth(sdev, 64);
2757
2758 if (sdev->type == TYPE_ENCLOSURE)
2759 return 0;
2760
2761 if (!device_link_add(&sdev->sdev_gendev, dev,
2762 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE)) {
2763 if (pm_runtime_enabled(dev)) {
2764 dev_info(dev, "add device link failed, disable runtime PM for the host\n");
2765 pm_runtime_disable(dev);
2766 }
2767 }
2768
2769 return 0;
2770}
2771
2772static struct device_attribute *host_attrs_v3_hw[] = {
2773 &dev_attr_phy_event_threshold,
2774 &dev_attr_intr_conv_v3_hw,
2775 &dev_attr_intr_coal_ticks_v3_hw,
2776 &dev_attr_intr_coal_count_v3_hw,
2777 NULL
2778};
2779
2780#define HISI_SAS_DEBUGFS_REG(x) {#x, x}
2781
2782struct hisi_sas_debugfs_reg_lu {
2783 char *name;
2784 int off;
2785};
2786
2787struct hisi_sas_debugfs_reg {
2788 const struct hisi_sas_debugfs_reg_lu *lu;
2789 int count;
2790 int base_off;
2791};
2792
2793static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
2794 HISI_SAS_DEBUGFS_REG(PHY_CFG),
2795 HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
2796 HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
2797 HISI_SAS_DEBUGFS_REG(PHY_CTRL),
2798 HISI_SAS_DEBUGFS_REG(SL_CFG),
2799 HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
2800 HISI_SAS_DEBUGFS_REG(SL_CONTROL),
2801 HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
2802 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
2803 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
2804 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
2805 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
2806 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
2807 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
2808 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
2809 HISI_SAS_DEBUGFS_REG(TXID_AUTO),
2810 HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
2811 HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
2812 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
2813 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
2814 HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
2815 HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
2816 HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
2817 HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
2818 HISI_SAS_DEBUGFS_REG(CHL_INT0),
2819 HISI_SAS_DEBUGFS_REG(CHL_INT1),
2820 HISI_SAS_DEBUGFS_REG(CHL_INT2),
2821 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
2822 HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
2823 HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
2824 HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
2825 HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
2826 HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
2827 HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
2828 HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
2829 HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
2830 HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
2831 HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
2832 HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
2833 HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
2834 HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
2835 HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
2836 HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
2837 HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
2838 HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
2839 HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
2840 HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
2841 {}
2842};
2843
2844static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
2845 .lu = debugfs_port_reg_lu,
2846 .count = 0x100,
2847 .base_off = PORT_BASE,
2848};
2849
2850static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
2851 HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
2852 HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
2853 HISI_SAS_DEBUGFS_REG(PHY_STATE),
2854 HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
2855 HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
2856 HISI_SAS_DEBUGFS_REG(ITCT_CLR),
2857 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
2858 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
2859 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
2860 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
2861 HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
2862 HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
2863 HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
2864 HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
2865 HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
2866 HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
2867 HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
2868 HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
2869 HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
2870 HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
2871 HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
2872 HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
2873 HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
2874 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
2875 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
2876 HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
2877 HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
2878 HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
2879 HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
2880 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
2881 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
2882 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
2883 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
2884 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
2885 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
2886 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
2887 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
2888 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
2889 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
2890 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
2891 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
2892 HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
2893 HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
2894 HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
2895 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
2896 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
2897 HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
2898 HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
2899 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
2900 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
2901 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
2902 HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
2903 HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
2904 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
2905 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
2906 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
2907 HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
2908 HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
2909 HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
2910 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
2911 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
2912 HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
2913 HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
2914 {}
2915};
2916
2917static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
2918 .lu = debugfs_global_reg_lu,
2919 .count = 0x800,
2920};
2921
2922static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
2923 HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS),
2924 HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS),
2925 HISI_SAS_DEBUGFS_REG(AXI_CFG),
2926 HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR),
2927 {}
2928};
2929
2930static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
2931 .lu = debugfs_axi_reg_lu,
2932 .count = 0x61,
2933 .base_off = AXI_MASTER_CFG_BASE,
2934};
2935
2936static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
2937 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0),
2938 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1),
2939 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK),
2940 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK),
2941 HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK),
2942 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2),
2943 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK),
2944 {}
2945};
2946
2947static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
2948 .lu = debugfs_ras_reg_lu,
2949 .count = 0x10,
2950 .base_off = RAS_BASE,
2951};
2952
2953static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
2954{
2955 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2956
2957 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
2958
2959 wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000);
2960
2961 hisi_sas_sync_irqs(hisi_hba);
2962}
2963
2964static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
2965{
2966 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
2967 (u32)((1ULL << hisi_hba->queue_count) - 1));
2968
2969 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2970}
2971
2972static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
2973 enum hisi_sas_debugfs_cache_type type,
2974 u32 *cache)
2975{
2976 u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ *
2977 HISI_SAS_IOST_ITCT_CACHE_NUM;
2978 struct device *dev = hisi_hba->dev;
2979 u32 *buf = cache;
2980 u32 i, val;
2981
2982 hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type);
2983
2984 for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) {
2985 val = hisi_sas_read32(hisi_hba, TAB_DFX);
2986 if (val == 0xffffffff)
2987 break;
2988 }
2989
2990 if (val != 0xffffffff) {
2991 dev_err(dev, "Issue occurred in reading IOST/ITCT cache!\n");
2992 return;
2993 }
2994
2995 memset(buf, 0, cache_dw_size * 4);
2996 buf[0] = val;
2997
2998 for (i = 1; i < cache_dw_size; i++)
2999 buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX);
3000}
3001
3002static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
3003{
3004 u32 reg_val;
3005 int phy_no = hisi_hba->debugfs_bist_phy_no;
3006 int i;
3007
3008
3009 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
3010
3011
3012 for (i = 0; i < FFE_CFG_MAX; i++)
3013 hisi_sas_phy_write32(hisi_hba, phy_no, TXDEEMPH_G1 + (i * 0x4),
3014 hisi_hba->debugfs_bist_ffe[phy_no][i]);
3015
3016
3017 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3018 reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
3019 hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3020}
3021
3022static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
3023{
3024 u32 reg_val;
3025 int phy_no = hisi_hba->debugfs_bist_phy_no;
3026
3027
3028 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);
3029 reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3030 CFG_BIST_TEST_MSK);
3031 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val);
3032
3033
3034 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3035 reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
3036 hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3037
3038
3039 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
3040
3041 reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3042 reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3043 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);
3044
3045
3046 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
3047}
3048
3049#define SAS_PHY_BIST_CODE_INIT 0x1
3050#define SAS_PHY_BIST_CODE1_INIT 0X80
3051static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
3052{
3053 u32 reg_val, mode_tmp;
3054 u32 linkrate = hisi_hba->debugfs_bist_linkrate;
3055 u32 phy_no = hisi_hba->debugfs_bist_phy_no;
3056 u32 *ffe = hisi_hba->debugfs_bist_ffe[phy_no];
3057 u32 code_mode = hisi_hba->debugfs_bist_code_mode;
3058 u32 path_mode = hisi_hba->debugfs_bist_mode;
3059 u32 *fix_code = &hisi_hba->debugfs_bist_fixed_code[0];
3060 struct device *dev = hisi_hba->dev;
3061
3062 dev_info(dev, "BIST info:phy%d link_rate=%d code_mode=%d path_mode=%d ffe={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x} fixed_code={0x%x, 0x%x}\n",
3063 phy_no, linkrate, code_mode, path_mode,
3064 ffe[FFE_SAS_1_5_GBPS], ffe[FFE_SAS_3_0_GBPS],
3065 ffe[FFE_SAS_6_0_GBPS], ffe[FFE_SAS_12_0_GBPS],
3066 ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS],
3067 ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE],
3068 fix_code[FIXED_CODE_1]);
3069 mode_tmp = path_mode ? 2 : 1;
3070 if (enable) {
3071
3072 hisi_sas_bist_test_prep_v3_hw(hisi_hba);
3073
3074
3075 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3076 PROG_PHY_LINK_RATE);
3077 reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3078 reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3079 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
3080 reg_val);
3081
3082
3083 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3084 SAS_PHY_BIST_CTRL);
3085 reg_val &= ~(CFG_BIST_MODE_SEL_MSK | CFG_LOOP_TEST_MODE_MSK |
3086 CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3087 CFG_BIST_TEST_MSK);
3088 reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
3089 (mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
3090 CFG_BIST_TEST_MSK);
3091 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3092 reg_val);
3093
3094
3095 if (code_mode == HISI_SAS_BIST_CODE_MODE_FIXED_DATA) {
3096 reg_val = hisi_hba->debugfs_bist_fixed_code[0];
3097 hisi_sas_phy_write32(hisi_hba, phy_no,
3098 SAS_PHY_BIST_CODE, reg_val);
3099
3100 reg_val = hisi_hba->debugfs_bist_fixed_code[1];
3101 hisi_sas_phy_write32(hisi_hba, phy_no,
3102 SAS_PHY_BIST_CODE1, reg_val);
3103 } else {
3104 hisi_sas_phy_write32(hisi_hba, phy_no,
3105 SAS_PHY_BIST_CODE,
3106 SAS_PHY_BIST_CODE_INIT);
3107 hisi_sas_phy_write32(hisi_hba, phy_no,
3108 SAS_PHY_BIST_CODE1,
3109 SAS_PHY_BIST_CODE1_INIT);
3110 }
3111
3112 mdelay(100);
3113 reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
3114 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3115 reg_val);
3116
3117
3118 mdelay(100);
3119 hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
3120 } else {
3121
3122 hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
3123 phy_no, SAS_BIST_ERR_CNT);
3124 hisi_sas_bist_test_restore_v3_hw(hisi_hba);
3125 }
3126
3127 return 0;
3128}
3129
3130static int hisi_sas_map_queues(struct Scsi_Host *shost)
3131{
3132 struct hisi_hba *hisi_hba = shost_priv(shost);
3133 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
3134
3135 return blk_mq_pci_map_queues(qmap, hisi_hba->pci_dev,
3136 BASE_VECTORS_V3_HW);
3137}
3138
3139static struct scsi_host_template sht_v3_hw = {
3140 .name = DRV_NAME,
3141 .proc_name = DRV_NAME,
3142 .module = THIS_MODULE,
3143 .queuecommand = sas_queuecommand,
3144 .dma_need_drain = ata_scsi_dma_need_drain,
3145 .target_alloc = sas_target_alloc,
3146 .slave_configure = slave_configure_v3_hw,
3147 .scan_finished = hisi_sas_scan_finished,
3148 .scan_start = hisi_sas_scan_start,
3149 .map_queues = hisi_sas_map_queues,
3150 .change_queue_depth = sas_change_queue_depth,
3151 .bios_param = sas_bios_param,
3152 .this_id = -1,
3153 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT,
3154 .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT,
3155 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
3156 .eh_device_reset_handler = sas_eh_device_reset_handler,
3157 .eh_target_reset_handler = sas_eh_target_reset_handler,
3158 .slave_alloc = sas_slave_alloc,
3159 .target_destroy = sas_target_destroy,
3160 .ioctl = sas_ioctl,
3161#ifdef CONFIG_COMPAT
3162 .compat_ioctl = sas_ioctl,
3163#endif
3164 .shost_attrs = host_attrs_v3_hw,
3165 .tag_alloc_policy = BLK_TAG_ALLOC_RR,
3166 .host_reset = hisi_sas_host_reset,
3167 .host_tagset = 1,
3168};
3169
3170static const struct hisi_sas_hw hisi_sas_v3_hw = {
3171 .setup_itct = setup_itct_v3_hw,
3172 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
3173 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
3174 .clear_itct = clear_itct_v3_hw,
3175 .sl_notify_ssp = sl_notify_ssp_v3_hw,
3176 .prep_ssp = prep_ssp_v3_hw,
3177 .prep_smp = prep_smp_v3_hw,
3178 .prep_stp = prep_ata_v3_hw,
3179 .prep_abort = prep_abort_v3_hw,
3180 .start_delivery = start_delivery_v3_hw,
3181 .phys_init = phys_init_v3_hw,
3182 .phy_start = start_phy_v3_hw,
3183 .phy_disable = disable_phy_v3_hw,
3184 .phy_hard_reset = phy_hard_reset_v3_hw,
3185 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
3186 .phy_set_linkrate = phy_set_linkrate_v3_hw,
3187 .dereg_device = dereg_device_v3_hw,
3188 .soft_reset = soft_reset_v3_hw,
3189 .get_phys_state = get_phys_state_v3_hw,
3190 .get_events = phy_get_events_v3_hw,
3191 .write_gpio = write_gpio_v3_hw,
3192 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
3193 .debugfs_snapshot_regs = debugfs_snapshot_regs_v3_hw,
3194};
3195
3196static struct Scsi_Host *
3197hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
3198{
3199 struct Scsi_Host *shost;
3200 struct hisi_hba *hisi_hba;
3201 struct device *dev = &pdev->dev;
3202
3203 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
3204 if (!shost) {
3205 dev_err(dev, "shost alloc failed\n");
3206 return NULL;
3207 }
3208 hisi_hba = shost_priv(shost);
3209
3210 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
3211 INIT_WORK(&hisi_hba->debugfs_work, debugfs_work_handler_v3_hw);
3212 hisi_hba->hw = &hisi_sas_v3_hw;
3213 hisi_hba->pci_dev = pdev;
3214 hisi_hba->dev = dev;
3215 hisi_hba->shost = shost;
3216 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
3217
3218 if (prot_mask & ~HISI_SAS_PROT_MASK)
3219 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
3220 prot_mask);
3221 else
3222 hisi_hba->prot_mask = prot_mask;
3223
3224 if (hisi_sas_get_fw_info(hisi_hba) < 0)
3225 goto err_out;
3226
3227 if (hisi_sas_alloc(hisi_hba)) {
3228 hisi_sas_free(hisi_hba);
3229 goto err_out;
3230 }
3231
3232 return shost;
3233err_out:
3234 scsi_host_put(shost);
3235 dev_err(dev, "shost alloc failed\n");
3236 return NULL;
3237}
3238
3239static void debugfs_snapshot_cq_reg_v3_hw(struct hisi_hba *hisi_hba)
3240{
3241 int queue_entry_size = hisi_hba->hw->complete_hdr_size;
3242 int dump_index = hisi_hba->debugfs_dump_index;
3243 int i;
3244
3245 for (i = 0; i < hisi_hba->queue_count; i++)
3246 memcpy(hisi_hba->debugfs_cq[dump_index][i].complete_hdr,
3247 hisi_hba->complete_hdr[i],
3248 HISI_SAS_QUEUE_SLOTS * queue_entry_size);
3249}
3250
3251static void debugfs_snapshot_dq_reg_v3_hw(struct hisi_hba *hisi_hba)
3252{
3253 int queue_entry_size = sizeof(struct hisi_sas_cmd_hdr);
3254 int dump_index = hisi_hba->debugfs_dump_index;
3255 int i;
3256
3257 for (i = 0; i < hisi_hba->queue_count; i++) {
3258 struct hisi_sas_cmd_hdr *debugfs_cmd_hdr, *cmd_hdr;
3259 int j;
3260
3261 debugfs_cmd_hdr = hisi_hba->debugfs_dq[dump_index][i].hdr;
3262 cmd_hdr = hisi_hba->cmd_hdr[i];
3263
3264 for (j = 0; j < HISI_SAS_QUEUE_SLOTS; j++)
3265 memcpy(&debugfs_cmd_hdr[j], &cmd_hdr[j],
3266 queue_entry_size);
3267 }
3268}
3269
3270static void debugfs_snapshot_port_reg_v3_hw(struct hisi_hba *hisi_hba)
3271{
3272 int dump_index = hisi_hba->debugfs_dump_index;
3273 const struct hisi_sas_debugfs_reg *port = &debugfs_port_reg;
3274 int i, phy_cnt;
3275 u32 offset;
3276 u32 *databuf;
3277
3278 for (phy_cnt = 0; phy_cnt < hisi_hba->n_phy; phy_cnt++) {
3279 databuf = hisi_hba->debugfs_port_reg[dump_index][phy_cnt].data;
3280 for (i = 0; i < port->count; i++, databuf++) {
3281 offset = port->base_off + 4 * i;
3282 *databuf = hisi_sas_phy_read32(hisi_hba, phy_cnt,
3283 offset);
3284 }
3285 }
3286}
3287
3288static void debugfs_snapshot_global_reg_v3_hw(struct hisi_hba *hisi_hba)
3289{
3290 int dump_index = hisi_hba->debugfs_dump_index;
3291 u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL].data;
3292 int i;
3293
3294 for (i = 0; i < debugfs_axi_reg.count; i++, databuf++)
3295 *databuf = hisi_sas_read32(hisi_hba, 4 * i);
3296}
3297
3298static void debugfs_snapshot_axi_reg_v3_hw(struct hisi_hba *hisi_hba)
3299{
3300 int dump_index = hisi_hba->debugfs_dump_index;
3301 u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI].data;
3302 const struct hisi_sas_debugfs_reg *axi = &debugfs_axi_reg;
3303 int i;
3304
3305 for (i = 0; i < axi->count; i++, databuf++)
3306 *databuf = hisi_sas_read32(hisi_hba, 4 * i + axi->base_off);
3307}
3308
3309static void debugfs_snapshot_ras_reg_v3_hw(struct hisi_hba *hisi_hba)
3310{
3311 int dump_index = hisi_hba->debugfs_dump_index;
3312 u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS].data;
3313 const struct hisi_sas_debugfs_reg *ras = &debugfs_ras_reg;
3314 int i;
3315
3316 for (i = 0; i < ras->count; i++, databuf++)
3317 *databuf = hisi_sas_read32(hisi_hba, 4 * i + ras->base_off);
3318}
3319
3320static void debugfs_snapshot_itct_reg_v3_hw(struct hisi_hba *hisi_hba)
3321{
3322 int dump_index = hisi_hba->debugfs_dump_index;
3323 void *cachebuf = hisi_hba->debugfs_itct_cache[dump_index].cache;
3324 void *databuf = hisi_hba->debugfs_itct[dump_index].itct;
3325 struct hisi_sas_itct *itct;
3326 int i;
3327
3328 read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_ITCT_CACHE, cachebuf);
3329
3330 itct = hisi_hba->itct;
3331
3332 for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3333 memcpy(databuf, itct, sizeof(struct hisi_sas_itct));
3334 databuf += sizeof(struct hisi_sas_itct);
3335 }
3336}
3337
3338static void debugfs_snapshot_iost_reg_v3_hw(struct hisi_hba *hisi_hba)
3339{
3340 int dump_index = hisi_hba->debugfs_dump_index;
3341 int max_command_entries = HISI_SAS_MAX_COMMANDS;
3342 void *cachebuf = hisi_hba->debugfs_iost_cache[dump_index].cache;
3343 void *databuf = hisi_hba->debugfs_iost[dump_index].iost;
3344 struct hisi_sas_iost *iost;
3345 int i;
3346
3347 read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_IOST_CACHE, cachebuf);
3348
3349 iost = hisi_hba->iost;
3350
3351 for (i = 0; i < max_command_entries; i++, iost++) {
3352 memcpy(databuf, iost, sizeof(struct hisi_sas_iost));
3353 databuf += sizeof(struct hisi_sas_iost);
3354 }
3355}
3356
3357static const char *
3358debugfs_to_reg_name_v3_hw(int off, int base_off,
3359 const struct hisi_sas_debugfs_reg_lu *lu)
3360{
3361 for (; lu->name; lu++) {
3362 if (off == lu->off - base_off)
3363 return lu->name;
3364 }
3365
3366 return NULL;
3367}
3368
3369static void debugfs_print_reg_v3_hw(u32 *regs_val, struct seq_file *s,
3370 const struct hisi_sas_debugfs_reg *reg)
3371{
3372 int i;
3373
3374 for (i = 0; i < reg->count; i++) {
3375 int off = i * 4;
3376 const char *name;
3377
3378 name = debugfs_to_reg_name_v3_hw(off, reg->base_off,
3379 reg->lu);
3380
3381 if (name)
3382 seq_printf(s, "0x%08x 0x%08x %s\n", off,
3383 regs_val[i], name);
3384 else
3385 seq_printf(s, "0x%08x 0x%08x\n", off,
3386 regs_val[i]);
3387 }
3388}
3389
3390static int debugfs_global_v3_hw_show(struct seq_file *s, void *p)
3391{
3392 struct hisi_sas_debugfs_regs *global = s->private;
3393
3394 debugfs_print_reg_v3_hw(global->data, s,
3395 &debugfs_global_reg);
3396
3397 return 0;
3398}
3399DEFINE_SHOW_ATTRIBUTE(debugfs_global_v3_hw);
3400
3401static int debugfs_axi_v3_hw_show(struct seq_file *s, void *p)
3402{
3403 struct hisi_sas_debugfs_regs *axi = s->private;
3404
3405 debugfs_print_reg_v3_hw(axi->data, s,
3406 &debugfs_axi_reg);
3407
3408 return 0;
3409}
3410DEFINE_SHOW_ATTRIBUTE(debugfs_axi_v3_hw);
3411
3412static int debugfs_ras_v3_hw_show(struct seq_file *s, void *p)
3413{
3414 struct hisi_sas_debugfs_regs *ras = s->private;
3415
3416 debugfs_print_reg_v3_hw(ras->data, s,
3417 &debugfs_ras_reg);
3418
3419 return 0;
3420}
3421DEFINE_SHOW_ATTRIBUTE(debugfs_ras_v3_hw);
3422
3423static int debugfs_port_v3_hw_show(struct seq_file *s, void *p)
3424{
3425 struct hisi_sas_debugfs_port *port = s->private;
3426 const struct hisi_sas_debugfs_reg *reg_port = &debugfs_port_reg;
3427
3428 debugfs_print_reg_v3_hw(port->data, s, reg_port);
3429
3430 return 0;
3431}
3432DEFINE_SHOW_ATTRIBUTE(debugfs_port_v3_hw);
3433
3434static void debugfs_show_row_64_v3_hw(struct seq_file *s, int index,
3435 int sz, __le64 *ptr)
3436{
3437 int i;
3438
3439
3440 seq_printf(s, "index %04d:\n\t", index);
3441 for (i = 1; i <= sz / 8; i++, ptr++) {
3442 seq_printf(s, " 0x%016llx", le64_to_cpu(*ptr));
3443 if (!(i % 2))
3444 seq_puts(s, "\n\t");
3445 }
3446
3447 seq_puts(s, "\n");
3448}
3449
3450static void debugfs_show_row_32_v3_hw(struct seq_file *s, int index,
3451 int sz, __le32 *ptr)
3452{
3453 int i;
3454
3455
3456 seq_printf(s, "index %04d:\n\t", index);
3457 for (i = 1; i <= sz / 4; i++, ptr++) {
3458 seq_printf(s, " 0x%08x", le32_to_cpu(*ptr));
3459 if (!(i % 4))
3460 seq_puts(s, "\n\t");
3461 }
3462 seq_puts(s, "\n");
3463}
3464
3465static void debugfs_cq_show_slot_v3_hw(struct seq_file *s, int slot,
3466 struct hisi_sas_debugfs_cq *debugfs_cq)
3467{
3468 struct hisi_sas_cq *cq = debugfs_cq->cq;
3469 struct hisi_hba *hisi_hba = cq->hisi_hba;
3470 __le32 *complete_hdr = debugfs_cq->complete_hdr +
3471 (hisi_hba->hw->complete_hdr_size * slot);
3472
3473 debugfs_show_row_32_v3_hw(s, slot,
3474 hisi_hba->hw->complete_hdr_size,
3475 complete_hdr);
3476}
3477
3478static int debugfs_cq_v3_hw_show(struct seq_file *s, void *p)
3479{
3480 struct hisi_sas_debugfs_cq *debugfs_cq = s->private;
3481 int slot;
3482
3483 for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3484 debugfs_cq_show_slot_v3_hw(s, slot, debugfs_cq);
3485
3486 return 0;
3487}
3488DEFINE_SHOW_ATTRIBUTE(debugfs_cq_v3_hw);
3489
3490static void debugfs_dq_show_slot_v3_hw(struct seq_file *s, int slot,
3491 void *dq_ptr)
3492{
3493 struct hisi_sas_debugfs_dq *debugfs_dq = dq_ptr;
3494 void *cmd_queue = debugfs_dq->hdr;
3495 __le32 *cmd_hdr = cmd_queue +
3496 sizeof(struct hisi_sas_cmd_hdr) * slot;
3497
3498 debugfs_show_row_32_v3_hw(s, slot, sizeof(struct hisi_sas_cmd_hdr),
3499 cmd_hdr);
3500}
3501
3502static int debugfs_dq_v3_hw_show(struct seq_file *s, void *p)
3503{
3504 int slot;
3505
3506 for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3507 debugfs_dq_show_slot_v3_hw(s, slot, s->private);
3508
3509 return 0;
3510}
3511DEFINE_SHOW_ATTRIBUTE(debugfs_dq_v3_hw);
3512
3513static int debugfs_iost_v3_hw_show(struct seq_file *s, void *p)
3514{
3515 struct hisi_sas_debugfs_iost *debugfs_iost = s->private;
3516 struct hisi_sas_iost *iost = debugfs_iost->iost;
3517 int i, max_command_entries = HISI_SAS_MAX_COMMANDS;
3518
3519 for (i = 0; i < max_command_entries; i++, iost++) {
3520 __le64 *data = &iost->qw0;
3521
3522 debugfs_show_row_64_v3_hw(s, i, sizeof(*iost), data);
3523 }
3524
3525 return 0;
3526}
3527DEFINE_SHOW_ATTRIBUTE(debugfs_iost_v3_hw);
3528
3529static int debugfs_iost_cache_v3_hw_show(struct seq_file *s, void *p)
3530{
3531 struct hisi_sas_debugfs_iost_cache *debugfs_iost_cache = s->private;
3532 struct hisi_sas_iost_itct_cache *iost_cache =
3533 debugfs_iost_cache->cache;
3534 u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
3535 int i, tab_idx;
3536 __le64 *iost;
3537
3538 for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, iost_cache++) {
3539
3540
3541
3542
3543
3544
3545 tab_idx = (iost_cache->data[1] & 0xffff);
3546 iost = (__le64 *)iost_cache;
3547
3548 debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, iost);
3549 }
3550
3551 return 0;
3552}
3553DEFINE_SHOW_ATTRIBUTE(debugfs_iost_cache_v3_hw);
3554
3555static int debugfs_itct_v3_hw_show(struct seq_file *s, void *p)
3556{
3557 int i;
3558 struct hisi_sas_debugfs_itct *debugfs_itct = s->private;
3559 struct hisi_sas_itct *itct = debugfs_itct->itct;
3560
3561 for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3562 __le64 *data = &itct->qw0;
3563
3564 debugfs_show_row_64_v3_hw(s, i, sizeof(*itct), data);
3565 }
3566
3567 return 0;
3568}
3569DEFINE_SHOW_ATTRIBUTE(debugfs_itct_v3_hw);
3570
3571static int debugfs_itct_cache_v3_hw_show(struct seq_file *s, void *p)
3572{
3573 struct hisi_sas_debugfs_itct_cache *debugfs_itct_cache = s->private;
3574 struct hisi_sas_iost_itct_cache *itct_cache =
3575 debugfs_itct_cache->cache;
3576 u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
3577 int i, tab_idx;
3578 __le64 *itct;
3579
3580 for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, itct_cache++) {
3581
3582
3583
3584
3585
3586
3587 tab_idx = itct_cache->data[1] & 0xffff;
3588 itct = (__le64 *)itct_cache;
3589
3590 debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, itct);
3591 }
3592
3593 return 0;
3594}
3595DEFINE_SHOW_ATTRIBUTE(debugfs_itct_cache_v3_hw);
3596
3597static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba)
3598{
3599 u64 *debugfs_timestamp;
3600 int dump_index = hisi_hba->debugfs_dump_index;
3601 struct dentry *dump_dentry;
3602 struct dentry *dentry;
3603 char name[256];
3604 int p;
3605 int c;
3606 int d;
3607
3608 snprintf(name, 256, "%d", dump_index);
3609
3610 dump_dentry = debugfs_create_dir(name, hisi_hba->debugfs_dump_dentry);
3611
3612 debugfs_timestamp = &hisi_hba->debugfs_timestamp[dump_index];
3613
3614 debugfs_create_u64("timestamp", 0400, dump_dentry,
3615 debugfs_timestamp);
3616
3617 debugfs_create_file("global", 0400, dump_dentry,
3618 &hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL],
3619 &debugfs_global_v3_hw_fops);
3620
3621
3622 dentry = debugfs_create_dir("port", dump_dentry);
3623 for (p = 0; p < hisi_hba->n_phy; p++) {
3624 snprintf(name, 256, "%d", p);
3625
3626 debugfs_create_file(name, 0400, dentry,
3627 &hisi_hba->debugfs_port_reg[dump_index][p],
3628 &debugfs_port_v3_hw_fops);
3629 }
3630
3631
3632 dentry = debugfs_create_dir("cq", dump_dentry);
3633 for (c = 0; c < hisi_hba->queue_count; c++) {
3634 snprintf(name, 256, "%d", c);
3635
3636 debugfs_create_file(name, 0400, dentry,
3637 &hisi_hba->debugfs_cq[dump_index][c],
3638 &debugfs_cq_v3_hw_fops);
3639 }
3640
3641
3642 dentry = debugfs_create_dir("dq", dump_dentry);
3643 for (d = 0; d < hisi_hba->queue_count; d++) {
3644 snprintf(name, 256, "%d", d);
3645
3646 debugfs_create_file(name, 0400, dentry,
3647 &hisi_hba->debugfs_dq[dump_index][d],
3648 &debugfs_dq_v3_hw_fops);
3649 }
3650
3651 debugfs_create_file("iost", 0400, dump_dentry,
3652 &hisi_hba->debugfs_iost[dump_index],
3653 &debugfs_iost_v3_hw_fops);
3654
3655 debugfs_create_file("iost_cache", 0400, dump_dentry,
3656 &hisi_hba->debugfs_iost_cache[dump_index],
3657 &debugfs_iost_cache_v3_hw_fops);
3658
3659 debugfs_create_file("itct", 0400, dump_dentry,
3660 &hisi_hba->debugfs_itct[dump_index],
3661 &debugfs_itct_v3_hw_fops);
3662
3663 debugfs_create_file("itct_cache", 0400, dump_dentry,
3664 &hisi_hba->debugfs_itct_cache[dump_index],
3665 &debugfs_itct_cache_v3_hw_fops);
3666
3667 debugfs_create_file("axi", 0400, dump_dentry,
3668 &hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI],
3669 &debugfs_axi_v3_hw_fops);
3670
3671 debugfs_create_file("ras", 0400, dump_dentry,
3672 &hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS],
3673 &debugfs_ras_v3_hw_fops);
3674}
3675
3676static void debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba)
3677{
3678 int debugfs_dump_index = hisi_hba->debugfs_dump_index;
3679 struct device *dev = hisi_hba->dev;
3680 u64 timestamp = local_clock();
3681
3682 if (debugfs_dump_index >= hisi_sas_debugfs_dump_count) {
3683 dev_warn(dev, "dump count exceeded!\n");
3684 return;
3685 }
3686
3687 do_div(timestamp, NSEC_PER_MSEC);
3688 hisi_hba->debugfs_timestamp[debugfs_dump_index] = timestamp;
3689 hisi_hba->debugfs_dump_index++;
3690
3691 debugfs_snapshot_prepare_v3_hw(hisi_hba);
3692
3693 debugfs_snapshot_global_reg_v3_hw(hisi_hba);
3694 debugfs_snapshot_port_reg_v3_hw(hisi_hba);
3695 debugfs_snapshot_axi_reg_v3_hw(hisi_hba);
3696 debugfs_snapshot_ras_reg_v3_hw(hisi_hba);
3697 debugfs_snapshot_cq_reg_v3_hw(hisi_hba);
3698 debugfs_snapshot_dq_reg_v3_hw(hisi_hba);
3699 debugfs_snapshot_itct_reg_v3_hw(hisi_hba);
3700 debugfs_snapshot_iost_reg_v3_hw(hisi_hba);
3701
3702 debugfs_create_files_v3_hw(hisi_hba);
3703
3704 debugfs_snapshot_restore_v3_hw(hisi_hba);
3705}
3706
3707static ssize_t debugfs_trigger_dump_v3_hw_write(struct file *file,
3708 const char __user *user_buf,
3709 size_t count, loff_t *ppos)
3710{
3711 struct hisi_hba *hisi_hba = file->f_inode->i_private;
3712 char buf[8];
3713
3714 if (hisi_hba->debugfs_dump_index >= hisi_sas_debugfs_dump_count)
3715 return -EFAULT;
3716
3717 if (count > 8)
3718 return -EFAULT;
3719
3720 if (copy_from_user(buf, user_buf, count))
3721 return -EFAULT;
3722
3723 if (buf[0] != '1')
3724 return -EFAULT;
3725
3726 queue_work(hisi_hba->wq, &hisi_hba->debugfs_work);
3727
3728 return count;
3729}
3730
3731static const struct file_operations debugfs_trigger_dump_v3_hw_fops = {
3732 .write = &debugfs_trigger_dump_v3_hw_write,
3733 .owner = THIS_MODULE,
3734};
3735
3736enum {
3737 HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL = 0,
3738 HISI_SAS_BIST_LOOPBACK_MODE_SERDES,
3739 HISI_SAS_BIST_LOOPBACK_MODE_REMOTE,
3740};
3741
3742static const struct {
3743 int value;
3744 char *name;
3745} debugfs_loop_linkrate_v3_hw[] = {
3746 { SAS_LINK_RATE_1_5_GBPS, "1.5 Gbit" },
3747 { SAS_LINK_RATE_3_0_GBPS, "3.0 Gbit" },
3748 { SAS_LINK_RATE_6_0_GBPS, "6.0 Gbit" },
3749 { SAS_LINK_RATE_12_0_GBPS, "12.0 Gbit" },
3750};
3751
3752static int debugfs_bist_linkrate_v3_hw_show(struct seq_file *s, void *p)
3753{
3754 struct hisi_hba *hisi_hba = s->private;
3755 int i;
3756
3757 for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
3758 int match = (hisi_hba->debugfs_bist_linkrate ==
3759 debugfs_loop_linkrate_v3_hw[i].value);
3760
3761 seq_printf(s, "%s%s%s ", match ? "[" : "",
3762 debugfs_loop_linkrate_v3_hw[i].name,
3763 match ? "]" : "");
3764 }
3765 seq_puts(s, "\n");
3766
3767 return 0;
3768}
3769
3770static ssize_t debugfs_bist_linkrate_v3_hw_write(struct file *filp,
3771 const char __user *buf,
3772 size_t count, loff_t *ppos)
3773{
3774 struct seq_file *m = filp->private_data;
3775 struct hisi_hba *hisi_hba = m->private;
3776 char kbuf[16] = {}, *pkbuf;
3777 bool found = false;
3778 int i;
3779
3780 if (hisi_hba->debugfs_bist_enable)
3781 return -EPERM;
3782
3783 if (count >= sizeof(kbuf))
3784 return -EOVERFLOW;
3785
3786 if (copy_from_user(kbuf, buf, count))
3787 return -EINVAL;
3788
3789 pkbuf = strstrip(kbuf);
3790
3791 for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
3792 if (!strncmp(debugfs_loop_linkrate_v3_hw[i].name,
3793 pkbuf, 16)) {
3794 hisi_hba->debugfs_bist_linkrate =
3795 debugfs_loop_linkrate_v3_hw[i].value;
3796 found = true;
3797 break;
3798 }
3799 }
3800
3801 if (!found)
3802 return -EINVAL;
3803
3804 return count;
3805}
3806
3807static int debugfs_bist_linkrate_v3_hw_open(struct inode *inode,
3808 struct file *filp)
3809{
3810 return single_open(filp, debugfs_bist_linkrate_v3_hw_show,
3811 inode->i_private);
3812}
3813
3814static const struct file_operations debugfs_bist_linkrate_v3_hw_fops = {
3815 .open = debugfs_bist_linkrate_v3_hw_open,
3816 .read = seq_read,
3817 .write = debugfs_bist_linkrate_v3_hw_write,
3818 .llseek = seq_lseek,
3819 .release = single_release,
3820 .owner = THIS_MODULE,
3821};
3822
3823static const struct {
3824 int value;
3825 char *name;
3826} debugfs_loop_code_mode_v3_hw[] = {
3827 { HISI_SAS_BIST_CODE_MODE_PRBS7, "PRBS7" },
3828 { HISI_SAS_BIST_CODE_MODE_PRBS23, "PRBS23" },
3829 { HISI_SAS_BIST_CODE_MODE_PRBS31, "PRBS31" },
3830 { HISI_SAS_BIST_CODE_MODE_JTPAT, "JTPAT" },
3831 { HISI_SAS_BIST_CODE_MODE_CJTPAT, "CJTPAT" },
3832 { HISI_SAS_BIST_CODE_MODE_SCRAMBED_0, "SCRAMBED_0" },
3833 { HISI_SAS_BIST_CODE_MODE_TRAIN, "TRAIN" },
3834 { HISI_SAS_BIST_CODE_MODE_TRAIN_DONE, "TRAIN_DONE" },
3835 { HISI_SAS_BIST_CODE_MODE_HFTP, "HFTP" },
3836 { HISI_SAS_BIST_CODE_MODE_MFTP, "MFTP" },
3837 { HISI_SAS_BIST_CODE_MODE_LFTP, "LFTP" },
3838 { HISI_SAS_BIST_CODE_MODE_FIXED_DATA, "FIXED_DATA" },
3839};
3840
3841static int debugfs_bist_code_mode_v3_hw_show(struct seq_file *s, void *p)
3842{
3843 struct hisi_hba *hisi_hba = s->private;
3844 int i;
3845
3846 for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
3847 int match = (hisi_hba->debugfs_bist_code_mode ==
3848 debugfs_loop_code_mode_v3_hw[i].value);
3849
3850 seq_printf(s, "%s%s%s ", match ? "[" : "",
3851 debugfs_loop_code_mode_v3_hw[i].name,
3852 match ? "]" : "");
3853 }
3854 seq_puts(s, "\n");
3855
3856 return 0;
3857}
3858
3859static ssize_t debugfs_bist_code_mode_v3_hw_write(struct file *filp,
3860 const char __user *buf,
3861 size_t count,
3862 loff_t *ppos)
3863{
3864 struct seq_file *m = filp->private_data;
3865 struct hisi_hba *hisi_hba = m->private;
3866 char kbuf[16] = {}, *pkbuf;
3867 bool found = false;
3868 int i;
3869
3870 if (hisi_hba->debugfs_bist_enable)
3871 return -EPERM;
3872
3873 if (count >= sizeof(kbuf))
3874 return -EINVAL;
3875
3876 if (copy_from_user(kbuf, buf, count))
3877 return -EOVERFLOW;
3878
3879 pkbuf = strstrip(kbuf);
3880
3881 for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
3882 if (!strncmp(debugfs_loop_code_mode_v3_hw[i].name,
3883 pkbuf, 16)) {
3884 hisi_hba->debugfs_bist_code_mode =
3885 debugfs_loop_code_mode_v3_hw[i].value;
3886 found = true;
3887 break;
3888 }
3889 }
3890
3891 if (!found)
3892 return -EINVAL;
3893
3894 return count;
3895}
3896
3897static int debugfs_bist_code_mode_v3_hw_open(struct inode *inode,
3898 struct file *filp)
3899{
3900 return single_open(filp, debugfs_bist_code_mode_v3_hw_show,
3901 inode->i_private);
3902}
3903
3904static const struct file_operations debugfs_bist_code_mode_v3_hw_fops = {
3905 .open = debugfs_bist_code_mode_v3_hw_open,
3906 .read = seq_read,
3907 .write = debugfs_bist_code_mode_v3_hw_write,
3908 .llseek = seq_lseek,
3909 .release = single_release,
3910 .owner = THIS_MODULE,
3911};
3912
3913static ssize_t debugfs_bist_phy_v3_hw_write(struct file *filp,
3914 const char __user *buf,
3915 size_t count, loff_t *ppos)
3916{
3917 struct seq_file *m = filp->private_data;
3918 struct hisi_hba *hisi_hba = m->private;
3919 unsigned int phy_no;
3920 int val;
3921
3922 if (hisi_hba->debugfs_bist_enable)
3923 return -EPERM;
3924
3925 val = kstrtouint_from_user(buf, count, 0, &phy_no);
3926 if (val)
3927 return val;
3928
3929 if (phy_no >= hisi_hba->n_phy)
3930 return -EINVAL;
3931
3932 hisi_hba->debugfs_bist_phy_no = phy_no;
3933
3934 return count;
3935}
3936
3937static int debugfs_bist_phy_v3_hw_show(struct seq_file *s, void *p)
3938{
3939 struct hisi_hba *hisi_hba = s->private;
3940
3941 seq_printf(s, "%d\n", hisi_hba->debugfs_bist_phy_no);
3942
3943 return 0;
3944}
3945
3946static int debugfs_bist_phy_v3_hw_open(struct inode *inode,
3947 struct file *filp)
3948{
3949 return single_open(filp, debugfs_bist_phy_v3_hw_show,
3950 inode->i_private);
3951}
3952
3953static const struct file_operations debugfs_bist_phy_v3_hw_fops = {
3954 .open = debugfs_bist_phy_v3_hw_open,
3955 .read = seq_read,
3956 .write = debugfs_bist_phy_v3_hw_write,
3957 .llseek = seq_lseek,
3958 .release = single_release,
3959 .owner = THIS_MODULE,
3960};
3961
3962static const struct {
3963 int value;
3964 char *name;
3965} debugfs_loop_modes_v3_hw[] = {
3966 { HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL, "digital" },
3967 { HISI_SAS_BIST_LOOPBACK_MODE_SERDES, "serdes" },
3968 { HISI_SAS_BIST_LOOPBACK_MODE_REMOTE, "remote" },
3969};
3970
3971static int debugfs_bist_mode_v3_hw_show(struct seq_file *s, void *p)
3972{
3973 struct hisi_hba *hisi_hba = s->private;
3974 int i;
3975
3976 for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
3977 int match = (hisi_hba->debugfs_bist_mode ==
3978 debugfs_loop_modes_v3_hw[i].value);
3979
3980 seq_printf(s, "%s%s%s ", match ? "[" : "",
3981 debugfs_loop_modes_v3_hw[i].name,
3982 match ? "]" : "");
3983 }
3984 seq_puts(s, "\n");
3985
3986 return 0;
3987}
3988
3989static ssize_t debugfs_bist_mode_v3_hw_write(struct file *filp,
3990 const char __user *buf,
3991 size_t count, loff_t *ppos)
3992{
3993 struct seq_file *m = filp->private_data;
3994 struct hisi_hba *hisi_hba = m->private;
3995 char kbuf[16] = {}, *pkbuf;
3996 bool found = false;
3997 int i;
3998
3999 if (hisi_hba->debugfs_bist_enable)
4000 return -EPERM;
4001
4002 if (count >= sizeof(kbuf))
4003 return -EINVAL;
4004
4005 if (copy_from_user(kbuf, buf, count))
4006 return -EOVERFLOW;
4007
4008 pkbuf = strstrip(kbuf);
4009
4010 for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4011 if (!strncmp(debugfs_loop_modes_v3_hw[i].name, pkbuf, 16)) {
4012 hisi_hba->debugfs_bist_mode =
4013 debugfs_loop_modes_v3_hw[i].value;
4014 found = true;
4015 break;
4016 }
4017 }
4018
4019 if (!found)
4020 return -EINVAL;
4021
4022 return count;
4023}
4024
4025static int debugfs_bist_mode_v3_hw_open(struct inode *inode,
4026 struct file *filp)
4027{
4028 return single_open(filp, debugfs_bist_mode_v3_hw_show,
4029 inode->i_private);
4030}
4031
4032static const struct file_operations debugfs_bist_mode_v3_hw_fops = {
4033 .open = debugfs_bist_mode_v3_hw_open,
4034 .read = seq_read,
4035 .write = debugfs_bist_mode_v3_hw_write,
4036 .llseek = seq_lseek,
4037 .release = single_release,
4038 .owner = THIS_MODULE,
4039};
4040
4041static ssize_t debugfs_bist_enable_v3_hw_write(struct file *filp,
4042 const char __user *buf,
4043 size_t count, loff_t *ppos)
4044{
4045 struct seq_file *m = filp->private_data;
4046 struct hisi_hba *hisi_hba = m->private;
4047 unsigned int enable;
4048 int val;
4049
4050 val = kstrtouint_from_user(buf, count, 0, &enable);
4051 if (val)
4052 return val;
4053
4054 if (enable > 1)
4055 return -EINVAL;
4056
4057 if (enable == hisi_hba->debugfs_bist_enable)
4058 return count;
4059
4060 val = debugfs_set_bist_v3_hw(hisi_hba, enable);
4061 if (val < 0)
4062 return val;
4063
4064 hisi_hba->debugfs_bist_enable = enable;
4065
4066 return count;
4067}
4068
4069static int debugfs_bist_enable_v3_hw_show(struct seq_file *s, void *p)
4070{
4071 struct hisi_hba *hisi_hba = s->private;
4072
4073 seq_printf(s, "%d\n", hisi_hba->debugfs_bist_enable);
4074
4075 return 0;
4076}
4077
4078static int debugfs_bist_enable_v3_hw_open(struct inode *inode,
4079 struct file *filp)
4080{
4081 return single_open(filp, debugfs_bist_enable_v3_hw_show,
4082 inode->i_private);
4083}
4084
4085static const struct file_operations debugfs_bist_enable_v3_hw_fops = {
4086 .open = debugfs_bist_enable_v3_hw_open,
4087 .read = seq_read,
4088 .write = debugfs_bist_enable_v3_hw_write,
4089 .llseek = seq_lseek,
4090 .release = single_release,
4091 .owner = THIS_MODULE,
4092};
4093
4094static const struct {
4095 char *name;
4096} debugfs_ffe_name_v3_hw[FFE_CFG_MAX] = {
4097 { "SAS_1_5_GBPS" },
4098 { "SAS_3_0_GBPS" },
4099 { "SAS_6_0_GBPS" },
4100 { "SAS_12_0_GBPS" },
4101 { "FFE_RESV" },
4102 { "SATA_1_5_GBPS" },
4103 { "SATA_3_0_GBPS" },
4104 { "SATA_6_0_GBPS" },
4105};
4106
4107static ssize_t debugfs_v3_hw_write(struct file *filp,
4108 const char __user *buf,
4109 size_t count, loff_t *ppos)
4110{
4111 struct seq_file *m = filp->private_data;
4112 u32 *val = m->private;
4113 int res;
4114
4115 res = kstrtouint_from_user(buf, count, 0, val);
4116 if (res)
4117 return res;
4118
4119 return count;
4120}
4121
4122static int debugfs_v3_hw_show(struct seq_file *s, void *p)
4123{
4124 u32 *val = s->private;
4125
4126 seq_printf(s, "0x%x\n", *val);
4127
4128 return 0;
4129}
4130
4131static int debugfs_v3_hw_open(struct inode *inode, struct file *filp)
4132{
4133 return single_open(filp, debugfs_v3_hw_show,
4134 inode->i_private);
4135}
4136
4137static const struct file_operations debugfs_v3_hw_fops = {
4138 .open = debugfs_v3_hw_open,
4139 .read = seq_read,
4140 .write = debugfs_v3_hw_write,
4141 .llseek = seq_lseek,
4142 .release = single_release,
4143 .owner = THIS_MODULE,
4144};
4145
4146static ssize_t debugfs_phy_down_cnt_v3_hw_write(struct file *filp,
4147 const char __user *buf,
4148 size_t count, loff_t *ppos)
4149{
4150 struct seq_file *s = filp->private_data;
4151 struct hisi_sas_phy *phy = s->private;
4152 unsigned int set_val;
4153 int res;
4154
4155 res = kstrtouint_from_user(buf, count, 0, &set_val);
4156 if (res)
4157 return res;
4158
4159 if (set_val > 0)
4160 return -EINVAL;
4161
4162 atomic_set(&phy->down_cnt, 0);
4163
4164 return count;
4165}
4166
4167static int debugfs_phy_down_cnt_v3_hw_show(struct seq_file *s, void *p)
4168{
4169 struct hisi_sas_phy *phy = s->private;
4170
4171 seq_printf(s, "%d\n", atomic_read(&phy->down_cnt));
4172
4173 return 0;
4174}
4175
4176static int debugfs_phy_down_cnt_v3_hw_open(struct inode *inode,
4177 struct file *filp)
4178{
4179 return single_open(filp, debugfs_phy_down_cnt_v3_hw_show,
4180 inode->i_private);
4181}
4182
4183static const struct file_operations debugfs_phy_down_cnt_v3_hw_fops = {
4184 .open = debugfs_phy_down_cnt_v3_hw_open,
4185 .read = seq_read,
4186 .write = debugfs_phy_down_cnt_v3_hw_write,
4187 .llseek = seq_lseek,
4188 .release = single_release,
4189 .owner = THIS_MODULE,
4190};
4191
4192enum fifo_dump_mode_v3_hw {
4193 FIFO_DUMP_FORVER = (1U << 0),
4194 FIFO_DUMP_AFTER_TRIGGER = (1U << 1),
4195 FIFO_DUMP_UNTILL_TRIGGER = (1U << 2),
4196};
4197
4198enum fifo_trigger_mode_v3_hw {
4199 FIFO_TRIGGER_EDGE = (1U << 0),
4200 FIFO_TRIGGER_SAME_LEVEL = (1U << 1),
4201 FIFO_TRIGGER_DIFF_LEVEL = (1U << 2),
4202};
4203
4204static int debugfs_is_fifo_config_valid_v3_hw(struct hisi_sas_phy *phy)
4205{
4206 struct hisi_hba *hisi_hba = phy->hisi_hba;
4207
4208 if (phy->fifo.signal_sel > 0xf) {
4209 dev_info(hisi_hba->dev, "Invalid signal select: %u\n",
4210 phy->fifo.signal_sel);
4211 return -EINVAL;
4212 }
4213
4214 switch (phy->fifo.dump_mode) {
4215 case FIFO_DUMP_FORVER:
4216 case FIFO_DUMP_AFTER_TRIGGER:
4217 case FIFO_DUMP_UNTILL_TRIGGER:
4218 break;
4219 default:
4220 dev_info(hisi_hba->dev, "Invalid dump mode: %u\n",
4221 phy->fifo.dump_mode);
4222 return -EINVAL;
4223 }
4224
4225
4226 if (phy->fifo.dump_mode == FIFO_DUMP_FORVER)
4227 return 0;
4228
4229 switch (phy->fifo.trigger_mode) {
4230 case FIFO_TRIGGER_EDGE:
4231 case FIFO_TRIGGER_SAME_LEVEL:
4232 case FIFO_TRIGGER_DIFF_LEVEL:
4233 break;
4234 default:
4235 dev_info(hisi_hba->dev, "Invalid trigger mode: %u\n",
4236 phy->fifo.trigger_mode);
4237 return -EINVAL;
4238 }
4239 return 0;
4240}
4241
4242static int debugfs_update_fifo_config_v3_hw(struct hisi_sas_phy *phy)
4243{
4244 u32 trigger_mode = phy->fifo.trigger_mode;
4245 u32 signal_sel = phy->fifo.signal_sel;
4246 u32 dump_mode = phy->fifo.dump_mode;
4247 struct hisi_hba *hisi_hba = phy->hisi_hba;
4248 int phy_no = phy->sas_phy.id;
4249 u32 reg_val;
4250 int res;
4251
4252
4253 res = debugfs_is_fifo_config_valid_v3_hw(phy);
4254 if (res)
4255 return res;
4256
4257 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4258
4259 reg_val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4260
4261
4262 reg_val &= ~(DFX_FIFO_CTRL_DUMP_MODE_MSK |
4263 DFX_FIFO_CTRL_SIGNAL_SEL_MSK |
4264 DFX_FIFO_CTRL_TRIGGER_MODE_MSK);
4265
4266 reg_val |= ((trigger_mode << DFX_FIFO_CTRL_TRIGGER_MODE_OFF) |
4267 (dump_mode << DFX_FIFO_CTRL_DUMP_MODE_OFF) |
4268 (signal_sel << DFX_FIFO_CTRL_SIGNAL_SEL_OFF));
4269 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);
4270
4271 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK,
4272 phy->fifo.dump_msk);
4273
4274 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER,
4275 phy->fifo.trigger);
4276
4277 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK,
4278 phy->fifo.trigger_msk);
4279
4280
4281 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4282 reg_val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4283 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);
4284
4285 return 0;
4286}
4287
4288static ssize_t debugfs_fifo_update_cfg_v3_hw_write(struct file *filp,
4289 const char __user *buf,
4290 size_t count, loff_t *ppos)
4291{
4292 struct hisi_sas_phy *phy = filp->private_data;
4293 bool update;
4294 int val;
4295
4296 val = kstrtobool_from_user(buf, count, &update);
4297 if (val)
4298 return val;
4299
4300 if (update != 1)
4301 return -EINVAL;
4302
4303 val = debugfs_update_fifo_config_v3_hw(phy);
4304 if (val)
4305 return val;
4306
4307 return count;
4308}
4309
4310static const struct file_operations debugfs_fifo_update_cfg_v3_hw_fops = {
4311 .open = simple_open,
4312 .write = debugfs_fifo_update_cfg_v3_hw_write,
4313 .owner = THIS_MODULE,
4314};
4315
4316static void debugfs_read_fifo_data_v3_hw(struct hisi_sas_phy *phy)
4317{
4318 struct hisi_hba *hisi_hba = phy->hisi_hba;
4319 u32 *buf = phy->fifo.rd_data;
4320 int phy_no = phy->sas_phy.id;
4321 u32 val;
4322 int i;
4323
4324 memset(buf, 0, sizeof(phy->fifo.rd_data));
4325
4326
4327 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4328 val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4329 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4330
4331 for (i = 0; i < HISI_SAS_FIFO_DATA_DW_SIZE; i++) {
4332 val = hisi_sas_phy_read32(hisi_hba, phy_no,
4333 DFX_FIFO_RD_DATA);
4334 buf[i] = val;
4335 }
4336
4337
4338 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4339 val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4340 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4341}
4342
4343static int debugfs_fifo_data_v3_hw_show(struct seq_file *s, void *p)
4344{
4345 struct hisi_sas_phy *phy = s->private;
4346
4347 debugfs_read_fifo_data_v3_hw(phy);
4348
4349 debugfs_show_row_32_v3_hw(s, 0, HISI_SAS_FIFO_DATA_DW_SIZE * 4,
4350 phy->fifo.rd_data);
4351
4352 return 0;
4353}
4354DEFINE_SHOW_ATTRIBUTE(debugfs_fifo_data_v3_hw);
4355
4356static void debugfs_fifo_init_v3_hw(struct hisi_hba *hisi_hba)
4357{
4358 int phy_no;
4359
4360 hisi_hba->debugfs_fifo_dentry =
4361 debugfs_create_dir("fifo", hisi_hba->debugfs_dir);
4362
4363 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4364 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
4365 struct dentry *port_dentry;
4366 char name[256];
4367 u32 val;
4368
4369
4370 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4371 val &= DFX_FIFO_CTRL_DUMP_MODE_MSK;
4372 val >>= DFX_FIFO_CTRL_DUMP_MODE_OFF;
4373 phy->fifo.dump_mode = val;
4374
4375 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4376 val &= DFX_FIFO_CTRL_TRIGGER_MODE_MSK;
4377 val >>= DFX_FIFO_CTRL_TRIGGER_MODE_OFF;
4378 phy->fifo.trigger_mode = val;
4379
4380 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4381 val &= DFX_FIFO_CTRL_SIGNAL_SEL_MSK;
4382 val >>= DFX_FIFO_CTRL_SIGNAL_SEL_OFF;
4383 phy->fifo.signal_sel = val;
4384
4385 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK);
4386 phy->fifo.dump_msk = val;
4387
4388 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER);
4389 phy->fifo.trigger = val;
4390 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK);
4391 phy->fifo.trigger_msk = val;
4392
4393 snprintf(name, 256, "%d", phy_no);
4394 port_dentry = debugfs_create_dir(name,
4395 hisi_hba->debugfs_fifo_dentry);
4396
4397 debugfs_create_file("update_config", 0200, port_dentry, phy,
4398 &debugfs_fifo_update_cfg_v3_hw_fops);
4399
4400 debugfs_create_file("signal_sel", 0600, port_dentry,
4401 &phy->fifo.signal_sel,
4402 &debugfs_v3_hw_fops);
4403
4404 debugfs_create_file("dump_msk", 0600, port_dentry,
4405 &phy->fifo.dump_msk,
4406 &debugfs_v3_hw_fops);
4407
4408 debugfs_create_file("dump_mode", 0600, port_dentry,
4409 &phy->fifo.dump_mode,
4410 &debugfs_v3_hw_fops);
4411
4412 debugfs_create_file("trigger_mode", 0600, port_dentry,
4413 &phy->fifo.trigger_mode,
4414 &debugfs_v3_hw_fops);
4415
4416 debugfs_create_file("trigger", 0600, port_dentry,
4417 &phy->fifo.trigger,
4418 &debugfs_v3_hw_fops);
4419
4420 debugfs_create_file("trigger_msk", 0600, port_dentry,
4421 &phy->fifo.trigger_msk,
4422 &debugfs_v3_hw_fops);
4423
4424 debugfs_create_file("fifo_data", 0400, port_dentry, phy,
4425 &debugfs_fifo_data_v3_hw_fops);
4426 }
4427}
4428
4429static void debugfs_work_handler_v3_hw(struct work_struct *work)
4430{
4431 struct hisi_hba *hisi_hba =
4432 container_of(work, struct hisi_hba, debugfs_work);
4433
4434 debugfs_snapshot_regs_v3_hw(hisi_hba);
4435}
4436
4437static void debugfs_release_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4438{
4439 struct device *dev = hisi_hba->dev;
4440 int i;
4441
4442 devm_kfree(dev, hisi_hba->debugfs_iost_cache[dump_index].cache);
4443 devm_kfree(dev, hisi_hba->debugfs_itct_cache[dump_index].cache);
4444 devm_kfree(dev, hisi_hba->debugfs_iost[dump_index].iost);
4445 devm_kfree(dev, hisi_hba->debugfs_itct[dump_index].itct);
4446
4447 for (i = 0; i < hisi_hba->queue_count; i++)
4448 devm_kfree(dev, hisi_hba->debugfs_dq[dump_index][i].hdr);
4449
4450 for (i = 0; i < hisi_hba->queue_count; i++)
4451 devm_kfree(dev,
4452 hisi_hba->debugfs_cq[dump_index][i].complete_hdr);
4453
4454 for (i = 0; i < DEBUGFS_REGS_NUM; i++)
4455 devm_kfree(dev, hisi_hba->debugfs_regs[dump_index][i].data);
4456
4457 for (i = 0; i < hisi_hba->n_phy; i++)
4458 devm_kfree(dev, hisi_hba->debugfs_port_reg[dump_index][i].data);
4459}
4460
4461static const struct hisi_sas_debugfs_reg *debugfs_reg_array_v3_hw[DEBUGFS_REGS_NUM] = {
4462 [DEBUGFS_GLOBAL] = &debugfs_global_reg,
4463 [DEBUGFS_AXI] = &debugfs_axi_reg,
4464 [DEBUGFS_RAS] = &debugfs_ras_reg,
4465};
4466
4467static int debugfs_alloc_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4468{
4469 const struct hisi_sas_hw *hw = hisi_hba->hw;
4470 struct device *dev = hisi_hba->dev;
4471 int p, c, d, r, i;
4472 size_t sz;
4473
4474 for (r = 0; r < DEBUGFS_REGS_NUM; r++) {
4475 struct hisi_sas_debugfs_regs *regs =
4476 &hisi_hba->debugfs_regs[dump_index][r];
4477
4478 sz = debugfs_reg_array_v3_hw[r]->count * 4;
4479 regs->data = devm_kmalloc(dev, sz, GFP_KERNEL);
4480 if (!regs->data)
4481 goto fail;
4482 regs->hisi_hba = hisi_hba;
4483 }
4484
4485 sz = debugfs_port_reg.count * 4;
4486 for (p = 0; p < hisi_hba->n_phy; p++) {
4487 struct hisi_sas_debugfs_port *port =
4488 &hisi_hba->debugfs_port_reg[dump_index][p];
4489
4490 port->data = devm_kmalloc(dev, sz, GFP_KERNEL);
4491 if (!port->data)
4492 goto fail;
4493 port->phy = &hisi_hba->phy[p];
4494 }
4495
4496 sz = hw->complete_hdr_size * HISI_SAS_QUEUE_SLOTS;
4497 for (c = 0; c < hisi_hba->queue_count; c++) {
4498 struct hisi_sas_debugfs_cq *cq =
4499 &hisi_hba->debugfs_cq[dump_index][c];
4500
4501 cq->complete_hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
4502 if (!cq->complete_hdr)
4503 goto fail;
4504 cq->cq = &hisi_hba->cq[c];
4505 }
4506
4507 sz = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
4508 for (d = 0; d < hisi_hba->queue_count; d++) {
4509 struct hisi_sas_debugfs_dq *dq =
4510 &hisi_hba->debugfs_dq[dump_index][d];
4511
4512 dq->hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
4513 if (!dq->hdr)
4514 goto fail;
4515 dq->dq = &hisi_hba->dq[d];
4516 }
4517
4518 sz = HISI_SAS_MAX_COMMANDS * sizeof(struct hisi_sas_iost);
4519
4520 hisi_hba->debugfs_iost[dump_index].iost =
4521 devm_kmalloc(dev, sz, GFP_KERNEL);
4522 if (!hisi_hba->debugfs_iost[dump_index].iost)
4523 goto fail;
4524
4525 sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4526 sizeof(struct hisi_sas_iost_itct_cache);
4527
4528 hisi_hba->debugfs_iost_cache[dump_index].cache =
4529 devm_kmalloc(dev, sz, GFP_KERNEL);
4530 if (!hisi_hba->debugfs_iost_cache[dump_index].cache)
4531 goto fail;
4532
4533 sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4534 sizeof(struct hisi_sas_iost_itct_cache);
4535
4536 hisi_hba->debugfs_itct_cache[dump_index].cache =
4537 devm_kmalloc(dev, sz, GFP_KERNEL);
4538 if (!hisi_hba->debugfs_itct_cache[dump_index].cache)
4539 goto fail;
4540
4541
4542 sz = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
4543
4544 hisi_hba->debugfs_itct[dump_index].itct =
4545 devm_kmalloc(dev, sz, GFP_KERNEL);
4546 if (!hisi_hba->debugfs_itct[dump_index].itct)
4547 goto fail;
4548
4549 return 0;
4550fail:
4551 for (i = 0; i < hisi_sas_debugfs_dump_count; i++)
4552 debugfs_release_v3_hw(hisi_hba, i);
4553 return -ENOMEM;
4554}
4555
4556static void debugfs_phy_down_cnt_init_v3_hw(struct hisi_hba *hisi_hba)
4557{
4558 struct dentry *dir = debugfs_create_dir("phy_down_cnt",
4559 hisi_hba->debugfs_dir);
4560 char name[16];
4561 int phy_no;
4562
4563 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4564 snprintf(name, 16, "%d", phy_no);
4565 debugfs_create_file(name, 0600, dir,
4566 &hisi_hba->phy[phy_no],
4567 &debugfs_phy_down_cnt_v3_hw_fops);
4568 }
4569}
4570
4571static void debugfs_bist_init_v3_hw(struct hisi_hba *hisi_hba)
4572{
4573 struct dentry *ports_dentry;
4574 int phy_no;
4575
4576 hisi_hba->debugfs_bist_dentry =
4577 debugfs_create_dir("bist", hisi_hba->debugfs_dir);
4578 debugfs_create_file("link_rate", 0600,
4579 hisi_hba->debugfs_bist_dentry, hisi_hba,
4580 &debugfs_bist_linkrate_v3_hw_fops);
4581
4582 debugfs_create_file("code_mode", 0600,
4583 hisi_hba->debugfs_bist_dentry, hisi_hba,
4584 &debugfs_bist_code_mode_v3_hw_fops);
4585
4586 debugfs_create_file("fixed_code", 0600,
4587 hisi_hba->debugfs_bist_dentry,
4588 &hisi_hba->debugfs_bist_fixed_code[0],
4589 &debugfs_v3_hw_fops);
4590
4591 debugfs_create_file("fixed_code_1", 0600,
4592 hisi_hba->debugfs_bist_dentry,
4593 &hisi_hba->debugfs_bist_fixed_code[1],
4594 &debugfs_v3_hw_fops);
4595
4596 debugfs_create_file("phy_id", 0600, hisi_hba->debugfs_bist_dentry,
4597 hisi_hba, &debugfs_bist_phy_v3_hw_fops);
4598
4599 debugfs_create_u32("cnt", 0600, hisi_hba->debugfs_bist_dentry,
4600 &hisi_hba->debugfs_bist_cnt);
4601
4602 debugfs_create_file("loopback_mode", 0600,
4603 hisi_hba->debugfs_bist_dentry,
4604 hisi_hba, &debugfs_bist_mode_v3_hw_fops);
4605
4606 debugfs_create_file("enable", 0600, hisi_hba->debugfs_bist_dentry,
4607 hisi_hba, &debugfs_bist_enable_v3_hw_fops);
4608
4609 ports_dentry = debugfs_create_dir("port", hisi_hba->debugfs_bist_dentry);
4610
4611 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4612 struct dentry *port_dentry;
4613 struct dentry *ffe_dentry;
4614 char name[256];
4615 int i;
4616
4617 snprintf(name, 256, "%d", phy_no);
4618 port_dentry = debugfs_create_dir(name, ports_dentry);
4619 ffe_dentry = debugfs_create_dir("ffe", port_dentry);
4620 for (i = 0; i < FFE_CFG_MAX; i++) {
4621 if (i == FFE_RESV)
4622 continue;
4623 debugfs_create_file(debugfs_ffe_name_v3_hw[i].name,
4624 0600, ffe_dentry,
4625 &hisi_hba->debugfs_bist_ffe[phy_no][i],
4626 &debugfs_v3_hw_fops);
4627 }
4628 }
4629
4630 hisi_hba->debugfs_bist_linkrate = SAS_LINK_RATE_1_5_GBPS;
4631}
4632
4633static void debugfs_init_v3_hw(struct hisi_hba *hisi_hba)
4634{
4635 struct device *dev = hisi_hba->dev;
4636 int i;
4637
4638 hisi_hba->debugfs_dir = debugfs_create_dir(dev_name(dev),
4639 hisi_sas_debugfs_dir);
4640 debugfs_create_file("trigger_dump", 0200,
4641 hisi_hba->debugfs_dir,
4642 hisi_hba,
4643 &debugfs_trigger_dump_v3_hw_fops);
4644
4645
4646 debugfs_bist_init_v3_hw(hisi_hba);
4647
4648 hisi_hba->debugfs_dump_dentry =
4649 debugfs_create_dir("dump", hisi_hba->debugfs_dir);
4650
4651 debugfs_phy_down_cnt_init_v3_hw(hisi_hba);
4652 debugfs_fifo_init_v3_hw(hisi_hba);
4653
4654 for (i = 0; i < hisi_sas_debugfs_dump_count; i++) {
4655 if (debugfs_alloc_v3_hw(hisi_hba, i)) {
4656 debugfs_remove_recursive(hisi_hba->debugfs_dir);
4657 dev_dbg(dev, "failed to init debugfs!\n");
4658 break;
4659 }
4660 }
4661}
4662
4663static void debugfs_exit_v3_hw(struct hisi_hba *hisi_hba)
4664{
4665 debugfs_remove_recursive(hisi_hba->debugfs_dir);
4666}
4667
4668static int
4669hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4670{
4671 struct Scsi_Host *shost;
4672 struct hisi_hba *hisi_hba;
4673 struct device *dev = &pdev->dev;
4674 struct asd_sas_phy **arr_phy;
4675 struct asd_sas_port **arr_port;
4676 struct sas_ha_struct *sha;
4677 int rc, phy_nr, port_nr, i;
4678
4679 rc = pci_enable_device(pdev);
4680 if (rc)
4681 goto err_out;
4682
4683 pci_set_master(pdev);
4684
4685 rc = pci_request_regions(pdev, DRV_NAME);
4686 if (rc)
4687 goto err_out_disable_device;
4688
4689 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4690 if (rc)
4691 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4692 if (rc) {
4693 dev_err(dev, "No usable DMA addressing method\n");
4694 rc = -ENODEV;
4695 goto err_out_regions;
4696 }
4697
4698 shost = hisi_sas_shost_alloc_pci(pdev);
4699 if (!shost) {
4700 rc = -ENOMEM;
4701 goto err_out_regions;
4702 }
4703
4704 sha = SHOST_TO_SAS_HA(shost);
4705 hisi_hba = shost_priv(shost);
4706 dev_set_drvdata(dev, sha);
4707
4708 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
4709 if (!hisi_hba->regs) {
4710 dev_err(dev, "cannot map register\n");
4711 rc = -ENOMEM;
4712 goto err_out_ha;
4713 }
4714
4715 phy_nr = port_nr = hisi_hba->n_phy;
4716
4717 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
4718 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
4719 if (!arr_phy || !arr_port) {
4720 rc = -ENOMEM;
4721 goto err_out_ha;
4722 }
4723
4724 sha->sas_phy = arr_phy;
4725 sha->sas_port = arr_port;
4726 sha->core.shost = shost;
4727 sha->lldd_ha = hisi_hba;
4728
4729 shost->transportt = hisi_sas_stt;
4730 shost->max_id = HISI_SAS_MAX_DEVICES;
4731 shost->max_lun = ~0;
4732 shost->max_channel = 1;
4733 shost->max_cmd_len = 16;
4734 shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
4735 shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
4736
4737 sha->sas_ha_name = DRV_NAME;
4738 sha->dev = dev;
4739 sha->lldd_module = THIS_MODULE;
4740 sha->sas_addr = &hisi_hba->sas_addr[0];
4741 sha->num_phys = hisi_hba->n_phy;
4742
4743 for (i = 0; i < hisi_hba->n_phy; i++) {
4744 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
4745 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
4746 }
4747
4748 if (hisi_hba->prot_mask) {
4749 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
4750 prot_mask);
4751 scsi_host_set_prot(hisi_hba->shost, prot_mask);
4752 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
4753 scsi_host_set_guard(hisi_hba->shost,
4754 SHOST_DIX_GUARD_CRC);
4755 }
4756
4757 if (hisi_sas_debugfs_enable)
4758 debugfs_init_v3_hw(hisi_hba);
4759
4760 rc = interrupt_preinit_v3_hw(hisi_hba);
4761 if (rc)
4762 goto err_out_debugfs;
4763 dev_err(dev, "%d hw queues\n", shost->nr_hw_queues);
4764 rc = scsi_add_host(shost, dev);
4765 if (rc)
4766 goto err_out_free_irq_vectors;
4767
4768 rc = sas_register_ha(sha);
4769 if (rc)
4770 goto err_out_register_ha;
4771
4772 rc = hisi_sas_v3_init(hisi_hba);
4773 if (rc)
4774 goto err_out_hw_init;
4775
4776 scsi_scan_host(shost);
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786 pm_suspend_ignore_children(dev, true);
4787 pm_runtime_put_noidle(&pdev->dev);
4788
4789 return 0;
4790
4791err_out_hw_init:
4792 sas_unregister_ha(sha);
4793err_out_register_ha:
4794 scsi_remove_host(shost);
4795err_out_free_irq_vectors:
4796 pci_free_irq_vectors(pdev);
4797err_out_debugfs:
4798 debugfs_exit_v3_hw(hisi_hba);
4799err_out_ha:
4800 hisi_sas_free(hisi_hba);
4801 scsi_host_put(shost);
4802err_out_regions:
4803 pci_release_regions(pdev);
4804err_out_disable_device:
4805 pci_disable_device(pdev);
4806err_out:
4807 return rc;
4808}
4809
4810static void
4811hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
4812{
4813 int i;
4814
4815 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 1), hisi_hba);
4816 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 2), hisi_hba);
4817 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 11), hisi_hba);
4818 for (i = 0; i < hisi_hba->cq_nvecs; i++) {
4819 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
4820 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
4821
4822 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, nr), cq);
4823 }
4824 pci_free_irq_vectors(pdev);
4825}
4826
4827static void hisi_sas_v3_remove(struct pci_dev *pdev)
4828{
4829 struct device *dev = &pdev->dev;
4830 struct sas_ha_struct *sha = dev_get_drvdata(dev);
4831 struct hisi_hba *hisi_hba = sha->lldd_ha;
4832 struct Scsi_Host *shost = sha->core.shost;
4833
4834 pm_runtime_get_noresume(dev);
4835 if (timer_pending(&hisi_hba->timer))
4836 del_timer(&hisi_hba->timer);
4837
4838 sas_unregister_ha(sha);
4839 flush_workqueue(hisi_hba->wq);
4840 sas_remove_host(sha->core.shost);
4841
4842 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
4843 pci_release_regions(pdev);
4844 pci_disable_device(pdev);
4845 hisi_sas_free(hisi_hba);
4846 debugfs_exit_v3_hw(hisi_hba);
4847 scsi_host_put(shost);
4848}
4849
4850static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
4851{
4852 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4853 struct hisi_hba *hisi_hba = sha->lldd_ha;
4854 struct device *dev = hisi_hba->dev;
4855 int rc;
4856
4857 dev_info(dev, "FLR prepare\n");
4858 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
4859 hisi_sas_controller_reset_prepare(hisi_hba);
4860
4861 rc = disable_host_v3_hw(hisi_hba);
4862 if (rc)
4863 dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
4864}
4865
4866static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
4867{
4868 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4869 struct hisi_hba *hisi_hba = sha->lldd_ha;
4870 struct device *dev = hisi_hba->dev;
4871 int rc;
4872
4873 hisi_sas_init_mem(hisi_hba);
4874
4875 rc = hw_init_v3_hw(hisi_hba);
4876 if (rc) {
4877 dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
4878 return;
4879 }
4880
4881 hisi_sas_controller_reset_done(hisi_hba);
4882 dev_info(dev, "FLR done\n");
4883}
4884
4885enum {
4886
4887 hip08,
4888};
4889
4890static int _suspend_v3_hw(struct device *device)
4891{
4892 struct pci_dev *pdev = to_pci_dev(device);
4893 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4894 struct hisi_hba *hisi_hba = sha->lldd_ha;
4895 struct device *dev = hisi_hba->dev;
4896 struct Scsi_Host *shost = hisi_hba->shost;
4897 int rc;
4898
4899 if (!pdev->pm_cap) {
4900 dev_err(dev, "PCI PM not supported\n");
4901 return -ENODEV;
4902 }
4903
4904 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
4905 return -1;
4906
4907 scsi_block_requests(shost);
4908 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
4909 flush_workqueue(hisi_hba->wq);
4910
4911 rc = disable_host_v3_hw(hisi_hba);
4912 if (rc) {
4913 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
4914 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
4915 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
4916 scsi_unblock_requests(shost);
4917 return rc;
4918 }
4919
4920 hisi_sas_init_mem(hisi_hba);
4921
4922 dev_warn(dev, "entering suspend state\n");
4923
4924 hisi_sas_release_tasks(hisi_hba);
4925
4926 sas_suspend_ha(sha);
4927 return 0;
4928}
4929
4930static int _resume_v3_hw(struct device *device)
4931{
4932 struct pci_dev *pdev = to_pci_dev(device);
4933 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4934 struct hisi_hba *hisi_hba = sha->lldd_ha;
4935 struct Scsi_Host *shost = hisi_hba->shost;
4936 struct device *dev = hisi_hba->dev;
4937 unsigned int rc;
4938 pci_power_t device_state = pdev->current_state;
4939
4940 dev_warn(dev, "resuming from operating state [D%d]\n",
4941 device_state);
4942
4943 scsi_unblock_requests(shost);
4944 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
4945
4946 sas_prep_resume_ha(sha);
4947 rc = hw_init_v3_hw(hisi_hba);
4948 if (rc) {
4949 scsi_remove_host(shost);
4950 return rc;
4951 }
4952 phys_init_v3_hw(hisi_hba);
4953 sas_resume_ha(sha);
4954 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
4955
4956 return 0;
4957}
4958
4959static int __maybe_unused suspend_v3_hw(struct device *device)
4960{
4961 struct pci_dev *pdev = to_pci_dev(device);
4962 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4963 struct hisi_hba *hisi_hba = sha->lldd_ha;
4964 int rc;
4965
4966 set_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
4967
4968 rc = _suspend_v3_hw(device);
4969 if (rc)
4970 clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
4971
4972 return rc;
4973}
4974
4975static int __maybe_unused resume_v3_hw(struct device *device)
4976{
4977 struct pci_dev *pdev = to_pci_dev(device);
4978 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4979 struct hisi_hba *hisi_hba = sha->lldd_ha;
4980 int rc = _resume_v3_hw(device);
4981
4982 clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
4983
4984 return rc;
4985}
4986
4987static const struct pci_device_id sas_v3_pci_table[] = {
4988 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
4989 {}
4990};
4991MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
4992
4993static const struct pci_error_handlers hisi_sas_err_handler = {
4994 .reset_prepare = hisi_sas_reset_prepare_v3_hw,
4995 .reset_done = hisi_sas_reset_done_v3_hw,
4996};
4997
4998static UNIVERSAL_DEV_PM_OPS(hisi_sas_v3_pm_ops,
4999 suspend_v3_hw,
5000 resume_v3_hw,
5001 NULL);
5002
5003static struct pci_driver sas_v3_pci_driver = {
5004 .name = DRV_NAME,
5005 .id_table = sas_v3_pci_table,
5006 .probe = hisi_sas_v3_probe,
5007 .remove = hisi_sas_v3_remove,
5008 .err_handler = &hisi_sas_err_handler,
5009 .driver.pm = &hisi_sas_v3_pm_ops,
5010};
5011
5012module_pci_driver(sas_v3_pci_driver);
5013module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
5014
5015MODULE_LICENSE("GPL");
5016MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
5017MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
5018MODULE_ALIAS("pci:" DRV_NAME);
5019