1
2
3
4
5
6#ifndef __QLA_DEF_H
7#define __QLA_DEF_H
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/types.h>
12#include <linux/module.h>
13#include <linux/list.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/dmapool.h>
19#include <linux/mempool.h>
20#include <linux/spinlock.h>
21#include <linux/completion.h>
22#include <linux/interrupt.h>
23#include <linux/workqueue.h>
24#include <linux/firmware.h>
25#include <linux/aer.h>
26#include <linux/mutex.h>
27#include <linux/btree.h>
28
29#include <scsi/scsi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_cmnd.h>
33#include <scsi/scsi_transport_fc.h>
34#include <scsi/scsi_bsg_fc.h>
35
36#include <uapi/scsi/fc/fc_els.h>
37
38
39typedef struct {
40 uint8_t domain;
41 uint8_t area;
42 uint8_t al_pa;
43} be_id_t;
44
45
46typedef struct {
47 uint8_t al_pa;
48 uint8_t area;
49 uint8_t domain;
50} le_id_t;
51
52#include "qla_bsg.h"
53#include "qla_dsd.h"
54#include "qla_nx.h"
55#include "qla_nx2.h"
56#include "qla_nvme.h"
57#define QLA2XXX_DRIVER_NAME "qla2xxx"
58#define QLA2XXX_APIDEV "ql2xapidev"
59#define QLA2XXX_MANUFACTURER "QLogic Corporation"
60
61
62
63
64
65
66#define MAILBOX_REGISTER_COUNT_2100 8
67#define MAILBOX_REGISTER_COUNT_2200 24
68#define MAILBOX_REGISTER_COUNT 32
69
70#define QLA2200A_RISC_ROM_VER 4
71#define FPM_2300 6
72#define FPM_2310 7
73
74#include "qla_settings.h"
75
76#define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
77
78
79
80
81#define BIT_0 0x1
82#define BIT_1 0x2
83#define BIT_2 0x4
84#define BIT_3 0x8
85#define BIT_4 0x10
86#define BIT_5 0x20
87#define BIT_6 0x40
88#define BIT_7 0x80
89#define BIT_8 0x100
90#define BIT_9 0x200
91#define BIT_10 0x400
92#define BIT_11 0x800
93#define BIT_12 0x1000
94#define BIT_13 0x2000
95#define BIT_14 0x4000
96#define BIT_15 0x8000
97#define BIT_16 0x10000
98#define BIT_17 0x20000
99#define BIT_18 0x40000
100#define BIT_19 0x80000
101#define BIT_20 0x100000
102#define BIT_21 0x200000
103#define BIT_22 0x400000
104#define BIT_23 0x800000
105#define BIT_24 0x1000000
106#define BIT_25 0x2000000
107#define BIT_26 0x4000000
108#define BIT_27 0x8000000
109#define BIT_28 0x10000000
110#define BIT_29 0x20000000
111#define BIT_30 0x40000000
112#define BIT_31 0x80000000
113
114#define LSB(x) ((uint8_t)(x))
115#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
116
117#define LSW(x) ((uint16_t)(x))
118#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
119
120#define LSD(x) ((uint32_t)((uint64_t)(x)))
121#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
122
123static inline uint32_t make_handle(uint16_t x, uint16_t y)
124{
125 return ((uint32_t)x << 16) | y;
126}
127
128
129
130
131
132static inline u8 rd_reg_byte(const volatile u8 __iomem *addr)
133{
134 return readb(addr);
135}
136
137static inline u16 rd_reg_word(const volatile __le16 __iomem *addr)
138{
139 return readw(addr);
140}
141
142static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr)
143{
144 return readl(addr);
145}
146
147static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr)
148{
149 return readb_relaxed(addr);
150}
151
152static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr)
153{
154 return readw_relaxed(addr);
155}
156
157static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr)
158{
159 return readl_relaxed(addr);
160}
161
162static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data)
163{
164 return writeb(data, addr);
165}
166
167static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data)
168{
169 return writew(data, addr);
170}
171
172static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data)
173{
174 return writel(data, addr);
175}
176
177
178
179
180#define QLA83XX_LED_PORT0 0x00201320
181#define QLA83XX_LED_PORT1 0x00201328
182#define QLA83XX_IDC_DEV_STATE 0x22102384
183#define QLA83XX_IDC_MAJOR_VERSION 0x22102380
184#define QLA83XX_IDC_MINOR_VERSION 0x22102398
185#define QLA83XX_IDC_DRV_PRESENCE 0x22102388
186#define QLA83XX_IDC_DRIVER_ACK 0x2210238c
187#define QLA83XX_IDC_CONTROL 0x22102390
188#define QLA83XX_IDC_AUDIT 0x22102394
189#define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
190#define QLA83XX_DRIVER_LOCKID 0x22102104
191#define QLA83XX_DRIVER_LOCK 0x8111c028
192#define QLA83XX_DRIVER_UNLOCK 0x8111c02c
193#define QLA83XX_FLASH_LOCKID 0x22102100
194#define QLA83XX_FLASH_LOCK 0x8111c010
195#define QLA83XX_FLASH_UNLOCK 0x8111c014
196#define QLA83XX_DEV_PARTINFO1 0x221023e0
197#define QLA83XX_DEV_PARTINFO2 0x221023e4
198#define QLA83XX_FW_HEARTBEAT 0x221020b0
199#define QLA83XX_PEG_HALT_STATUS1 0x221020a8
200#define QLA83XX_PEG_HALT_STATUS2 0x221020ac
201
202
203#define IDC_DEVICE_STATE_CHANGE BIT_0
204#define IDC_PEG_HALT_STATUS_CHANGE BIT_1
205#define IDC_NIC_FW_REPORTED_FAILURE BIT_2
206#define IDC_HEARTBEAT_FAILURE BIT_3
207
208
209#define ERR_LEVEL_NON_FATAL 0x1
210#define ERR_LEVEL_RECOVERABLE_FATAL 0x2
211#define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
212
213
214#define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
215#define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
216
217
218#define QLA83XX_NIC_CORE_RESET 0x1
219#define QLA83XX_IDC_STATE_HANDLER 0x2
220#define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
221
222
223#define QLA83XX_IDC_RESET_DISABLED BIT_0
224#define QLA83XX_IDC_GRACEFUL_RESET BIT_1
225
226
227#define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
228#define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
229#define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
230
231
232#define QLA83XX_CLASS_TYPE_NONE 0x0
233#define QLA83XX_CLASS_TYPE_NIC 0x1
234#define QLA83XX_CLASS_TYPE_FCOE 0x2
235#define QLA83XX_CLASS_TYPE_ISCSI 0x3
236
237
238#define IDC_LOCK_RECOVERY_STAGE1 0x1
239
240
241#define IDC_LOCK_RECOVERY_STAGE2 0x2
242
243
244#define IDC_AUDIT_TIMESTAMP 0x0
245
246
247
248#define IDC_AUDIT_COMPLETION 0x1
249
250
251
252
253#define PORT_0_2031 0x00201340
254#define PORT_1_2031 0x00201350
255#define LASER_ON_2031 0x01800100
256#define LASER_OFF_2031 0x01800180
257
258
259
260
261
262#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
263#define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
264
265
266
267
268#define WWN_SIZE 8
269#define MAX_FIBRE_DEVICES_2100 512
270#define MAX_FIBRE_DEVICES_2400 2048
271#define MAX_FIBRE_DEVICES_LOOP 128
272#define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
273#define LOOPID_MAP_SIZE (ha->max_fibre_devices)
274#define MAX_FIBRE_LUNS 0xFFFF
275#define MAX_HOST_COUNT 16
276
277
278
279
280#define MAX_BUSES 1
281#define MIN_LUNS 8
282#define MAX_LUNS MAX_FIBRE_LUNS
283#define MAX_CMDS_PER_LUN 255
284
285
286
287
288#define SNS_LAST_LOOP_ID_2100 0xfe
289#define SNS_LAST_LOOP_ID_2300 0x7ff
290
291#define LAST_LOCAL_LOOP_ID 0x7d
292#define SNS_FL_PORT 0x7e
293#define FABRIC_CONTROLLER 0x7f
294#define SIMPLE_NAME_SERVER 0x80
295#define SNS_FIRST_LOOP_ID 0x81
296#define MANAGEMENT_SERVER 0xfe
297#define BROADCAST 0xff
298
299
300
301
302
303#define NPH_LAST_HANDLE 0x7ee
304#define NPH_MGMT_SERVER 0x7ef
305#define NPH_SNS 0x7fc
306#define NPH_FABRIC_CONTROLLER 0x7fd
307#define NPH_F_PORT 0x7fe
308#define NPH_IP_BROADCAST 0x7ff
309
310#define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
311
312#define MAX_CMDSZ 16
313#include "qla_fw.h"
314
315struct name_list_extended {
316 struct get_name_list_extended *l;
317 dma_addr_t ldma;
318 struct list_head fcports;
319 u32 size;
320 u8 sent;
321};
322
323
324
325#define PORT_RETRY_TIME 1
326#define LOOP_DOWN_TIMEOUT 60
327#define LOOP_DOWN_TIME 255
328#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
329
330#define DEFAULT_OUTSTANDING_COMMANDS 4096
331#define MIN_OUTSTANDING_COMMANDS 128
332
333
334#define REQUEST_ENTRY_CNT_2100 128
335#define REQUEST_ENTRY_CNT_2200 2048
336#define REQUEST_ENTRY_CNT_24XX 2048
337#define REQUEST_ENTRY_CNT_83XX 8192
338#define RESPONSE_ENTRY_CNT_83XX 4096
339#define RESPONSE_ENTRY_CNT_2100 64
340#define RESPONSE_ENTRY_CNT_2300 512
341#define RESPONSE_ENTRY_CNT_MQ 128
342#define ATIO_ENTRY_CNT_24XX 4096
343#define RESPONSE_ENTRY_CNT_FX00 256
344#define FW_DEF_EXCHANGES_CNT 2048
345#define FW_MAX_EXCHANGES_CNT (32 * 1024)
346#define REDUCE_EXCHANGES_CNT (8 * 1024)
347
348struct req_que;
349struct qla_tgt_sess;
350
351
352
353
354struct srb_cmd {
355 struct scsi_cmnd *cmd;
356 uint32_t request_sense_length;
357 uint32_t fw_sense_length;
358 uint8_t *request_sense_ptr;
359 struct ct6_dsd *ct6_ctx;
360 struct crc_context *crc_ctx;
361};
362
363
364
365
366#define SRB_DMA_VALID BIT_0
367#define SRB_FCP_CMND_DMA_VALID BIT_12
368#define SRB_CRC_CTX_DMA_VALID BIT_2
369#define SRB_CRC_PROT_DMA_VALID BIT_4
370#define SRB_CRC_CTX_DSD_VALID BIT_5
371#define SRB_WAKEUP_ON_COMP BIT_6
372#define SRB_DIF_BUNDL_DMA_VALID BIT_7
373
374
375#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
376
377
378
379
380typedef union {
381 uint32_t b24 : 24;
382
383 struct {
384#ifdef __BIG_ENDIAN
385 uint8_t domain;
386 uint8_t area;
387 uint8_t al_pa;
388#elif defined(__LITTLE_ENDIAN)
389 uint8_t al_pa;
390 uint8_t area;
391 uint8_t domain;
392#else
393#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
394#endif
395 uint8_t rsvd_1;
396 } b;
397} port_id_t;
398#define INVALID_PORT_ID 0xFFFFFF
399#define ISP_REG16_DISCONNECT 0xFFFF
400
401static inline le_id_t be_id_to_le(be_id_t id)
402{
403 le_id_t res;
404
405 res.domain = id.domain;
406 res.area = id.area;
407 res.al_pa = id.al_pa;
408
409 return res;
410}
411
412static inline be_id_t le_id_to_be(le_id_t id)
413{
414 be_id_t res;
415
416 res.domain = id.domain;
417 res.area = id.area;
418 res.al_pa = id.al_pa;
419
420 return res;
421}
422
423static inline port_id_t be_to_port_id(be_id_t id)
424{
425 port_id_t res;
426
427 res.b.domain = id.domain;
428 res.b.area = id.area;
429 res.b.al_pa = id.al_pa;
430 res.b.rsvd_1 = 0;
431
432 return res;
433}
434
435static inline be_id_t port_id_to_be_id(port_id_t port_id)
436{
437 be_id_t res;
438
439 res.domain = port_id.b.domain;
440 res.area = port_id.b.area;
441 res.al_pa = port_id.b.al_pa;
442
443 return res;
444}
445
446struct els_logo_payload {
447 uint8_t opcode;
448 uint8_t rsvd[3];
449 uint8_t s_id[3];
450 uint8_t rsvd1[1];
451 uint8_t wwpn[WWN_SIZE];
452};
453
454struct els_plogi_payload {
455 uint8_t opcode;
456 uint8_t rsvd[3];
457 __be32 data[112 / 4];
458};
459
460struct ct_arg {
461 void *iocb;
462 u16 nport_handle;
463 dma_addr_t req_dma;
464 dma_addr_t rsp_dma;
465 u32 req_size;
466 u32 rsp_size;
467 u32 req_allocated_size;
468 u32 rsp_allocated_size;
469 void *req;
470 void *rsp;
471 port_id_t id;
472};
473
474
475
476
477struct srb_iocb {
478 union {
479 struct {
480 uint16_t flags;
481#define SRB_LOGIN_RETRIED BIT_0
482#define SRB_LOGIN_COND_PLOGI BIT_1
483#define SRB_LOGIN_SKIP_PRLI BIT_2
484#define SRB_LOGIN_NVME_PRLI BIT_3
485#define SRB_LOGIN_PRLI_ONLY BIT_4
486 uint16_t data[2];
487 u32 iop[2];
488 } logio;
489 struct {
490#define ELS_DCMD_TIMEOUT 20
491#define ELS_DCMD_LOGO 0x5
492 uint32_t flags;
493 uint32_t els_cmd;
494 struct completion comp;
495 struct els_logo_payload *els_logo_pyld;
496 dma_addr_t els_logo_pyld_dma;
497 } els_logo;
498 struct els_plogi {
499#define ELS_DCMD_PLOGI 0x3
500 uint32_t flags;
501 uint32_t els_cmd;
502 struct completion comp;
503 struct els_plogi_payload *els_plogi_pyld;
504 struct els_plogi_payload *els_resp_pyld;
505 u32 tx_size;
506 u32 rx_size;
507 dma_addr_t els_plogi_pyld_dma;
508 dma_addr_t els_resp_pyld_dma;
509 __le32 fw_status[3];
510 __le16 comp_status;
511 __le16 len;
512 } els_plogi;
513 struct {
514
515
516
517
518
519 uint64_t lun;
520 uint32_t flags;
521 uint32_t data;
522 struct completion comp;
523 __le16 comp_status;
524 } tmf;
525 struct {
526#define SRB_FXDISC_REQ_DMA_VALID BIT_0
527#define SRB_FXDISC_RESP_DMA_VALID BIT_1
528#define SRB_FXDISC_REQ_DWRD_VALID BIT_2
529#define SRB_FXDISC_RSP_DWRD_VALID BIT_3
530#define FXDISC_TIMEOUT 20
531 uint8_t flags;
532 uint32_t req_len;
533 uint32_t rsp_len;
534 void *req_addr;
535 void *rsp_addr;
536 dma_addr_t req_dma_handle;
537 dma_addr_t rsp_dma_handle;
538 __le32 adapter_id;
539 __le32 adapter_id_hi;
540 __le16 req_func_type;
541 __le32 req_data;
542 __le32 req_data_extra;
543 __le32 result;
544 __le32 seq_number;
545 __le16 fw_flags;
546 struct completion fxiocb_comp;
547 __le32 reserved_0;
548 uint8_t reserved_1;
549 } fxiocb;
550 struct {
551 uint32_t cmd_hndl;
552 __le16 comp_status;
553 __le16 req_que_no;
554 struct completion comp;
555 } abt;
556 struct ct_arg ctarg;
557#define MAX_IOCB_MB_REG 28
558#define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
559 struct {
560 u16 in_mb[MAX_IOCB_MB_REG];
561 u16 out_mb[MAX_IOCB_MB_REG];
562 void *out, *in;
563 dma_addr_t out_dma, in_dma;
564 struct completion comp;
565 int rc;
566 } mbx;
567 struct {
568 struct imm_ntfy_from_isp *ntfy;
569 } nack;
570 struct {
571 __le16 comp_status;
572 __le16 rsp_pyld_len;
573 uint8_t aen_op;
574 void *desc;
575
576
577 int cmd_len;
578 int rsp_len;
579 dma_addr_t cmd_dma;
580 dma_addr_t rsp_dma;
581 enum nvmefc_fcp_datadir dir;
582 uint32_t dl;
583 uint32_t timeout_sec;
584 struct list_head entry;
585 } nvme;
586 struct {
587 u16 cmd;
588 u16 vp_index;
589 } ctrlvp;
590 } u;
591
592 struct timer_list timer;
593 void (*timeout)(void *);
594};
595
596
597#define SRB_LOGIN_CMD 1
598#define SRB_LOGOUT_CMD 2
599#define SRB_ELS_CMD_RPT 3
600#define SRB_ELS_CMD_HST 4
601#define SRB_CT_CMD 5
602#define SRB_ADISC_CMD 6
603#define SRB_TM_CMD 7
604#define SRB_SCSI_CMD 8
605#define SRB_BIDI_CMD 9
606#define SRB_FXIOCB_DCMD 10
607#define SRB_FXIOCB_BCMD 11
608#define SRB_ABT_CMD 12
609#define SRB_ELS_DCMD 13
610#define SRB_MB_IOCB 14
611#define SRB_CT_PTHRU_CMD 15
612#define SRB_NACK_PLOGI 16
613#define SRB_NACK_PRLI 17
614#define SRB_NACK_LOGO 18
615#define SRB_NVME_CMD 19
616#define SRB_NVME_LS 20
617#define SRB_PRLI_CMD 21
618#define SRB_CTRL_VP 22
619#define SRB_PRLO_CMD 23
620
621enum {
622 TYPE_SRB,
623 TYPE_TGT_CMD,
624 TYPE_TGT_TMCMD,
625};
626
627struct iocb_resource {
628 u8 res_type;
629 u8 pad;
630 u16 iocb_cnt;
631};
632
633typedef struct srb {
634
635
636
637
638 uint8_t cmd_type;
639 uint8_t pad[3];
640 struct iocb_resource iores;
641 struct kref cmd_kref;
642 void *priv;
643 wait_queue_head_t nvme_ls_waitq;
644 struct fc_port *fcport;
645 struct scsi_qla_host *vha;
646 unsigned int start_timer:1;
647
648 uint32_t handle;
649 uint16_t flags;
650 uint16_t type;
651 const char *name;
652 int iocbs;
653 struct qla_qpair *qpair;
654 struct srb *cmd_sp;
655 struct list_head elem;
656 u32 gen1;
657 u32 gen2;
658 int rc;
659 int retry_count;
660 struct completion *comp;
661 union {
662 struct srb_iocb iocb_cmd;
663 struct bsg_job *bsg_job;
664 struct srb_cmd scmd;
665 } u;
666
667
668
669
670
671 void (*done)(struct srb *sp, int res);
672
673 void (*free)(struct srb *sp);
674
675
676
677
678 void (*put_fn)(struct kref *kref);
679} srb_t;
680
681#define GET_CMD_SP(sp) (sp->u.scmd.cmd)
682
683#define GET_CMD_SENSE_LEN(sp) \
684 (sp->u.scmd.request_sense_length)
685#define SET_CMD_SENSE_LEN(sp, len) \
686 (sp->u.scmd.request_sense_length = len)
687#define GET_CMD_SENSE_PTR(sp) \
688 (sp->u.scmd.request_sense_ptr)
689#define SET_CMD_SENSE_PTR(sp, ptr) \
690 (sp->u.scmd.request_sense_ptr = ptr)
691#define GET_FW_SENSE_LEN(sp) \
692 (sp->u.scmd.fw_sense_length)
693#define SET_FW_SENSE_LEN(sp, len) \
694 (sp->u.scmd.fw_sense_length = len)
695
696struct msg_echo_lb {
697 dma_addr_t send_dma;
698 dma_addr_t rcv_dma;
699 uint16_t req_sg_cnt;
700 uint16_t rsp_sg_cnt;
701 uint16_t options;
702 uint32_t transfer_size;
703 uint32_t iteration_count;
704};
705
706
707
708
709struct device_reg_2xxx {
710 __le16 flash_address;
711 __le16 flash_data;
712 __le16 unused_1[1];
713 __le16 ctrl_status;
714#define CSR_FLASH_64K_BANK BIT_3
715#define CSR_FLASH_ENABLE BIT_1
716#define CSR_ISP_SOFT_RESET BIT_0
717
718 __le16 ictrl;
719#define ICR_EN_INT BIT_15
720#define ICR_EN_RISC BIT_3
721
722 __le16 istatus;
723#define ISR_RISC_INT BIT_3
724
725 __le16 semaphore;
726 __le16 nvram;
727#define NVR_DESELECT 0
728#define NVR_BUSY BIT_15
729#define NVR_WRT_ENABLE BIT_14
730#define NVR_PR_ENABLE BIT_13
731#define NVR_DATA_IN BIT_3
732#define NVR_DATA_OUT BIT_2
733#define NVR_SELECT BIT_1
734#define NVR_CLOCK BIT_0
735
736#define NVR_WAIT_CNT 20000
737
738 union {
739 struct {
740 __le16 mailbox0;
741 __le16 mailbox1;
742 __le16 mailbox2;
743 __le16 mailbox3;
744 __le16 mailbox4;
745 __le16 mailbox5;
746 __le16 mailbox6;
747 __le16 mailbox7;
748 __le16 unused_2[59];
749 } __attribute__((packed)) isp2100;
750 struct {
751
752 __le16 req_q_in;
753 __le16 req_q_out;
754
755 __le16 rsp_q_in;
756 __le16 rsp_q_out;
757
758
759 __le32 host_status;
760#define HSR_RISC_INT BIT_15
761#define HSR_RISC_PAUSED BIT_8
762
763
764 __le16 host_semaphore;
765 __le16 unused_3[17];
766 __le16 mailbox0;
767 __le16 mailbox1;
768 __le16 mailbox2;
769 __le16 mailbox3;
770 __le16 mailbox4;
771 __le16 mailbox5;
772 __le16 mailbox6;
773 __le16 mailbox7;
774 __le16 mailbox8;
775 __le16 mailbox9;
776 __le16 mailbox10;
777 __le16 mailbox11;
778 __le16 mailbox12;
779 __le16 mailbox13;
780 __le16 mailbox14;
781 __le16 mailbox15;
782 __le16 mailbox16;
783 __le16 mailbox17;
784 __le16 mailbox18;
785 __le16 mailbox19;
786 __le16 mailbox20;
787 __le16 mailbox21;
788 __le16 mailbox22;
789 __le16 mailbox23;
790 __le16 mailbox24;
791 __le16 mailbox25;
792 __le16 mailbox26;
793 __le16 mailbox27;
794 __le16 mailbox28;
795 __le16 mailbox29;
796 __le16 mailbox30;
797 __le16 mailbox31;
798 __le16 fb_cmd;
799 __le16 unused_4[10];
800 } __attribute__((packed)) isp2300;
801 } u;
802
803 __le16 fpm_diag_config;
804 __le16 unused_5[0x4];
805 __le16 risc_hw;
806 __le16 unused_5_1;
807 __le16 pcr;
808 __le16 unused_6[0x5];
809 __le16 mctr;
810 __le16 unused_7[0x3];
811 __le16 fb_cmd_2100;
812 __le16 unused_8[0x3];
813 __le16 hccr;
814#define HCCR_HOST_INT BIT_7
815#define HCCR_RISC_PAUSE BIT_5
816
817#define HCCR_RESET_RISC 0x1000
818#define HCCR_PAUSE_RISC 0x2000
819#define HCCR_RELEASE_RISC 0x3000
820#define HCCR_SET_HOST_INT 0x5000
821#define HCCR_CLR_HOST_INT 0x6000
822#define HCCR_CLR_RISC_INT 0x7000
823#define HCCR_DISABLE_PARITY_PAUSE 0x4001
824#define HCCR_ENABLE_PARITY 0xA000
825
826 __le16 unused_9[5];
827 __le16 gpiod;
828 __le16 gpioe;
829#define GPIO_LED_MASK 0x00C0
830#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
831#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
832#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
833#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
834#define GPIO_LED_ALL_OFF 0x0000
835#define GPIO_LED_RED_ON_OTHER_OFF 0x0001
836#define GPIO_LED_RGA_ON 0x00C1
837
838 union {
839 struct {
840 __le16 unused_10[8];
841 __le16 mailbox8;
842 __le16 mailbox9;
843 __le16 mailbox10;
844 __le16 mailbox11;
845 __le16 mailbox12;
846 __le16 mailbox13;
847 __le16 mailbox14;
848 __le16 mailbox15;
849 __le16 mailbox16;
850 __le16 mailbox17;
851 __le16 mailbox18;
852 __le16 mailbox19;
853 __le16 mailbox20;
854 __le16 mailbox21;
855 __le16 mailbox22;
856 __le16 mailbox23;
857 } __attribute__((packed)) isp2200;
858 } u_end;
859};
860
861struct device_reg_25xxmq {
862 __le32 req_q_in;
863 __le32 req_q_out;
864 __le32 rsp_q_in;
865 __le32 rsp_q_out;
866 __le32 atio_q_in;
867 __le32 atio_q_out;
868};
869
870
871struct device_reg_fx00 {
872 __le32 mailbox0;
873 __le32 mailbox1;
874 __le32 mailbox2;
875 __le32 mailbox3;
876 __le32 mailbox4;
877 __le32 mailbox5;
878 __le32 mailbox6;
879 __le32 mailbox7;
880 __le32 mailbox8;
881 __le32 mailbox9;
882 __le32 mailbox10;
883 __le32 mailbox11;
884 __le32 mailbox12;
885 __le32 mailbox13;
886 __le32 mailbox14;
887 __le32 mailbox15;
888 __le32 mailbox16;
889 __le32 mailbox17;
890 __le32 mailbox18;
891 __le32 mailbox19;
892 __le32 mailbox20;
893 __le32 mailbox21;
894 __le32 mailbox22;
895 __le32 mailbox23;
896 __le32 mailbox24;
897 __le32 mailbox25;
898 __le32 mailbox26;
899 __le32 mailbox27;
900 __le32 mailbox28;
901 __le32 mailbox29;
902 __le32 mailbox30;
903 __le32 mailbox31;
904 __le32 aenmailbox0;
905 __le32 aenmailbox1;
906 __le32 aenmailbox2;
907 __le32 aenmailbox3;
908 __le32 aenmailbox4;
909 __le32 aenmailbox5;
910 __le32 aenmailbox6;
911 __le32 aenmailbox7;
912
913 __le32 req_q_in;
914 __le32 req_q_out;
915
916 __le32 rsp_q_in;
917 __le32 rsp_q_out;
918
919 __le32 initval0;
920 __le32 initval1;
921 __le32 initval2;
922 __le32 initval3;
923 __le32 initval4;
924 __le32 initval5;
925 __le32 initval6;
926 __le32 initval7;
927 __le32 fwheartbeat;
928 __le32 pseudoaen;
929};
930
931
932
933typedef union {
934 struct device_reg_2xxx isp;
935 struct device_reg_24xx isp24;
936 struct device_reg_25xxmq isp25mq;
937 struct device_reg_82xx isp82;
938 struct device_reg_fx00 ispfx00;
939} __iomem device_reg_t;
940
941#define ISP_REQ_Q_IN(ha, reg) \
942 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
943 &(reg)->u.isp2100.mailbox4 : \
944 &(reg)->u.isp2300.req_q_in)
945#define ISP_REQ_Q_OUT(ha, reg) \
946 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
947 &(reg)->u.isp2100.mailbox4 : \
948 &(reg)->u.isp2300.req_q_out)
949#define ISP_RSP_Q_IN(ha, reg) \
950 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
951 &(reg)->u.isp2100.mailbox5 : \
952 &(reg)->u.isp2300.rsp_q_in)
953#define ISP_RSP_Q_OUT(ha, reg) \
954 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
955 &(reg)->u.isp2100.mailbox5 : \
956 &(reg)->u.isp2300.rsp_q_out)
957
958#define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
959#define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
960
961#define MAILBOX_REG(ha, reg, num) \
962 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
963 (num < 8 ? \
964 &(reg)->u.isp2100.mailbox0 + (num) : \
965 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
966 &(reg)->u.isp2300.mailbox0 + (num))
967#define RD_MAILBOX_REG(ha, reg, num) \
968 rd_reg_word(MAILBOX_REG(ha, reg, num))
969#define WRT_MAILBOX_REG(ha, reg, num, data) \
970 wrt_reg_word(MAILBOX_REG(ha, reg, num), data)
971
972#define FB_CMD_REG(ha, reg) \
973 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
974 &(reg)->fb_cmd_2100 : \
975 &(reg)->u.isp2300.fb_cmd)
976#define RD_FB_CMD_REG(ha, reg) \
977 rd_reg_word(FB_CMD_REG(ha, reg))
978#define WRT_FB_CMD_REG(ha, reg, data) \
979 wrt_reg_word(FB_CMD_REG(ha, reg), data)
980
981typedef struct {
982 uint32_t out_mb;
983 uint32_t in_mb;
984 uint16_t mb[MAILBOX_REGISTER_COUNT];
985 long buf_size;
986 void *bufp;
987 uint32_t tov;
988 uint8_t flags;
989#define MBX_DMA_IN BIT_0
990#define MBX_DMA_OUT BIT_1
991#define IOCTL_CMD BIT_2
992} mbx_cmd_t;
993
994struct mbx_cmd_32 {
995 uint32_t out_mb;
996 uint32_t in_mb;
997 uint32_t mb[MAILBOX_REGISTER_COUNT];
998 long buf_size;
999 void *bufp;
1000 uint32_t tov;
1001 uint8_t flags;
1002#define MBX_DMA_IN BIT_0
1003#define MBX_DMA_OUT BIT_1
1004#define IOCTL_CMD BIT_2
1005};
1006
1007
1008#define MBX_TOV_SECONDS 30
1009
1010
1011
1012
1013#define PROD_ID_1 0x4953
1014#define PROD_ID_2 0x0000
1015#define PROD_ID_2a 0x5020
1016#define PROD_ID_3 0x2020
1017
1018
1019
1020
1021#define MBS_FRM_ALIVE 0
1022#define MBS_CHKSUM_ERR 1
1023#define MBS_BUSY 4
1024
1025
1026
1027
1028#define MBS_COMMAND_COMPLETE 0x4000
1029#define MBS_INVALID_COMMAND 0x4001
1030#define MBS_HOST_INTERFACE_ERROR 0x4002
1031#define MBS_TEST_FAILED 0x4003
1032#define MBS_COMMAND_ERROR 0x4005
1033#define MBS_COMMAND_PARAMETER_ERROR 0x4006
1034#define MBS_PORT_ID_USED 0x4007
1035#define MBS_LOOP_ID_USED 0x4008
1036#define MBS_ALL_IDS_IN_USE 0x4009
1037#define MBS_NOT_LOGGED_IN 0x400A
1038#define MBS_LINK_DOWN_ERROR 0x400B
1039#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1040
1041static inline bool qla2xxx_is_valid_mbs(unsigned int mbs)
1042{
1043 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR;
1044}
1045
1046
1047
1048
1049#define MBA_ASYNC_EVENT 0x8000
1050#define MBA_RESET 0x8001
1051#define MBA_SYSTEM_ERR 0x8002
1052#define MBA_REQ_TRANSFER_ERR 0x8003
1053#define MBA_RSP_TRANSFER_ERR 0x8004
1054#define MBA_WAKEUP_THRES 0x8005
1055#define MBA_LIP_OCCURRED 0x8010
1056
1057#define MBA_LOOP_UP 0x8011
1058#define MBA_LOOP_DOWN 0x8012
1059#define MBA_LIP_RESET 0x8013
1060#define MBA_PORT_UPDATE 0x8014
1061#define MBA_RSCN_UPDATE 0x8015
1062#define MBA_LIP_F8 0x8016
1063#define MBA_LOOP_INIT_ERR 0x8017
1064#define MBA_FABRIC_AUTH_REQ 0x801b
1065#define MBA_CONGN_NOTI_RECV 0x801e
1066#define MBA_SCSI_COMPLETION 0x8020
1067#define MBA_CTIO_COMPLETION 0x8021
1068#define MBA_IP_COMPLETION 0x8022
1069#define MBA_IP_RECEIVE 0x8023
1070#define MBA_IP_BROADCAST 0x8024
1071#define MBA_IP_LOW_WATER_MARK 0x8025
1072#define MBA_IP_RCV_BUFFER_EMPTY 0x8026
1073#define MBA_IP_HDR_DATA_SPLIT 0x8027
1074
1075#define MBA_TRACE_NOTIFICATION 0x8028
1076#define MBA_POINT_TO_POINT 0x8030
1077#define MBA_CMPLT_1_16BIT 0x8031
1078#define MBA_CMPLT_2_16BIT 0x8032
1079#define MBA_CMPLT_3_16BIT 0x8033
1080#define MBA_CMPLT_4_16BIT 0x8034
1081#define MBA_CMPLT_5_16BIT 0x8035
1082#define MBA_CHG_IN_CONNECTION 0x8036
1083#define MBA_RIO_RESPONSE 0x8040
1084#define MBA_ZIO_RESPONSE 0x8040
1085#define MBA_CMPLT_2_32BIT 0x8042
1086#define MBA_BYPASS_NOTIFICATION 0x8043
1087#define MBA_DISCARD_RND_FRAME 0x8048
1088#define MBA_REJECTED_FCP_CMD 0x8049
1089#define MBA_FW_NOT_STARTED 0x8050
1090#define MBA_FW_STARTING 0x8051
1091#define MBA_FW_RESTART_CMPLT 0x8060
1092#define MBA_INIT_REQUIRED 0x8061
1093#define MBA_SHUTDOWN_REQUESTED 0x8062
1094#define MBA_TEMPERATURE_ALERT 0x8070
1095#define MBA_DPORT_DIAGNOSTICS 0x8080
1096#define MBA_TRANS_INSERT 0x8130
1097#define MBA_TRANS_REMOVE 0x8131
1098#define MBA_FW_INIT_FAILURE 0x8401
1099#define MBA_MIRROR_LUN_CHANGE 0x8402
1100
1101#define MBA_FW_POLL_STATE 0x8600
1102#define MBA_FW_RESET_FCT 0x8502
1103#define MBA_FW_INIT_INPROGRESS 0x8500
1104
1105#define MBA_IDC_AEN 0x8200
1106
1107
1108#define INTR_ROM_MB_SUCCESS 0x1
1109#define INTR_ROM_MB_FAILED 0x2
1110#define INTR_MB_SUCCESS 0x10
1111#define INTR_MB_FAILED 0x11
1112#define INTR_ASYNC_EVENT 0x12
1113#define INTR_RSP_QUE_UPDATE 0x13
1114#define INTR_RSP_QUE_UPDATE_83XX 0x14
1115#define INTR_ATIO_QUE_UPDATE 0x1C
1116#define INTR_ATIO_RSP_QUE_UPDATE 0x1D
1117#define INTR_ATIO_QUE_UPDATE_27XX 0x1E
1118
1119
1120#define MBS_LB_RESET 0x17
1121
1122
1123
1124#define FO1_AE_ON_LIPF8 BIT_0
1125#define FO1_AE_ALL_LIP_RESET BIT_1
1126#define FO1_CTIO_RETRY BIT_3
1127#define FO1_DISABLE_LIP_F7_SW BIT_4
1128#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1129#define FO1_DISABLE_GPIO6_7 BIT_6
1130#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1131#define FO1_SET_EMPHASIS_SWING BIT_8
1132#define FO1_AE_AUTO_BYPASS BIT_9
1133#define FO1_ENABLE_PURE_IOCB BIT_10
1134#define FO1_AE_PLOGI_RJT BIT_11
1135#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1136#define FO1_AE_QUEUE_FULL BIT_13
1137
1138#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1139#define FO2_REV_LOOPBACK BIT_1
1140
1141#define FO3_ENABLE_EMERG_IOCB BIT_0
1142#define FO3_AE_RND_ERROR BIT_1
1143
1144
1145#define ADD_FO_COUNT 3
1146#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6
1147#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1148
1149#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1150
1151#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1152
1153
1154
1155
1156#define MBC_LOAD_RAM 1
1157#define MBC_EXECUTE_FIRMWARE 2
1158#define MBC_READ_RAM_WORD 5
1159#define MBC_MAILBOX_REGISTER_TEST 6
1160#define MBC_VERIFY_CHECKSUM 7
1161#define MBC_GET_FIRMWARE_VERSION 8
1162#define MBC_LOAD_RISC_RAM 9
1163#define MBC_DUMP_RISC_RAM 0xa
1164#define MBC_SECURE_FLASH_UPDATE 0xa
1165#define MBC_LOAD_RISC_RAM_EXTENDED 0xb
1166#define MBC_DUMP_RISC_RAM_EXTENDED 0xc
1167#define MBC_WRITE_RAM_WORD_EXTENDED 0xd
1168#define MBC_READ_RAM_EXTENDED 0xf
1169#define MBC_IOCB_COMMAND 0x12
1170#define MBC_STOP_FIRMWARE 0x14
1171#define MBC_ABORT_COMMAND 0x15
1172#define MBC_ABORT_DEVICE 0x16
1173#define MBC_ABORT_TARGET 0x17
1174#define MBC_RESET 0x18
1175#define MBC_GET_ADAPTER_LOOP_ID 0x20
1176#define MBC_GET_SET_ZIO_THRESHOLD 0x21
1177#define MBC_GET_RETRY_COUNT 0x22
1178#define MBC_DISABLE_VI 0x24
1179#define MBC_ENABLE_VI 0x25
1180#define MBC_GET_FIRMWARE_OPTION 0x28
1181#define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34
1182#define MBC_SET_FIRMWARE_OPTION 0x38
1183#define MBC_SET_GET_FC_LED_CONFIG 0x3b
1184#define MBC_LOOP_PORT_BYPASS 0x40
1185#define MBC_LOOP_PORT_ENABLE 0x41
1186#define MBC_GET_RESOURCE_COUNTS 0x42
1187#define MBC_NON_PARTICIPATE 0x43
1188#define MBC_DIAGNOSTIC_ECHO 0x44
1189#define MBC_DIAGNOSTIC_LOOP_BACK 0x45
1190#define MBC_ONLINE_SELF_TEST 0x46
1191#define MBC_ENHANCED_GET_PORT_DATABASE 0x47
1192#define MBC_CONFIGURE_VF 0x4b
1193#define MBC_RESET_LINK_STATUS 0x52
1194#define MBC_IOCB_COMMAND_A64 0x54
1195#define MBC_PORT_LOGOUT 0x56
1196#define MBC_SEND_RNID_ELS 0x57
1197#define MBC_SET_RNID_PARAMS 0x59
1198#define MBC_GET_RNID_PARAMS 0x5a
1199#define MBC_DATA_RATE 0x5d
1200#define MBC_INITIALIZE_FIRMWARE 0x60
1201#define MBC_INITIATE_LIP 0x62
1202
1203#define MBC_GET_FC_AL_POSITION_MAP 0x63
1204#define MBC_GET_PORT_DATABASE 0x64
1205#define MBC_CLEAR_ACA 0x65
1206#define MBC_TARGET_RESET 0x66
1207#define MBC_CLEAR_TASK_SET 0x67
1208#define MBC_ABORT_TASK_SET 0x68
1209#define MBC_GET_FIRMWARE_STATE 0x69
1210#define MBC_GET_PORT_NAME 0x6a
1211#define MBC_GET_LINK_STATUS 0x6b
1212#define MBC_LIP_RESET 0x6c
1213#define MBC_SEND_SNS_COMMAND 0x6e
1214
1215#define MBC_LOGIN_FABRIC_PORT 0x6f
1216#define MBC_SEND_CHANGE_REQUEST 0x70
1217#define MBC_LOGOUT_FABRIC_PORT 0x71
1218#define MBC_LIP_FULL_LOGIN 0x72
1219#define MBC_LOGIN_LOOP_PORT 0x74
1220#define MBC_PORT_NODE_NAME_LIST 0x75
1221#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77
1222#define MBC_UNLOAD_IP 0x79
1223#define MBC_GET_ID_LIST 0x7C
1224#define MBC_SEND_LFA_COMMAND 0x7D
1225#define MBC_LUN_RESET 0x7E
1226
1227
1228
1229
1230
1231#define MBC_MR_DRV_SHUTDOWN 0x6A
1232
1233
1234
1235
1236#define MBC_WRITE_SERDES 0x3
1237#define MBC_READ_SERDES 0x4
1238#define MBC_LOAD_DUMP_MPI_RAM 0x5
1239#define MBC_SERDES_PARAMS 0x10
1240#define MBC_GET_IOCB_STATUS 0x12
1241#define MBC_PORT_PARAMS 0x1A
1242#define MBC_GET_TIMEOUT_PARAMS 0x22
1243#define MBC_TRACE_CONTROL 0x27
1244#define MBC_GEN_SYSTEM_ERROR 0x2a
1245#define MBC_WRITE_SFP 0x30
1246#define MBC_READ_SFP 0x31
1247#define MBC_SET_TIMEOUT_PARAMS 0x32
1248#define MBC_DPORT_DIAGNOSTICS 0x47
1249#define MBC_MID_INITIALIZE_FIRMWARE 0x48
1250#define MBC_MID_GET_VP_DATABASE 0x49
1251#define MBC_MID_GET_VP_ENTRY 0x4a
1252#define MBC_HOST_MEMORY_COPY 0x53
1253#define MBC_SEND_RNFT_ELS 0x5e
1254#define MBC_GET_LINK_PRIV_STATS 0x6d
1255#define MBC_LINK_INITIALIZATION 0x72
1256#define MBC_SET_VENDOR_ID 0x76
1257#define MBC_PORT_RESET 0x120
1258#define MBC_SET_PORT_CONFIG 0x122
1259#define MBC_GET_PORT_CONFIG 0x123
1260
1261
1262
1263
1264#define MBC_WRITE_MPI_REGISTER 0x01
1265
1266
1267
1268
1269#define MBC_SET_GET_ETH_SERDES_REG 0x150
1270#define HCS_WRITE_SERDES 0x3
1271#define HCS_READ_SERDES 0x4
1272
1273
1274#define FCAL_MAP_SIZE 128
1275
1276
1277#define MBX_31 BIT_31
1278#define MBX_30 BIT_30
1279#define MBX_29 BIT_29
1280#define MBX_28 BIT_28
1281#define MBX_27 BIT_27
1282#define MBX_26 BIT_26
1283#define MBX_25 BIT_25
1284#define MBX_24 BIT_24
1285#define MBX_23 BIT_23
1286#define MBX_22 BIT_22
1287#define MBX_21 BIT_21
1288#define MBX_20 BIT_20
1289#define MBX_19 BIT_19
1290#define MBX_18 BIT_18
1291#define MBX_17 BIT_17
1292#define MBX_16 BIT_16
1293#define MBX_15 BIT_15
1294#define MBX_14 BIT_14
1295#define MBX_13 BIT_13
1296#define MBX_12 BIT_12
1297#define MBX_11 BIT_11
1298#define MBX_10 BIT_10
1299#define MBX_9 BIT_9
1300#define MBX_8 BIT_8
1301#define MBX_7 BIT_7
1302#define MBX_6 BIT_6
1303#define MBX_5 BIT_5
1304#define MBX_4 BIT_4
1305#define MBX_3 BIT_3
1306#define MBX_2 BIT_2
1307#define MBX_1 BIT_1
1308#define MBX_0 BIT_0
1309
1310#define RNID_TYPE_ELS_CMD 0x5
1311#define RNID_TYPE_PORT_LOGIN 0x7
1312#define RNID_BUFFER_CREDITS 0x8
1313#define RNID_TYPE_SET_VERSION 0x9
1314#define RNID_TYPE_ASIC_TEMP 0xC
1315
1316#define ELS_CMD_MAP_SIZE 32
1317
1318
1319
1320
1321#define FSTATE_CONFIG_WAIT 0
1322#define FSTATE_WAIT_AL_PA 1
1323#define FSTATE_WAIT_LOGIN 2
1324#define FSTATE_READY 3
1325#define FSTATE_LOSS_OF_SYNC 4
1326#define FSTATE_ERROR 5
1327#define FSTATE_REINIT 6
1328#define FSTATE_NON_PART 7
1329
1330#define FSTATE_CONFIG_CORRECT 0
1331#define FSTATE_P2P_RCV_LIP 1
1332#define FSTATE_P2P_CHOOSE_LOOP 2
1333#define FSTATE_P2P_RCV_UNIDEN_LIP 3
1334#define FSTATE_FATAL_ERROR 4
1335#define FSTATE_LOOP_BACK_CONN 5
1336
1337#define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1338#define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1339#define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1340#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1341#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1342#define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
1343#define QLA27XX_DEFAULT_IMAGE 0
1344#define QLA27XX_PRIMARY_IMAGE 1
1345#define QLA27XX_SECONDARY_IMAGE 2
1346
1347
1348
1349
1350
1351#define PORT_DATABASE_SIZE 128
1352typedef struct {
1353 uint8_t options;
1354 uint8_t control;
1355 uint8_t master_state;
1356 uint8_t slave_state;
1357 uint8_t reserved[2];
1358 uint8_t hard_address;
1359 uint8_t reserved_1;
1360 uint8_t port_id[4];
1361 uint8_t node_name[WWN_SIZE];
1362 uint8_t port_name[WWN_SIZE];
1363 __le16 execution_throttle;
1364 uint16_t execution_count;
1365 uint8_t reset_count;
1366 uint8_t reserved_2;
1367 uint16_t resource_allocation;
1368 uint16_t current_allocation;
1369 uint16_t queue_head;
1370 uint16_t queue_tail;
1371 uint16_t transmit_execution_list_next;
1372 uint16_t transmit_execution_list_previous;
1373 uint16_t common_features;
1374 uint16_t total_concurrent_sequences;
1375 uint16_t RO_by_information_category;
1376 uint8_t recipient;
1377 uint8_t initiator;
1378 uint16_t receive_data_size;
1379 uint16_t concurrent_sequences;
1380 uint16_t open_sequences_per_exchange;
1381 uint16_t lun_abort_flags;
1382 uint16_t lun_stop_flags;
1383 uint16_t stop_queue_head;
1384 uint16_t stop_queue_tail;
1385 uint16_t port_retry_timer;
1386 uint16_t next_sequence_id;
1387 uint16_t frame_count;
1388 uint16_t PRLI_payload_length;
1389 uint8_t prli_svc_param_word_0[2];
1390
1391 uint8_t prli_svc_param_word_3[2];
1392
1393 uint16_t loop_id;
1394 uint16_t extended_lun_info_list_pointer;
1395 uint16_t extended_lun_stop_list_pointer;
1396} port_database_t;
1397
1398
1399
1400
1401#define PD_STATE_DISCOVERY 0
1402#define PD_STATE_WAIT_DISCOVERY_ACK 1
1403#define PD_STATE_PORT_LOGIN 2
1404#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1405#define PD_STATE_PROCESS_LOGIN 4
1406#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1407#define PD_STATE_PORT_LOGGED_IN 6
1408#define PD_STATE_PORT_UNAVAILABLE 7
1409#define PD_STATE_PROCESS_LOGOUT 8
1410#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1411#define PD_STATE_PORT_LOGOUT 10
1412#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1413
1414
1415#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1416#define QLA_ZIO_DISABLED 0
1417#define QLA_ZIO_DEFAULT_TIMER 2
1418
1419
1420
1421
1422
1423#define ICB_VERSION 1
1424typedef struct {
1425 uint8_t version;
1426 uint8_t reserved_1;
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447 uint8_t firmware_options[2];
1448
1449 __le16 frame_payload_size;
1450 __le16 max_iocb_allocation;
1451 __le16 execution_throttle;
1452 uint8_t retry_count;
1453 uint8_t retry_delay;
1454 uint8_t port_name[WWN_SIZE];
1455 uint16_t hard_address;
1456 uint8_t inquiry_data;
1457 uint8_t login_timeout;
1458 uint8_t node_name[WWN_SIZE];
1459
1460 __le16 request_q_outpointer;
1461 __le16 response_q_inpointer;
1462 __le16 request_q_length;
1463 __le16 response_q_length;
1464 __le64 request_q_address __packed;
1465 __le64 response_q_address __packed;
1466
1467 __le16 lun_enables;
1468 uint8_t command_resource_count;
1469 uint8_t immediate_notify_resource_count;
1470 __le16 timeout;
1471 uint8_t reserved_2[2];
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492 uint8_t add_firmware_options[2];
1493
1494 uint8_t response_accumulation_timer;
1495 uint8_t interrupt_delay_timer;
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516 uint8_t special_options[2];
1517
1518 uint8_t reserved_3[26];
1519} init_cb_t;
1520
1521
1522struct init_sf_cb {
1523 uint8_t format;
1524 uint8_t reserved0;
1525
1526
1527
1528
1529
1530
1531 __le16 flags;
1532 uint8_t reserved1[32];
1533 uint16_t discard_OHRB_timeout_value;
1534 uint16_t remote_write_opt_queue_num;
1535 uint8_t reserved2[40];
1536 uint8_t scm_related_parameter[16];
1537 uint8_t reserved3[32];
1538};
1539
1540
1541
1542
1543#define GLSO_SEND_RPS BIT_0
1544#define GLSO_USE_DID BIT_3
1545
1546struct link_statistics {
1547 __le32 link_fail_cnt;
1548 __le32 loss_sync_cnt;
1549 __le32 loss_sig_cnt;
1550 __le32 prim_seq_err_cnt;
1551 __le32 inval_xmit_word_cnt;
1552 __le32 inval_crc_cnt;
1553 __le32 lip_cnt;
1554 __le32 link_up_cnt;
1555 __le32 link_down_loop_init_tmo;
1556 __le32 link_down_los;
1557 __le32 link_down_loss_rcv_clk;
1558 uint32_t reserved0[5];
1559 __le32 port_cfg_chg;
1560 uint32_t reserved1[11];
1561 __le32 rsp_q_full;
1562 __le32 atio_q_full;
1563 __le32 drop_ae;
1564 __le32 els_proto_err;
1565 __le32 reserved2;
1566 __le32 tx_frames;
1567 __le32 rx_frames;
1568 __le32 discarded_frames;
1569 __le32 dropped_frames;
1570 uint32_t reserved3;
1571 __le32 nos_rcvd;
1572 uint32_t reserved4[4];
1573 __le32 tx_prjt;
1574 __le32 rcv_exfail;
1575 __le32 rcv_abts;
1576 __le32 seq_frm_miss;
1577 __le32 corr_err;
1578 __le32 mb_rqst;
1579 __le32 nport_full;
1580 __le32 eofa;
1581 uint32_t reserved5;
1582 __le64 fpm_recv_word_cnt;
1583 __le64 fpm_disc_word_cnt;
1584 __le64 fpm_xmit_word_cnt;
1585 uint32_t reserved6[70];
1586};
1587
1588
1589
1590
1591#define NV_START_BIT BIT_2
1592#define NV_WRITE_OP (BIT_26+BIT_24)
1593#define NV_READ_OP (BIT_26+BIT_25)
1594#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1595#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1596#define NV_DELAY_COUNT 10
1597
1598
1599
1600
1601typedef struct {
1602
1603
1604
1605 uint8_t id[4];
1606 uint8_t nvram_version;
1607 uint8_t reserved_0;
1608
1609
1610
1611
1612 uint8_t parameter_block_version;
1613 uint8_t reserved_1;
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634 uint8_t firmware_options[2];
1635
1636 __le16 frame_payload_size;
1637 __le16 max_iocb_allocation;
1638 __le16 execution_throttle;
1639 uint8_t retry_count;
1640 uint8_t retry_delay;
1641 uint8_t port_name[WWN_SIZE];
1642 uint16_t hard_address;
1643 uint8_t inquiry_data;
1644 uint8_t login_timeout;
1645 uint8_t node_name[WWN_SIZE];
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666 uint8_t add_firmware_options[2];
1667
1668 uint8_t response_accumulation_timer;
1669 uint8_t interrupt_delay_timer;
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690 uint8_t special_options[2];
1691
1692
1693 uint8_t reserved_2[22];
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732 uint8_t seriallink_options[4];
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755 uint8_t host_p[2];
1756
1757 uint8_t boot_node_name[WWN_SIZE];
1758 uint8_t boot_lun_number;
1759 uint8_t reset_delay;
1760 uint8_t port_down_retry_count;
1761 uint8_t boot_id_number;
1762 __le16 max_luns_per_target;
1763 uint8_t fcode_boot_port_name[WWN_SIZE];
1764 uint8_t alternate_port_name[WWN_SIZE];
1765 uint8_t alternate_node_name[WWN_SIZE];
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777 uint8_t efi_parameters;
1778
1779 uint8_t link_down_timeout;
1780
1781 uint8_t adapter_id[16];
1782
1783 uint8_t alt1_boot_node_name[WWN_SIZE];
1784 uint16_t alt1_boot_lun_number;
1785 uint8_t alt2_boot_node_name[WWN_SIZE];
1786 uint16_t alt2_boot_lun_number;
1787 uint8_t alt3_boot_node_name[WWN_SIZE];
1788 uint16_t alt3_boot_lun_number;
1789 uint8_t alt4_boot_node_name[WWN_SIZE];
1790 uint16_t alt4_boot_lun_number;
1791 uint8_t alt5_boot_node_name[WWN_SIZE];
1792 uint16_t alt5_boot_lun_number;
1793 uint8_t alt6_boot_node_name[WWN_SIZE];
1794 uint16_t alt6_boot_lun_number;
1795 uint8_t alt7_boot_node_name[WWN_SIZE];
1796 uint16_t alt7_boot_lun_number;
1797
1798 uint8_t reserved_3[2];
1799
1800
1801 uint8_t model_number[16];
1802
1803
1804 uint8_t oem_specific[16];
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827 uint8_t adapter_features[2];
1828
1829 uint8_t reserved_4[16];
1830
1831
1832 uint16_t subsystem_vendor_id_2200;
1833
1834
1835 uint16_t subsystem_device_id_2200;
1836
1837 uint8_t reserved_5;
1838 uint8_t checksum;
1839} nvram_t;
1840
1841
1842
1843
1844typedef struct {
1845 uint8_t entry_type;
1846 uint8_t entry_count;
1847 uint8_t sys_define;
1848 uint8_t entry_status;
1849 uint32_t handle;
1850 uint8_t data[52];
1851 uint32_t signature;
1852#define RESPONSE_PROCESSED 0xDEADDEAD
1853} response_t;
1854
1855
1856
1857
1858struct atio {
1859 uint8_t entry_type;
1860 uint8_t entry_count;
1861 __le16 attr_n_length;
1862 uint8_t data[56];
1863 uint32_t signature;
1864#define ATIO_PROCESSED 0xDEADDEAD
1865};
1866
1867typedef union {
1868 __le16 extended;
1869 struct {
1870 uint8_t reserved;
1871 uint8_t standard;
1872 } id;
1873} target_id_t;
1874
1875#define SET_TARGET_ID(ha, to, from) \
1876do { \
1877 if (HAS_EXTENDED_IDS(ha)) \
1878 to.extended = cpu_to_le16(from); \
1879 else \
1880 to.id.standard = (uint8_t)from; \
1881} while (0)
1882
1883
1884
1885
1886#define COMMAND_TYPE 0x11
1887typedef struct {
1888 uint8_t entry_type;
1889 uint8_t entry_count;
1890 uint8_t sys_define;
1891 uint8_t entry_status;
1892 uint32_t handle;
1893 target_id_t target;
1894 __le16 lun;
1895 __le16 control_flags;
1896#define CF_WRITE BIT_6
1897#define CF_READ BIT_5
1898#define CF_SIMPLE_TAG BIT_3
1899#define CF_ORDERED_TAG BIT_2
1900#define CF_HEAD_TAG BIT_1
1901 uint16_t reserved_1;
1902 __le16 timeout;
1903 __le16 dseg_count;
1904 uint8_t scsi_cdb[MAX_CMDSZ];
1905 __le32 byte_count;
1906 union {
1907 struct dsd32 dsd32[3];
1908 struct dsd64 dsd64[2];
1909 };
1910} cmd_entry_t;
1911
1912
1913
1914
1915#define COMMAND_A64_TYPE 0x19
1916typedef struct {
1917 uint8_t entry_type;
1918 uint8_t entry_count;
1919 uint8_t sys_define;
1920 uint8_t entry_status;
1921 uint32_t handle;
1922 target_id_t target;
1923 __le16 lun;
1924 __le16 control_flags;
1925 uint16_t reserved_1;
1926 __le16 timeout;
1927 __le16 dseg_count;
1928 uint8_t scsi_cdb[MAX_CMDSZ];
1929 uint32_t byte_count;
1930 struct dsd64 dsd[2];
1931} cmd_a64_entry_t, request_t;
1932
1933
1934
1935
1936#define CONTINUE_TYPE 0x02
1937typedef struct {
1938 uint8_t entry_type;
1939 uint8_t entry_count;
1940 uint8_t sys_define;
1941 uint8_t entry_status;
1942 uint32_t reserved;
1943 struct dsd32 dsd[7];
1944} cont_entry_t;
1945
1946
1947
1948
1949#define CONTINUE_A64_TYPE 0x0A
1950typedef struct {
1951 uint8_t entry_type;
1952 uint8_t entry_count;
1953 uint8_t sys_define;
1954 uint8_t entry_status;
1955 struct dsd64 dsd[5];
1956} cont_a64_entry_t;
1957
1958#define PO_MODE_DIF_INSERT 0
1959#define PO_MODE_DIF_REMOVE 1
1960#define PO_MODE_DIF_PASS 2
1961#define PO_MODE_DIF_REPLACE 3
1962#define PO_MODE_DIF_TCP_CKSUM 6
1963#define PO_ENABLE_INCR_GUARD_SEED BIT_3
1964#define PO_DISABLE_GUARD_CHECK BIT_4
1965#define PO_DISABLE_INCR_REF_TAG BIT_5
1966#define PO_DIS_HEADER_MODE BIT_7
1967#define PO_ENABLE_DIF_BUNDLING BIT_8
1968#define PO_DIS_FRAME_MODE BIT_9
1969#define PO_DIS_VALD_APP_ESC BIT_10
1970#define PO_DIS_VALD_APP_REF_ESC BIT_11
1971
1972#define PO_DIS_APP_TAG_REPL BIT_12
1973#define PO_DIS_REF_TAG_REPL BIT_13
1974#define PO_DIS_APP_TAG_VALD BIT_14
1975#define PO_DIS_REF_TAG_VALD BIT_15
1976
1977
1978
1979
1980struct crc_context {
1981 uint32_t handle;
1982 __le32 ref_tag;
1983 __le16 app_tag;
1984 uint8_t ref_tag_mask[4];
1985 uint8_t app_tag_mask[2];
1986 __le16 guard_seed;
1987 __le16 prot_opts;
1988 __le16 blk_size;
1989 __le16 runt_blk_guard;
1990
1991 __le32 byte_count;
1992
1993 union {
1994 struct {
1995 uint32_t reserved_1;
1996 uint16_t reserved_2;
1997 uint16_t reserved_3;
1998 uint32_t reserved_4;
1999 struct dsd64 data_dsd[1];
2000 uint32_t reserved_5[2];
2001 uint32_t reserved_6;
2002 } nobundling;
2003 struct {
2004 __le32 dif_byte_count;
2005
2006 uint16_t reserved_1;
2007 __le16 dseg_count;
2008 uint32_t reserved_2;
2009 struct dsd64 data_dsd[1];
2010 struct dsd64 dif_dsd;
2011 } bundling;
2012 } u;
2013
2014 struct fcp_cmnd fcp_cmnd;
2015 dma_addr_t crc_ctx_dma;
2016
2017 struct list_head dsd_list;
2018
2019
2020 struct list_head ldif_dsd_list;
2021 u8 no_ldif_dsd;
2022
2023 struct list_head ldif_dma_hndl_list;
2024 u32 dif_bundl_len;
2025 u8 no_dif_bundl;
2026
2027};
2028
2029#define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
2030#define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
2031
2032
2033
2034
2035#define STATUS_TYPE 0x03
2036typedef struct {
2037 uint8_t entry_type;
2038 uint8_t entry_count;
2039 uint8_t sys_define;
2040 uint8_t entry_status;
2041 uint32_t handle;
2042 __le16 scsi_status;
2043 __le16 comp_status;
2044 __le16 state_flags;
2045 __le16 status_flags;
2046 __le16 rsp_info_len;
2047 __le16 req_sense_length;
2048 __le32 residual_length;
2049 uint8_t rsp_info[8];
2050 uint8_t req_sense_data[32];
2051} sts_entry_t;
2052
2053
2054
2055
2056#define RF_RQ_DMA_ERROR BIT_6
2057#define RF_INV_E_ORDER BIT_5
2058#define RF_INV_E_COUNT BIT_4
2059#define RF_INV_E_PARAM BIT_3
2060#define RF_INV_E_TYPE BIT_2
2061#define RF_BUSY BIT_1
2062#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
2063 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
2064#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
2065 RF_INV_E_TYPE)
2066
2067
2068
2069
2070#define SS_MASK 0xfff
2071#define SS_RESIDUAL_UNDER BIT_11
2072#define SS_RESIDUAL_OVER BIT_10
2073#define SS_SENSE_LEN_VALID BIT_9
2074#define SS_RESPONSE_INFO_LEN_VALID BIT_8
2075#define SS_SCSI_STATUS_BYTE 0xff
2076
2077#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
2078#define SS_BUSY_CONDITION BIT_3
2079#define SS_CONDITION_MET BIT_2
2080#define SS_CHECK_CONDITION BIT_1
2081
2082
2083
2084
2085#define CS_COMPLETE 0x0
2086#define CS_INCOMPLETE 0x1
2087#define CS_DMA 0x2
2088#define CS_TRANSPORT 0x3
2089#define CS_RESET 0x4
2090#define CS_ABORTED 0x5
2091#define CS_TIMEOUT 0x6
2092#define CS_DATA_OVERRUN 0x7
2093#define CS_DIF_ERROR 0xC
2094
2095#define CS_DATA_UNDERRUN 0x15
2096#define CS_QUEUE_FULL 0x1C
2097#define CS_PORT_UNAVAILABLE 0x28
2098
2099#define CS_PORT_LOGGED_OUT 0x29
2100#define CS_PORT_CONFIG_CHG 0x2A
2101#define CS_PORT_BUSY 0x2B
2102#define CS_COMPLETE_CHKCOND 0x30
2103#define CS_IOCB_ERROR 0x31
2104
2105#define CS_REJECT_RECEIVED 0x4E
2106#define CS_BAD_PAYLOAD 0x80
2107#define CS_UNKNOWN 0x81
2108#define CS_RETRY 0x82
2109#define CS_LOOP_DOWN_ABORT 0x83
2110
2111#define CS_BIDIR_RD_OVERRUN 0x700
2112#define CS_BIDIR_RD_WR_OVERRUN 0x707
2113#define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
2114#define CS_BIDIR_RD_UNDERRUN 0x1500
2115#define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
2116#define CS_BIDIR_RD_WR_UNDERRUN 0x1515
2117#define CS_BIDIR_DMA 0x200
2118
2119
2120
2121#define SF_ABTS_TERMINATED BIT_10
2122#define SF_LOGOUT_SENT BIT_13
2123
2124
2125
2126
2127#define STATUS_CONT_TYPE 0x10
2128typedef struct {
2129 uint8_t entry_type;
2130 uint8_t entry_count;
2131 uint8_t sys_define;
2132 uint8_t entry_status;
2133 uint8_t data[60];
2134} sts_cont_entry_t;
2135
2136
2137
2138
2139
2140#define STATUS_TYPE_21 0x21
2141typedef struct {
2142 uint8_t entry_type;
2143 uint8_t entry_count;
2144 uint8_t handle_count;
2145 uint8_t entry_status;
2146 uint32_t handle[15];
2147} sts21_entry_t;
2148
2149
2150
2151
2152
2153#define STATUS_TYPE_22 0x22
2154typedef struct {
2155 uint8_t entry_type;
2156 uint8_t entry_count;
2157 uint8_t handle_count;
2158 uint8_t entry_status;
2159 uint16_t handle[30];
2160} sts22_entry_t;
2161
2162
2163
2164
2165#define MARKER_TYPE 0x04
2166typedef struct {
2167 uint8_t entry_type;
2168 uint8_t entry_count;
2169 uint8_t handle_count;
2170 uint8_t entry_status;
2171 uint32_t sys_define_2;
2172 target_id_t target;
2173 uint8_t modifier;
2174#define MK_SYNC_ID_LUN 0
2175#define MK_SYNC_ID 1
2176#define MK_SYNC_ALL 2
2177#define MK_SYNC_LIP 3
2178
2179
2180 uint8_t reserved_1;
2181 __le16 sequence_number;
2182 __le16 lun;
2183 uint8_t reserved_2[48];
2184} mrk_entry_t;
2185
2186
2187
2188
2189#define MS_IOCB_TYPE 0x29
2190typedef struct {
2191 uint8_t entry_type;
2192 uint8_t entry_count;
2193 uint8_t handle_count;
2194 uint8_t entry_status;
2195 uint32_t handle1;
2196 target_id_t loop_id;
2197 __le16 status;
2198 __le16 control_flags;
2199 uint16_t reserved2;
2200 __le16 timeout;
2201 __le16 cmd_dsd_count;
2202 __le16 total_dsd_count;
2203 uint8_t type;
2204 uint8_t r_ctl;
2205 __le16 rx_id;
2206 uint16_t reserved3;
2207 uint32_t handle2;
2208 __le32 rsp_bytecount;
2209 __le32 req_bytecount;
2210 struct dsd64 req_dsd;
2211 struct dsd64 rsp_dsd;
2212} ms_iocb_entry_t;
2213
2214#define SCM_EDC_ACC_RECEIVED BIT_6
2215#define SCM_RDF_ACC_RECEIVED BIT_7
2216
2217
2218
2219
2220#define MBX_IOCB_TYPE 0x39
2221struct mbx_entry {
2222 uint8_t entry_type;
2223 uint8_t entry_count;
2224 uint8_t sys_define1;
2225
2226#define SOURCE_SCSI 0x00
2227#define SOURCE_IP 0x01
2228#define SOURCE_VI 0x02
2229#define SOURCE_SCTP 0x03
2230#define SOURCE_MP 0x04
2231#define SOURCE_MPIOCTL 0x05
2232#define SOURCE_ASYNC_IOCB 0x07
2233
2234 uint8_t entry_status;
2235
2236 uint32_t handle;
2237 target_id_t loop_id;
2238
2239 __le16 status;
2240 __le16 state_flags;
2241 __le16 status_flags;
2242
2243 uint32_t sys_define2[2];
2244
2245 __le16 mb0;
2246 __le16 mb1;
2247 __le16 mb2;
2248 __le16 mb3;
2249 __le16 mb6;
2250 __le16 mb7;
2251 __le16 mb9;
2252 __le16 mb10;
2253 uint32_t reserved_2[2];
2254 uint8_t node_name[WWN_SIZE];
2255 uint8_t port_name[WWN_SIZE];
2256};
2257
2258#ifndef IMMED_NOTIFY_TYPE
2259#define IMMED_NOTIFY_TYPE 0x0D
2260
2261
2262
2263
2264
2265
2266
2267struct imm_ntfy_from_isp {
2268 uint8_t entry_type;
2269 uint8_t entry_count;
2270 uint8_t sys_define;
2271 uint8_t entry_status;
2272 union {
2273 struct {
2274 __le32 sys_define_2;
2275 target_id_t target;
2276 __le16 lun;
2277 uint8_t target_id;
2278 uint8_t reserved_1;
2279 __le16 status_modifier;
2280 __le16 status;
2281 __le16 task_flags;
2282 __le16 seq_id;
2283 __le16 srr_rx_id;
2284 __le32 srr_rel_offs;
2285 __le16 srr_ui;
2286#define SRR_IU_DATA_IN 0x1
2287#define SRR_IU_DATA_OUT 0x5
2288#define SRR_IU_STATUS 0x7
2289 __le16 srr_ox_id;
2290 uint8_t reserved_2[28];
2291 } isp2x;
2292 struct {
2293 uint32_t reserved;
2294 __le16 nport_handle;
2295 uint16_t reserved_2;
2296 __le16 flags;
2297#define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2298#define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2299 __le16 srr_rx_id;
2300 __le16 status;
2301 uint8_t status_subcode;
2302 uint8_t fw_handle;
2303 __le32 exchange_address;
2304 __le32 srr_rel_offs;
2305 __le16 srr_ui;
2306 __le16 srr_ox_id;
2307 union {
2308 struct {
2309 uint8_t node_name[8];
2310 } plogi;
2311 struct {
2312
2313 __le16 wd3_lo;
2314 uint8_t resv0[6];
2315 } prli;
2316 struct {
2317 uint8_t port_id[3];
2318 uint8_t resv1;
2319 __le16 nport_handle;
2320 uint16_t resv2;
2321 } req_els;
2322 } u;
2323 uint8_t port_name[8];
2324 uint8_t resv3[3];
2325 uint8_t vp_index;
2326 uint32_t reserved_5;
2327 uint8_t port_id[3];
2328 uint8_t reserved_6;
2329 } isp24;
2330 } u;
2331 uint16_t reserved_7;
2332 __le16 ox_id;
2333} __packed;
2334#endif
2335
2336
2337
2338
2339#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2340#define REQUEST_ENTRY_SIZE (sizeof(request_t))
2341
2342
2343
2344
2345
2346
2347typedef struct {
2348 port_id_t d_id;
2349 uint8_t node_name[WWN_SIZE];
2350 uint8_t port_name[WWN_SIZE];
2351 uint8_t fabric_port_name[WWN_SIZE];
2352 uint16_t fp_speed;
2353 uint8_t fc4_type;
2354 uint8_t fc4_features;
2355} sw_info_t;
2356
2357
2358#define FC4_TYPE_FCP_SCSI 0x08
2359#define FC4_TYPE_NVME 0x28
2360#define FC4_TYPE_OTHER 0x0
2361#define FC4_TYPE_UNKNOWN 0xff
2362
2363
2364struct mbx_24xx_entry {
2365 uint8_t entry_type;
2366 uint8_t entry_count;
2367 uint8_t sys_define1;
2368 uint8_t entry_status;
2369 uint32_t handle;
2370 uint16_t mb[28];
2371};
2372
2373#define IOCB_SIZE 64
2374
2375
2376
2377
2378typedef enum {
2379 FCT_UNKNOWN,
2380 FCT_RSCN,
2381 FCT_SWITCH,
2382 FCT_BROADCAST,
2383 FCT_INITIATOR,
2384 FCT_TARGET,
2385 FCT_NVME_INITIATOR = 0x10,
2386 FCT_NVME_TARGET = 0x20,
2387 FCT_NVME_DISCOVERY = 0x40,
2388 FCT_NVME = 0xf0,
2389} fc_port_type_t;
2390
2391enum qla_sess_deletion {
2392 QLA_SESS_DELETION_NONE = 0,
2393 QLA_SESS_DELETION_IN_PROGRESS,
2394 QLA_SESS_DELETED,
2395};
2396
2397enum qlt_plogi_link_t {
2398 QLT_PLOGI_LINK_SAME_WWN,
2399 QLT_PLOGI_LINK_CONFLICT,
2400 QLT_PLOGI_LINK_MAX
2401};
2402
2403struct qlt_plogi_ack_t {
2404 struct list_head list;
2405 struct imm_ntfy_from_isp iocb;
2406 port_id_t id;
2407 int ref_count;
2408 void *fcport;
2409};
2410
2411struct ct_sns_desc {
2412 struct ct_sns_pkt *ct_sns;
2413 dma_addr_t ct_sns_dma;
2414};
2415
2416enum discovery_state {
2417 DSC_DELETED,
2418 DSC_GNN_ID,
2419 DSC_GNL,
2420 DSC_LOGIN_PEND,
2421 DSC_LOGIN_FAILED,
2422 DSC_GPDB,
2423 DSC_UPD_FCPORT,
2424 DSC_LOGIN_COMPLETE,
2425 DSC_ADISC,
2426 DSC_DELETE_PEND,
2427};
2428
2429enum login_state {
2430 DSC_LS_LLIOCB_SENT = 2,
2431 DSC_LS_PLOGI_PEND,
2432 DSC_LS_PLOGI_COMP,
2433 DSC_LS_PRLI_PEND,
2434 DSC_LS_PRLI_COMP,
2435 DSC_LS_PORT_UNAVAIL,
2436 DSC_LS_PRLO_PEND = 9,
2437 DSC_LS_LOGO_PEND,
2438};
2439
2440enum rscn_addr_format {
2441 RSCN_PORT_ADDR,
2442 RSCN_AREA_ADDR,
2443 RSCN_DOM_ADDR,
2444 RSCN_FAB_ADDR,
2445};
2446
2447
2448
2449
2450typedef struct fc_port {
2451 struct list_head list;
2452 struct scsi_qla_host *vha;
2453
2454 unsigned int conf_compl_supported:1;
2455 unsigned int deleted:2;
2456 unsigned int free_pending:1;
2457 unsigned int local:1;
2458 unsigned int logout_on_delete:1;
2459 unsigned int logo_ack_needed:1;
2460 unsigned int keep_nport_handle:1;
2461 unsigned int send_els_logo:1;
2462 unsigned int login_pause:1;
2463 unsigned int login_succ:1;
2464 unsigned int query:1;
2465 unsigned int id_changed:1;
2466 unsigned int scan_needed:1;
2467 unsigned int n2n_flag:1;
2468 unsigned int explicit_logout:1;
2469 unsigned int prli_pend_timer:1;
2470 uint8_t nvme_flag;
2471
2472 uint8_t node_name[WWN_SIZE];
2473 uint8_t port_name[WWN_SIZE];
2474 port_id_t d_id;
2475 uint16_t loop_id;
2476 uint16_t old_loop_id;
2477
2478 struct completion nvme_del_done;
2479 uint32_t nvme_prli_service_param;
2480#define NVME_PRLI_SP_PI_CTRL BIT_9
2481#define NVME_PRLI_SP_SLER BIT_8
2482#define NVME_PRLI_SP_CONF BIT_7
2483#define NVME_PRLI_SP_INITIATOR BIT_5
2484#define NVME_PRLI_SP_TARGET BIT_4
2485#define NVME_PRLI_SP_DISCOVERY BIT_3
2486#define NVME_PRLI_SP_FIRST_BURST BIT_0
2487
2488 uint32_t nvme_first_burst_size;
2489#define NVME_FLAG_REGISTERED 4
2490#define NVME_FLAG_DELETING 2
2491#define NVME_FLAG_RESETTING 1
2492
2493 struct fc_port *conflict;
2494 unsigned char logout_completed;
2495 int generation;
2496
2497 struct se_session *se_sess;
2498 struct list_head sess_cmd_list;
2499 spinlock_t sess_cmd_lock;
2500 struct kref sess_kref;
2501 struct qla_tgt *tgt;
2502 unsigned long expires;
2503 struct list_head del_list_entry;
2504 struct work_struct free_work;
2505 struct work_struct reg_work;
2506 uint64_t jiffies_at_registration;
2507 unsigned long prli_expired;
2508 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2509
2510 uint16_t tgt_id;
2511 uint16_t old_tgt_id;
2512 uint16_t sec_since_registration;
2513
2514 uint8_t fcp_prio;
2515
2516 uint8_t fabric_port_name[WWN_SIZE];
2517 uint16_t fp_speed;
2518
2519 fc_port_type_t port_type;
2520
2521 atomic_t state;
2522 uint32_t flags;
2523
2524 int login_retry;
2525
2526 struct fc_rport *rport, *drport;
2527 u32 supported_classes;
2528
2529 uint8_t fc4_type;
2530 uint8_t fc4_features;
2531 uint8_t scan_state;
2532
2533 unsigned long last_queue_full;
2534 unsigned long last_ramp_up;
2535
2536 uint16_t port_id;
2537
2538 struct nvme_fc_remote_port *nvme_remote_port;
2539
2540 unsigned long retry_delay_timestamp;
2541 struct qla_tgt_sess *tgt_session;
2542 struct ct_sns_desc ct_desc;
2543 enum discovery_state disc_state;
2544 atomic_t shadow_disc_state;
2545 enum discovery_state next_disc_state;
2546 enum login_state fw_login_state;
2547 unsigned long dm_login_expire;
2548 unsigned long plogi_nack_done_deadline;
2549
2550 u32 login_gen, last_login_gen;
2551 u32 rscn_gen, last_rscn_gen;
2552 u32 chip_reset;
2553 struct list_head gnl_entry;
2554 struct work_struct del_work;
2555 u8 iocb[IOCB_SIZE];
2556 u8 current_login_state;
2557 u8 last_login_state;
2558 u16 n2n_link_reset_cnt;
2559 u16 n2n_chip_reset;
2560
2561 struct dentry *dfs_rport_dir;
2562
2563 u64 tgt_short_link_down_cnt;
2564 u64 tgt_link_down_time;
2565 u64 dev_loss_tmo;
2566} fc_port_t;
2567
2568enum {
2569 FC4_PRIORITY_NVME = 1,
2570 FC4_PRIORITY_FCP = 2,
2571};
2572
2573#define QLA_FCPORT_SCAN 1
2574#define QLA_FCPORT_FOUND 2
2575
2576struct event_arg {
2577 fc_port_t *fcport;
2578 srb_t *sp;
2579 port_id_t id;
2580 u16 data[2], rc;
2581 u8 port_name[WWN_SIZE];
2582 u32 iop[2];
2583};
2584
2585#include "qla_mr.h"
2586
2587
2588
2589
2590#define FCS_UNCONFIGURED 1
2591#define FCS_DEVICE_DEAD 2
2592#define FCS_DEVICE_LOST 3
2593#define FCS_ONLINE 4
2594
2595extern const char *const port_state_str[5];
2596
2597static const char * const port_dstate_str[] = {
2598 "DELETED",
2599 "GNN_ID",
2600 "GNL",
2601 "LOGIN_PEND",
2602 "LOGIN_FAILED",
2603 "GPDB",
2604 "UPD_FCPORT",
2605 "LOGIN_COMPLETE",
2606 "ADISC",
2607 "DELETE_PEND"
2608};
2609
2610
2611
2612
2613#define FCF_FABRIC_DEVICE BIT_0
2614#define FCF_LOGIN_NEEDED BIT_1
2615#define FCF_FCP2_DEVICE BIT_2
2616#define FCF_ASYNC_SENT BIT_3
2617#define FCF_CONF_COMP_SUPPORTED BIT_4
2618#define FCF_ASYNC_ACTIVE BIT_5
2619
2620
2621#define FC_NO_LOOP_ID 0x1000
2622
2623
2624
2625
2626
2627
2628
2629#define CT_REJECT_RESPONSE 0x8001
2630#define CT_ACCEPT_RESPONSE 0x8002
2631#define CT_REASON_INVALID_COMMAND_CODE 0x01
2632#define CT_REASON_CANNOT_PERFORM 0x09
2633#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2634#define CT_EXPL_ALREADY_REGISTERED 0x10
2635#define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2636#define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2637#define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2638#define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2639#define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2640#define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2641#define CT_EXPL_HBA_NOT_REGISTERED 0x17
2642#define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2643#define CT_EXPL_PORT_NOT_REGISTERED 0x21
2644#define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2645#define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2646
2647#define NS_N_PORT_TYPE 0x01
2648#define NS_NL_PORT_TYPE 0x02
2649#define NS_NX_PORT_TYPE 0x7F
2650
2651#define GA_NXT_CMD 0x100
2652#define GA_NXT_REQ_SIZE (16 + 4)
2653#define GA_NXT_RSP_SIZE (16 + 620)
2654
2655#define GPN_FT_CMD 0x172
2656#define GPN_FT_REQ_SIZE (16 + 4)
2657#define GNN_FT_CMD 0x173
2658#define GNN_FT_REQ_SIZE (16 + 4)
2659
2660#define GID_PT_CMD 0x1A1
2661#define GID_PT_REQ_SIZE (16 + 4)
2662
2663#define GPN_ID_CMD 0x112
2664#define GPN_ID_REQ_SIZE (16 + 4)
2665#define GPN_ID_RSP_SIZE (16 + 8)
2666
2667#define GNN_ID_CMD 0x113
2668#define GNN_ID_REQ_SIZE (16 + 4)
2669#define GNN_ID_RSP_SIZE (16 + 8)
2670
2671#define GFT_ID_CMD 0x117
2672#define GFT_ID_REQ_SIZE (16 + 4)
2673#define GFT_ID_RSP_SIZE (16 + 32)
2674
2675#define GID_PN_CMD 0x121
2676#define GID_PN_REQ_SIZE (16 + 8)
2677#define GID_PN_RSP_SIZE (16 + 4)
2678
2679#define RFT_ID_CMD 0x217
2680#define RFT_ID_REQ_SIZE (16 + 4 + 32)
2681#define RFT_ID_RSP_SIZE 16
2682
2683#define RFF_ID_CMD 0x21F
2684#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2685#define RFF_ID_RSP_SIZE 16
2686
2687#define RNN_ID_CMD 0x213
2688#define RNN_ID_REQ_SIZE (16 + 4 + 8)
2689#define RNN_ID_RSP_SIZE 16
2690
2691#define RSNN_NN_CMD 0x239
2692#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2693#define RSNN_NN_RSP_SIZE 16
2694
2695#define GFPN_ID_CMD 0x11C
2696#define GFPN_ID_REQ_SIZE (16 + 4)
2697#define GFPN_ID_RSP_SIZE (16 + 8)
2698
2699#define GPSC_CMD 0x127
2700#define GPSC_REQ_SIZE (16 + 8)
2701#define GPSC_RSP_SIZE (16 + 2 + 2)
2702
2703#define GFF_ID_CMD 0x011F
2704#define GFF_ID_REQ_SIZE (16 + 4)
2705#define GFF_ID_RSP_SIZE (16 + 128)
2706
2707
2708
2709
2710#define FDMI1_HBA_ATTR_COUNT 9
2711#define FDMI2_HBA_ATTR_COUNT 17
2712
2713#define FDMI_HBA_NODE_NAME 0x1
2714#define FDMI_HBA_MANUFACTURER 0x2
2715#define FDMI_HBA_SERIAL_NUMBER 0x3
2716#define FDMI_HBA_MODEL 0x4
2717#define FDMI_HBA_MODEL_DESCRIPTION 0x5
2718#define FDMI_HBA_HARDWARE_VERSION 0x6
2719#define FDMI_HBA_DRIVER_VERSION 0x7
2720#define FDMI_HBA_OPTION_ROM_VERSION 0x8
2721#define FDMI_HBA_FIRMWARE_VERSION 0x9
2722#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2723#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2724
2725#define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2726#define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd
2727#define FDMI_HBA_NUM_PORTS 0xe
2728#define FDMI_HBA_FABRIC_NAME 0xf
2729#define FDMI_HBA_BOOT_BIOS_NAME 0x10
2730#define FDMI_HBA_VENDOR_IDENTIFIER 0xe0
2731
2732struct ct_fdmi_hba_attr {
2733 __be16 type;
2734 __be16 len;
2735 union {
2736 uint8_t node_name[WWN_SIZE];
2737 uint8_t manufacturer[64];
2738 uint8_t serial_num[32];
2739 uint8_t model[16+1];
2740 uint8_t model_desc[80];
2741 uint8_t hw_version[32];
2742 uint8_t driver_version[32];
2743 uint8_t orom_version[16];
2744 uint8_t fw_version[32];
2745 uint8_t os_version[128];
2746 __be32 max_ct_len;
2747
2748 uint8_t sym_name[256];
2749 __be32 vendor_specific_info;
2750 __be32 num_ports;
2751 uint8_t fabric_name[WWN_SIZE];
2752 uint8_t bios_name[32];
2753 uint8_t vendor_identifier[8];
2754 } a;
2755};
2756
2757struct ct_fdmi1_hba_attributes {
2758 __be32 count;
2759 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT];
2760};
2761
2762struct ct_fdmi2_hba_attributes {
2763 __be32 count;
2764 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT];
2765};
2766
2767
2768
2769
2770#define FDMI1_PORT_ATTR_COUNT 6
2771#define FDMI2_PORT_ATTR_COUNT 16
2772#define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23
2773
2774#define FDMI_PORT_FC4_TYPES 0x1
2775#define FDMI_PORT_SUPPORT_SPEED 0x2
2776#define FDMI_PORT_CURRENT_SPEED 0x3
2777#define FDMI_PORT_MAX_FRAME_SIZE 0x4
2778#define FDMI_PORT_OS_DEVICE_NAME 0x5
2779#define FDMI_PORT_HOST_NAME 0x6
2780
2781#define FDMI_PORT_NODE_NAME 0x7
2782#define FDMI_PORT_NAME 0x8
2783#define FDMI_PORT_SYM_NAME 0x9
2784#define FDMI_PORT_TYPE 0xa
2785#define FDMI_PORT_SUPP_COS 0xb
2786#define FDMI_PORT_FABRIC_NAME 0xc
2787#define FDMI_PORT_FC4_TYPE 0xd
2788#define FDMI_PORT_STATE 0x101
2789#define FDMI_PORT_COUNT 0x102
2790#define FDMI_PORT_IDENTIFIER 0x103
2791
2792#define FDMI_SMARTSAN_SERVICE 0xF100
2793#define FDMI_SMARTSAN_GUID 0xF101
2794#define FDMI_SMARTSAN_VERSION 0xF102
2795#define FDMI_SMARTSAN_PROD_NAME 0xF103
2796#define FDMI_SMARTSAN_PORT_INFO 0xF104
2797#define FDMI_SMARTSAN_QOS_SUPPORT 0xF105
2798#define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106
2799
2800#define FDMI_PORT_SPEED_1GB 0x1
2801#define FDMI_PORT_SPEED_2GB 0x2
2802#define FDMI_PORT_SPEED_10GB 0x4
2803#define FDMI_PORT_SPEED_4GB 0x8
2804#define FDMI_PORT_SPEED_8GB 0x10
2805#define FDMI_PORT_SPEED_16GB 0x20
2806#define FDMI_PORT_SPEED_32GB 0x40
2807#define FDMI_PORT_SPEED_64GB 0x80
2808#define FDMI_PORT_SPEED_UNKNOWN 0x8000
2809
2810#define FC_CLASS_2 0x04
2811#define FC_CLASS_3 0x08
2812#define FC_CLASS_2_3 0x0C
2813
2814struct ct_fdmi_port_attr {
2815 __be16 type;
2816 __be16 len;
2817 union {
2818 uint8_t fc4_types[32];
2819 __be32 sup_speed;
2820 __be32 cur_speed;
2821 __be32 max_frame_size;
2822 uint8_t os_dev_name[32];
2823 uint8_t host_name[256];
2824
2825 uint8_t node_name[WWN_SIZE];
2826 uint8_t port_name[WWN_SIZE];
2827 uint8_t port_sym_name[128];
2828 __be32 port_type;
2829 __be32 port_supported_cos;
2830 uint8_t fabric_name[WWN_SIZE];
2831 uint8_t port_fc4_type[32];
2832 __be32 port_state;
2833 __be32 num_ports;
2834 __be32 port_id;
2835
2836 uint8_t smartsan_service[24];
2837 uint8_t smartsan_guid[16];
2838 uint8_t smartsan_version[24];
2839 uint8_t smartsan_prod_name[16];
2840 __be32 smartsan_port_info;
2841 __be32 smartsan_qos_support;
2842 __be32 smartsan_security_support;
2843 } a;
2844};
2845
2846struct ct_fdmi1_port_attributes {
2847 __be32 count;
2848 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT];
2849};
2850
2851struct ct_fdmi2_port_attributes {
2852 __be32 count;
2853 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT];
2854};
2855
2856#define FDMI_ATTR_TYPELEN(obj) \
2857 (sizeof((obj)->type) + sizeof((obj)->len))
2858
2859#define FDMI_ATTR_ALIGNMENT(len) \
2860 (4 - ((len) & 3))
2861
2862
2863#define CALLOPT_FDMI1 0
2864#define CALLOPT_FDMI2 1
2865#define CALLOPT_FDMI2_SMARTSAN 2
2866
2867
2868#define GRHL_CMD 0x100
2869#define GHAT_CMD 0x101
2870#define GRPL_CMD 0x102
2871#define GPAT_CMD 0x110
2872
2873#define RHBA_CMD 0x200
2874#define RHBA_RSP_SIZE 16
2875
2876#define RHAT_CMD 0x201
2877
2878#define RPRT_CMD 0x210
2879#define RPRT_RSP_SIZE 24
2880
2881#define RPA_CMD 0x211
2882#define RPA_RSP_SIZE 16
2883#define SMARTSAN_RPA_RSP_SIZE 24
2884
2885#define DHBA_CMD 0x300
2886#define DHBA_REQ_SIZE (16 + 8)
2887#define DHBA_RSP_SIZE 16
2888
2889#define DHAT_CMD 0x301
2890#define DPRT_CMD 0x310
2891#define DPA_CMD 0x311
2892
2893
2894struct ct_cmd_hdr {
2895 uint8_t revision;
2896 uint8_t in_id[3];
2897 uint8_t gs_type;
2898 uint8_t gs_subtype;
2899 uint8_t options;
2900 uint8_t reserved;
2901};
2902
2903
2904struct ct_sns_req {
2905 struct ct_cmd_hdr header;
2906 __be16 command;
2907 __be16 max_rsp_size;
2908 uint8_t fragment_id;
2909 uint8_t reserved[3];
2910
2911 union {
2912
2913 struct {
2914 uint8_t reserved;
2915 be_id_t port_id;
2916 } port_id;
2917
2918 struct {
2919 uint8_t reserved;
2920 uint8_t domain;
2921 uint8_t area;
2922 uint8_t port_type;
2923 } gpn_ft;
2924
2925 struct {
2926 uint8_t port_type;
2927 uint8_t domain;
2928 uint8_t area;
2929 uint8_t reserved;
2930 } gid_pt;
2931
2932 struct {
2933 uint8_t reserved;
2934 be_id_t port_id;
2935 uint8_t fc4_types[32];
2936 } rft_id;
2937
2938 struct {
2939 uint8_t reserved;
2940 be_id_t port_id;
2941 uint16_t reserved2;
2942 uint8_t fc4_feature;
2943 uint8_t fc4_type;
2944 } rff_id;
2945
2946 struct {
2947 uint8_t reserved;
2948 be_id_t port_id;
2949 uint8_t node_name[8];
2950 } rnn_id;
2951
2952 struct {
2953 uint8_t node_name[8];
2954 uint8_t name_len;
2955 uint8_t sym_node_name[255];
2956 } rsnn_nn;
2957
2958 struct {
2959 uint8_t hba_identifier[8];
2960 } ghat;
2961
2962 struct {
2963 uint8_t hba_identifier[8];
2964 __be32 entry_count;
2965 uint8_t port_name[8];
2966 struct ct_fdmi2_hba_attributes attrs;
2967 } rhba;
2968
2969 struct {
2970 uint8_t hba_identifier[8];
2971 struct ct_fdmi1_hba_attributes attrs;
2972 } rhat;
2973
2974 struct {
2975 uint8_t port_name[8];
2976 struct ct_fdmi2_port_attributes attrs;
2977 } rpa;
2978
2979 struct {
2980 uint8_t hba_identifier[8];
2981 uint8_t port_name[8];
2982 struct ct_fdmi2_port_attributes attrs;
2983 } rprt;
2984
2985 struct {
2986 uint8_t port_name[8];
2987 } dhba;
2988
2989 struct {
2990 uint8_t port_name[8];
2991 } dhat;
2992
2993 struct {
2994 uint8_t port_name[8];
2995 } dprt;
2996
2997 struct {
2998 uint8_t port_name[8];
2999 } dpa;
3000
3001 struct {
3002 uint8_t port_name[8];
3003 } gpsc;
3004
3005 struct {
3006 uint8_t reserved;
3007 uint8_t port_id[3];
3008 } gff_id;
3009
3010 struct {
3011 uint8_t port_name[8];
3012 } gid_pn;
3013 } req;
3014};
3015
3016
3017struct ct_rsp_hdr {
3018 struct ct_cmd_hdr header;
3019 __be16 response;
3020 uint16_t residual;
3021 uint8_t fragment_id;
3022 uint8_t reason_code;
3023 uint8_t explanation_code;
3024 uint8_t vendor_unique;
3025};
3026
3027struct ct_sns_gid_pt_data {
3028 uint8_t control_byte;
3029 be_id_t port_id;
3030};
3031
3032
3033struct ct_sns_gpnft_rsp {
3034 struct {
3035 struct ct_cmd_hdr header;
3036 uint16_t response;
3037 uint16_t residual;
3038 uint8_t fragment_id;
3039 uint8_t reason_code;
3040 uint8_t explanation_code;
3041 uint8_t vendor_unique;
3042 };
3043
3044 struct ct_sns_gpn_ft_data {
3045 u8 control_byte;
3046 u8 port_id[3];
3047 u32 reserved;
3048 u8 port_name[8];
3049 } entries[1];
3050};
3051
3052
3053struct ct_sns_rsp {
3054 struct ct_rsp_hdr header;
3055
3056 union {
3057 struct {
3058 uint8_t port_type;
3059 be_id_t port_id;
3060 uint8_t port_name[8];
3061 uint8_t sym_port_name_len;
3062 uint8_t sym_port_name[255];
3063 uint8_t node_name[8];
3064 uint8_t sym_node_name_len;
3065 uint8_t sym_node_name[255];
3066 uint8_t init_proc_assoc[8];
3067 uint8_t node_ip_addr[16];
3068 uint8_t class_of_service[4];
3069 uint8_t fc4_types[32];
3070 uint8_t ip_address[16];
3071 uint8_t fabric_port_name[8];
3072 uint8_t reserved;
3073 uint8_t hard_address[3];
3074 } ga_nxt;
3075
3076 struct {
3077
3078 struct ct_sns_gid_pt_data
3079 entries[MAX_FIBRE_DEVICES_MAX];
3080 } gid_pt;
3081
3082 struct {
3083 uint8_t port_name[8];
3084 } gpn_id;
3085
3086 struct {
3087 uint8_t node_name[8];
3088 } gnn_id;
3089
3090 struct {
3091 uint8_t fc4_types[32];
3092 } gft_id;
3093
3094 struct {
3095 uint32_t entry_count;
3096 uint8_t port_name[8];
3097 struct ct_fdmi1_hba_attributes attrs;
3098 } ghat;
3099
3100 struct {
3101 uint8_t port_name[8];
3102 } gfpn_id;
3103
3104 struct {
3105 __be16 speeds;
3106 __be16 speed;
3107 } gpsc;
3108
3109#define GFF_FCP_SCSI_OFFSET 7
3110#define GFF_NVME_OFFSET 23
3111 struct {
3112 uint8_t fc4_features[128];
3113 } gff_id;
3114 struct {
3115 uint8_t reserved;
3116 uint8_t port_id[3];
3117 } gid_pn;
3118 } rsp;
3119};
3120
3121struct ct_sns_pkt {
3122 union {
3123 struct ct_sns_req req;
3124 struct ct_sns_rsp rsp;
3125 } p;
3126};
3127
3128struct ct_sns_gpnft_pkt {
3129 union {
3130 struct ct_sns_req req;
3131 struct ct_sns_gpnft_rsp rsp;
3132 } p;
3133};
3134
3135enum scan_flags_t {
3136 SF_SCANNING = BIT_0,
3137 SF_QUEUED = BIT_1,
3138};
3139
3140enum fc4type_t {
3141 FS_FC4TYPE_FCP = BIT_0,
3142 FS_FC4TYPE_NVME = BIT_1,
3143 FS_FCP_IS_N2N = BIT_7,
3144};
3145
3146struct fab_scan_rp {
3147 port_id_t id;
3148 enum fc4type_t fc4type;
3149 u8 port_name[8];
3150 u8 node_name[8];
3151};
3152
3153struct fab_scan {
3154 struct fab_scan_rp *l;
3155 u32 size;
3156 u16 scan_retry;
3157#define MAX_SCAN_RETRIES 5
3158 enum scan_flags_t scan_flags;
3159 struct delayed_work scan_work;
3160};
3161
3162
3163
3164
3165#define RFT_ID_SNS_SCMD_LEN 22
3166#define RFT_ID_SNS_CMD_SIZE 60
3167#define RFT_ID_SNS_DATA_SIZE 16
3168
3169#define RNN_ID_SNS_SCMD_LEN 10
3170#define RNN_ID_SNS_CMD_SIZE 36
3171#define RNN_ID_SNS_DATA_SIZE 16
3172
3173#define GA_NXT_SNS_SCMD_LEN 6
3174#define GA_NXT_SNS_CMD_SIZE 28
3175#define GA_NXT_SNS_DATA_SIZE (620 + 16)
3176
3177#define GID_PT_SNS_SCMD_LEN 6
3178#define GID_PT_SNS_CMD_SIZE 28
3179
3180
3181
3182
3183#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3184
3185#define GPN_ID_SNS_SCMD_LEN 6
3186#define GPN_ID_SNS_CMD_SIZE 28
3187#define GPN_ID_SNS_DATA_SIZE (8 + 16)
3188
3189#define GNN_ID_SNS_SCMD_LEN 6
3190#define GNN_ID_SNS_CMD_SIZE 28
3191#define GNN_ID_SNS_DATA_SIZE (8 + 16)
3192
3193struct sns_cmd_pkt {
3194 union {
3195 struct {
3196 __le16 buffer_length;
3197 __le16 reserved_1;
3198 __le64 buffer_address __packed;
3199 __le16 subcommand_length;
3200 __le16 reserved_2;
3201 __le16 subcommand;
3202 __le16 size;
3203 uint32_t reserved_3;
3204 uint8_t param[36];
3205 } cmd;
3206
3207 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3208 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3209 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3210 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3211 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3212 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3213 } p;
3214};
3215
3216struct fw_blob {
3217 char *name;
3218 uint32_t segs[4];
3219 const struct firmware *fw;
3220};
3221
3222
3223struct gid_list_info {
3224 uint8_t al_pa;
3225 uint8_t area;
3226 uint8_t domain;
3227 uint8_t loop_id_2100;
3228 __le16 loop_id;
3229 uint16_t reserved_1;
3230};
3231
3232
3233typedef struct vport_info {
3234 uint8_t port_name[WWN_SIZE];
3235 uint8_t node_name[WWN_SIZE];
3236 int vp_id;
3237 uint16_t loop_id;
3238 unsigned long host_no;
3239 uint8_t port_id[3];
3240 int loop_state;
3241} vport_info_t;
3242
3243typedef struct vport_params {
3244 uint8_t port_name[WWN_SIZE];
3245 uint8_t node_name[WWN_SIZE];
3246 uint32_t options;
3247#define VP_OPTS_RETRY_ENABLE BIT_0
3248#define VP_OPTS_VP_DISABLE BIT_1
3249} vport_params_t;
3250
3251
3252#define VP_RET_CODE_OK 0
3253#define VP_RET_CODE_FATAL 1
3254#define VP_RET_CODE_WRONG_ID 2
3255#define VP_RET_CODE_WWPN 3
3256#define VP_RET_CODE_RESOURCES 4
3257#define VP_RET_CODE_NO_MEM 5
3258#define VP_RET_CODE_NOT_FOUND 6
3259
3260struct qla_hw_data;
3261struct rsp_que;
3262
3263
3264
3265struct isp_operations {
3266
3267 int (*pci_config) (struct scsi_qla_host *);
3268 int (*reset_chip)(struct scsi_qla_host *);
3269 int (*chip_diag) (struct scsi_qla_host *);
3270 void (*config_rings) (struct scsi_qla_host *);
3271 int (*reset_adapter)(struct scsi_qla_host *);
3272 int (*nvram_config) (struct scsi_qla_host *);
3273 void (*update_fw_options) (struct scsi_qla_host *);
3274 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3275
3276 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t);
3277 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3278
3279 irq_handler_t intr_handler;
3280 void (*enable_intrs) (struct qla_hw_data *);
3281 void (*disable_intrs) (struct qla_hw_data *);
3282
3283 int (*abort_command) (srb_t *);
3284 int (*target_reset) (struct fc_port *, uint64_t, int);
3285 int (*lun_reset) (struct fc_port *, uint64_t, int);
3286 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3287 uint8_t, uint8_t, uint16_t *, uint8_t);
3288 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3289 uint8_t, uint8_t);
3290
3291 uint16_t (*calc_req_entries) (uint16_t);
3292 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3293 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3294 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3295 uint32_t);
3296
3297 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
3298 uint32_t, uint32_t);
3299 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
3300 uint32_t);
3301
3302 void (*fw_dump)(struct scsi_qla_host *vha);
3303 void (*mpi_fw_dump)(struct scsi_qla_host *, int);
3304
3305
3306 int (*beacon_on) (struct scsi_qla_host *);
3307 int (*beacon_off) (struct scsi_qla_host *);
3308
3309 void (*beacon_blink) (struct scsi_qla_host *);
3310
3311 void *(*read_optrom)(struct scsi_qla_host *, void *,
3312 uint32_t, uint32_t);
3313 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
3314 uint32_t);
3315
3316 int (*get_flash_version) (struct scsi_qla_host *, void *);
3317 int (*start_scsi) (srb_t *);
3318 int (*start_scsi_mq) (srb_t *);
3319
3320
3321 int (*abort_isp) (struct scsi_qla_host *);
3322
3323 int (*iospace_config)(struct qla_hw_data *);
3324 int (*initialize_adapter)(struct scsi_qla_host *);
3325};
3326
3327
3328
3329#define QLA_MSIX_CHIP_REV_24XX 3
3330#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3331#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3332
3333#define QLA_BASE_VECTORS 2
3334#define QLA_MSIX_RSP_Q 0x01
3335#define QLA_ATIO_VECTOR 0x02
3336#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3337#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04
3338
3339#define QLA_MIDX_DEFAULT 0
3340#define QLA_MIDX_RSP_Q 1
3341#define QLA_PCI_MSIX_CONTROL 0xa2
3342#define QLA_83XX_PCI_MSIX_CONTROL 0x92
3343
3344struct scsi_qla_host;
3345
3346
3347#define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1
3348
3349struct qla_msix_entry {
3350 int have_irq;
3351 int in_use;
3352 uint32_t vector;
3353 uint16_t entry;
3354 char name[30];
3355 void *handle;
3356 int cpuid;
3357};
3358
3359#define WATCH_INTERVAL 1
3360
3361
3362enum qla_work_type {
3363 QLA_EVT_AEN,
3364 QLA_EVT_IDC_ACK,
3365 QLA_EVT_ASYNC_LOGIN,
3366 QLA_EVT_ASYNC_LOGOUT,
3367 QLA_EVT_ASYNC_ADISC,
3368 QLA_EVT_UEVENT,
3369 QLA_EVT_AENFX,
3370 QLA_EVT_GPNID,
3371 QLA_EVT_UNMAP,
3372 QLA_EVT_NEW_SESS,
3373 QLA_EVT_GPDB,
3374 QLA_EVT_PRLI,
3375 QLA_EVT_GPSC,
3376 QLA_EVT_GNL,
3377 QLA_EVT_NACK,
3378 QLA_EVT_RELOGIN,
3379 QLA_EVT_ASYNC_PRLO,
3380 QLA_EVT_ASYNC_PRLO_DONE,
3381 QLA_EVT_GPNFT,
3382 QLA_EVT_GPNFT_DONE,
3383 QLA_EVT_GNNFT_DONE,
3384 QLA_EVT_GNNID,
3385 QLA_EVT_GFPNID,
3386 QLA_EVT_SP_RETRY,
3387 QLA_EVT_IIDMA,
3388 QLA_EVT_ELS_PLOGI,
3389};
3390
3391
3392struct qla_work_evt {
3393 struct list_head list;
3394 enum qla_work_type type;
3395 u32 flags;
3396#define QLA_EVT_FLAG_FREE 0x1
3397
3398 union {
3399 struct {
3400 enum fc_host_event_code code;
3401 u32 data;
3402 } aen;
3403 struct {
3404#define QLA_IDC_ACK_REGS 7
3405 uint16_t mb[QLA_IDC_ACK_REGS];
3406 } idc_ack;
3407 struct {
3408 struct fc_port *fcport;
3409#define QLA_LOGIO_LOGIN_RETRIED BIT_0
3410 u16 data[2];
3411 } logio;
3412 struct {
3413 u32 code;
3414#define QLA_UEVENT_CODE_FW_DUMP 0
3415 } uevent;
3416 struct {
3417 uint32_t evtcode;
3418 uint32_t mbx[8];
3419 uint32_t count;
3420 } aenfx;
3421 struct {
3422 srb_t *sp;
3423 } iosb;
3424 struct {
3425 port_id_t id;
3426 } gpnid;
3427 struct {
3428 port_id_t id;
3429 u8 port_name[8];
3430 u8 node_name[8];
3431 void *pla;
3432 u8 fc4_type;
3433 } new_sess;
3434 struct {
3435 fc_port_t *fcport;
3436 u8 opt;
3437 } fcport;
3438 struct {
3439 fc_port_t *fcport;
3440 u8 iocb[IOCB_SIZE];
3441 int type;
3442 } nack;
3443 struct {
3444 u8 fc4_type;
3445 srb_t *sp;
3446 } gpnft;
3447 } u;
3448};
3449
3450struct qla_chip_state_84xx {
3451 struct list_head list;
3452 struct kref kref;
3453
3454 void *bus;
3455 spinlock_t access_lock;
3456 struct mutex fw_update_mutex;
3457 uint32_t fw_update;
3458 uint32_t op_fw_version;
3459 uint32_t op_fw_size;
3460 uint32_t op_fw_seq_size;
3461 uint32_t diag_fw_version;
3462 uint32_t gold_fw_version;
3463};
3464
3465struct qla_dif_statistics {
3466 uint64_t dif_input_bytes;
3467 uint64_t dif_output_bytes;
3468 uint64_t dif_input_requests;
3469 uint64_t dif_output_requests;
3470 uint32_t dif_guard_err;
3471 uint32_t dif_ref_tag_err;
3472 uint32_t dif_app_tag_err;
3473};
3474
3475struct qla_statistics {
3476 uint32_t total_isp_aborts;
3477 uint64_t input_bytes;
3478 uint64_t output_bytes;
3479 uint64_t input_requests;
3480 uint64_t output_requests;
3481 uint32_t control_requests;
3482
3483 uint64_t jiffies_at_last_reset;
3484 uint32_t stat_max_pend_cmds;
3485 uint32_t stat_max_qfull_cmds_alloc;
3486 uint32_t stat_max_qfull_cmds_dropped;
3487
3488 struct qla_dif_statistics qla_dif_stats;
3489};
3490
3491struct bidi_statistics {
3492 unsigned long long io_count;
3493 unsigned long long transfer_bytes;
3494};
3495
3496struct qla_tc_param {
3497 struct scsi_qla_host *vha;
3498 uint32_t blk_sz;
3499 uint32_t bufflen;
3500 struct scatterlist *sg;
3501 struct scatterlist *prot_sg;
3502 struct crc_context *ctx;
3503 uint8_t *ctx_dsd_alloced;
3504};
3505
3506
3507#define MBC_INITIALIZE_MULTIQ 0x1f
3508#define QLA_QUE_PAGE 0X1000
3509#define QLA_MQ_SIZE 32
3510#define QLA_MAX_QUEUES 256
3511#define ISP_QUE_REG(ha, id) \
3512 ((ha->mqenable || IS_QLA83XX(ha) || \
3513 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
3514 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3515 ((void __iomem *)ha->iobase))
3516#define QLA_REQ_QUE_ID(tag) \
3517 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3518#define QLA_DEFAULT_QUE_QOS 5
3519#define QLA_PRECONFIG_VPORTS 32
3520#define QLA_MAX_VPORTS_QLA24XX 128
3521#define QLA_MAX_VPORTS_QLA25XX 256
3522
3523struct qla_tgt_counters {
3524 uint64_t qla_core_sbt_cmd;
3525 uint64_t core_qla_que_buf;
3526 uint64_t qla_core_ret_ctio;
3527 uint64_t core_qla_snd_status;
3528 uint64_t qla_core_ret_sta_ctio;
3529 uint64_t core_qla_free_cmd;
3530 uint64_t num_q_full_sent;
3531 uint64_t num_alloc_iocb_failed;
3532 uint64_t num_term_xchg_sent;
3533};
3534
3535struct qla_counters {
3536 uint64_t input_bytes;
3537 uint64_t input_requests;
3538 uint64_t output_bytes;
3539 uint64_t output_requests;
3540
3541};
3542
3543struct qla_qpair;
3544
3545
3546struct rsp_que {
3547 dma_addr_t dma;
3548 response_t *ring;
3549 response_t *ring_ptr;
3550 __le32 __iomem *rsp_q_in;
3551 __le32 __iomem *rsp_q_out;
3552 uint16_t ring_index;
3553 uint16_t out_ptr;
3554 uint16_t *in_ptr;
3555 uint16_t length;
3556 uint16_t options;
3557 uint16_t rid;
3558 uint16_t id;
3559 uint16_t vp_idx;
3560 struct qla_hw_data *hw;
3561 struct qla_msix_entry *msix;
3562 struct req_que *req;
3563 srb_t *status_srb;
3564 struct qla_qpair *qpair;
3565
3566 dma_addr_t dma_fx00;
3567 response_t *ring_fx00;
3568 uint16_t length_fx00;
3569 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3570};
3571
3572
3573struct req_que {
3574 dma_addr_t dma;
3575 request_t *ring;
3576 request_t *ring_ptr;
3577 __le32 __iomem *req_q_in;
3578 __le32 __iomem *req_q_out;
3579 uint16_t ring_index;
3580 uint16_t in_ptr;
3581 uint16_t *out_ptr;
3582 uint16_t cnt;
3583 uint16_t length;
3584 uint16_t options;
3585 uint16_t rid;
3586 uint16_t id;
3587 uint16_t qos;
3588 uint16_t vp_idx;
3589 struct rsp_que *rsp;
3590 srb_t **outstanding_cmds;
3591 uint32_t current_outstanding_cmd;
3592 uint16_t num_outstanding_cmds;
3593 int max_q_depth;
3594
3595 dma_addr_t dma_fx00;
3596 request_t *ring_fx00;
3597 uint16_t length_fx00;
3598 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3599};
3600
3601struct qla_fw_resources {
3602 u16 iocbs_total;
3603 u16 iocbs_limit;
3604 u16 iocbs_qp_limit;
3605 u16 iocbs_used;
3606};
3607
3608#define QLA_IOCB_PCT_LIMIT 95
3609
3610
3611struct qla_qpair {
3612 spinlock_t qp_lock;
3613 atomic_t ref_count;
3614 uint32_t lun_cnt;
3615
3616
3617
3618
3619 spinlock_t *qp_lock_ptr;
3620 struct scsi_qla_host *vha;
3621 u32 chip_reset;
3622
3623
3624
3625
3626
3627
3628 uint32_t online:1;
3629
3630 uint32_t difdix_supported:1;
3631 uint32_t delete_in_progress:1;
3632 uint32_t fw_started:1;
3633 uint32_t enable_class_2:1;
3634 uint32_t enable_explicit_conf:1;
3635 uint32_t use_shadow_reg:1;
3636 uint32_t rcv_intr:1;
3637
3638 uint16_t id;
3639 uint16_t vp_idx;
3640 mempool_t *srb_mempool;
3641
3642 struct pci_dev *pdev;
3643 void (*reqq_start_iocbs)(struct qla_qpair *);
3644
3645
3646 struct req_que *req;
3647 struct rsp_que *rsp;
3648 struct atio_que *atio;
3649 struct qla_msix_entry *msix;
3650 struct qla_hw_data *hw;
3651 struct work_struct q_work;
3652 struct qla_counters counters;
3653
3654 struct list_head qp_list_elem;
3655 struct list_head hints_list;
3656
3657 uint16_t retry_term_cnt;
3658 __le32 retry_term_exchg_addr;
3659 uint64_t retry_term_jiff;
3660 struct qla_tgt_counters tgt_counters;
3661 uint16_t cpuid;
3662 struct qla_fw_resources fwres ____cacheline_aligned;
3663 u32 cmd_cnt;
3664 u32 cmd_completion_cnt;
3665};
3666
3667
3668struct qlfc_fw {
3669 void *fw_buf;
3670 dma_addr_t fw_dma;
3671 uint32_t len;
3672};
3673
3674struct rdp_req_payload {
3675 uint32_t els_request;
3676 uint32_t desc_list_len;
3677
3678
3679 struct {
3680 uint32_t desc_tag;
3681 uint32_t desc_len;
3682 uint8_t reserved;
3683 uint8_t nport_id[3];
3684 } npiv_desc;
3685};
3686
3687struct rdp_rsp_payload {
3688 struct {
3689 __be32 cmd;
3690 __be32 len;
3691 } hdr;
3692
3693
3694 struct {
3695 __be32 desc_tag;
3696 __be32 desc_len;
3697 __be32 req_payload_word_0;
3698 } ls_req_info_desc;
3699
3700
3701 struct {
3702 __be32 desc_tag;
3703 __be32 desc_len;
3704 __be32 req_payload_word_0;
3705 } ls_req_info_desc2;
3706
3707
3708 struct {
3709 __be32 desc_tag;
3710 __be32 desc_len;
3711 __be16 temperature;
3712 __be16 vcc;
3713 __be16 tx_bias;
3714 __be16 tx_power;
3715 __be16 rx_power;
3716 __be16 sfp_flags;
3717 } sfp_diag_desc;
3718
3719
3720 struct {
3721 __be32 desc_tag;
3722 __be32 desc_len;
3723 __be16 speed_capab;
3724 __be16 operating_speed;
3725 } port_speed_desc;
3726
3727
3728 struct {
3729 __be32 desc_tag;
3730 __be32 desc_len;
3731 __be32 link_fail_cnt;
3732 __be32 loss_sync_cnt;
3733 __be32 loss_sig_cnt;
3734 __be32 prim_seq_err_cnt;
3735 __be32 inval_xmit_word_cnt;
3736 __be32 inval_crc_cnt;
3737 uint8_t pn_port_phy_type;
3738 uint8_t reserved[3];
3739 } ls_err_desc;
3740
3741
3742 struct {
3743 __be32 desc_tag;
3744 __be32 desc_len;
3745 uint8_t WWNN[WWN_SIZE];
3746 uint8_t WWPN[WWN_SIZE];
3747 } port_name_diag_desc;
3748
3749
3750 struct {
3751 __be32 desc_tag;
3752 __be32 desc_len;
3753 uint8_t WWNN[WWN_SIZE];
3754 uint8_t WWPN[WWN_SIZE];
3755 } port_name_direct_desc;
3756
3757
3758 struct {
3759 __be32 desc_tag;
3760 __be32 desc_len;
3761 __be32 fcport_b2b;
3762 __be32 attached_fcport_b2b;
3763 __be32 fcport_rtt;
3764 } buffer_credit_desc;
3765
3766
3767 struct {
3768 __be32 desc_tag;
3769 __be32 desc_len;
3770 __be16 high_alarm;
3771 __be16 low_alarm;
3772 __be16 high_warn;
3773 __be16 low_warn;
3774 __be32 element_flags;
3775 } optical_elmt_desc[5];
3776
3777
3778 struct {
3779 __be32 desc_tag;
3780 __be32 desc_len;
3781 uint8_t vendor_name[16];
3782 uint8_t part_number[16];
3783 uint8_t serial_number[16];
3784 uint8_t revision[4];
3785 uint8_t date[8];
3786 } optical_prod_desc;
3787};
3788
3789#define RDP_DESC_LEN(obj) \
3790 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len))
3791
3792#define RDP_PORT_SPEED_1GB BIT_15
3793#define RDP_PORT_SPEED_2GB BIT_14
3794#define RDP_PORT_SPEED_4GB BIT_13
3795#define RDP_PORT_SPEED_10GB BIT_12
3796#define RDP_PORT_SPEED_8GB BIT_11
3797#define RDP_PORT_SPEED_16GB BIT_10
3798#define RDP_PORT_SPEED_32GB BIT_9
3799#define RDP_PORT_SPEED_64GB BIT_8
3800#define RDP_PORT_SPEED_UNKNOWN BIT_0
3801
3802struct scsi_qlt_host {
3803 void *target_lport_ptr;
3804 struct mutex tgt_mutex;
3805 struct mutex tgt_host_action_mutex;
3806 struct qla_tgt *qla_tgt;
3807};
3808
3809struct qlt_hw_data {
3810
3811 uint32_t node_name_set:1;
3812
3813 dma_addr_t atio_dma;
3814 struct atio *atio_ring;
3815 struct atio *atio_ring_ptr;
3816 uint16_t atio_ring_index;
3817 uint16_t atio_q_length;
3818 __le32 __iomem *atio_q_in;
3819 __le32 __iomem *atio_q_out;
3820
3821 const struct qla_tgt_func_tmpl *tgt_ops;
3822 struct qla_tgt_vp_map *tgt_vp_map;
3823
3824 int saved_set;
3825 __le16 saved_exchange_count;
3826 __le32 saved_firmware_options_1;
3827 __le32 saved_firmware_options_2;
3828 __le32 saved_firmware_options_3;
3829 uint8_t saved_firmware_options[2];
3830 uint8_t saved_add_firmware_options[2];
3831
3832 uint8_t tgt_node_name[WWN_SIZE];
3833
3834 struct dentry *dfs_tgt_sess;
3835 struct dentry *dfs_tgt_port_database;
3836 struct dentry *dfs_naqp;
3837
3838 struct list_head q_full_list;
3839 uint32_t num_pend_cmds;
3840 uint32_t num_qfull_cmds_alloc;
3841 uint32_t num_qfull_cmds_dropped;
3842 spinlock_t q_full_lock;
3843 uint32_t leak_exchg_thresh_hold;
3844 spinlock_t sess_lock;
3845 int num_act_qpairs;
3846#define DEFAULT_NAQP 2
3847 spinlock_t atio_lock ____cacheline_aligned;
3848 struct btree_head32 host_map;
3849};
3850
3851#define MAX_QFULL_CMDS_ALLOC 8192
3852#define Q_FULL_THRESH_HOLD_PERCENT 90
3853#define Q_FULL_THRESH_HOLD(ha) \
3854 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3855
3856#define LEAK_EXCHG_THRESH_HOLD_PERCENT 75
3857
3858struct qla_hw_data_stat {
3859 u32 num_fw_dump;
3860 u32 num_mpi_reset;
3861};
3862
3863
3864typedef enum {
3865 QLA_PCI_RESUME,
3866 QLA_PCI_ERR_DETECTED,
3867 QLA_PCI_MMIO_ENABLED,
3868 QLA_PCI_SLOT_RESET,
3869} pci_error_state_t;
3870
3871
3872
3873struct qla_hw_data {
3874 struct pci_dev *pdev;
3875
3876#define SRB_MIN_REQ 128
3877 mempool_t *srb_mempool;
3878
3879 volatile struct {
3880 uint32_t mbox_int :1;
3881 uint32_t mbox_busy :1;
3882 uint32_t disable_risc_code_load :1;
3883 uint32_t enable_64bit_addressing :1;
3884 uint32_t enable_lip_reset :1;
3885 uint32_t enable_target_reset :1;
3886 uint32_t enable_lip_full_login :1;
3887 uint32_t enable_led_scheme :1;
3888
3889 uint32_t msi_enabled :1;
3890 uint32_t msix_enabled :1;
3891 uint32_t disable_serdes :1;
3892 uint32_t gpsc_supported :1;
3893 uint32_t npiv_supported :1;
3894 uint32_t pci_channel_io_perm_failure :1;
3895 uint32_t fce_enabled :1;
3896 uint32_t fac_supported :1;
3897
3898 uint32_t chip_reset_done :1;
3899 uint32_t running_gold_fw :1;
3900 uint32_t eeh_busy :1;
3901 uint32_t disable_msix_handshake :1;
3902 uint32_t fcp_prio_enabled :1;
3903 uint32_t isp82xx_fw_hung:1;
3904 uint32_t nic_core_hung:1;
3905
3906 uint32_t quiesce_owner:1;
3907 uint32_t nic_core_reset_hdlr_active:1;
3908 uint32_t nic_core_reset_owner:1;
3909 uint32_t isp82xx_no_md_cap:1;
3910 uint32_t host_shutting_down:1;
3911 uint32_t idc_compl_status:1;
3912 uint32_t mr_reset_hdlr_active:1;
3913 uint32_t mr_intr_valid:1;
3914
3915 uint32_t dport_enabled:1;
3916 uint32_t fawwpn_enabled:1;
3917 uint32_t exlogins_enabled:1;
3918 uint32_t exchoffld_enabled:1;
3919
3920 uint32_t lip_ae:1;
3921 uint32_t n2n_ae:1;
3922 uint32_t fw_started:1;
3923 uint32_t fw_init_done:1;
3924
3925 uint32_t lr_detected:1;
3926
3927 uint32_t rida_fmt2:1;
3928 uint32_t purge_mbox:1;
3929 uint32_t n2n_bigger:1;
3930 uint32_t secure_adapter:1;
3931 uint32_t secure_fw:1;
3932
3933 uint32_t scm_supported_a:1;
3934
3935 uint32_t scm_supported_f:1;
3936
3937 uint32_t scm_enabled:1;
3938 uint32_t max_req_queue_warned:1;
3939 uint32_t plogi_template_valid:1;
3940 uint32_t port_isolated:1;
3941 } flags;
3942
3943 uint16_t max_exchg;
3944 uint16_t lr_distance;
3945#define LR_DISTANCE_5K 1
3946#define LR_DISTANCE_10K 0
3947
3948
3949
3950
3951
3952
3953
3954
3955 spinlock_t hardware_lock ____cacheline_aligned;
3956 int bars;
3957 int mem_only;
3958 device_reg_t *iobase;
3959 resource_size_t pio_address;
3960
3961#define MIN_IOBASE_LEN 0x100
3962 dma_addr_t bar0_hdl;
3963
3964 void __iomem *cregbase;
3965 dma_addr_t bar2_hdl;
3966#define BAR0_LEN_FX00 (1024 * 1024)
3967#define BAR2_LEN_FX00 (128 * 1024)
3968
3969 uint32_t rqstq_intr_code;
3970 uint32_t mbx_intr_code;
3971 uint32_t req_que_len;
3972 uint32_t rsp_que_len;
3973 uint32_t req_que_off;
3974 uint32_t rsp_que_off;
3975
3976
3977 device_reg_t *mqiobase;
3978 device_reg_t *msixbase;
3979 uint16_t msix_count;
3980 uint8_t mqenable;
3981 struct req_que **req_q_map;
3982 struct rsp_que **rsp_q_map;
3983 struct qla_qpair **queue_pair_map;
3984 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3985 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3986 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3987 / sizeof(unsigned long)];
3988 uint8_t max_req_queues;
3989 uint8_t max_rsp_queues;
3990 uint8_t max_qpairs;
3991 uint8_t num_qpairs;
3992 struct qla_qpair *base_qpair;
3993 struct qla_npiv_entry *npiv_info;
3994 uint16_t nvram_npiv_size;
3995
3996 uint16_t switch_cap;
3997#define FLOGI_SEQ_DEL BIT_8
3998#define FLOGI_MID_SUPPORT BIT_10
3999#define FLOGI_VSAN_SUPPORT BIT_12
4000#define FLOGI_SP_SUPPORT BIT_13
4001
4002 uint8_t port_no;
4003 uint8_t exch_starvation;
4004
4005
4006 uint8_t loop_down_abort_time;
4007 atomic_t loop_down_timer;
4008 uint8_t link_down_timeout;
4009 uint16_t max_loop_id;
4010 uint16_t max_fibre_devices;
4011
4012 uint16_t fb_rev;
4013 uint16_t min_external_loopid;
4014
4015#define PORT_SPEED_UNKNOWN 0xFFFF
4016#define PORT_SPEED_1GB 0x00
4017#define PORT_SPEED_2GB 0x01
4018#define PORT_SPEED_AUTO 0x02
4019#define PORT_SPEED_4GB 0x03
4020#define PORT_SPEED_8GB 0x04
4021#define PORT_SPEED_16GB 0x05
4022#define PORT_SPEED_32GB 0x06
4023#define PORT_SPEED_64GB 0x07
4024#define PORT_SPEED_10GB 0x13
4025 uint16_t link_data_rate;
4026 uint16_t set_data_rate;
4027
4028 uint8_t current_topology;
4029 uint8_t prev_topology;
4030#define ISP_CFG_NL 1
4031#define ISP_CFG_N 2
4032#define ISP_CFG_FL 4
4033#define ISP_CFG_F 8
4034
4035 uint8_t operating_mode;
4036#define LOOP 0
4037#define P2P 1
4038#define LOOP_P2P 2
4039#define P2P_LOOP 3
4040 uint8_t interrupts_on;
4041 uint32_t isp_abort_cnt;
4042#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
4043#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
4044#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
4045#define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
4046#define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
4047#define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
4048#define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
4049#define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
4050#define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
4051#define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
4052#define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
4053#define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
4054#define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
4055
4056 uint32_t isp_type;
4057#define DT_ISP2100 BIT_0
4058#define DT_ISP2200 BIT_1
4059#define DT_ISP2300 BIT_2
4060#define DT_ISP2312 BIT_3
4061#define DT_ISP2322 BIT_4
4062#define DT_ISP6312 BIT_5
4063#define DT_ISP6322 BIT_6
4064#define DT_ISP2422 BIT_7
4065#define DT_ISP2432 BIT_8
4066#define DT_ISP5422 BIT_9
4067#define DT_ISP5432 BIT_10
4068#define DT_ISP2532 BIT_11
4069#define DT_ISP8432 BIT_12
4070#define DT_ISP8001 BIT_13
4071#define DT_ISP8021 BIT_14
4072#define DT_ISP2031 BIT_15
4073#define DT_ISP8031 BIT_16
4074#define DT_ISPFX00 BIT_17
4075#define DT_ISP8044 BIT_18
4076#define DT_ISP2071 BIT_19
4077#define DT_ISP2271 BIT_20
4078#define DT_ISP2261 BIT_21
4079#define DT_ISP2061 BIT_22
4080#define DT_ISP2081 BIT_23
4081#define DT_ISP2089 BIT_24
4082#define DT_ISP2281 BIT_25
4083#define DT_ISP2289 BIT_26
4084#define DT_ISP_LAST (DT_ISP2289 << 1)
4085
4086 uint32_t device_type;
4087#define DT_T10_PI BIT_25
4088#define DT_IIDMA BIT_26
4089#define DT_FWI2 BIT_27
4090#define DT_ZIO_SUPPORTED BIT_28
4091#define DT_OEM_001 BIT_29
4092#define DT_ISP2200A BIT_30
4093#define DT_EXTENDED_IDS BIT_31
4094
4095#define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
4096#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
4097#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
4098#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
4099#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
4100#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
4101#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
4102#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
4103#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
4104#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
4105#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
4106#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
4107#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
4108#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
4109#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
4110#define IS_QLA81XX(ha) (IS_QLA8001(ha))
4111#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
4112#define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
4113#define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
4114#define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
4115#define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
4116#define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
4117#define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
4118#define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
4119#define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
4120#define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
4121
4122#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
4123 IS_QLA6312(ha) || IS_QLA6322(ha))
4124#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
4125#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
4126#define IS_QLA25XX(ha) (IS_QLA2532(ha))
4127#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
4128#define IS_QLA84XX(ha) (IS_QLA8432(ha))
4129#define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
4130#define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
4131#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
4132 IS_QLA84XX(ha))
4133#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
4134 IS_QLA8031(ha) || IS_QLA8044(ha))
4135#define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
4136#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
4137 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
4138 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
4139 IS_QLA8044(ha) || IS_QLA27XX(ha) || \
4140 IS_QLA28XX(ha))
4141#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4142 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4143#define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
4144#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4145 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4146#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4147 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4148#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
4149
4150#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
4151#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
4152#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
4153#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
4154#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
4155#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
4156#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
4157#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
4158 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4159#define IS_BIDI_CAPABLE(ha) \
4160 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4161
4162#define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
4163 ((ha)->fw_attributes_ext[0] & BIT_0))
4164#define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14)
4165#define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS)
4166#define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD)
4167#define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp))
4168#define QLA_LS_ABTS_WAIT_ENABLED(_sp) \
4169 (QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4170#define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \
4171 (QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4172#define QLA_ABTS_WAIT_ENABLED(_sp) \
4173 (QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4174
4175#define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4176#define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4177#define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
4178#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4179 IS_QLA28XX(ha))
4180#define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
4181 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
4182#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4183 IS_QLA28XX(ha))
4184#define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
4185#define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
4186#define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4187 IS_QLA28XX(ha))
4188#define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4189 IS_QLA28XX(ha))
4190#define IS_EXCHG_OFFLD_CAPABLE(ha) \
4191 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4192#define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
4193 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4194 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4195#define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
4196 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4197
4198#define IS_ZIO_THRESHOLD_CAPABLE(ha) \
4199 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\
4200 (ha->zio_mode == QLA_ZIO_MODE_6))
4201
4202
4203 uint8_t serial0;
4204 uint8_t serial1;
4205 uint8_t serial2;
4206
4207
4208#define MAX_NVRAM_SIZE 4096
4209#define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
4210 uint16_t nvram_size;
4211 uint16_t nvram_base;
4212 void *nvram;
4213 uint16_t vpd_size;
4214 uint16_t vpd_base;
4215 void *vpd;
4216
4217 uint16_t loop_reset_delay;
4218 uint8_t retry_count;
4219 uint8_t login_timeout;
4220 uint16_t r_a_tov;
4221 int port_down_retry_count;
4222 uint8_t mbx_count;
4223 uint8_t aen_mbx_count;
4224 atomic_t num_pend_mbx_stage1;
4225 atomic_t num_pend_mbx_stage2;
4226 atomic_t num_pend_mbx_stage3;
4227 uint16_t frame_payload_size;
4228
4229 uint32_t login_retry_count;
4230
4231 ms_iocb_entry_t *ms_iocb;
4232 dma_addr_t ms_iocb_dma;
4233 struct ct_sns_pkt *ct_sns;
4234 dma_addr_t ct_sns_dma;
4235
4236 struct sns_cmd_pkt *sns_cmd;
4237 dma_addr_t sns_cmd_dma;
4238
4239#define SFP_DEV_SIZE 512
4240#define SFP_BLOCK_SIZE 64
4241#define SFP_RTDI_LEN SFP_BLOCK_SIZE
4242
4243 void *sfp_data;
4244 dma_addr_t sfp_data_dma;
4245
4246 struct qla_flt_header *flt;
4247 dma_addr_t flt_dma;
4248
4249#define XGMAC_DATA_SIZE 4096
4250 void *xgmac_data;
4251 dma_addr_t xgmac_data_dma;
4252
4253#define DCBX_TLV_DATA_SIZE 4096
4254 void *dcbx_tlv;
4255 dma_addr_t dcbx_tlv_dma;
4256
4257 struct task_struct *dpc_thread;
4258 uint8_t dpc_active;
4259
4260 dma_addr_t gid_list_dma;
4261 struct gid_list_info *gid_list;
4262 int gid_list_info_size;
4263
4264
4265#define DMA_POOL_SIZE 256
4266 struct dma_pool *s_dma_pool;
4267
4268 dma_addr_t init_cb_dma;
4269 init_cb_t *init_cb;
4270 int init_cb_size;
4271 dma_addr_t ex_init_cb_dma;
4272 struct ex_init_cb_81xx *ex_init_cb;
4273 dma_addr_t sf_init_cb_dma;
4274 struct init_sf_cb *sf_init_cb;
4275
4276 void *scm_fpin_els_buff;
4277 uint64_t scm_fpin_els_buff_size;
4278 bool scm_fpin_valid;
4279 bool scm_fpin_payload_size;
4280
4281 void *async_pd;
4282 dma_addr_t async_pd_dma;
4283
4284#define ENABLE_EXTENDED_LOGIN BIT_7
4285
4286
4287 void *exlogin_buf;
4288 dma_addr_t exlogin_buf_dma;
4289 uint32_t exlogin_size;
4290
4291#define ENABLE_EXCHANGE_OFFLD BIT_2
4292
4293
4294 void *exchoffld_buf;
4295 dma_addr_t exchoffld_buf_dma;
4296 int exchoffld_size;
4297 int exchoffld_count;
4298
4299
4300 struct fc_els_flogi plogi_els_payld;
4301#define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4)
4302
4303 void *swl;
4304
4305
4306 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
4307 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
4308 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
4309
4310 mbx_cmd_t *mcp;
4311 struct mbx_cmd_32 *mcp32;
4312
4313 unsigned long mbx_cmd_flags;
4314#define MBX_INTERRUPT 1
4315#define MBX_INTR_WAIT 2
4316#define MBX_UPDATE_FLASH_ACTIVE 3
4317
4318 struct mutex vport_lock;
4319 spinlock_t vport_slock;
4320 struct mutex mq_lock;
4321 struct completion mbx_cmd_comp;
4322 struct completion mbx_intr_comp;
4323 struct completion dcbx_comp;
4324 struct completion lb_portup_comp;
4325
4326#define DCBX_COMP_TIMEOUT 20
4327#define LB_PORTUP_COMP_TIMEOUT 10
4328
4329 int notify_dcbx_comp;
4330 int notify_lb_portup_comp;
4331 struct mutex selflogin_lock;
4332
4333
4334 uint16_t fw_major_version;
4335 uint16_t fw_minor_version;
4336 uint16_t fw_subminor_version;
4337 uint16_t fw_attributes;
4338 uint16_t fw_attributes_h;
4339#define FW_ATTR_H_NVME_FBURST BIT_1
4340#define FW_ATTR_H_NVME BIT_10
4341#define FW_ATTR_H_NVME_UPDATED BIT_14
4342
4343
4344#define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12
4345
4346#define FW_ATTR_EXT0_SCM_BROCADE 0x00001000
4347
4348#define FW_ATTR_EXT0_SCM_CISCO 0x00002000
4349#define FW_ATTR_EXT0_NVME2 BIT_13
4350 uint16_t fw_attributes_ext[2];
4351 uint32_t fw_memory_size;
4352 uint32_t fw_transfer_size;
4353 uint32_t fw_srisc_address;
4354#define RISC_START_ADDRESS_2100 0x1000
4355#define RISC_START_ADDRESS_2300 0x800
4356#define RISC_START_ADDRESS_2400 0x100000
4357
4358 uint16_t orig_fw_tgt_xcb_count;
4359 uint16_t cur_fw_tgt_xcb_count;
4360 uint16_t orig_fw_xcb_count;
4361 uint16_t cur_fw_xcb_count;
4362 uint16_t orig_fw_iocb_count;
4363 uint16_t cur_fw_iocb_count;
4364 uint16_t fw_max_fcf_count;
4365
4366 uint32_t fw_shared_ram_start;
4367 uint32_t fw_shared_ram_end;
4368 uint32_t fw_ddr_ram_start;
4369 uint32_t fw_ddr_ram_end;
4370
4371 uint16_t fw_options[16];
4372 uint8_t fw_seriallink_options[4];
4373 __le16 fw_seriallink_options24[4];
4374
4375 uint8_t serdes_version[3];
4376 uint8_t mpi_version[3];
4377 uint32_t mpi_capabilities;
4378 uint8_t phy_version[3];
4379 uint8_t pep_version[3];
4380
4381
4382 struct fwdt {
4383 void *template;
4384 ulong length;
4385 ulong dump_size;
4386 } fwdt[2];
4387 struct qla2xxx_fw_dump *fw_dump;
4388 uint32_t fw_dump_len;
4389 u32 fw_dump_alloc_len;
4390 bool fw_dumped;
4391 unsigned long fw_dump_cap_flags;
4392#define RISC_PAUSE_CMPL 0
4393#define DMA_SHUTDOWN_CMPL 1
4394#define ISP_RESET_CMPL 2
4395#define RISC_RDY_AFT_RESET 3
4396#define RISC_SRAM_DUMP_CMPL 4
4397#define RISC_EXT_MEM_DUMP_CMPL 5
4398#define ISP_MBX_RDY 6
4399#define ISP_SOFT_RESET_CMPL 7
4400 int fw_dump_reading;
4401 void *mpi_fw_dump;
4402 u32 mpi_fw_dump_len;
4403 unsigned int mpi_fw_dump_reading:1;
4404 unsigned int mpi_fw_dumped:1;
4405 int prev_minidump_failed;
4406 dma_addr_t eft_dma;
4407 void *eft;
4408
4409#define MCTP_DUMP_SIZE 0x086064
4410 dma_addr_t mctp_dump_dma;
4411 void *mctp_dump;
4412 int mctp_dumped;
4413 int mctp_dump_reading;
4414 uint32_t chain_offset;
4415 struct dentry *dfs_dir;
4416 struct dentry *dfs_fce;
4417 struct dentry *dfs_tgt_counters;
4418 struct dentry *dfs_fw_resource_cnt;
4419
4420 dma_addr_t fce_dma;
4421 void *fce;
4422 uint32_t fce_bufs;
4423 uint16_t fce_mb[8];
4424 uint64_t fce_wr, fce_rd;
4425 struct mutex fce_mutex;
4426
4427 uint32_t pci_attr;
4428 uint16_t chip_revision;
4429
4430 uint16_t product_id[4];
4431
4432 uint8_t model_number[16+1];
4433 char model_desc[80];
4434 uint8_t adapter_id[16+1];
4435
4436
4437 char *optrom_buffer;
4438 uint32_t optrom_size;
4439 int optrom_state;
4440#define QLA_SWAITING 0
4441#define QLA_SREADING 1
4442#define QLA_SWRITING 2
4443 uint32_t optrom_region_start;
4444 uint32_t optrom_region_size;
4445 struct mutex optrom_mutex;
4446
4447
4448#define ROM_CODE_TYPE_BIOS 0
4449#define ROM_CODE_TYPE_FCODE 1
4450#define ROM_CODE_TYPE_EFI 3
4451 uint8_t bios_revision[2];
4452 uint8_t efi_revision[2];
4453 uint8_t fcode_revision[16];
4454 uint32_t fw_revision[4];
4455
4456 uint32_t gold_fw_version[4];
4457
4458
4459 uint32_t flash_conf_off;
4460 uint32_t flash_data_off;
4461 uint32_t nvram_conf_off;
4462 uint32_t nvram_data_off;
4463
4464 uint32_t fdt_wrt_disable;
4465 uint32_t fdt_wrt_enable;
4466 uint32_t fdt_erase_cmd;
4467 uint32_t fdt_block_size;
4468 uint32_t fdt_unprotect_sec_cmd;
4469 uint32_t fdt_protect_sec_cmd;
4470 uint32_t fdt_wrt_sts_reg_cmd;
4471
4472 struct {
4473 uint32_t flt_region_flt;
4474 uint32_t flt_region_fdt;
4475 uint32_t flt_region_boot;
4476 uint32_t flt_region_boot_sec;
4477 uint32_t flt_region_fw;
4478 uint32_t flt_region_fw_sec;
4479 uint32_t flt_region_vpd_nvram;
4480 uint32_t flt_region_vpd_nvram_sec;
4481 uint32_t flt_region_vpd;
4482 uint32_t flt_region_vpd_sec;
4483 uint32_t flt_region_nvram;
4484 uint32_t flt_region_nvram_sec;
4485 uint32_t flt_region_npiv_conf;
4486 uint32_t flt_region_gold_fw;
4487 uint32_t flt_region_fcp_prio;
4488 uint32_t flt_region_bootload;
4489 uint32_t flt_region_img_status_pri;
4490 uint32_t flt_region_img_status_sec;
4491 uint32_t flt_region_aux_img_status_pri;
4492 uint32_t flt_region_aux_img_status_sec;
4493 };
4494 uint8_t active_image;
4495
4496
4497 uint16_t beacon_blink_led;
4498 uint8_t beacon_color_state;
4499#define QLA_LED_GRN_ON 0x01
4500#define QLA_LED_YLW_ON 0x02
4501#define QLA_LED_ABR_ON 0x04
4502#define QLA_LED_ALL_ON 0x07
4503
4504 uint16_t zio_mode;
4505 uint16_t zio_timer;
4506
4507 struct qla_msix_entry *msix_entries;
4508
4509 struct list_head vp_list;
4510 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4511 sizeof(unsigned long)];
4512 uint16_t num_vhosts;
4513 uint16_t num_vsans;
4514 uint16_t max_npiv_vports;
4515 int cur_vport_count;
4516
4517 struct qla_chip_state_84xx *cs84xx;
4518 struct isp_operations *isp_ops;
4519 struct workqueue_struct *wq;
4520 struct qlfc_fw fw_buf;
4521
4522
4523 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4524
4525 struct dma_pool *dl_dma_pool;
4526#define DSD_LIST_DMA_POOL_SIZE 512
4527
4528 struct dma_pool *fcp_cmnd_dma_pool;
4529 mempool_t *ctx_mempool;
4530#define FCP_CMND_DMA_POOL_SIZE 512
4531
4532 void __iomem *nx_pcibase;
4533 void __iomem *nxdb_rd_ptr;
4534 void __iomem *nxdb_wr_ptr;
4535
4536 uint32_t crb_win;
4537 uint32_t curr_window;
4538 uint32_t ddr_mn_window;
4539 unsigned long mn_win_crb;
4540 unsigned long ms_win_crb;
4541 int qdr_sn_window;
4542 uint32_t fcoe_dev_init_timeout;
4543 uint32_t fcoe_reset_timeout;
4544 rwlock_t hw_lock;
4545 uint16_t portnum;
4546 int link_width;
4547 struct fw_blob *hablob;
4548 struct qla82xx_legacy_intr_set nx_legacy_intr;
4549
4550 uint16_t gbl_dsd_inuse;
4551 uint16_t gbl_dsd_avail;
4552 struct list_head gbl_dsd_list;
4553#define NUM_DSD_CHAIN 4096
4554
4555 uint8_t fw_type;
4556 uint32_t file_prd_off;
4557
4558 uint32_t md_template_size;
4559 void *md_tmplt_hdr;
4560 dma_addr_t md_tmplt_hdr_dma;
4561 void *md_dump;
4562 uint32_t md_dump_size;
4563
4564 void *loop_id_map;
4565
4566
4567 uint32_t idc_audit_ts;
4568 uint32_t idc_extend_tmo;
4569
4570
4571 struct workqueue_struct *dpc_lp_wq;
4572 struct work_struct idc_aen;
4573
4574 struct workqueue_struct *dpc_hp_wq;
4575 struct work_struct nic_core_reset;
4576 struct work_struct idc_state_handler;
4577 struct work_struct nic_core_unrecoverable;
4578 struct work_struct board_disable;
4579
4580 struct mr_data_fx00 mr;
4581 uint32_t chip_reset;
4582
4583 struct qlt_hw_data tgt;
4584 int allow_cna_fw_dump;
4585 uint32_t fw_ability_mask;
4586 uint16_t min_supported_speed;
4587 uint16_t max_supported_speed;
4588
4589
4590 struct dma_pool *dif_bundl_pool;
4591 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4592 struct {
4593 struct {
4594 struct list_head head;
4595 uint count;
4596 } good;
4597 struct {
4598 struct list_head head;
4599 uint count;
4600 } unusable;
4601 } pool;
4602
4603 unsigned long long dif_bundle_crossed_pages;
4604 unsigned long long dif_bundle_reads;
4605 unsigned long long dif_bundle_writes;
4606 unsigned long long dif_bundle_kallocs;
4607 unsigned long long dif_bundle_dma_allocs;
4608
4609 atomic_t nvme_active_aen_cnt;
4610 uint16_t nvme_last_rptd_aen;
4611
4612 uint8_t fc4_type_priority;
4613
4614 atomic_t zio_threshold;
4615 uint16_t last_zio_threshold;
4616
4617#define DEFAULT_ZIO_THRESHOLD 5
4618
4619 struct qla_hw_data_stat stat;
4620 pci_error_state_t pci_error_state;
4621 u64 prev_cmd_cnt;
4622};
4623
4624struct active_regions {
4625 uint8_t global;
4626 struct {
4627 uint8_t board_config;
4628 uint8_t vpd_nvram;
4629 uint8_t npiv_config_0_1;
4630 uint8_t npiv_config_2_3;
4631 } aux;
4632};
4633
4634#define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4635#define FW_ABILITY_MAX_SPEED_16G 0x0
4636#define FW_ABILITY_MAX_SPEED_32G 0x1
4637#define FW_ABILITY_MAX_SPEED(ha) \
4638 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4639
4640#define QLA_GET_DATA_RATE 0
4641#define QLA_SET_DATA_RATE_NOLR 1
4642#define QLA_SET_DATA_RATE_LR 2
4643
4644#define QLA_DEFAULT_PAYLOAD_SIZE 64
4645
4646
4647
4648
4649
4650struct purex_item {
4651 struct list_head list;
4652 struct scsi_qla_host *vha;
4653 void (*process_item)(struct scsi_qla_host *vha,
4654 struct purex_item *pkt);
4655 atomic_t in_use;
4656 uint16_t size;
4657 struct {
4658 uint8_t iocb[64];
4659 } iocb;
4660};
4661
4662#define SCM_FLAG_RDF_REJECT 0x00
4663#define SCM_FLAG_RDF_COMPLETED 0x01
4664
4665#define QLA_CON_PRIMITIVE_RECEIVED 0x1
4666#define QLA_CONGESTION_ARB_WARNING 0x1
4667#define QLA_CONGESTION_ARB_ALARM 0X2
4668
4669
4670
4671
4672typedef struct scsi_qla_host {
4673 struct list_head list;
4674 struct list_head vp_fcports;
4675 struct list_head work_list;
4676 spinlock_t work_lock;
4677 struct work_struct iocb_work;
4678
4679
4680 struct Scsi_Host *host;
4681 unsigned long host_no;
4682 uint8_t host_str[16];
4683
4684 volatile struct {
4685 uint32_t init_done :1;
4686 uint32_t online :1;
4687 uint32_t reset_active :1;
4688
4689 uint32_t management_server_logged_in :1;
4690 uint32_t process_response_queue :1;
4691 uint32_t difdix_supported:1;
4692 uint32_t delete_progress:1;
4693
4694 uint32_t fw_tgt_reported:1;
4695 uint32_t bbcr_enable:1;
4696 uint32_t qpairs_available:1;
4697 uint32_t qpairs_req_created:1;
4698 uint32_t qpairs_rsp_created:1;
4699 uint32_t nvme_enabled:1;
4700 uint32_t nvme_first_burst:1;
4701 uint32_t nvme2_enabled:1;
4702 } flags;
4703
4704 atomic_t loop_state;
4705#define LOOP_TIMEOUT 1
4706#define LOOP_DOWN 2
4707#define LOOP_UP 3
4708#define LOOP_UPDATE 4
4709#define LOOP_READY 5
4710#define LOOP_DEAD 6
4711
4712 unsigned long relogin_jif;
4713 unsigned long dpc_flags;
4714#define RESET_MARKER_NEEDED 0
4715#define RESET_ACTIVE 1
4716#define ISP_ABORT_NEEDED 2
4717#define ABORT_ISP_ACTIVE 3
4718#define LOOP_RESYNC_NEEDED 4
4719#define LOOP_RESYNC_ACTIVE 5
4720#define LOCAL_LOOP_UPDATE 6
4721#define RSCN_UPDATE 7
4722#define RELOGIN_NEEDED 8
4723#define REGISTER_FC4_NEEDED 9
4724#define ISP_ABORT_RETRY 10
4725#define BEACON_BLINK_NEEDED 11
4726#define REGISTER_FDMI_NEEDED 12
4727#define FCPORT_UPDATE_NEEDED 13
4728#define VP_DPC_NEEDED 14
4729#define UNLOADING 15
4730#define NPIV_CONFIG_NEEDED 16
4731#define ISP_UNRECOVERABLE 17
4732#define FCOE_CTX_RESET_NEEDED 18
4733#define MPI_RESET_NEEDED 19
4734#define ISP_QUIESCE_NEEDED 20
4735#define N2N_LINK_RESET 21
4736#define PORT_UPDATE_NEEDED 22
4737#define FX00_RESET_RECOVERY 23
4738#define FX00_TARGET_SCAN 24
4739#define FX00_CRITEMP_RECOVERY 25
4740#define FX00_HOST_INFO_RESEND 26
4741#define QPAIR_ONLINE_CHECK_NEEDED 27
4742#define DO_EEH_RECOVERY 28
4743#define DETECT_SFP_CHANGE 29
4744#define N2N_LOGIN_NEEDED 30
4745#define IOCB_WORK_ACTIVE 31
4746#define SET_ZIO_THRESHOLD_NEEDED 32
4747#define ISP_ABORT_TO_ROM 33
4748#define VPORT_DELETE 34
4749#define HEARTBEAT_CHK 38
4750
4751#define PROCESS_PUREX_IOCB 63
4752
4753 unsigned long pci_flags;
4754#define PFLG_DISCONNECTED 0
4755#define PFLG_DRIVER_REMOVING 1
4756#define PFLG_DRIVER_PROBING 2
4757
4758 uint32_t device_flags;
4759#define SWITCH_FOUND BIT_0
4760#define DFLG_NO_CABLE BIT_1
4761#define DFLG_DEV_FAILED BIT_5
4762
4763
4764 uint16_t loop_id;
4765 uint16_t self_login_loop_id;
4766
4767
4768 fc_port_t bidir_fcport;
4769
4770
4771
4772
4773 port_id_t d_id;
4774 uint8_t marker_needed;
4775 uint16_t mgmt_svr_loop_id;
4776
4777
4778
4779
4780 uint8_t loop_down_abort_time;
4781 atomic_t loop_down_timer;
4782 uint8_t link_down_timeout;
4783
4784 uint32_t timer_active;
4785 struct timer_list timer;
4786
4787 uint8_t node_name[WWN_SIZE];
4788 uint8_t port_name[WWN_SIZE];
4789 uint8_t fabric_node_name[WWN_SIZE];
4790 uint8_t fabric_port_name[WWN_SIZE];
4791
4792 struct nvme_fc_local_port *nvme_local_port;
4793 struct completion nvme_del_done;
4794
4795 uint16_t fcoe_vlan_id;
4796 uint16_t fcoe_fcf_idx;
4797 uint8_t fcoe_vn_port_mac[6];
4798
4799
4800 struct list_head qla_cmd_list;
4801 struct list_head qla_sess_op_cmd_list;
4802 struct list_head unknown_atio_list;
4803 spinlock_t cmd_list_lock;
4804 struct delayed_work unknown_atio_work;
4805
4806
4807 atomic_t generation_tick;
4808
4809 int total_fcport_update_gen;
4810
4811 struct list_head logo_list;
4812
4813 struct list_head plogi_ack_list;
4814
4815 struct list_head qp_list;
4816
4817 uint32_t vp_abort_cnt;
4818
4819 struct fc_vport *fc_vport;
4820 uint16_t vp_idx;
4821 struct qla_qpair *qpair;
4822
4823 unsigned long vp_flags;
4824#define VP_IDX_ACQUIRED 0
4825#define VP_CREATE_NEEDED 1
4826#define VP_BIND_NEEDED 2
4827#define VP_DELETE_NEEDED 3
4828#define VP_SCR_NEEDED 4
4829#define VP_CONFIG_OK 5
4830 atomic_t vp_state;
4831#define VP_OFFLINE 0
4832#define VP_ACTIVE 1
4833#define VP_FAILED 2
4834
4835 uint16_t vp_err_state;
4836 uint16_t vp_prev_err_state;
4837#define VP_ERR_UNKWN 0
4838#define VP_ERR_PORTDWN 1
4839#define VP_ERR_FAB_UNSUPPORTED 2
4840#define VP_ERR_FAB_NORESOURCES 3
4841#define VP_ERR_FAB_LOGOUT 4
4842#define VP_ERR_ADAP_NORESOURCES 5
4843 struct qla_hw_data *hw;
4844 struct scsi_qlt_host vha_tgt;
4845 struct req_que *req;
4846 int fw_heartbeat_counter;
4847 int seconds_since_last_heartbeat;
4848 struct fc_host_statistics fc_host_stat;
4849 struct qla_statistics qla_stats;
4850 struct bidi_statistics bidi_stats;
4851 atomic_t vref_count;
4852 struct qla8044_reset_template reset_tmplt;
4853 uint16_t bbcr;
4854
4855 uint16_t u_ql2xexchoffld;
4856 uint16_t u_ql2xiniexchg;
4857 uint16_t qlini_mode;
4858 uint16_t ql2xexchoffld;
4859 uint16_t ql2xiniexchg;
4860
4861 struct dentry *dfs_rport_root;
4862
4863 struct purex_list {
4864 struct list_head head;
4865 spinlock_t lock;
4866 } purex_list;
4867 struct purex_item default_item;
4868
4869 struct name_list_extended gnl;
4870
4871 int fcport_count;
4872 wait_queue_head_t fcport_waitQ;
4873 wait_queue_head_t vref_waitq;
4874 uint8_t min_supported_speed;
4875 uint8_t n2n_node_name[WWN_SIZE];
4876 uint8_t n2n_port_name[WWN_SIZE];
4877 uint16_t n2n_id;
4878 __le16 dport_data[4];
4879 struct list_head gpnid_list;
4880 struct fab_scan scan;
4881 uint8_t scm_fabric_connection_flags;
4882
4883 unsigned int irq_offset;
4884
4885 u64 hw_err_cnt;
4886 u64 interface_err_cnt;
4887 u64 cmd_timeout_cnt;
4888 u64 reset_cmd_err_cnt;
4889 u64 link_down_time;
4890 u64 short_link_down_cnt;
4891} scsi_qla_host_t;
4892
4893struct qla27xx_image_status {
4894 uint8_t image_status_mask;
4895 __le16 generation;
4896 uint8_t ver_major;
4897 uint8_t ver_minor;
4898 uint8_t bitmap;
4899 uint8_t reserved[2];
4900 __le32 checksum;
4901 __le32 signature;
4902} __packed;
4903
4904
4905#define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
4906#define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
4907#define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
4908#define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
4909
4910#define SET_VP_IDX 1
4911#define SET_AL_PA 2
4912#define RESET_VP_IDX 3
4913#define RESET_AL_PA 4
4914struct qla_tgt_vp_map {
4915 uint8_t idx;
4916 scsi_qla_host_t *vha;
4917};
4918
4919struct qla2_sgx {
4920 dma_addr_t dma_addr;
4921 uint32_t dma_len;
4922
4923 uint32_t tot_bytes;
4924 struct scatterlist *cur_sg;
4925
4926
4927 uint32_t bytes_consumed;
4928 uint32_t num_bytes;
4929 uint32_t tot_partial;
4930
4931
4932 uint32_t num_sg;
4933 srb_t *sp;
4934};
4935
4936#define QLA_FW_STARTED(_ha) { \
4937 int i; \
4938 _ha->flags.fw_started = 1; \
4939 _ha->base_qpair->fw_started = 1; \
4940 for (i = 0; i < _ha->max_qpairs; i++) { \
4941 if (_ha->queue_pair_map[i]) \
4942 _ha->queue_pair_map[i]->fw_started = 1; \
4943 } \
4944}
4945
4946#define QLA_FW_STOPPED(_ha) { \
4947 int i; \
4948 _ha->flags.fw_started = 0; \
4949 _ha->base_qpair->fw_started = 0; \
4950 for (i = 0; i < _ha->max_qpairs; i++) { \
4951 if (_ha->queue_pair_map[i]) \
4952 _ha->queue_pair_map[i]->fw_started = 0; \
4953 } \
4954}
4955
4956
4957#define SFUB_CHECKSUM_SIZE 4
4958
4959struct secure_flash_update_block {
4960 uint32_t block_info;
4961 uint32_t signature_lo;
4962 uint32_t signature_hi;
4963 uint32_t signature_upper[0x3e];
4964};
4965
4966struct secure_flash_update_block_pk {
4967 uint32_t block_info;
4968 uint32_t signature_lo;
4969 uint32_t signature_hi;
4970 uint32_t signature_upper[0x3e];
4971 uint32_t public_key[0x41];
4972};
4973
4974
4975
4976
4977#define LOOP_TRANSITION(ha) \
4978 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4979 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4980 atomic_read(&ha->loop_state) == LOOP_DOWN)
4981
4982#define STATE_TRANSITION(ha) \
4983 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4984 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4985
4986#define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4987 atomic_inc(&__vha->vref_count); \
4988 mb(); \
4989 if (__vha->flags.delete_progress) { \
4990 atomic_dec(&__vha->vref_count); \
4991 wake_up(&__vha->vref_waitq); \
4992 __bail = 1; \
4993 } else { \
4994 __bail = 0; \
4995 } \
4996} while (0)
4997
4998#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4999 atomic_dec(&__vha->vref_count); \
5000 wake_up(&__vha->vref_waitq); \
5001} while (0) \
5002
5003#define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
5004 atomic_inc(&__qpair->ref_count); \
5005 mb(); \
5006 if (__qpair->delete_in_progress) { \
5007 atomic_dec(&__qpair->ref_count); \
5008 __bail = 1; \
5009 } else { \
5010 __bail = 0; \
5011 } \
5012} while (0)
5013
5014#define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
5015 atomic_dec(&__qpair->ref_count)
5016
5017#define QLA_ENA_CONF(_ha) {\
5018 int i;\
5019 _ha->base_qpair->enable_explicit_conf = 1; \
5020 for (i = 0; i < _ha->max_qpairs; i++) { \
5021 if (_ha->queue_pair_map[i]) \
5022 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
5023 } \
5024}
5025
5026#define QLA_DIS_CONF(_ha) {\
5027 int i;\
5028 _ha->base_qpair->enable_explicit_conf = 0; \
5029 for (i = 0; i < _ha->max_qpairs; i++) { \
5030 if (_ha->queue_pair_map[i]) \
5031 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
5032 } \
5033}
5034
5035
5036
5037
5038#define MBS_MASK 0x3fff
5039
5040#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
5041#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
5042#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
5043#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
5044#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
5045#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
5046#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
5047#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
5048#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
5049#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
5050
5051#define QLA_FUNCTION_TIMEOUT 0x100
5052#define QLA_FUNCTION_PARAMETER_ERROR 0x101
5053#define QLA_FUNCTION_FAILED 0x102
5054#define QLA_MEMORY_ALLOC_FAILED 0x103
5055#define QLA_LOCK_TIMEOUT 0x104
5056#define QLA_ABORTED 0x105
5057#define QLA_SUSPENDED 0x106
5058#define QLA_BUSY 0x107
5059#define QLA_ALREADY_REGISTERED 0x109
5060#define QLA_OS_TIMER_EXPIRED 0x10a
5061
5062#define NVRAM_DELAY() udelay(10)
5063
5064
5065
5066
5067#define OPTROM_SIZE_2300 0x20000
5068#define OPTROM_SIZE_2322 0x100000
5069#define OPTROM_SIZE_24XX 0x100000
5070#define OPTROM_SIZE_25XX 0x200000
5071#define OPTROM_SIZE_81XX 0x400000
5072#define OPTROM_SIZE_82XX 0x800000
5073#define OPTROM_SIZE_83XX 0x1000000
5074#define OPTROM_SIZE_28XX 0x2000000
5075
5076#define OPTROM_BURST_SIZE 0x1000
5077#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
5078
5079#define QLA_DSDS_PER_IOCB 37
5080
5081#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
5082
5083#define QLA_SG_ALL 1024
5084
5085enum nexus_wait_type {
5086 WAIT_HOST = 0,
5087 WAIT_TARGET,
5088 WAIT_LUN,
5089};
5090
5091
5092struct sff_8247_a0 {
5093 u8 txid;
5094 u8 ext_txid;
5095 u8 connector;
5096
5097 u8 eth_infi_cc3;
5098 u8 sonet_cc4[2];
5099 u8 eth_cc6;
5100
5101#define FC_LL_VL BIT_7
5102#define FC_LL_S BIT_6
5103#define FC_LL_I BIT_5
5104#define FC_LL_L BIT_4
5105#define FC_LL_M BIT_3
5106#define FC_LL_SA BIT_2
5107#define FC_LL_LC BIT_1
5108#define FC_LL_EL BIT_0
5109 u8 fc_ll_cc7;
5110
5111#define FC_TEC_EL BIT_7
5112#define FC_TEC_SN BIT_6
5113#define FC_TEC_SL BIT_5
5114#define FC_TEC_LL BIT_4
5115#define FC_TEC_ACT BIT_3
5116#define FC_TEC_PAS BIT_2
5117 u8 fc_tec_cc8;
5118
5119#define FC_MED_TW BIT_7
5120#define FC_MED_TP BIT_6
5121#define FC_MED_MI BIT_5
5122#define FC_MED_TV BIT_4
5123#define FC_MED_M6 BIT_3
5124#define FC_MED_M5 BIT_2
5125#define FC_MED_SM BIT_0
5126 u8 fc_med_cc9;
5127
5128#define FC_SP_12 BIT_7
5129#define FC_SP_8 BIT_6
5130#define FC_SP_16 BIT_5
5131#define FC_SP_4 BIT_4
5132#define FC_SP_32 BIT_3
5133#define FC_SP_2 BIT_2
5134#define FC_SP_1 BIT_0
5135 u8 fc_sp_cc10;
5136 u8 encode;
5137 u8 bitrate;
5138 u8 rate_id;
5139 u8 length_km;
5140 u8 length_100m;
5141 u8 length_50um_10m;
5142 u8 length_62um_10m;
5143 u8 length_om4_10m;
5144 u8 length_om3_10m;
5145#define SFF_VEN_NAME_LEN 16
5146 u8 vendor_name[SFF_VEN_NAME_LEN];
5147 u8 tx_compat;
5148 u8 vendor_oui[3];
5149#define SFF_PART_NAME_LEN 16
5150 u8 vendor_pn[SFF_PART_NAME_LEN];
5151 u8 vendor_rev[4];
5152 u8 wavelength[2];
5153 u8 resv;
5154 u8 cc_base;
5155 u8 options[2];
5156 u8 br_max;
5157 u8 br_min;
5158 u8 vendor_sn[16];
5159 u8 date_code[8];
5160 u8 diag;
5161 u8 enh_options;
5162 u8 sff_revision;
5163 u8 cc_ext;
5164 u8 vendor_specific[32];
5165 u8 resv2[128];
5166};
5167
5168
5169#define IS_BPM_CAPABLE(ha) \
5170 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
5171 IS_QLA27XX(ha) || IS_QLA28XX(ha))
5172#define IS_BPM_RANGE_CAPABLE(ha) \
5173 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5174#define IS_BPM_ENABLED(vha) \
5175 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw))
5176
5177#define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
5178
5179#define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
5180 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
5181
5182#define SAVE_TOPO(_ha) { \
5183 if (_ha->current_topology) \
5184 _ha->prev_topology = _ha->current_topology; \
5185}
5186
5187#define N2N_TOPO(ha) \
5188 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
5189 ha->current_topology == ISP_CFG_N || \
5190 !ha->current_topology)
5191
5192#define QLA_N2N_WAIT_TIME 5
5193
5194#define NVME_TYPE(fcport) \
5195 (fcport->fc4_type & FS_FC4TYPE_NVME) \
5196
5197#define FCP_TYPE(fcport) \
5198 (fcport->fc4_type & FS_FC4TYPE_FCP) \
5199
5200#define NVME_ONLY_TARGET(fcport) \
5201 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \
5202
5203#define NVME_FCP_TARGET(fcport) \
5204 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \
5205
5206#define NVME_TARGET(ha, fcport) \
5207 ((NVME_FCP_TARGET(fcport) && \
5208 (ha->fc4_type_priority == FC4_PRIORITY_NVME)) || \
5209 NVME_ONLY_TARGET(fcport)) \
5210
5211#define PRLI_PHASE(_cls) \
5212 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP))
5213
5214enum ql_vnd_host_stat_action {
5215 QLA_STOP = 0,
5216 QLA_START,
5217 QLA_CLEAR,
5218};
5219
5220struct ql_vnd_mng_host_stats_param {
5221 u32 stat_type;
5222 enum ql_vnd_host_stat_action action;
5223} __packed;
5224
5225struct ql_vnd_mng_host_stats_resp {
5226 u32 status;
5227} __packed;
5228
5229struct ql_vnd_stats_param {
5230 u32 stat_type;
5231} __packed;
5232
5233struct ql_vnd_tgt_stats_param {
5234 s32 tgt_id;
5235 u32 stat_type;
5236} __packed;
5237
5238enum ql_vnd_host_port_action {
5239 QLA_ENABLE = 0,
5240 QLA_DISABLE,
5241};
5242
5243struct ql_vnd_mng_host_port_param {
5244 enum ql_vnd_host_port_action action;
5245} __packed;
5246
5247struct ql_vnd_mng_host_port_resp {
5248 u32 status;
5249} __packed;
5250
5251struct ql_vnd_stat_entry {
5252 u32 stat_type;
5253 u32 tgt_num;
5254 u64 cnt;
5255} __packed;
5256
5257struct ql_vnd_stats {
5258 u64 entry_count;
5259 u64 rservd;
5260 struct ql_vnd_stat_entry entry[0];
5261} __packed;
5262
5263struct ql_vnd_host_stats_resp {
5264 u32 status;
5265 struct ql_vnd_stats stats;
5266} __packed;
5267
5268struct ql_vnd_tgt_stats_resp {
5269 u32 status;
5270 struct ql_vnd_stats stats;
5271} __packed;
5272
5273#include "qla_target.h"
5274#include "qla_gbl.h"
5275#include "qla_dbg.h"
5276#include "qla_inline.h"
5277#endif
5278