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11#include <linux/platform_device.h>
12#include <linux/pm_runtime.h>
13#include <linux/of.h>
14
15#include "ufshcd.h"
16#include "ufshcd-pltfrm.h"
17#include "unipro.h"
18
19#define UFSHCD_DEFAULT_LANES_PER_DIRECTION 2
20
21static int ufshcd_parse_clock_info(struct ufs_hba *hba)
22{
23 int ret = 0;
24 int cnt;
25 int i;
26 struct device *dev = hba->dev;
27 struct device_node *np = dev->of_node;
28 char *name;
29 u32 *clkfreq = NULL;
30 struct ufs_clk_info *clki;
31 int len = 0;
32 size_t sz = 0;
33
34 if (!np)
35 goto out;
36
37 cnt = of_property_count_strings(np, "clock-names");
38 if (!cnt || (cnt == -EINVAL)) {
39 dev_info(dev, "%s: Unable to find clocks, assuming enabled\n",
40 __func__);
41 } else if (cnt < 0) {
42 dev_err(dev, "%s: count clock strings failed, err %d\n",
43 __func__, cnt);
44 ret = cnt;
45 }
46
47 if (cnt <= 0)
48 goto out;
49
50 if (!of_get_property(np, "freq-table-hz", &len)) {
51 dev_info(dev, "freq-table-hz property not specified\n");
52 goto out;
53 }
54
55 if (len <= 0)
56 goto out;
57
58 sz = len / sizeof(*clkfreq);
59 if (sz != 2 * cnt) {
60 dev_err(dev, "%s len mismatch\n", "freq-table-hz");
61 ret = -EINVAL;
62 goto out;
63 }
64
65 clkfreq = devm_kcalloc(dev, sz, sizeof(*clkfreq),
66 GFP_KERNEL);
67 if (!clkfreq) {
68 ret = -ENOMEM;
69 goto out;
70 }
71
72 ret = of_property_read_u32_array(np, "freq-table-hz",
73 clkfreq, sz);
74 if (ret && (ret != -EINVAL)) {
75 dev_err(dev, "%s: error reading array %d\n",
76 "freq-table-hz", ret);
77 return ret;
78 }
79
80 for (i = 0; i < sz; i += 2) {
81 ret = of_property_read_string_index(np,
82 "clock-names", i/2, (const char **)&name);
83 if (ret)
84 goto out;
85
86 clki = devm_kzalloc(dev, sizeof(*clki), GFP_KERNEL);
87 if (!clki) {
88 ret = -ENOMEM;
89 goto out;
90 }
91
92 clki->min_freq = clkfreq[i];
93 clki->max_freq = clkfreq[i+1];
94 clki->name = kstrdup(name, GFP_KERNEL);
95 if (!strcmp(name, "ref_clk"))
96 clki->keep_link_active = true;
97 dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table-hz",
98 clki->min_freq, clki->max_freq, clki->name);
99 list_add_tail(&clki->list, &hba->clk_list_head);
100 }
101out:
102 return ret;
103}
104
105#define MAX_PROP_SIZE 32
106static int ufshcd_populate_vreg(struct device *dev, const char *name,
107 struct ufs_vreg **out_vreg)
108{
109 char prop_name[MAX_PROP_SIZE];
110 struct ufs_vreg *vreg = NULL;
111 struct device_node *np = dev->of_node;
112
113 if (!np) {
114 dev_err(dev, "%s: non DT initialization\n", __func__);
115 goto out;
116 }
117
118 snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", name);
119 if (!of_parse_phandle(np, prop_name, 0)) {
120 dev_info(dev, "%s: Unable to find %s regulator, assuming enabled\n",
121 __func__, prop_name);
122 goto out;
123 }
124
125 vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
126 if (!vreg)
127 return -ENOMEM;
128
129 vreg->name = kstrdup(name, GFP_KERNEL);
130
131 snprintf(prop_name, MAX_PROP_SIZE, "%s-max-microamp", name);
132 if (of_property_read_u32(np, prop_name, &vreg->max_uA)) {
133 dev_info(dev, "%s: unable to find %s\n", __func__, prop_name);
134 vreg->max_uA = 0;
135 }
136out:
137 *out_vreg = vreg;
138 return 0;
139}
140
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148
149
150static int ufshcd_parse_regulator_info(struct ufs_hba *hba)
151{
152 int err;
153 struct device *dev = hba->dev;
154 struct ufs_vreg_info *info = &hba->vreg_info;
155
156 err = ufshcd_populate_vreg(dev, "vdd-hba", &info->vdd_hba);
157 if (err)
158 goto out;
159
160 err = ufshcd_populate_vreg(dev, "vcc", &info->vcc);
161 if (err)
162 goto out;
163
164 err = ufshcd_populate_vreg(dev, "vccq", &info->vccq);
165 if (err)
166 goto out;
167
168 err = ufshcd_populate_vreg(dev, "vccq2", &info->vccq2);
169out:
170 return err;
171}
172
173#ifdef CONFIG_PM
174
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178
179
180
181int ufshcd_pltfrm_suspend(struct device *dev)
182{
183 return ufshcd_system_suspend(dev_get_drvdata(dev));
184}
185EXPORT_SYMBOL_GPL(ufshcd_pltfrm_suspend);
186
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191
192
193
194int ufshcd_pltfrm_resume(struct device *dev)
195{
196 return ufshcd_system_resume(dev_get_drvdata(dev));
197}
198EXPORT_SYMBOL_GPL(ufshcd_pltfrm_resume);
199
200int ufshcd_pltfrm_runtime_suspend(struct device *dev)
201{
202 return ufshcd_runtime_suspend(dev_get_drvdata(dev));
203}
204EXPORT_SYMBOL_GPL(ufshcd_pltfrm_runtime_suspend);
205
206int ufshcd_pltfrm_runtime_resume(struct device *dev)
207{
208 return ufshcd_runtime_resume(dev_get_drvdata(dev));
209}
210EXPORT_SYMBOL_GPL(ufshcd_pltfrm_runtime_resume);
211
212int ufshcd_pltfrm_runtime_idle(struct device *dev)
213{
214 return ufshcd_runtime_idle(dev_get_drvdata(dev));
215}
216EXPORT_SYMBOL_GPL(ufshcd_pltfrm_runtime_idle);
217
218#endif
219
220void ufshcd_pltfrm_shutdown(struct platform_device *pdev)
221{
222 ufshcd_shutdown((struct ufs_hba *)platform_get_drvdata(pdev));
223}
224EXPORT_SYMBOL_GPL(ufshcd_pltfrm_shutdown);
225
226static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba)
227{
228 struct device *dev = hba->dev;
229 int ret;
230
231 ret = of_property_read_u32(dev->of_node, "lanes-per-direction",
232 &hba->lanes_per_direction);
233 if (ret) {
234 dev_dbg(hba->dev,
235 "%s: failed to read lanes-per-direction, ret=%d\n",
236 __func__, ret);
237 hba->lanes_per_direction = UFSHCD_DEFAULT_LANES_PER_DIRECTION;
238 }
239}
240
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242
243
244
245
246
247
248
249
250int ufshcd_get_pwr_dev_param(struct ufs_dev_params *pltfrm_param,
251 struct ufs_pa_layer_attr *dev_max,
252 struct ufs_pa_layer_attr *agreed_pwr)
253{
254 int min_pltfrm_gear;
255 int min_dev_gear;
256 bool is_dev_sup_hs = false;
257 bool is_pltfrm_max_hs = false;
258
259 if (dev_max->pwr_rx == FAST_MODE)
260 is_dev_sup_hs = true;
261
262 if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {
263 is_pltfrm_max_hs = true;
264 min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,
265 pltfrm_param->hs_tx_gear);
266 } else {
267 min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,
268 pltfrm_param->pwm_tx_gear);
269 }
270
271
272
273
274
275
276 if (!is_dev_sup_hs && is_pltfrm_max_hs) {
277 pr_info("%s: device doesn't support HS\n",
278 __func__);
279 return -ENOTSUPP;
280 } else if (is_dev_sup_hs && is_pltfrm_max_hs) {
281
282
283
284
285
286
287 agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;
288 agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
289 } else {
290
291
292
293
294
295
296 agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;
297 agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
298 }
299
300
301
302
303
304
305 agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
306 pltfrm_param->tx_lanes);
307 agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
308 pltfrm_param->rx_lanes);
309
310
311 min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
312
313
314
315
316
317
318
319
320
321 if ((is_dev_sup_hs && is_pltfrm_max_hs) ||
322 (!is_dev_sup_hs && !is_pltfrm_max_hs)) {
323 agreed_pwr->gear_rx =
324 min_t(u32, min_dev_gear, min_pltfrm_gear);
325 } else if (!is_dev_sup_hs) {
326 agreed_pwr->gear_rx = min_dev_gear;
327 } else {
328 agreed_pwr->gear_rx = min_pltfrm_gear;
329 }
330 agreed_pwr->gear_tx = agreed_pwr->gear_rx;
331
332 agreed_pwr->hs_rate = pltfrm_param->hs_rate;
333
334 return 0;
335}
336EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
337
338void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
339{
340 dev_param->tx_lanes = 2;
341 dev_param->rx_lanes = 2;
342 dev_param->hs_rx_gear = UFS_HS_G3;
343 dev_param->hs_tx_gear = UFS_HS_G3;
344 dev_param->pwm_rx_gear = UFS_PWM_G4;
345 dev_param->pwm_tx_gear = UFS_PWM_G4;
346 dev_param->rx_pwr_pwm = SLOW_MODE;
347 dev_param->tx_pwr_pwm = SLOW_MODE;
348 dev_param->rx_pwr_hs = FAST_MODE;
349 dev_param->tx_pwr_hs = FAST_MODE;
350 dev_param->hs_rate = PA_HS_MODE_B;
351 dev_param->desired_working_mode = UFS_HS_MODE;
352}
353EXPORT_SYMBOL_GPL(ufshcd_init_pwr_dev_param);
354
355
356
357
358
359
360
361
362int ufshcd_pltfrm_init(struct platform_device *pdev,
363 const struct ufs_hba_variant_ops *vops)
364{
365 struct ufs_hba *hba;
366 void __iomem *mmio_base;
367 int irq, err;
368 struct device *dev = &pdev->dev;
369
370 mmio_base = devm_platform_ioremap_resource(pdev, 0);
371 if (IS_ERR(mmio_base)) {
372 err = PTR_ERR(mmio_base);
373 goto out;
374 }
375
376 irq = platform_get_irq(pdev, 0);
377 if (irq < 0) {
378 err = irq;
379 goto out;
380 }
381
382 err = ufshcd_alloc_host(dev, &hba);
383 if (err) {
384 dev_err(&pdev->dev, "Allocation failed\n");
385 goto out;
386 }
387
388 hba->vops = vops;
389
390 err = ufshcd_parse_clock_info(hba);
391 if (err) {
392 dev_err(&pdev->dev, "%s: clock parse failed %d\n",
393 __func__, err);
394 goto dealloc_host;
395 }
396 err = ufshcd_parse_regulator_info(hba);
397 if (err) {
398 dev_err(&pdev->dev, "%s: regulator init failed %d\n",
399 __func__, err);
400 goto dealloc_host;
401 }
402
403 ufshcd_init_lanes_per_dir(hba);
404
405 err = ufshcd_init(hba, mmio_base, irq);
406 if (err) {
407 dev_err(dev, "Initialization failed\n");
408 goto dealloc_host;
409 }
410
411 platform_set_drvdata(pdev, hba);
412
413 pm_runtime_set_active(&pdev->dev);
414 pm_runtime_enable(&pdev->dev);
415
416 return 0;
417
418dealloc_host:
419 ufshcd_dealloc_host(hba);
420out:
421 return err;
422}
423EXPORT_SYMBOL_GPL(ufshcd_pltfrm_init);
424
425MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
426MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
427MODULE_DESCRIPTION("UFS host controller Platform bus based glue driver");
428MODULE_LICENSE("GPL");
429MODULE_VERSION(UFSHCD_DRIVER_VERSION);
430