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8#include <linux/clk.h>
9#include <linux/interrupt.h>
10#include <linux/workqueue.h>
11#include <linux/device.h>
12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/sysfs.h>
15#include <linux/list.h>
16#include <linux/spi/spi.h>
17#include <linux/regulator/consumer.h>
18#include <linux/err.h>
19#include <linux/module.h>
20#include <asm/div64.h>
21
22#include <linux/iio/iio.h>
23#include <linux/iio/sysfs.h>
24#include "dds.h"
25
26#include "ad9834.h"
27
28
29
30#define AD9834_REG_CMD 0
31#define AD9834_REG_FREQ0 BIT(14)
32#define AD9834_REG_FREQ1 BIT(15)
33#define AD9834_REG_PHASE0 (BIT(15) | BIT(14))
34#define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13))
35
36
37
38#define AD9834_B28 BIT(13)
39#define AD9834_HLB BIT(12)
40#define AD9834_FSEL BIT(11)
41#define AD9834_PSEL BIT(10)
42#define AD9834_PIN_SW BIT(9)
43#define AD9834_RESET BIT(8)
44#define AD9834_SLEEP1 BIT(7)
45#define AD9834_SLEEP12 BIT(6)
46#define AD9834_OPBITEN BIT(5)
47#define AD9834_SIGN_PIB BIT(4)
48#define AD9834_DIV2 BIT(3)
49#define AD9834_MODE BIT(1)
50
51#define AD9834_FREQ_BITS 28
52#define AD9834_PHASE_BITS 12
53
54#define RES_MASK(bits) (BIT(bits) - 1)
55
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70
71struct ad9834_state {
72 struct spi_device *spi;
73 struct clk *mclk;
74 unsigned short control;
75 unsigned short devid;
76 struct spi_transfer xfer;
77 struct spi_message msg;
78 struct spi_transfer freq_xfer[2];
79 struct spi_message freq_msg;
80 struct mutex lock;
81
82
83
84
85
86 __be16 data ____cacheline_aligned;
87 __be16 freq_data[2];
88};
89
90
91
92
93
94enum ad9834_supported_device_ids {
95 ID_AD9833,
96 ID_AD9834,
97 ID_AD9837,
98 ID_AD9838,
99};
100
101static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout)
102{
103 unsigned long long freqreg = (u64)fout * (u64)BIT(AD9834_FREQ_BITS);
104
105 do_div(freqreg, mclk);
106 return freqreg;
107}
108
109static int ad9834_write_frequency(struct ad9834_state *st,
110 unsigned long addr, unsigned long fout)
111{
112 unsigned long clk_freq;
113 unsigned long regval;
114
115 clk_freq = clk_get_rate(st->mclk);
116
117 if (fout > (clk_freq / 2))
118 return -EINVAL;
119
120 regval = ad9834_calc_freqreg(clk_freq, fout);
121
122 st->freq_data[0] = cpu_to_be16(addr | (regval &
123 RES_MASK(AD9834_FREQ_BITS / 2)));
124 st->freq_data[1] = cpu_to_be16(addr | ((regval >>
125 (AD9834_FREQ_BITS / 2)) &
126 RES_MASK(AD9834_FREQ_BITS / 2)));
127
128 return spi_sync(st->spi, &st->freq_msg);
129}
130
131static int ad9834_write_phase(struct ad9834_state *st,
132 unsigned long addr, unsigned long phase)
133{
134 if (phase > BIT(AD9834_PHASE_BITS))
135 return -EINVAL;
136 st->data = cpu_to_be16(addr | phase);
137
138 return spi_sync(st->spi, &st->msg);
139}
140
141static ssize_t ad9834_write(struct device *dev,
142 struct device_attribute *attr,
143 const char *buf,
144 size_t len)
145{
146 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
147 struct ad9834_state *st = iio_priv(indio_dev);
148 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
149 int ret;
150 unsigned long val;
151
152 ret = kstrtoul(buf, 10, &val);
153 if (ret)
154 return ret;
155
156 mutex_lock(&st->lock);
157 switch ((u32)this_attr->address) {
158 case AD9834_REG_FREQ0:
159 case AD9834_REG_FREQ1:
160 ret = ad9834_write_frequency(st, this_attr->address, val);
161 break;
162 case AD9834_REG_PHASE0:
163 case AD9834_REG_PHASE1:
164 ret = ad9834_write_phase(st, this_attr->address, val);
165 break;
166 case AD9834_OPBITEN:
167 if (st->control & AD9834_MODE) {
168 ret = -EINVAL;
169 break;
170 }
171
172 if (val)
173 st->control |= AD9834_OPBITEN;
174 else
175 st->control &= ~AD9834_OPBITEN;
176
177 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
178 ret = spi_sync(st->spi, &st->msg);
179 break;
180 case AD9834_PIN_SW:
181 if (val)
182 st->control |= AD9834_PIN_SW;
183 else
184 st->control &= ~AD9834_PIN_SW;
185 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
186 ret = spi_sync(st->spi, &st->msg);
187 break;
188 case AD9834_FSEL:
189 case AD9834_PSEL:
190 if (!val) {
191 st->control &= ~(this_attr->address | AD9834_PIN_SW);
192 } else if (val == 1) {
193 st->control |= this_attr->address;
194 st->control &= ~AD9834_PIN_SW;
195 } else {
196 ret = -EINVAL;
197 break;
198 }
199 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
200 ret = spi_sync(st->spi, &st->msg);
201 break;
202 case AD9834_RESET:
203 if (val)
204 st->control &= ~AD9834_RESET;
205 else
206 st->control |= AD9834_RESET;
207
208 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
209 ret = spi_sync(st->spi, &st->msg);
210 break;
211 default:
212 ret = -ENODEV;
213 }
214 mutex_unlock(&st->lock);
215
216 return ret ? ret : len;
217}
218
219static ssize_t ad9834_store_wavetype(struct device *dev,
220 struct device_attribute *attr,
221 const char *buf,
222 size_t len)
223{
224 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
225 struct ad9834_state *st = iio_priv(indio_dev);
226 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
227 int ret = 0;
228 bool is_ad9833_7 = (st->devid == ID_AD9833) || (st->devid == ID_AD9837);
229
230 mutex_lock(&st->lock);
231
232 switch ((u32)this_attr->address) {
233 case 0:
234 if (sysfs_streq(buf, "sine")) {
235 st->control &= ~AD9834_MODE;
236 if (is_ad9833_7)
237 st->control &= ~AD9834_OPBITEN;
238 } else if (sysfs_streq(buf, "triangle")) {
239 if (is_ad9833_7) {
240 st->control &= ~AD9834_OPBITEN;
241 st->control |= AD9834_MODE;
242 } else if (st->control & AD9834_OPBITEN) {
243 ret = -EINVAL;
244 } else {
245 st->control |= AD9834_MODE;
246 }
247 } else if (is_ad9833_7 && sysfs_streq(buf, "square")) {
248 st->control &= ~AD9834_MODE;
249 st->control |= AD9834_OPBITEN;
250 } else {
251 ret = -EINVAL;
252 }
253
254 break;
255 case 1:
256 if (sysfs_streq(buf, "square") &&
257 !(st->control & AD9834_MODE)) {
258 st->control &= ~AD9834_MODE;
259 st->control |= AD9834_OPBITEN;
260 } else {
261 ret = -EINVAL;
262 }
263 break;
264 default:
265 ret = -EINVAL;
266 break;
267 }
268
269 if (!ret) {
270 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
271 ret = spi_sync(st->spi, &st->msg);
272 }
273 mutex_unlock(&st->lock);
274
275 return ret ? ret : len;
276}
277
278static
279ssize_t ad9834_show_out0_wavetype_available(struct device *dev,
280 struct device_attribute *attr,
281 char *buf)
282{
283 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
284 struct ad9834_state *st = iio_priv(indio_dev);
285 char *str;
286
287 if (st->devid == ID_AD9833 || st->devid == ID_AD9837)
288 str = "sine triangle square";
289 else if (st->control & AD9834_OPBITEN)
290 str = "sine";
291 else
292 str = "sine triangle";
293
294 return sprintf(buf, "%s\n", str);
295}
296
297static IIO_DEVICE_ATTR(out_altvoltage0_out0_wavetype_available, 0444,
298 ad9834_show_out0_wavetype_available, NULL, 0);
299
300static
301ssize_t ad9834_show_out1_wavetype_available(struct device *dev,
302 struct device_attribute *attr,
303 char *buf)
304{
305 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
306 struct ad9834_state *st = iio_priv(indio_dev);
307 char *str;
308
309 if (st->control & AD9834_MODE)
310 str = "";
311 else
312 str = "square";
313
314 return sprintf(buf, "%s\n", str);
315}
316
317static IIO_DEVICE_ATTR(out_altvoltage0_out1_wavetype_available, 0444,
318 ad9834_show_out1_wavetype_available, NULL, 0);
319
320
321
322
323
324static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9834_write, AD9834_REG_FREQ0);
325static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9834_write, AD9834_REG_FREQ1);
326static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9834_write, AD9834_FSEL);
327static IIO_CONST_ATTR_FREQ_SCALE(0, "1");
328
329static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9834_write, AD9834_REG_PHASE0);
330static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9834_write, AD9834_REG_PHASE1);
331static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL, ad9834_write, AD9834_PSEL);
332static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808");
333
334static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
335 ad9834_write, AD9834_PIN_SW);
336static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL, ad9834_write, AD9834_RESET);
337static IIO_DEV_ATTR_OUTY_ENABLE(0, 1, 0200, NULL,
338 ad9834_write, AD9834_OPBITEN);
339static IIO_DEV_ATTR_OUT_WAVETYPE(0, 0, ad9834_store_wavetype, 0);
340static IIO_DEV_ATTR_OUT_WAVETYPE(0, 1, ad9834_store_wavetype, 1);
341
342static struct attribute *ad9834_attributes[] = {
343 &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
344 &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
345 &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
346 &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
347 &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
348 &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
349 &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
350 &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
351 &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
352 &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
353 &iio_dev_attr_out_altvoltage0_out1_enable.dev_attr.attr,
354 &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
355 &iio_dev_attr_out_altvoltage0_out1_wavetype.dev_attr.attr,
356 &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
357 &iio_dev_attr_out_altvoltage0_out1_wavetype_available.dev_attr.attr,
358 NULL,
359};
360
361static struct attribute *ad9833_attributes[] = {
362 &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
363 &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
364 &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
365 &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
366 &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
367 &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
368 &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
369 &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
370 &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
371 &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
372 &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
373 NULL,
374};
375
376static const struct attribute_group ad9834_attribute_group = {
377 .attrs = ad9834_attributes,
378};
379
380static const struct attribute_group ad9833_attribute_group = {
381 .attrs = ad9833_attributes,
382};
383
384static const struct iio_info ad9834_info = {
385 .attrs = &ad9834_attribute_group,
386};
387
388static const struct iio_info ad9833_info = {
389 .attrs = &ad9833_attribute_group,
390};
391
392static void ad9834_disable_reg(void *data)
393{
394 struct regulator *reg = data;
395
396 regulator_disable(reg);
397}
398
399static void ad9834_disable_clk(void *data)
400{
401 struct clk *clk = data;
402
403 clk_disable_unprepare(clk);
404}
405
406static int ad9834_probe(struct spi_device *spi)
407{
408 struct ad9834_state *st;
409 struct iio_dev *indio_dev;
410 struct regulator *reg;
411 int ret;
412
413 reg = devm_regulator_get(&spi->dev, "avdd");
414 if (IS_ERR(reg))
415 return PTR_ERR(reg);
416
417 ret = regulator_enable(reg);
418 if (ret) {
419 dev_err(&spi->dev, "Failed to enable specified AVDD supply\n");
420 return ret;
421 }
422
423 ret = devm_add_action_or_reset(&spi->dev, ad9834_disable_reg, reg);
424 if (ret)
425 return ret;
426
427 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
428 if (!indio_dev) {
429 ret = -ENOMEM;
430 return ret;
431 }
432 st = iio_priv(indio_dev);
433 mutex_init(&st->lock);
434 st->mclk = devm_clk_get(&spi->dev, NULL);
435 if (IS_ERR(st->mclk)) {
436 ret = PTR_ERR(st->mclk);
437 return ret;
438 }
439
440 ret = clk_prepare_enable(st->mclk);
441 if (ret) {
442 dev_err(&spi->dev, "Failed to enable master clock\n");
443 return ret;
444 }
445
446 ret = devm_add_action_or_reset(&spi->dev, ad9834_disable_clk, st->mclk);
447 if (ret)
448 return ret;
449
450 st->spi = spi;
451 st->devid = spi_get_device_id(spi)->driver_data;
452 indio_dev->name = spi_get_device_id(spi)->name;
453 switch (st->devid) {
454 case ID_AD9833:
455 case ID_AD9837:
456 indio_dev->info = &ad9833_info;
457 break;
458 default:
459 indio_dev->info = &ad9834_info;
460 break;
461 }
462 indio_dev->modes = INDIO_DIRECT_MODE;
463
464
465
466 st->xfer.tx_buf = &st->data;
467 st->xfer.len = 2;
468
469 spi_message_init(&st->msg);
470 spi_message_add_tail(&st->xfer, &st->msg);
471
472 st->freq_xfer[0].tx_buf = &st->freq_data[0];
473 st->freq_xfer[0].len = 2;
474 st->freq_xfer[0].cs_change = 1;
475 st->freq_xfer[1].tx_buf = &st->freq_data[1];
476 st->freq_xfer[1].len = 2;
477
478 spi_message_init(&st->freq_msg);
479 spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
480 spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
481
482 st->control = AD9834_B28 | AD9834_RESET;
483 st->control |= AD9834_DIV2;
484
485 if (st->devid == ID_AD9834)
486 st->control |= AD9834_SIGN_PIB;
487
488 st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
489 ret = spi_sync(st->spi, &st->msg);
490 if (ret) {
491 dev_err(&spi->dev, "device init failed\n");
492 return ret;
493 }
494
495 ret = ad9834_write_frequency(st, AD9834_REG_FREQ0, 1000000);
496 if (ret)
497 return ret;
498
499 ret = ad9834_write_frequency(st, AD9834_REG_FREQ1, 5000000);
500 if (ret)
501 return ret;
502
503 ret = ad9834_write_phase(st, AD9834_REG_PHASE0, 512);
504 if (ret)
505 return ret;
506
507 ret = ad9834_write_phase(st, AD9834_REG_PHASE1, 1024);
508 if (ret)
509 return ret;
510
511 return devm_iio_device_register(&spi->dev, indio_dev);
512}
513
514static const struct spi_device_id ad9834_id[] = {
515 {"ad9833", ID_AD9833},
516 {"ad9834", ID_AD9834},
517 {"ad9837", ID_AD9837},
518 {"ad9838", ID_AD9838},
519 {}
520};
521MODULE_DEVICE_TABLE(spi, ad9834_id);
522
523static const struct of_device_id ad9834_of_match[] = {
524 {.compatible = "adi,ad9833"},
525 {.compatible = "adi,ad9834"},
526 {.compatible = "adi,ad9837"},
527 {.compatible = "adi,ad9838"},
528 {}
529};
530
531MODULE_DEVICE_TABLE(of, ad9834_of_match);
532
533static struct spi_driver ad9834_driver = {
534 .driver = {
535 .name = "ad9834",
536 .of_match_table = ad9834_of_match
537 },
538 .probe = ad9834_probe,
539 .id_table = ad9834_id,
540};
541module_spi_driver(ad9834_driver);
542
543MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
544MODULE_DESCRIPTION("Analog Devices AD9833/AD9834/AD9837/AD9838 DDS");
545MODULE_LICENSE("GPL v2");
546
