LXR linux/drivers/staging/media/atomisp/pci/hive_isp_css

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Support for Intel Camera Imaging ISP subsystem.
   4 * Copyright (c) 2010-2015, Intel Corporation.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 */
  15
  16#include "sp.h"
  17
  18#ifndef __INLINE_SP__
  19#include "sp_private.h"
  20#endif /* __INLINE_SP__ */
  21
  22#include "assert_support.h"
  23
  24void cnd_sp_irq_enable(
  25    const sp_ID_t               ID,
  26    const bool          cnd)
  27{
  28        if (cnd) {
  29                sp_ctrl_setbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT);
  30                /* Enabling the IRQ immediately triggers an interrupt, clear it */
  31                sp_ctrl_setbit(ID, SP_IRQ_CLEAR_REG, SP_IRQ_CLEAR_BIT);
  32        } else {
  33                sp_ctrl_clearbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT);
  34        }
  35}
  36
  37void sp_get_state(
  38    const sp_ID_t                       ID,
  39    sp_state_t                          *state,
  40    sp_stall_t                          *stall)
  41{
  42        hrt_data sc = sp_ctrl_load(ID, SP_SC_REG);
  43
  44        assert(state);
  45        assert(stall);
  46
  47        state->pc = sp_ctrl_load(ID, SP_PC_REG);
  48        state->status_register = sc;
  49        state->is_broken   = (sc & (1U << SP_BROKEN_BIT)) != 0;
  50        state->is_idle     = (sc & (1U << SP_IDLE_BIT)) != 0;
  51        state->is_sleeping = (sc & (1U << SP_SLEEPING_BIT)) != 0;
  52        state->is_stalling = (sc & (1U << SP_STALLING_BIT)) != 0;
  53        stall->fifo0 =
  54            !sp_ctrl_getbit(ID, SP_FIFO0_SINK_REG, SP_FIFO0_SINK_BIT);
  55        stall->fifo1 =
  56            !sp_ctrl_getbit(ID, SP_FIFO1_SINK_REG, SP_FIFO1_SINK_BIT);
  57        stall->fifo2 =
  58            !sp_ctrl_getbit(ID, SP_FIFO2_SINK_REG, SP_FIFO2_SINK_BIT);
  59        stall->fifo3 =
  60            !sp_ctrl_getbit(ID, SP_FIFO3_SINK_REG, SP_FIFO3_SINK_BIT);
  61        stall->fifo4 =
  62            !sp_ctrl_getbit(ID, SP_FIFO4_SINK_REG, SP_FIFO4_SINK_BIT);
  63        stall->fifo5 =
  64            !sp_ctrl_getbit(ID, SP_FIFO5_SINK_REG, SP_FIFO5_SINK_BIT);
  65        stall->fifo6 =
  66            !sp_ctrl_getbit(ID, SP_FIFO6_SINK_REG, SP_FIFO6_SINK_BIT);
  67        stall->fifo7 =
  68            !sp_ctrl_getbit(ID, SP_FIFO7_SINK_REG, SP_FIFO7_SINK_BIT);
  69        stall->fifo8 =
  70            !sp_ctrl_getbit(ID, SP_FIFO8_SINK_REG, SP_FIFO8_SINK_BIT);
  71        stall->fifo9 =
  72            !sp_ctrl_getbit(ID, SP_FIFO9_SINK_REG, SP_FIFO9_SINK_BIT);
  73        stall->fifoa =
  74            !sp_ctrl_getbit(ID, SP_FIFOA_SINK_REG, SP_FIFOA_SINK_BIT);
  75        stall->dmem =
  76            !sp_ctrl_getbit(ID, SP_DMEM_SINK_REG, SP_DMEM_SINK_BIT);
  77        stall->control_master =
  78            !sp_ctrl_getbit(ID, SP_CTRL_MT_SINK_REG, SP_CTRL_MT_SINK_BIT);
  79        stall->icache_master =
  80            !sp_ctrl_getbit(ID, SP_ICACHE_MT_SINK_REG,
  81                            SP_ICACHE_MT_SINK_BIT);
  82}
  83