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9#include <linux/clk.h>
10
11#include "hantro.h"
12#include "hantro_jpeg.h"
13#include "hantro_g1_regs.h"
14#include "hantro_h1_regs.h"
15#include "rockchip_vpu2_regs.h"
16
17#define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
18#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
19
20
21
22
23
24static const struct hantro_fmt rockchip_vpu_enc_fmts[] = {
25 {
26 .fourcc = V4L2_PIX_FMT_YUV420M,
27 .codec_mode = HANTRO_MODE_NONE,
28 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P,
29 },
30 {
31 .fourcc = V4L2_PIX_FMT_NV12M,
32 .codec_mode = HANTRO_MODE_NONE,
33 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP,
34 },
35 {
36 .fourcc = V4L2_PIX_FMT_YUYV,
37 .codec_mode = HANTRO_MODE_NONE,
38 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422,
39 },
40 {
41 .fourcc = V4L2_PIX_FMT_UYVY,
42 .codec_mode = HANTRO_MODE_NONE,
43 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422,
44 },
45 {
46 .fourcc = V4L2_PIX_FMT_JPEG,
47 .codec_mode = HANTRO_MODE_JPEG_ENC,
48 .max_depth = 2,
49 .header_size = JPEG_HEADER_SIZE,
50 .frmsize = {
51 .min_width = 96,
52 .max_width = 8192,
53 .step_width = MB_DIM,
54 .min_height = 32,
55 .max_height = 8192,
56 .step_height = MB_DIM,
57 },
58 },
59};
60
61static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = {
62 {
63 .fourcc = V4L2_PIX_FMT_YUYV,
64 .codec_mode = HANTRO_MODE_NONE,
65 },
66};
67
68static const struct hantro_fmt rk3066_vpu_dec_fmts[] = {
69 {
70 .fourcc = V4L2_PIX_FMT_NV12,
71 .codec_mode = HANTRO_MODE_NONE,
72 },
73 {
74 .fourcc = V4L2_PIX_FMT_H264_SLICE,
75 .codec_mode = HANTRO_MODE_H264_DEC,
76 .max_depth = 2,
77 .frmsize = {
78 .min_width = 48,
79 .max_width = 1920,
80 .step_width = MB_DIM,
81 .min_height = 48,
82 .max_height = 1088,
83 .step_height = MB_DIM,
84 },
85 },
86 {
87 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
88 .codec_mode = HANTRO_MODE_MPEG2_DEC,
89 .max_depth = 2,
90 .frmsize = {
91 .min_width = 48,
92 .max_width = 1920,
93 .step_width = MB_DIM,
94 .min_height = 48,
95 .max_height = 1088,
96 .step_height = MB_DIM,
97 },
98 },
99 {
100 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
101 .codec_mode = HANTRO_MODE_VP8_DEC,
102 .max_depth = 2,
103 .frmsize = {
104 .min_width = 48,
105 .max_width = 1920,
106 .step_width = MB_DIM,
107 .min_height = 48,
108 .max_height = 1088,
109 .step_height = MB_DIM,
110 },
111 },
112};
113
114static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
115 {
116 .fourcc = V4L2_PIX_FMT_NV12,
117 .codec_mode = HANTRO_MODE_NONE,
118 },
119 {
120 .fourcc = V4L2_PIX_FMT_H264_SLICE,
121 .codec_mode = HANTRO_MODE_H264_DEC,
122 .max_depth = 2,
123 .frmsize = {
124 .min_width = 48,
125 .max_width = 4096,
126 .step_width = MB_DIM,
127 .min_height = 48,
128 .max_height = 2304,
129 .step_height = MB_DIM,
130 },
131 },
132 {
133 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
134 .codec_mode = HANTRO_MODE_MPEG2_DEC,
135 .max_depth = 2,
136 .frmsize = {
137 .min_width = 48,
138 .max_width = 1920,
139 .step_width = MB_DIM,
140 .min_height = 48,
141 .max_height = 1088,
142 .step_height = MB_DIM,
143 },
144 },
145 {
146 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
147 .codec_mode = HANTRO_MODE_VP8_DEC,
148 .max_depth = 2,
149 .frmsize = {
150 .min_width = 48,
151 .max_width = 3840,
152 .step_width = MB_DIM,
153 .min_height = 48,
154 .max_height = 2160,
155 .step_height = MB_DIM,
156 },
157 },
158};
159
160static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
161 {
162 .fourcc = V4L2_PIX_FMT_NV12,
163 .codec_mode = HANTRO_MODE_NONE,
164 },
165 {
166 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
167 .codec_mode = HANTRO_MODE_MPEG2_DEC,
168 .max_depth = 2,
169 .frmsize = {
170 .min_width = 48,
171 .max_width = 1920,
172 .step_width = MB_DIM,
173 .min_height = 48,
174 .max_height = 1088,
175 .step_height = MB_DIM,
176 },
177 },
178 {
179 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
180 .codec_mode = HANTRO_MODE_VP8_DEC,
181 .max_depth = 2,
182 .frmsize = {
183 .min_width = 48,
184 .max_width = 3840,
185 .step_width = MB_DIM,
186 .min_height = 48,
187 .max_height = 2160,
188 .step_height = MB_DIM,
189 },
190 },
191};
192
193static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
194{
195 struct hantro_dev *vpu = dev_id;
196 enum vb2_buffer_state state;
197 u32 status;
198
199 status = vepu_read(vpu, H1_REG_INTERRUPT);
200 state = (status & H1_REG_INTERRUPT_FRAME_RDY) ?
201 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
202
203 vepu_write(vpu, 0, H1_REG_INTERRUPT);
204 vepu_write(vpu, 0, H1_REG_AXI_CTRL);
205
206 hantro_irq_done(vpu, state);
207
208 return IRQ_HANDLED;
209}
210
211static irqreturn_t rockchip_vpu2_vdpu_irq(int irq, void *dev_id)
212{
213 struct hantro_dev *vpu = dev_id;
214 enum vb2_buffer_state state;
215 u32 status;
216
217 status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
218 state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?
219 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
220
221 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
222 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
223
224 hantro_irq_done(vpu, state);
225
226 return IRQ_HANDLED;
227}
228
229static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id)
230{
231 struct hantro_dev *vpu = dev_id;
232 enum vb2_buffer_state state;
233 u32 status;
234
235 status = vepu_read(vpu, VEPU_REG_INTERRUPT);
236 state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
237 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
238
239 vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
240 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
241
242 hantro_irq_done(vpu, state);
243
244 return IRQ_HANDLED;
245}
246
247static int rk3036_vpu_hw_init(struct hantro_dev *vpu)
248{
249
250 clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
251 return 0;
252}
253
254static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
255{
256
257 clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
258 clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);
259 return 0;
260}
261
262static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
263{
264
265 clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
266 return 0;
267}
268
269static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
270{
271 struct hantro_dev *vpu = ctx->dev;
272
273 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
274 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
275}
276
277static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx)
278{
279 struct hantro_dev *vpu = ctx->dev;
280
281 vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);
282 vepu_write(vpu, 0, H1_REG_ENC_CTRL);
283 vepu_write(vpu, 0, H1_REG_AXI_CTRL);
284}
285
286static void rockchip_vpu2_dec_reset(struct hantro_ctx *ctx)
287{
288 struct hantro_dev *vpu = ctx->dev;
289
290 vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
291 vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
292 vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
293}
294
295static void rockchip_vpu2_enc_reset(struct hantro_ctx *ctx)
296{
297 struct hantro_dev *vpu = ctx->dev;
298
299 vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
300 vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
301 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
302}
303
304
305
306
307static const struct hantro_codec_ops rk3036_vpu_codec_ops[] = {
308 [HANTRO_MODE_H264_DEC] = {
309 .run = hantro_g1_h264_dec_run,
310 .reset = hantro_g1_reset,
311 .init = hantro_h264_dec_init,
312 .exit = hantro_h264_dec_exit,
313 },
314 [HANTRO_MODE_MPEG2_DEC] = {
315 .run = hantro_g1_mpeg2_dec_run,
316 .reset = hantro_g1_reset,
317 .init = hantro_mpeg2_dec_init,
318 .exit = hantro_mpeg2_dec_exit,
319 },
320 [HANTRO_MODE_VP8_DEC] = {
321 .run = hantro_g1_vp8_dec_run,
322 .reset = hantro_g1_reset,
323 .init = hantro_vp8_dec_init,
324 .exit = hantro_vp8_dec_exit,
325 },
326};
327
328static const struct hantro_codec_ops rk3066_vpu_codec_ops[] = {
329 [HANTRO_MODE_JPEG_ENC] = {
330 .run = hantro_h1_jpeg_enc_run,
331 .reset = rockchip_vpu1_enc_reset,
332 .init = hantro_jpeg_enc_init,
333 .done = hantro_jpeg_enc_done,
334 .exit = hantro_jpeg_enc_exit,
335 },
336 [HANTRO_MODE_H264_DEC] = {
337 .run = hantro_g1_h264_dec_run,
338 .reset = rk3066_vpu_dec_reset,
339 .init = hantro_h264_dec_init,
340 .exit = hantro_h264_dec_exit,
341 },
342 [HANTRO_MODE_MPEG2_DEC] = {
343 .run = hantro_g1_mpeg2_dec_run,
344 .reset = rk3066_vpu_dec_reset,
345 .init = hantro_mpeg2_dec_init,
346 .exit = hantro_mpeg2_dec_exit,
347 },
348 [HANTRO_MODE_VP8_DEC] = {
349 .run = hantro_g1_vp8_dec_run,
350 .reset = rk3066_vpu_dec_reset,
351 .init = hantro_vp8_dec_init,
352 .exit = hantro_vp8_dec_exit,
353 },
354};
355
356static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
357 [HANTRO_MODE_JPEG_ENC] = {
358 .run = hantro_h1_jpeg_enc_run,
359 .reset = rockchip_vpu1_enc_reset,
360 .init = hantro_jpeg_enc_init,
361 .done = hantro_jpeg_enc_done,
362 .exit = hantro_jpeg_enc_exit,
363 },
364 [HANTRO_MODE_H264_DEC] = {
365 .run = hantro_g1_h264_dec_run,
366 .reset = hantro_g1_reset,
367 .init = hantro_h264_dec_init,
368 .exit = hantro_h264_dec_exit,
369 },
370 [HANTRO_MODE_MPEG2_DEC] = {
371 .run = hantro_g1_mpeg2_dec_run,
372 .reset = hantro_g1_reset,
373 .init = hantro_mpeg2_dec_init,
374 .exit = hantro_mpeg2_dec_exit,
375 },
376 [HANTRO_MODE_VP8_DEC] = {
377 .run = hantro_g1_vp8_dec_run,
378 .reset = hantro_g1_reset,
379 .init = hantro_vp8_dec_init,
380 .exit = hantro_vp8_dec_exit,
381 },
382};
383
384static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
385 [HANTRO_MODE_JPEG_ENC] = {
386 .run = rockchip_vpu2_jpeg_enc_run,
387 .reset = rockchip_vpu2_enc_reset,
388 .init = hantro_jpeg_enc_init,
389 .exit = hantro_jpeg_enc_exit,
390 },
391 [HANTRO_MODE_MPEG2_DEC] = {
392 .run = rockchip_vpu2_mpeg2_dec_run,
393 .reset = rockchip_vpu2_dec_reset,
394 .init = hantro_mpeg2_dec_init,
395 .exit = hantro_mpeg2_dec_exit,
396 },
397 [HANTRO_MODE_VP8_DEC] = {
398 .run = rockchip_vpu2_vp8_dec_run,
399 .reset = rockchip_vpu2_dec_reset,
400 .init = hantro_vp8_dec_init,
401 .exit = hantro_vp8_dec_exit,
402 },
403};
404
405
406
407
408
409static const struct hantro_irq rockchip_vdpu1_irqs[] = {
410 { "vdpu", hantro_g1_irq },
411};
412
413static const struct hantro_irq rockchip_vpu1_irqs[] = {
414 { "vepu", rockchip_vpu1_vepu_irq },
415 { "vdpu", hantro_g1_irq },
416};
417
418static const struct hantro_irq rockchip_vdpu2_irqs[] = {
419 { "vdpu", rockchip_vpu2_vdpu_irq },
420};
421
422static const struct hantro_irq rockchip_vpu2_irqs[] = {
423 { "vepu", rockchip_vpu2_vepu_irq },
424 { "vdpu", rockchip_vpu2_vdpu_irq },
425};
426
427static const char * const rk3066_vpu_clk_names[] = {
428 "aclk_vdpu", "hclk_vdpu",
429 "aclk_vepu", "hclk_vepu"
430};
431
432static const char * const rockchip_vpu_clk_names[] = {
433 "aclk", "hclk"
434};
435
436const struct hantro_variant rk3036_vpu_variant = {
437 .dec_offset = 0x400,
438 .dec_fmts = rk3066_vpu_dec_fmts,
439 .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
440 .postproc_fmts = rockchip_vpu1_postproc_fmts,
441 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
442 .postproc_regs = &hantro_g1_postproc_regs,
443 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
444 HANTRO_H264_DECODER,
445 .codec_ops = rk3036_vpu_codec_ops,
446 .irqs = rockchip_vdpu1_irqs,
447 .num_irqs = ARRAY_SIZE(rockchip_vdpu1_irqs),
448 .init = rk3036_vpu_hw_init,
449 .clk_names = rockchip_vpu_clk_names,
450 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
451};
452
453
454
455
456
457
458const struct hantro_variant rk3066_vpu_variant = {
459 .enc_offset = 0x0,
460 .enc_fmts = rockchip_vpu_enc_fmts,
461 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
462 .dec_offset = 0x400,
463 .dec_fmts = rk3066_vpu_dec_fmts,
464 .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
465 .postproc_fmts = rockchip_vpu1_postproc_fmts,
466 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
467 .postproc_regs = &hantro_g1_postproc_regs,
468 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
469 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
470 .codec_ops = rk3066_vpu_codec_ops,
471 .irqs = rockchip_vpu1_irqs,
472 .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
473 .init = rk3066_vpu_hw_init,
474 .clk_names = rk3066_vpu_clk_names,
475 .num_clocks = ARRAY_SIZE(rk3066_vpu_clk_names)
476};
477
478const struct hantro_variant rk3288_vpu_variant = {
479 .enc_offset = 0x0,
480 .enc_fmts = rockchip_vpu_enc_fmts,
481 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
482 .dec_offset = 0x400,
483 .dec_fmts = rk3288_vpu_dec_fmts,
484 .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
485 .postproc_fmts = rockchip_vpu1_postproc_fmts,
486 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
487 .postproc_regs = &hantro_g1_postproc_regs,
488 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
489 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
490 .codec_ops = rk3288_vpu_codec_ops,
491 .irqs = rockchip_vpu1_irqs,
492 .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
493 .init = rockchip_vpu_hw_init,
494 .clk_names = rockchip_vpu_clk_names,
495 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
496};
497
498const struct hantro_variant rk3328_vpu_variant = {
499 .dec_offset = 0x400,
500 .dec_fmts = rk3399_vpu_dec_fmts,
501 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
502 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER,
503 .codec_ops = rk3399_vpu_codec_ops,
504 .irqs = rockchip_vdpu2_irqs,
505 .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
506 .init = rockchip_vpu_hw_init,
507 .clk_names = rockchip_vpu_clk_names,
508 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
509};
510
511const struct hantro_variant rk3399_vpu_variant = {
512 .enc_offset = 0x0,
513 .enc_fmts = rockchip_vpu_enc_fmts,
514 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
515 .dec_offset = 0x400,
516 .dec_fmts = rk3399_vpu_dec_fmts,
517 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
518 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
519 HANTRO_VP8_DECODER,
520 .codec_ops = rk3399_vpu_codec_ops,
521 .irqs = rockchip_vpu2_irqs,
522 .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
523 .init = rockchip_vpu_hw_init,
524 .clk_names = rockchip_vpu_clk_names,
525 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
526};
527