LXR linux/drivers/staging/rtl8188eu/include/rtl8188e

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/******************************************************************************
   3 *
   4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5 *
   6 ******************************************************************************/
   7#ifndef __RTL8188E_HAL_H__
   8#define __RTL8188E_HAL_H__
   9
  10/* include HAL Related header after HAL Related compiling flags */
  11#include "rtl8188e_spec.h"
  12#include "hal8188e_phy_reg.h"
  13#include "hal8188e_phy_cfg.h"
  14#include "rtl8188e_dm.h"
  15#include "rtl8188e_recv.h"
  16#include "rtl8188e_xmit.h"
  17#include "rtl8188e_cmd.h"
  18#include "pwrseq.h"
  19#include "rtw_efuse.h"
  20#include "rtw_sreset.h"
  21#include "odm_precomp.h"
  22
  23/* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
  24#define Rtl8188E_NIC_PWR_ON_FLOW                rtl8188E_power_on_flow
  25#define Rtl8188E_NIC_RF_OFF_FLOW                rtl8188E_radio_off_flow
  26#define Rtl8188E_NIC_DISABLE_FLOW               rtl8188E_card_disable_flow
  27#define Rtl8188E_NIC_ENABLE_FLOW                rtl8188E_card_enable_flow
  28#define Rtl8188E_NIC_SUSPEND_FLOW               rtl8188E_suspend_flow
  29#define Rtl8188E_NIC_RESUME_FLOW                rtl8188E_resume_flow
  30#define Rtl8188E_NIC_PDN_FLOW                   rtl8188E_hwpdn_flow
  31#define Rtl8188E_NIC_LPS_ENTER_FLOW             rtl8188E_enter_lps_flow
  32#define Rtl8188E_NIC_LPS_LEAVE_FLOW             rtl8188E_leave_lps_flow
  33
  34#define DRVINFO_SZ      4 /*  unit is 8bytes */
  35#define PageNum_128(_Len)       (u32)(((_Len) >> 7) + ((_Len) & 0x7F ? 1 : 0))
  36
  37/*  download firmware related data structure */
  38#define FW_8188E_SIZE                   0x4000 /* 16384,16k */
  39#define FW_8188E_START_ADDRESS          0x1000
  40#define FW_8188E_END_ADDRESS            0x1FFF /* 0x5FFF */
  41
  42#define MAX_PAGE_SIZE                   4096    /*  @ page : 4k bytes */
  43
  44#define IS_FW_HEADER_EXIST(_pFwHdr)                              \
  45        ((le16_to_cpu(_pFwHdr->signature) & 0xFFF0) == 0x92C0 || \
  46        (le16_to_cpu(_pFwHdr->signature) & 0xFFF0) == 0x88C0 ||  \
  47        (le16_to_cpu(_pFwHdr->signature) & 0xFFF0) == 0x2300 ||  \
  48        (le16_to_cpu(_pFwHdr->signature) & 0xFFF0) == 0x88E0)
  49
  50#define DRIVER_EARLY_INT_TIME           0x05
  51#define BCN_DMA_ATIME_INT_TIME          0x02
  52
  53enum usb_rx_agg_mode {
  54        USB_RX_AGG_DISABLE,
  55        USB_RX_AGG_DMA,
  56        USB_RX_AGG_USB,
  57        USB_RX_AGG_MIX
  58};
  59
  60#define MAX_RX_DMA_BUFFER_SIZE_88E                              \
  61      0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
  62              * WOLPattern(16*24))
  63              */
  64
  65#define MAX_TX_REPORT_BUFFER_SIZE               0x0400 /*  1k */
  66
  67/*  BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
  68#define MAX_TX_QUEUE                    9
  69
  70#define TX_SELE_HQ                      BIT(0)          /*  High Queue */
  71#define TX_SELE_LQ                      BIT(1)          /*  Low Queue */
  72#define TX_SELE_NQ                      BIT(2)          /*  Normal Queue */
  73
  74/*  Note: We will divide number of page equally for each queue other
  75 *  than public queue!
  76 */
  77/*  22k = 22528 bytes = 176 pages (@page =  128 bytes) */
  78/*  must reserved about 7 pages for LPS =>  176-7 = 169 (0xA9) */
  79/*  2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
  80 *  null-data
  81 */
  82
  83#define TX_TOTAL_PAGE_NUMBER_88E                0xA9/*   169 (21632=> 21k) */
  84
  85#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
  86
  87/* Note: For Normal Chip Setting ,modify later */
  88#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER                 \
  89        TX_TOTAL_PAGE_NUMBER_88E  /* 0xA9 , 0xb0=>176=>22k */
  90#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E                 \
  91        (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */
  92
  93/* Chip specific */
  94#define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
  95#define CHIP_BONDING_92C_1T2R   0x1
  96#define CHIP_BONDING_88C_USB_MCARD      0x2
  97#define CHIP_BONDING_88C_USB_HP 0x1
  98#include "HalVerDef.h"
  99#include "hal_com.h"
 100
 101/* Channel Plan */
 102enum ChannelPlan {
 103        CHPL_FCC        = 0,
 104        CHPL_IC         = 1,
 105        CHPL_ETSI       = 2,
 106        CHPL_SPA        = 3,
 107        CHPL_FRANCE     = 4,
 108        CHPL_MKK        = 5,
 109        CHPL_MKK1       = 6,
 110        CHPL_ISRAEL     = 7,
 111        CHPL_TELEC      = 8,
 112        CHPL_GLOBAL     = 9,
 113        CHPL_WORLD      = 10,
 114};
 115
 116struct txpowerinfo24g {
 117        u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 118        u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 119        /* If only one tx, only BW20 and OFDM are used. */
 120        s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 121        s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 122        s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 123        s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 124};
 125
 126#define EFUSE_REAL_CONTENT_LEN          512
 127#define EFUSE_MAX_SECTION               16
 128#define EFUSE_IC_ID_OFFSET              506 /* For some inferior IC purpose*/
 129#define AVAILABLE_EFUSE_ADDR(addr)      (addr < EFUSE_REAL_CONTENT_LEN)
 130/*  To prevent out of boundary programming case, */
 131/*  leave 1byte and program full section */
 132/*  9bytes + 1byt + 5bytes and pre 1byte. */
 133/*  For worst case: */
 134/*  | 1byte|----8bytes----|1byte|--5bytes--| */
 135/*  |         |            Reserved(14bytes)          | */
 136
 137/*  PG data exclude header, dummy 6 bytes from CP test and reserved 1byte. */
 138#define EFUSE_OOB_PROTECT_BYTES                 15
 139
 140#define         HWSET_MAX_SIZE_88E              512
 141
 142#define         EFUSE_REAL_CONTENT_LEN_88E      256
 143#define         EFUSE_MAP_LEN_88E               512
 144#define EFUSE_MAP_LEN                   EFUSE_MAP_LEN_88E
 145#define         EFUSE_MAX_SECTION_88E           64
 146#define         EFUSE_MAX_WORD_UNIT_88E         4
 147#define         EFUSE_IC_ID_OFFSET_88E          506
 148#define         AVAILABLE_EFUSE_ADDR_88E(addr)                  \
 149        (addr < EFUSE_REAL_CONTENT_LEN_88E)
 150/*  To prevent out of boundary programming case, leave 1byte and program
 151 *  full section
 152 */
 153/*  9bytes + 1byt + 5bytes and pre 1byte. */
 154/*  For worst case: */
 155/*  | 2byte|----8bytes----|1byte|--7bytes--| 92D */
 156/*  PG data exclude header, dummy 7 bytes from CP test and reserved 1byte. */
 157#define         EFUSE_OOB_PROTECT_BYTES_88E     18
 158#define         EFUSE_PROTECT_BYTES_BANK_88E    16
 159
 160/* EFUSE for BT definition */
 161#define EFUSE_BT_REAL_CONTENT_LEN       1536    /*  512*3 */
 162#define EFUSE_BT_MAP_LEN                1024    /*  1k bytes */
 163#define EFUSE_BT_MAX_SECTION            128     /*  1024/8 */
 164
 165#define EFUSE_PROTECT_BYTES_BANK        16
 166
 167struct hal_data_8188e {
 168        struct HAL_VERSION      VersionID;
 169        u16     CustomerID;
 170        u16     FirmwareVersion;
 171        u16     FirmwareVersionRev;
 172        u16     FirmwareSubVersion;
 173        u16     FirmwareSignature;
 174        u8      PGMaxGroup;
 175        /* current WIFI_PHY values */
 176        u32     ReceiveConfig;
 177        enum wireless_mode CurrentWirelessMode;
 178        enum ht_channel_width CurrentChannelBW;
 179        u8      CurrentChannel;
 180        u8      nCur40MhzPrimeSC;/*  Control channel sub-carrier */
 181
 182        u16     BasicRateSet;
 183
 184        u8      BoardType;
 185
 186        /*  EEPROM setting. */
 187        u16     EEPROMVID;
 188        u16     EEPROMPID;
 189        u16     EEPROMSVID;
 190        u16     EEPROMSDID;
 191        u8      EEPROMCustomerID;
 192        u8      EEPROMSubCustomerID;
 193        u8      EEPROMVersion;
 194        u8      EEPROMRegulatory;
 195
 196        u8      bTXPowerDataReadFromEEPORM;
 197        u8      EEPROMThermalMeter;
 198
 199        bool    EepromOrEfuse;
 200
 201        u8      Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 202        u8      Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 203        /* If only one tx, only BW20 and OFDM are used. */
 204        s8      CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 205        s8      OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 206        s8      BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 207        s8      BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 208
 209        u8      TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 210        /*  For HT 40MHZ pwr */
 211        u8      TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 212        /*  For HT 40MHZ pwr */
 213        u8      TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 214        /*  HT 20<->40 Pwr diff */
 215        u8      TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 216        /*  For HT<->legacy pwr diff */
 217        u8      TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 218        /*  For power group */
 219        u8      PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 220        u8      PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 221
 222        /*  Read/write are allow for following hardware information variables */
 223        u8      framesync;
 224        u8      pwrGroupCnt;
 225        u32     MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
 226
 227        u8      CrystalCap;
 228
 229        u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
 230
 231        struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */
 232
 233        u32     RfRegChnlVal[2];
 234
 235        /* RDG enable */
 236        bool     bRDGEnable;
 237
 238        /* for host message to fw */
 239        u8      LastHMEBoxNum;
 240
 241        u8      RegTxPause;
 242        /*  Beacon function related global variable. */
 243        u32     RegBcnCtrlVal;
 244        u8      RegFwHwTxQCtrl;
 245        u8      RegReg542;
 246        u8      RegCR_1;
 247
 248        struct dm_priv  dmpriv;
 249        struct odm_dm_struct odmpriv;
 250        struct sreset_priv srestpriv;
 251
 252        u8      CurAntenna;
 253        u8      AntDivCfg;
 254        u8      TRxAntDivType;
 255
 256        u8      bDumpRxPkt;/* for debug */
 257        u8      bDumpTxPkt;/* for debug */
 258
 259        /*  Add for dual MAC  0--Mac0 1--Mac1 */
 260        u32     interfaceIndex;
 261
 262        u8      OutEpQueueSel;
 263        u8      OutEpNumber;
 264
 265        u16     EfuseUsedBytes;
 266
 267        /*  Auto FSM to Turn On, include clock, isolation, power control
 268         *  for MAC only
 269         */
 270        u8      bMacPwrCtrlOn;
 271
 272        u32     UsbBulkOutSize;
 273
 274        /*  Interrupt relatd register information. */
 275        u32     IntArray[3];/* HISR0,HISR1,HSISR */
 276        u32     IntrMask[3];
 277        u8      C2hArray[16];
 278        u8      UsbTxAggMode;
 279        u8      UsbTxAggDescNum;
 280        u16     HwRxPageSize;           /*  Hardware setting */
 281
 282        enum usb_rx_agg_mode UsbRxAggMode;
 283        u8      UsbRxAggBlockCount;     /*  USB Block count. Block size is
 284                                         * 512-byte in high speed and 64-byte
 285                                         * in full speed
 286                                         */
 287        u8      UsbRxAggBlockTimeout;
 288        u8      UsbRxAggPageCount;      /*  8192C DMA page count */
 289        u8      UsbRxAggPageTimeout;
 290};
 291
 292void Hal_GetChnlGroup88E(u8 chnl, u8 *group);
 293
 294/*  rtl8188e_hal_init.c */
 295void _8051Reset88E(struct adapter *padapter);
 296void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
 297
 298s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
 299
 300/*  EFuse */
 301void Hal_InitPGData88E(struct adapter *padapter);
 302void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
 303void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
 304                            bool AutoLoadFail);
 305
 306void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo,
 307                                bool AutoLoadFail);
 308void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
 309                                 bool AutoLoadFail);
 310void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo,
 311                                 bool AutoLoadFail);
 312void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent,
 313                                 bool AutoLoadFail);
 314void Hal_ReadThermalMeter_88E(struct adapter *dapter, u8 *PROMContent,
 315                              bool AutoloadFail);
 316void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
 317                              bool AutoLoadFail);
 318void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo,
 319                                bool AutoLoadFail);
 320void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
 321                                bool AutoLoadFail);
 322
 323/*  register */
 324
 325void rtl8188e_start_thread(struct adapter *padapter);
 326void rtl8188e_stop_thread(struct adapter *padapter);
 327
 328s32 iol_execute(struct adapter *padapter, u8 control);
 329void iol_mode_enable(struct adapter *padapter, u8 enable);
 330s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
 331void rtw_cancel_all_timer(struct adapter *padapter);
 332
 333#endif /* __RTL8188E_HAL_H__ */
 334