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7#include "rtl_core.h"
8#include "r8192E_phyreg.h"
9#include "r8192E_phy.h"
10#include "r8190P_rtl8256.h"
11
12void rtl92e_set_bandwidth(struct net_device *dev,
13 enum ht_channel_width Bandwidth)
14{
15 u8 eRFPath;
16 struct r8192_priv *priv = rtllib_priv(dev);
17
18 if (priv->card_8192_version != VERSION_8190_BD &&
19 priv->card_8192_version != VERSION_8190_BE) {
20 netdev_warn(dev, "%s(): Unknown HW version.\n", __func__);
21 return;
22 }
23
24 for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) {
25 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
26 continue;
27
28 switch (Bandwidth) {
29 case HT_CHANNEL_WIDTH_20:
30 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
31 0x0b, bMask12Bits, 0x100);
32 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
33 0x2c, bMask12Bits, 0x3d7);
34 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
35 0x0e, bMask12Bits, 0x021);
36 break;
37 case HT_CHANNEL_WIDTH_20_40:
38 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
39 0x0b, bMask12Bits, 0x300);
40 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
41 0x2c, bMask12Bits, 0x3ff);
42 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
43 0x0e, bMask12Bits, 0x0e1);
44 break;
45 default:
46 netdev_err(dev, "%s(): Unknown bandwidth: %#X\n",
47 __func__, Bandwidth);
48 break;
49 }
50 }
51}
52
53bool rtl92e_config_rf(struct net_device *dev)
54{
55 u32 u4RegValue = 0;
56 u8 eRFPath;
57 bool rtStatus = true;
58 struct bb_reg_definition *pPhyReg;
59 struct r8192_priv *priv = rtllib_priv(dev);
60 u32 RegOffSetToBeCheck = 0x3;
61 u32 RegValueToBeCheck = 0x7f1;
62 u32 RF3_Final_Value = 0;
63 u8 ConstRetryTimes = 5, RetryTimes = 5;
64 u8 ret = 0;
65
66 priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
67
68 for (eRFPath = (enum rf90_radio_path)RF90_PATH_A;
69 eRFPath < priv->NumTotalRFPath; eRFPath++) {
70 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
71 continue;
72
73 pPhyReg = &priv->PHYRegDef[eRFPath];
74
75 switch (eRFPath) {
76 case RF90_PATH_A:
77 case RF90_PATH_C:
78 u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs,
79 bRFSI_RFENV);
80 break;
81 case RF90_PATH_B:
82 case RF90_PATH_D:
83 u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs,
84 bRFSI_RFENV<<16);
85 break;
86 }
87
88 rtl92e_set_bb_reg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
89
90 rtl92e_set_bb_reg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
91
92 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
93 b3WireAddressLength, 0x0);
94 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
95 b3WireDataLength, 0x0);
96
97 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 0x0,
98 bMask12Bits, 0xbf);
99
100 rtStatus = rtl92e_check_bb_and_rf(dev, HW90_BLOCK_RF,
101 (enum rf90_radio_path)eRFPath);
102 if (!rtStatus) {
103 netdev_err(dev, "%s(): Failed to check RF Path %d.\n",
104 __func__, eRFPath);
105 goto fail;
106 }
107
108 RetryTimes = ConstRetryTimes;
109 RF3_Final_Value = 0;
110 while (RF3_Final_Value != RegValueToBeCheck &&
111 RetryTimes != 0) {
112 ret = rtl92e_config_rf_path(dev,
113 (enum rf90_radio_path)eRFPath);
114 RF3_Final_Value = rtl92e_get_rf_reg(dev,
115 (enum rf90_radio_path)eRFPath,
116 RegOffSetToBeCheck,
117 bMask12Bits);
118 RT_TRACE(COMP_RF,
119 "RF %d %d register final value: %x\n",
120 eRFPath, RegOffSetToBeCheck,
121 RF3_Final_Value);
122 RetryTimes--;
123 }
124
125 switch (eRFPath) {
126 case RF90_PATH_A:
127 case RF90_PATH_C:
128 rtl92e_set_bb_reg(dev, pPhyReg->rfintfs, bRFSI_RFENV,
129 u4RegValue);
130 break;
131 case RF90_PATH_B:
132 case RF90_PATH_D:
133 rtl92e_set_bb_reg(dev, pPhyReg->rfintfs,
134 bRFSI_RFENV<<16, u4RegValue);
135 break;
136 }
137
138 if (ret) {
139 netdev_err(dev,
140 "%s(): Failed to initialize RF Path %d.\n",
141 __func__, eRFPath);
142 goto fail;
143 }
144 }
145
146 RT_TRACE(COMP_PHY, "PHY Initialization Success\n");
147 return true;
148
149fail:
150 return false;
151}
152
153void rtl92e_set_cck_tx_power(struct net_device *dev, u8 powerlevel)
154{
155 u32 TxAGC = 0;
156 struct r8192_priv *priv = rtllib_priv(dev);
157
158 TxAGC = powerlevel;
159 if (priv->bDynamicTxLowPower) {
160 if (priv->CustomerID == RT_CID_819x_Netcore)
161 TxAGC = 0x22;
162 else
163 TxAGC += priv->CckPwEnl;
164 }
165 if (TxAGC > 0x24)
166 TxAGC = 0x24;
167 rtl92e_set_bb_reg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
168}
169
170void rtl92e_set_ofdm_tx_power(struct net_device *dev, u8 powerlevel)
171{
172 struct r8192_priv *priv = rtllib_priv(dev);
173 u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
174 u8 index = 0;
175 u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
176 u8 byte0, byte1, byte2, byte3;
177
178 powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff;
179 powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
180 (powerBase0 << 8) | powerBase0;
181 powerBase1 = powerlevel;
182 powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) |
183 (powerBase1 << 8) | powerBase1;
184
185 for (index = 0; index < 6; index++) {
186 writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] +
187 ((index < 2) ? powerBase0 : powerBase1));
188 byte0 = (u8)(writeVal & 0x7f);
189 byte1 = (u8)((writeVal & 0x7f00)>>8);
190 byte2 = (u8)((writeVal & 0x7f0000)>>16);
191 byte3 = (u8)((writeVal & 0x7f000000)>>24);
192 if (byte0 > 0x24)
193 byte0 = 0x24;
194 if (byte1 > 0x24)
195 byte1 = 0x24;
196 if (byte2 > 0x24)
197 byte2 = 0x24;
198 if (byte3 > 0x24)
199 byte3 = 0x24;
200
201 if (index == 3) {
202 writeVal_tmp = (byte3 << 24) | (byte2 << 16) |
203 (byte1 << 8) | byte0;
204 priv->Pwr_Track = writeVal_tmp;
205 }
206
207 if (priv->bDynamicTxHighPower)
208 writeVal = 0x03030303;
209 else
210 writeVal = (byte3 << 24) | (byte2 << 16) |
211 (byte1 << 8) | byte0;
212 rtl92e_set_bb_reg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
213 }
214}
215
