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36#include <linux/file.h>
37#include "device.h"
38#include "card.h"
39#include "channel.h"
40#include "baseband.h"
41#include "mac.h"
42#include "power.h"
43#include "rxtx.h"
44#include "dpc.h"
45#include "rf.h"
46#include <linux/delay.h>
47#include <linux/kthread.h>
48#include <linux/slab.h>
49
50
51
52
53
54MODULE_AUTHOR("VIA Networking Technologies, Inc., <lyndonchen@vntek.com.tw>");
55MODULE_LICENSE("GPL");
56MODULE_DESCRIPTION("VIA Networking Solomon-A/B/G Wireless LAN Adapter Driver");
57
58#define DEVICE_PARAM(N, D)
59
60#define RX_DESC_MIN0 16
61#define RX_DESC_MAX0 128
62#define RX_DESC_DEF0 32
63DEVICE_PARAM(RxDescriptors0, "Number of receive descriptors0");
64
65#define RX_DESC_MIN1 16
66#define RX_DESC_MAX1 128
67#define RX_DESC_DEF1 32
68DEVICE_PARAM(RxDescriptors1, "Number of receive descriptors1");
69
70#define TX_DESC_MIN0 16
71#define TX_DESC_MAX0 128
72#define TX_DESC_DEF0 32
73DEVICE_PARAM(TxDescriptors0, "Number of transmit descriptors0");
74
75#define TX_DESC_MIN1 16
76#define TX_DESC_MAX1 128
77#define TX_DESC_DEF1 64
78DEVICE_PARAM(TxDescriptors1, "Number of transmit descriptors1");
79
80#define INT_WORKS_DEF 20
81#define INT_WORKS_MIN 10
82#define INT_WORKS_MAX 64
83
84DEVICE_PARAM(int_works, "Number of packets per interrupt services");
85
86#define RTS_THRESH_DEF 2347
87
88#define FRAG_THRESH_DEF 2346
89
90#define SHORT_RETRY_MIN 0
91#define SHORT_RETRY_MAX 31
92#define SHORT_RETRY_DEF 8
93
94DEVICE_PARAM(ShortRetryLimit, "Short frame retry limits");
95
96#define LONG_RETRY_MIN 0
97#define LONG_RETRY_MAX 15
98#define LONG_RETRY_DEF 4
99
100DEVICE_PARAM(LongRetryLimit, "long frame retry limits");
101
102
103
104
105
106
107#define BBP_TYPE_MIN 0
108#define BBP_TYPE_MAX 2
109#define BBP_TYPE_DEF 2
110
111DEVICE_PARAM(BasebandType, "baseband type");
112
113
114
115
116static const struct pci_device_id vt6655_pci_id_table[] = {
117 { PCI_VDEVICE(VIA, 0x3253) },
118 { 0, }
119};
120
121
122
123static int vt6655_probe(struct pci_dev *pcid, const struct pci_device_id *ent);
124static void device_free_info(struct vnt_private *priv);
125static void device_print_info(struct vnt_private *priv);
126
127static int device_init_rd0_ring(struct vnt_private *priv);
128static int device_init_rd1_ring(struct vnt_private *priv);
129static int device_init_td0_ring(struct vnt_private *priv);
130static int device_init_td1_ring(struct vnt_private *priv);
131
132static int device_rx_srv(struct vnt_private *priv, unsigned int idx);
133static int device_tx_srv(struct vnt_private *priv, unsigned int idx);
134static bool device_alloc_rx_buf(struct vnt_private *, struct vnt_rx_desc *);
135static void device_free_rx_buf(struct vnt_private *priv,
136 struct vnt_rx_desc *rd);
137static void device_init_registers(struct vnt_private *priv);
138static void device_free_tx_buf(struct vnt_private *, struct vnt_tx_desc *);
139static void device_free_td0_ring(struct vnt_private *priv);
140static void device_free_td1_ring(struct vnt_private *priv);
141static void device_free_rd0_ring(struct vnt_private *priv);
142static void device_free_rd1_ring(struct vnt_private *priv);
143static void device_free_rings(struct vnt_private *priv);
144
145
146
147
148
149static void vt6655_remove(struct pci_dev *pcid)
150{
151 struct vnt_private *priv = pci_get_drvdata(pcid);
152
153 if (!priv)
154 return;
155 device_free_info(priv);
156}
157
158static void device_get_options(struct vnt_private *priv)
159{
160 struct vnt_options *opts = &priv->opts;
161
162 opts->rx_descs0 = RX_DESC_DEF0;
163 opts->rx_descs1 = RX_DESC_DEF1;
164 opts->tx_descs[0] = TX_DESC_DEF0;
165 opts->tx_descs[1] = TX_DESC_DEF1;
166 opts->int_works = INT_WORKS_DEF;
167
168 opts->short_retry = SHORT_RETRY_DEF;
169 opts->long_retry = LONG_RETRY_DEF;
170 opts->bbp_type = BBP_TYPE_DEF;
171}
172
173static void
174device_set_options(struct vnt_private *priv)
175{
176 priv->byShortRetryLimit = priv->opts.short_retry;
177 priv->byLongRetryLimit = priv->opts.long_retry;
178 priv->byBBType = priv->opts.bbp_type;
179 priv->byPacketType = priv->byBBType;
180 priv->byAutoFBCtrl = AUTO_FB_0;
181 priv->bUpdateBBVGA = true;
182 priv->byPreambleType = 0;
183
184 pr_debug(" byShortRetryLimit= %d\n", (int)priv->byShortRetryLimit);
185 pr_debug(" byLongRetryLimit= %d\n", (int)priv->byLongRetryLimit);
186 pr_debug(" byPreambleType= %d\n", (int)priv->byPreambleType);
187 pr_debug(" byShortPreamble= %d\n", (int)priv->byShortPreamble);
188 pr_debug(" byBBType= %d\n", (int)priv->byBBType);
189}
190
191
192
193
194
195static void device_init_registers(struct vnt_private *priv)
196{
197 unsigned long flags;
198 unsigned int ii;
199 unsigned char byValue;
200 unsigned char byCCKPwrdBm = 0;
201 unsigned char byOFDMPwrdBm = 0;
202
203 MACbShutdown(priv);
204 bb_software_reset(priv);
205
206
207 MACbSoftwareReset(priv);
208
209 priv->bAES = false;
210
211
212 priv->bProtectMode = false;
213
214 priv->bNonERPPresent = false;
215 priv->bBarkerPreambleMd = false;
216 priv->wCurrentRate = RATE_1M;
217 priv->byTopOFDMBasicRate = RATE_24M;
218 priv->byTopCCKBasicRate = RATE_1M;
219
220
221 MACvInitialize(priv);
222
223
224 VNSvInPortB(priv->PortOffset + MAC_REG_LOCALID, &priv->byLocalID);
225
226 spin_lock_irqsave(&priv->lock, flags);
227
228 SROMvReadAllContents(priv->PortOffset, priv->abyEEPROM);
229
230 spin_unlock_irqrestore(&priv->lock, flags);
231
232
233 priv->byMinChannel = 1;
234 priv->byMaxChannel = CB_MAX_CHANNEL;
235
236
237 byValue = SROMbyReadEmbedded(priv->PortOffset, EEP_OFS_ANTENNA);
238 if (byValue & EEP_ANTINV)
239 priv->bTxRxAntInv = true;
240 else
241 priv->bTxRxAntInv = false;
242
243 byValue &= (EEP_ANTENNA_AUX | EEP_ANTENNA_MAIN);
244
245 if (byValue == 0)
246 byValue = (EEP_ANTENNA_AUX | EEP_ANTENNA_MAIN);
247
248 if (byValue == (EEP_ANTENNA_AUX | EEP_ANTENNA_MAIN)) {
249 priv->byAntennaCount = 2;
250 priv->byTxAntennaMode = ANT_B;
251 priv->dwTxAntennaSel = 1;
252 priv->dwRxAntennaSel = 1;
253
254 if (priv->bTxRxAntInv)
255 priv->byRxAntennaMode = ANT_A;
256 else
257 priv->byRxAntennaMode = ANT_B;
258 } else {
259 priv->byAntennaCount = 1;
260 priv->dwTxAntennaSel = 0;
261 priv->dwRxAntennaSel = 0;
262
263 if (byValue & EEP_ANTENNA_AUX) {
264 priv->byTxAntennaMode = ANT_A;
265
266 if (priv->bTxRxAntInv)
267 priv->byRxAntennaMode = ANT_B;
268 else
269 priv->byRxAntennaMode = ANT_A;
270 } else {
271 priv->byTxAntennaMode = ANT_B;
272
273 if (priv->bTxRxAntInv)
274 priv->byRxAntennaMode = ANT_A;
275 else
276 priv->byRxAntennaMode = ANT_B;
277 }
278 }
279
280
281 bb_set_tx_antenna_mode(priv, priv->byTxAntennaMode);
282 bb_set_rx_antenna_mode(priv, priv->byRxAntennaMode);
283
284
285 priv->byOriginalZonetype = priv->abyEEPROM[EEP_OFS_ZONETYPE];
286
287 if (!priv->bZoneRegExist)
288 priv->byZoneType = priv->abyEEPROM[EEP_OFS_ZONETYPE];
289
290 pr_debug("priv->byZoneType = %x\n", priv->byZoneType);
291
292
293 RFbInit(priv);
294
295
296 priv->byCurPwr = 0xFF;
297 priv->byCCKPwr = SROMbyReadEmbedded(priv->PortOffset, EEP_OFS_PWR_CCK);
298 priv->byOFDMPwrG = SROMbyReadEmbedded(priv->PortOffset,
299 EEP_OFS_PWR_OFDMG);
300
301
302 for (ii = 0; ii < CB_MAX_CHANNEL_24G; ii++) {
303 priv->abyCCKPwrTbl[ii + 1] =
304 SROMbyReadEmbedded(priv->PortOffset,
305 (unsigned char)(ii + EEP_OFS_CCK_PWR_TBL));
306 if (priv->abyCCKPwrTbl[ii + 1] == 0)
307 priv->abyCCKPwrTbl[ii + 1] = priv->byCCKPwr;
308
309 priv->abyOFDMPwrTbl[ii + 1] =
310 SROMbyReadEmbedded(priv->PortOffset,
311 (unsigned char)(ii + EEP_OFS_OFDM_PWR_TBL));
312 if (priv->abyOFDMPwrTbl[ii + 1] == 0)
313 priv->abyOFDMPwrTbl[ii + 1] = priv->byOFDMPwrG;
314
315 priv->abyCCKDefaultPwr[ii + 1] = byCCKPwrdBm;
316 priv->abyOFDMDefaultPwr[ii + 1] = byOFDMPwrdBm;
317 }
318
319
320 for (ii = 11; ii < 14; ii++) {
321 priv->abyCCKPwrTbl[ii] = priv->abyCCKPwrTbl[10];
322 priv->abyOFDMPwrTbl[ii] = priv->abyOFDMPwrTbl[10];
323 }
324
325
326 for (ii = 0; ii < CB_MAX_CHANNEL_5G; ii++) {
327 priv->abyOFDMPwrTbl[ii + CB_MAX_CHANNEL_24G + 1] =
328 SROMbyReadEmbedded(priv->PortOffset,
329 (unsigned char)(ii + EEP_OFS_OFDMA_PWR_TBL));
330
331 priv->abyOFDMDefaultPwr[ii + CB_MAX_CHANNEL_24G + 1] =
332 SROMbyReadEmbedded(priv->PortOffset,
333 (unsigned char)(ii + EEP_OFS_OFDMA_PWR_dBm));
334 }
335
336 if (priv->byLocalID > REV_ID_VT3253_B1) {
337 MACvSelectPage1(priv->PortOffset);
338
339 VNSvOutPortB(priv->PortOffset + MAC_REG_MSRCTL + 1,
340 (MSRCTL1_TXPWR | MSRCTL1_CSAPAREN));
341
342 MACvSelectPage0(priv->PortOffset);
343 }
344
345
346 MACvWordRegBitsOn(priv->PortOffset,
347 MAC_REG_CFG, (CFG_TKIPOPT | CFG_NOTXTIMEOUT));
348
349
350 MACvSetShortRetryLimit(priv, priv->byShortRetryLimit);
351 MACvSetLongRetryLimit(priv, priv->byLongRetryLimit);
352
353
354 VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTRST);
355
356 VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTREN);
357
358
359 bb_vt3253_init(priv);
360
361 if (priv->bUpdateBBVGA) {
362 priv->byBBVGACurrent = priv->abyBBVGA[0];
363 priv->byBBVGANew = priv->byBBVGACurrent;
364 bb_set_vga_gain_offset(priv, priv->abyBBVGA[0]);
365 }
366
367 bb_set_rx_antenna_mode(priv, priv->byRxAntennaMode);
368 bb_set_tx_antenna_mode(priv, priv->byTxAntennaMode);
369
370
371
372 priv->wCurrentRate = RATE_54M;
373
374 priv->bRadioOff = false;
375
376 priv->byRadioCtl = SROMbyReadEmbedded(priv->PortOffset,
377 EEP_OFS_RADIOCTL);
378 priv->bHWRadioOff = false;
379
380 if (priv->byRadioCtl & EEP_RADIOCTL_ENABLE) {
381
382 MACvGPIOIn(priv->PortOffset, &priv->byGPIO);
383
384 if (((priv->byGPIO & GPIO0_DATA) &&
385 !(priv->byRadioCtl & EEP_RADIOCTL_INV)) ||
386 (!(priv->byGPIO & GPIO0_DATA) &&
387 (priv->byRadioCtl & EEP_RADIOCTL_INV)))
388 priv->bHWRadioOff = true;
389 }
390
391 if (priv->bHWRadioOff || priv->bRadioControlOff)
392 CARDbRadioPowerOff(priv);
393
394
395 SROMvReadEtherAddress(priv->PortOffset, priv->abyCurrentNetAddr);
396 pr_debug("Network address = %pM\n", priv->abyCurrentNetAddr);
397
398
399 CARDvSafeResetRx(priv);
400
401 CARDvSafeResetTx(priv);
402
403 if (priv->byLocalID <= REV_ID_VT3253_A1)
404 MACvRegBitsOn(priv->PortOffset, MAC_REG_RCR, RCR_WPAERR);
405
406
407 MACvReceive0(priv->PortOffset);
408 MACvReceive1(priv->PortOffset);
409
410
411 MACvStart(priv->PortOffset);
412}
413
414static void device_print_info(struct vnt_private *priv)
415{
416 dev_info(&priv->pcid->dev, "MAC=%pM IO=0x%lx Mem=0x%lx IRQ=%d\n",
417 priv->abyCurrentNetAddr, (unsigned long)priv->ioaddr,
418 (unsigned long)priv->PortOffset, priv->pcid->irq);
419}
420
421static void device_free_info(struct vnt_private *priv)
422{
423 if (!priv)
424 return;
425
426 if (priv->mac_hw)
427 ieee80211_unregister_hw(priv->hw);
428
429 if (priv->PortOffset)
430 iounmap(priv->PortOffset);
431
432 if (priv->pcid)
433 pci_release_regions(priv->pcid);
434
435 if (priv->hw)
436 ieee80211_free_hw(priv->hw);
437}
438
439static bool device_init_rings(struct vnt_private *priv)
440{
441 void *vir_pool;
442
443
444 vir_pool = dma_alloc_coherent(&priv->pcid->dev,
445 priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc) +
446 priv->opts.rx_descs1 * sizeof(struct vnt_rx_desc) +
447 priv->opts.tx_descs[0] * sizeof(struct vnt_tx_desc) +
448 priv->opts.tx_descs[1] * sizeof(struct vnt_tx_desc),
449 &priv->pool_dma, GFP_ATOMIC);
450 if (!vir_pool) {
451 dev_err(&priv->pcid->dev, "allocate desc dma memory failed\n");
452 return false;
453 }
454
455 priv->aRD0Ring = vir_pool;
456 priv->aRD1Ring = vir_pool +
457 priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc);
458
459 priv->rd0_pool_dma = priv->pool_dma;
460 priv->rd1_pool_dma = priv->rd0_pool_dma +
461 priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc);
462
463 priv->tx0_bufs = dma_alloc_coherent(&priv->pcid->dev,
464 priv->opts.tx_descs[0] * PKT_BUF_SZ +
465 priv->opts.tx_descs[1] * PKT_BUF_SZ +
466 CB_BEACON_BUF_SIZE +
467 CB_MAX_BUF_SIZE,
468 &priv->tx_bufs_dma0, GFP_ATOMIC);
469 if (!priv->tx0_bufs) {
470 dev_err(&priv->pcid->dev, "allocate buf dma memory failed\n");
471
472 dma_free_coherent(&priv->pcid->dev,
473 priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc) +
474 priv->opts.rx_descs1 * sizeof(struct vnt_rx_desc) +
475 priv->opts.tx_descs[0] * sizeof(struct vnt_tx_desc) +
476 priv->opts.tx_descs[1] * sizeof(struct vnt_tx_desc),
477 vir_pool, priv->pool_dma);
478 return false;
479 }
480
481 priv->td0_pool_dma = priv->rd1_pool_dma +
482 priv->opts.rx_descs1 * sizeof(struct vnt_rx_desc);
483
484 priv->td1_pool_dma = priv->td0_pool_dma +
485 priv->opts.tx_descs[0] * sizeof(struct vnt_tx_desc);
486
487
488 priv->apTD0Rings = vir_pool
489 + priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc)
490 + priv->opts.rx_descs1 * sizeof(struct vnt_rx_desc);
491
492 priv->apTD1Rings = vir_pool
493 + priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc)
494 + priv->opts.rx_descs1 * sizeof(struct vnt_rx_desc)
495 + priv->opts.tx_descs[0] * sizeof(struct vnt_tx_desc);
496
497 priv->tx1_bufs = priv->tx0_bufs +
498 priv->opts.tx_descs[0] * PKT_BUF_SZ;
499
500 priv->tx_beacon_bufs = priv->tx1_bufs +
501 priv->opts.tx_descs[1] * PKT_BUF_SZ;
502
503 priv->pbyTmpBuff = priv->tx_beacon_bufs +
504 CB_BEACON_BUF_SIZE;
505
506 priv->tx_bufs_dma1 = priv->tx_bufs_dma0 +
507 priv->opts.tx_descs[0] * PKT_BUF_SZ;
508
509 priv->tx_beacon_dma = priv->tx_bufs_dma1 +
510 priv->opts.tx_descs[1] * PKT_BUF_SZ;
511
512 return true;
513}
514
515static void device_free_rings(struct vnt_private *priv)
516{
517 dma_free_coherent(&priv->pcid->dev,
518 priv->opts.rx_descs0 * sizeof(struct vnt_rx_desc) +
519 priv->opts.rx_descs1 * sizeof(struct vnt_rx_desc) +
520 priv->opts.tx_descs[0] * sizeof(struct vnt_tx_desc) +
521 priv->opts.tx_descs[1] * sizeof(struct vnt_tx_desc),
522 priv->aRD0Ring, priv->pool_dma);
523
524 if (priv->tx0_bufs)
525 dma_free_coherent(&priv->pcid->dev,
526 priv->opts.tx_descs[0] * PKT_BUF_SZ +
527 priv->opts.tx_descs[1] * PKT_BUF_SZ +
528 CB_BEACON_BUF_SIZE +
529 CB_MAX_BUF_SIZE,
530 priv->tx0_bufs, priv->tx_bufs_dma0);
531}
532
533static int device_init_rd0_ring(struct vnt_private *priv)
534{
535 int i;
536 dma_addr_t curr = priv->rd0_pool_dma;
537 struct vnt_rx_desc *desc;
538 int ret;
539
540
541 for (i = 0; i < priv->opts.rx_descs0;
542 i ++, curr += sizeof(struct vnt_rx_desc)) {
543 desc = &priv->aRD0Ring[i];
544 desc->rd_info = kzalloc(sizeof(*desc->rd_info), GFP_KERNEL);
545 if (!desc->rd_info) {
546 ret = -ENOMEM;
547 goto err_free_desc;
548 }
549
550 if (!device_alloc_rx_buf(priv, desc)) {
551 dev_err(&priv->pcid->dev, "can not alloc rx bufs\n");
552 ret = -ENOMEM;
553 goto err_free_rd;
554 }
555
556 desc->next = &priv->aRD0Ring[(i + 1) % priv->opts.rx_descs0];
557 desc->next_desc = cpu_to_le32(curr + sizeof(struct vnt_rx_desc));
558 }
559
560 if (i > 0)
561 priv->aRD0Ring[i - 1].next_desc = cpu_to_le32(priv->rd0_pool_dma);
562 priv->pCurrRD[0] = &priv->aRD0Ring[0];
563
564 return 0;
565
566err_free_rd:
567 kfree(desc->rd_info);
568
569err_free_desc:
570 while (--i) {
571 desc = &priv->aRD0Ring[i];
572 device_free_rx_buf(priv, desc);
573 kfree(desc->rd_info);
574 }
575
576 return ret;
577}
578
579static int device_init_rd1_ring(struct vnt_private *priv)
580{
581 int i;
582 dma_addr_t curr = priv->rd1_pool_dma;
583 struct vnt_rx_desc *desc;
584 int ret;
585
586
587 for (i = 0; i < priv->opts.rx_descs1;
588 i ++, curr += sizeof(struct vnt_rx_desc)) {
589 desc = &priv->aRD1Ring[i];
590 desc->rd_info = kzalloc(sizeof(*desc->rd_info), GFP_KERNEL);
591 if (!desc->rd_info) {
592 ret = -ENOMEM;
593 goto err_free_desc;
594 }
595
596 if (!device_alloc_rx_buf(priv, desc)) {
597 dev_err(&priv->pcid->dev, "can not alloc rx bufs\n");
598 ret = -ENOMEM;
599 goto err_free_rd;
600 }
601
602 desc->next = &priv->aRD1Ring[(i + 1) % priv->opts.rx_descs1];
603 desc->next_desc = cpu_to_le32(curr + sizeof(struct vnt_rx_desc));
604 }
605
606 if (i > 0)
607 priv->aRD1Ring[i - 1].next_desc = cpu_to_le32(priv->rd1_pool_dma);
608 priv->pCurrRD[1] = &priv->aRD1Ring[0];
609
610 return 0;
611
612err_free_rd:
613 kfree(desc->rd_info);
614
615err_free_desc:
616 while (--i) {
617 desc = &priv->aRD1Ring[i];
618 device_free_rx_buf(priv, desc);
619 kfree(desc->rd_info);
620 }
621
622 return ret;
623}
624
625static void device_free_rd0_ring(struct vnt_private *priv)
626{
627 int i;
628
629 for (i = 0; i < priv->opts.rx_descs0; i++) {
630 struct vnt_rx_desc *desc = &priv->aRD0Ring[i];
631
632 device_free_rx_buf(priv, desc);
633 kfree(desc->rd_info);
634 }
635}
636
637static void device_free_rd1_ring(struct vnt_private *priv)
638{
639 int i;
640
641 for (i = 0; i < priv->opts.rx_descs1; i++) {
642 struct vnt_rx_desc *desc = &priv->aRD1Ring[i];
643
644 device_free_rx_buf(priv, desc);
645 kfree(desc->rd_info);
646 }
647}
648
649static int device_init_td0_ring(struct vnt_private *priv)
650{
651 int i;
652 dma_addr_t curr;
653 struct vnt_tx_desc *desc;
654 int ret;
655
656 curr = priv->td0_pool_dma;
657 for (i = 0; i < priv->opts.tx_descs[0];
658 i++, curr += sizeof(struct vnt_tx_desc)) {
659 desc = &priv->apTD0Rings[i];
660 desc->td_info = kzalloc(sizeof(*desc->td_info), GFP_KERNEL);
661 if (!desc->td_info) {
662 ret = -ENOMEM;
663 goto err_free_desc;
664 }
665
666 desc->td_info->buf = priv->tx0_bufs + i * PKT_BUF_SZ;
667 desc->td_info->buf_dma = priv->tx_bufs_dma0 + i * PKT_BUF_SZ;
668
669 desc->next = &(priv->apTD0Rings[(i + 1) % priv->opts.tx_descs[0]]);
670 desc->next_desc = cpu_to_le32(curr +
671 sizeof(struct vnt_tx_desc));
672 }
673
674 if (i > 0)
675 priv->apTD0Rings[i - 1].next_desc = cpu_to_le32(priv->td0_pool_dma);
676 priv->apTailTD[0] = priv->apCurrTD[0] = &priv->apTD0Rings[0];
677
678 return 0;
679
680err_free_desc:
681 while (--i) {
682 desc = &priv->apTD0Rings[i];
683 kfree(desc->td_info);
684 }
685
686 return ret;
687}
688
689static int device_init_td1_ring(struct vnt_private *priv)
690{
691 int i;
692 dma_addr_t curr;
693 struct vnt_tx_desc *desc;
694 int ret;
695
696
697 curr = priv->td1_pool_dma;
698 for (i = 0; i < priv->opts.tx_descs[1];
699 i++, curr += sizeof(struct vnt_tx_desc)) {
700 desc = &priv->apTD1Rings[i];
701 desc->td_info = kzalloc(sizeof(*desc->td_info), GFP_KERNEL);
702 if (!desc->td_info) {
703 ret = -ENOMEM;
704 goto err_free_desc;
705 }
706
707 desc->td_info->buf = priv->tx1_bufs + i * PKT_BUF_SZ;
708 desc->td_info->buf_dma = priv->tx_bufs_dma1 + i * PKT_BUF_SZ;
709
710 desc->next = &(priv->apTD1Rings[(i + 1) % priv->opts.tx_descs[1]]);
711 desc->next_desc = cpu_to_le32(curr + sizeof(struct vnt_tx_desc));
712 }
713
714 if (i > 0)
715 priv->apTD1Rings[i - 1].next_desc = cpu_to_le32(priv->td1_pool_dma);
716 priv->apTailTD[1] = priv->apCurrTD[1] = &priv->apTD1Rings[0];
717
718 return 0;
719
720err_free_desc:
721 while (--i) {
722 desc = &priv->apTD1Rings[i];
723 kfree(desc->td_info);
724 }
725
726 return ret;
727}
728
729static void device_free_td0_ring(struct vnt_private *priv)
730{
731 int i;
732
733 for (i = 0; i < priv->opts.tx_descs[0]; i++) {
734 struct vnt_tx_desc *desc = &priv->apTD0Rings[i];
735 struct vnt_td_info *td_info = desc->td_info;
736
737 dev_kfree_skb(td_info->skb);
738 kfree(desc->td_info);
739 }
740}
741
742static void device_free_td1_ring(struct vnt_private *priv)
743{
744 int i;
745
746 for (i = 0; i < priv->opts.tx_descs[1]; i++) {
747 struct vnt_tx_desc *desc = &priv->apTD1Rings[i];
748 struct vnt_td_info *td_info = desc->td_info;
749
750 dev_kfree_skb(td_info->skb);
751 kfree(desc->td_info);
752 }
753}
754
755
756
757static int device_rx_srv(struct vnt_private *priv, unsigned int idx)
758{
759 struct vnt_rx_desc *rd;
760 int works = 0;
761
762 for (rd = priv->pCurrRD[idx];
763 rd->rd0.owner == OWNED_BY_HOST;
764 rd = rd->next) {
765 if (works++ > 15)
766 break;
767
768 if (!rd->rd_info->skb)
769 break;
770
771 if (vnt_receive_frame(priv, rd)) {
772 if (!device_alloc_rx_buf(priv, rd)) {
773 dev_err(&priv->pcid->dev,
774 "can not allocate rx buf\n");
775 break;
776 }
777 }
778 rd->rd0.owner = OWNED_BY_NIC;
779 }
780
781 priv->pCurrRD[idx] = rd;
782
783 return works;
784}
785
786static bool device_alloc_rx_buf(struct vnt_private *priv,
787 struct vnt_rx_desc *rd)
788{
789 struct vnt_rd_info *rd_info = rd->rd_info;
790
791 rd_info->skb = dev_alloc_skb((int)priv->rx_buf_sz);
792 if (!rd_info->skb)
793 return false;
794
795 rd_info->skb_dma =
796 dma_map_single(&priv->pcid->dev,
797 skb_put(rd_info->skb, skb_tailroom(rd_info->skb)),
798 priv->rx_buf_sz, DMA_FROM_DEVICE);
799 if (dma_mapping_error(&priv->pcid->dev, rd_info->skb_dma)) {
800 dev_kfree_skb(rd_info->skb);
801 rd_info->skb = NULL;
802 return false;
803 }
804
805 *((unsigned int *)&rd->rd0) = 0;
806
807 rd->rd0.res_count = cpu_to_le16(priv->rx_buf_sz);
808 rd->rd0.owner = OWNED_BY_NIC;
809 rd->rd1.req_count = cpu_to_le16(priv->rx_buf_sz);
810 rd->buff_addr = cpu_to_le32(rd_info->skb_dma);
811
812 return true;
813}
814
815static void device_free_rx_buf(struct vnt_private *priv,
816 struct vnt_rx_desc *rd)
817{
818 struct vnt_rd_info *rd_info = rd->rd_info;
819
820 dma_unmap_single(&priv->pcid->dev, rd_info->skb_dma,
821 priv->rx_buf_sz, DMA_FROM_DEVICE);
822 dev_kfree_skb(rd_info->skb);
823}
824
825static const u8 fallback_rate0[5][5] = {
826 {RATE_18M, RATE_18M, RATE_12M, RATE_12M, RATE_12M},
827 {RATE_24M, RATE_24M, RATE_18M, RATE_12M, RATE_12M},
828 {RATE_36M, RATE_36M, RATE_24M, RATE_18M, RATE_18M},
829 {RATE_48M, RATE_48M, RATE_36M, RATE_24M, RATE_24M},
830 {RATE_54M, RATE_54M, RATE_48M, RATE_36M, RATE_36M}
831};
832
833static const u8 fallback_rate1[5][5] = {
834 {RATE_18M, RATE_18M, RATE_12M, RATE_6M, RATE_6M},
835 {RATE_24M, RATE_24M, RATE_18M, RATE_6M, RATE_6M},
836 {RATE_36M, RATE_36M, RATE_24M, RATE_12M, RATE_12M},
837 {RATE_48M, RATE_48M, RATE_24M, RATE_12M, RATE_12M},
838 {RATE_54M, RATE_54M, RATE_36M, RATE_18M, RATE_18M}
839};
840
841static int vnt_int_report_rate(struct vnt_private *priv,
842 struct vnt_td_info *context, u8 tsr0, u8 tsr1)
843{
844 struct vnt_tx_fifo_head *fifo_head;
845 struct ieee80211_tx_info *info;
846 struct ieee80211_rate *rate;
847 u16 fb_option;
848 u8 tx_retry = (tsr0 & TSR0_NCR);
849 s8 idx;
850
851 if (!context)
852 return -ENOMEM;
853
854 if (!context->skb)
855 return -EINVAL;
856
857 fifo_head = (struct vnt_tx_fifo_head *)context->buf;
858 fb_option = (le16_to_cpu(fifo_head->fifo_ctl) &
859 (FIFOCTL_AUTO_FB_0 | FIFOCTL_AUTO_FB_1));
860
861 info = IEEE80211_SKB_CB(context->skb);
862 idx = info->control.rates[0].idx;
863
864 if (fb_option && !(tsr1 & TSR1_TERR)) {
865 u8 tx_rate;
866 u8 retry = tx_retry;
867
868 rate = ieee80211_get_tx_rate(priv->hw, info);
869 tx_rate = rate->hw_value - RATE_18M;
870
871 if (retry > 4)
872 retry = 4;
873
874 if (fb_option & FIFOCTL_AUTO_FB_0)
875 tx_rate = fallback_rate0[tx_rate][retry];
876 else if (fb_option & FIFOCTL_AUTO_FB_1)
877 tx_rate = fallback_rate1[tx_rate][retry];
878
879 if (info->band == NL80211_BAND_5GHZ)
880 idx = tx_rate - RATE_6M;
881 else
882 idx = tx_rate;
883 }
884
885 ieee80211_tx_info_clear_status(info);
886
887 info->status.rates[0].count = tx_retry;
888
889 if (!(tsr1 & TSR1_TERR)) {
890 info->status.rates[0].idx = idx;
891
892 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
893 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
894 else
895 info->flags |= IEEE80211_TX_STAT_ACK;
896 }
897
898 return 0;
899}
900
901static int device_tx_srv(struct vnt_private *priv, unsigned int idx)
902{
903 struct vnt_tx_desc *desc;
904 int works = 0;
905 unsigned char byTsr0;
906 unsigned char byTsr1;
907
908 for (desc = priv->apTailTD[idx]; priv->iTDUsed[idx] > 0; desc = desc->next) {
909 if (desc->td0.owner == OWNED_BY_NIC)
910 break;
911 if (works++ > 15)
912 break;
913
914 byTsr0 = desc->td0.tsr0;
915 byTsr1 = desc->td0.tsr1;
916
917
918 if (desc->td1.tcr & TCR_STP) {
919 if ((desc->td_info->flags & TD_FLAGS_NETIF_SKB) != 0) {
920 if (!(byTsr1 & TSR1_TERR)) {
921 if (byTsr0 != 0) {
922 pr_debug(" Tx[%d] OK but has error. tsr1[%02X] tsr0[%02X]\n",
923 (int)idx, byTsr1,
924 byTsr0);
925 }
926 } else {
927 pr_debug(" Tx[%d] dropped & tsr1[%02X] tsr0[%02X]\n",
928 (int)idx, byTsr1, byTsr0);
929 }
930 }
931
932 if (byTsr1 & TSR1_TERR) {
933 if ((desc->td_info->flags & TD_FLAGS_PRIV_SKB) != 0) {
934 pr_debug(" Tx[%d] fail has error. tsr1[%02X] tsr0[%02X]\n",
935 (int)idx, byTsr1, byTsr0);
936 }
937 }
938
939 vnt_int_report_rate(priv, desc->td_info, byTsr0, byTsr1);
940
941 device_free_tx_buf(priv, desc);
942 priv->iTDUsed[idx]--;
943 }
944 }
945
946 priv->apTailTD[idx] = desc;
947
948 return works;
949}
950
951static void device_error(struct vnt_private *priv, unsigned short status)
952{
953 if (status & ISR_FETALERR) {
954 dev_err(&priv->pcid->dev, "Hardware fatal error\n");
955
956 MACbShutdown(priv);
957 return;
958 }
959}
960
961static void device_free_tx_buf(struct vnt_private *priv,
962 struct vnt_tx_desc *desc)
963{
964 struct vnt_td_info *td_info = desc->td_info;
965 struct sk_buff *skb = td_info->skb;
966
967 if (skb)
968 ieee80211_tx_status_irqsafe(priv->hw, skb);
969
970 td_info->skb = NULL;
971 td_info->flags = 0;
972}
973
974static void vnt_check_bb_vga(struct vnt_private *priv)
975{
976 long dbm;
977 int i;
978
979 if (!priv->bUpdateBBVGA)
980 return;
981
982 if (priv->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
983 return;
984
985 if (!(priv->vif->bss_conf.assoc && priv->uCurrRSSI))
986 return;
987
988 RFvRSSITodBm(priv, (u8)priv->uCurrRSSI, &dbm);
989
990 for (i = 0; i < BB_VGA_LEVEL; i++) {
991 if (dbm < priv->ldBmThreshold[i]) {
992 priv->byBBVGANew = priv->abyBBVGA[i];
993 break;
994 }
995 }
996
997 if (priv->byBBVGANew == priv->byBBVGACurrent) {
998 priv->uBBVGADiffCount = 1;
999 return;
1000 }
1001
1002 priv->uBBVGADiffCount++;
1003
1004 if (priv->uBBVGADiffCount == 1) {
1005
1006 bb_set_vga_gain_offset(priv, priv->byBBVGANew);
1007
1008 dev_dbg(&priv->pcid->dev,
1009 "First RSSI[%d] NewGain[%d] OldGain[%d] Count[%d]\n",
1010 (int)dbm, priv->byBBVGANew,
1011 priv->byBBVGACurrent,
1012 (int)priv->uBBVGADiffCount);
1013 }
1014
1015 if (priv->uBBVGADiffCount >= BB_VGA_CHANGE_THRESHOLD) {
1016 dev_dbg(&priv->pcid->dev,
1017 "RSSI[%d] NewGain[%d] OldGain[%d] Count[%d]\n",
1018 (int)dbm, priv->byBBVGANew,
1019 priv->byBBVGACurrent,
1020 (int)priv->uBBVGADiffCount);
1021
1022 bb_set_vga_gain_offset(priv, priv->byBBVGANew);
1023 }
1024}
1025
1026static void vnt_interrupt_process(struct vnt_private *priv)
1027{
1028 struct ieee80211_low_level_stats *low_stats = &priv->low_stats;
1029 int max_count = 0;
1030 u32 mib_counter;
1031 u32 isr;
1032 unsigned long flags;
1033
1034 MACvReadISR(priv->PortOffset, &isr);
1035
1036 if (isr == 0)
1037 return;
1038
1039 if (isr == 0xffffffff) {
1040 pr_debug("isr = 0xffff\n");
1041 return;
1042 }
1043
1044 spin_lock_irqsave(&priv->lock, flags);
1045
1046
1047 MACvReadMIBCounter(priv->PortOffset, &mib_counter);
1048
1049 low_stats->dot11RTSSuccessCount += mib_counter & 0xff;
1050 low_stats->dot11RTSFailureCount += (mib_counter >> 8) & 0xff;
1051 low_stats->dot11ACKFailureCount += (mib_counter >> 16) & 0xff;
1052 low_stats->dot11FCSErrorCount += (mib_counter >> 24) & 0xff;
1053
1054
1055
1056
1057
1058
1059
1060 while (isr && priv->vif) {
1061 MACvWriteISR(priv->PortOffset, isr);
1062
1063 if (isr & ISR_FETALERR) {
1064 pr_debug(" ISR_FETALERR\n");
1065 VNSvOutPortB(priv->PortOffset + MAC_REG_SOFTPWRCTL, 0);
1066 VNSvOutPortW(priv->PortOffset +
1067 MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPECTI);
1068 device_error(priv, isr);
1069 }
1070
1071 if (isr & ISR_TBTT) {
1072 if (priv->op_mode != NL80211_IFTYPE_ADHOC)
1073 vnt_check_bb_vga(priv);
1074
1075 priv->bBeaconSent = false;
1076 if (priv->bEnablePSMode)
1077 PSbIsNextTBTTWakeUp((void *)priv);
1078
1079 if ((priv->op_mode == NL80211_IFTYPE_AP ||
1080 priv->op_mode == NL80211_IFTYPE_ADHOC) &&
1081 priv->vif->bss_conf.enable_beacon)
1082 MACvOneShotTimer1MicroSec(priv,
1083 (priv->vif->bss_conf.beacon_int -
1084 MAKE_BEACON_RESERVED) << 10);
1085
1086
1087 }
1088
1089 if (isr & ISR_BNTX) {
1090 if (priv->op_mode == NL80211_IFTYPE_ADHOC) {
1091 priv->bIsBeaconBufReadySet = false;
1092 priv->cbBeaconBufReadySetCnt = 0;
1093 }
1094
1095 priv->bBeaconSent = true;
1096 }
1097
1098 if (isr & ISR_RXDMA0)
1099 max_count += device_rx_srv(priv, TYPE_RXDMA0);
1100
1101 if (isr & ISR_RXDMA1)
1102 max_count += device_rx_srv(priv, TYPE_RXDMA1);
1103
1104 if (isr & ISR_TXDMA0)
1105 max_count += device_tx_srv(priv, TYPE_TXDMA0);
1106
1107 if (isr & ISR_AC0DMA)
1108 max_count += device_tx_srv(priv, TYPE_AC0DMA);
1109
1110 if (isr & ISR_SOFTTIMER1) {
1111 if (priv->vif->bss_conf.enable_beacon)
1112 vnt_beacon_make(priv, priv->vif);
1113 }
1114
1115
1116 if (AVAIL_TD(priv, TYPE_TXDMA0) &&
1117 AVAIL_TD(priv, TYPE_AC0DMA) &&
1118 ieee80211_queue_stopped(priv->hw, 0))
1119 ieee80211_wake_queues(priv->hw);
1120
1121 MACvReadISR(priv->PortOffset, &isr);
1122
1123 MACvReceive0(priv->PortOffset);
1124 MACvReceive1(priv->PortOffset);
1125
1126 if (max_count > priv->opts.int_works)
1127 break;
1128 }
1129
1130 spin_unlock_irqrestore(&priv->lock, flags);
1131}
1132
1133static void vnt_interrupt_work(struct work_struct *work)
1134{
1135 struct vnt_private *priv =
1136 container_of(work, struct vnt_private, interrupt_work);
1137
1138 if (priv->vif)
1139 vnt_interrupt_process(priv);
1140
1141 MACvIntEnable(priv->PortOffset, IMR_MASK_VALUE);
1142}
1143
1144static irqreturn_t vnt_interrupt(int irq, void *arg)
1145{
1146 struct vnt_private *priv = arg;
1147
1148 schedule_work(&priv->interrupt_work);
1149
1150 MACvIntDisable(priv->PortOffset);
1151
1152 return IRQ_HANDLED;
1153}
1154
1155static int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb)
1156{
1157 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1158 struct vnt_tx_desc *head_td;
1159 u32 dma_idx;
1160 unsigned long flags;
1161
1162 spin_lock_irqsave(&priv->lock, flags);
1163
1164 if (ieee80211_is_data(hdr->frame_control))
1165 dma_idx = TYPE_AC0DMA;
1166 else
1167 dma_idx = TYPE_TXDMA0;
1168
1169 if (AVAIL_TD(priv, dma_idx) < 1) {
1170 spin_unlock_irqrestore(&priv->lock, flags);
1171 ieee80211_stop_queues(priv->hw);
1172 return -ENOMEM;
1173 }
1174
1175 head_td = priv->apCurrTD[dma_idx];
1176
1177 head_td->td1.tcr = 0;
1178
1179 head_td->td_info->skb = skb;
1180
1181 if (dma_idx == TYPE_AC0DMA)
1182 head_td->td_info->flags = TD_FLAGS_NETIF_SKB;
1183
1184 priv->apCurrTD[dma_idx] = head_td->next;
1185
1186 spin_unlock_irqrestore(&priv->lock, flags);
1187
1188 vnt_generate_fifo_header(priv, dma_idx, head_td, skb);
1189
1190 spin_lock_irqsave(&priv->lock, flags);
1191
1192 priv->bPWBitOn = false;
1193
1194
1195 head_td->td1.tcr |= (TCR_STP | TCR_EDP | EDMSDU);
1196 head_td->td1.req_count = cpu_to_le16(head_td->td_info->req_count);
1197
1198 head_td->buff_addr = cpu_to_le32(head_td->td_info->buf_dma);
1199
1200
1201 wmb();
1202 head_td->td0.owner = OWNED_BY_NIC;
1203 wmb();
1204
1205 if (head_td->td_info->flags & TD_FLAGS_NETIF_SKB)
1206 MACvTransmitAC0(priv->PortOffset);
1207 else
1208 MACvTransmit0(priv->PortOffset);
1209
1210 priv->iTDUsed[dma_idx]++;
1211
1212 spin_unlock_irqrestore(&priv->lock, flags);
1213
1214 return 0;
1215}
1216
1217static void vnt_tx_80211(struct ieee80211_hw *hw,
1218 struct ieee80211_tx_control *control,
1219 struct sk_buff *skb)
1220{
1221 struct vnt_private *priv = hw->priv;
1222
1223 if (vnt_tx_packet(priv, skb))
1224 ieee80211_free_txskb(hw, skb);
1225}
1226
1227static int vnt_start(struct ieee80211_hw *hw)
1228{
1229 struct vnt_private *priv = hw->priv;
1230 int ret;
1231
1232 priv->rx_buf_sz = PKT_BUF_SZ;
1233 if (!device_init_rings(priv))
1234 return -ENOMEM;
1235
1236 ret = request_irq(priv->pcid->irq, vnt_interrupt,
1237 IRQF_SHARED, "vt6655", priv);
1238 if (ret) {
1239 dev_dbg(&priv->pcid->dev, "failed to start irq\n");
1240 goto err_free_rings;
1241 }
1242
1243 dev_dbg(&priv->pcid->dev, "call device init rd0 ring\n");
1244 ret = device_init_rd0_ring(priv);
1245 if (ret)
1246 goto err_free_irq;
1247 ret = device_init_rd1_ring(priv);
1248 if (ret)
1249 goto err_free_rd0_ring;
1250 ret = device_init_td0_ring(priv);
1251 if (ret)
1252 goto err_free_rd1_ring;
1253 ret = device_init_td1_ring(priv);
1254 if (ret)
1255 goto err_free_td0_ring;
1256
1257 device_init_registers(priv);
1258
1259 dev_dbg(&priv->pcid->dev, "call MACvIntEnable\n");
1260 MACvIntEnable(priv->PortOffset, IMR_MASK_VALUE);
1261
1262 ieee80211_wake_queues(hw);
1263
1264 return 0;
1265
1266err_free_td0_ring:
1267 device_free_td0_ring(priv);
1268err_free_rd1_ring:
1269 device_free_rd1_ring(priv);
1270err_free_rd0_ring:
1271 device_free_rd0_ring(priv);
1272err_free_irq:
1273 free_irq(priv->pcid->irq, priv);
1274err_free_rings:
1275 device_free_rings(priv);
1276 return ret;
1277}
1278
1279static void vnt_stop(struct ieee80211_hw *hw)
1280{
1281 struct vnt_private *priv = hw->priv;
1282
1283 ieee80211_stop_queues(hw);
1284
1285 cancel_work_sync(&priv->interrupt_work);
1286
1287 MACbShutdown(priv);
1288 MACbSoftwareReset(priv);
1289 CARDbRadioPowerOff(priv);
1290
1291 device_free_td0_ring(priv);
1292 device_free_td1_ring(priv);
1293 device_free_rd0_ring(priv);
1294 device_free_rd1_ring(priv);
1295 device_free_rings(priv);
1296
1297 free_irq(priv->pcid->irq, priv);
1298}
1299
1300static int vnt_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1301{
1302 struct vnt_private *priv = hw->priv;
1303
1304 priv->vif = vif;
1305
1306 switch (vif->type) {
1307 case NL80211_IFTYPE_STATION:
1308 break;
1309 case NL80211_IFTYPE_ADHOC:
1310 MACvRegBitsOff(priv->PortOffset, MAC_REG_RCR, RCR_UNICAST);
1311
1312 MACvRegBitsOn(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_ADHOC);
1313
1314 break;
1315 case NL80211_IFTYPE_AP:
1316 MACvRegBitsOff(priv->PortOffset, MAC_REG_RCR, RCR_UNICAST);
1317
1318 MACvRegBitsOn(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_AP);
1319
1320 break;
1321 default:
1322 return -EOPNOTSUPP;
1323 }
1324
1325 priv->op_mode = vif->type;
1326
1327 return 0;
1328}
1329
1330static void vnt_remove_interface(struct ieee80211_hw *hw,
1331 struct ieee80211_vif *vif)
1332{
1333 struct vnt_private *priv = hw->priv;
1334
1335 switch (vif->type) {
1336 case NL80211_IFTYPE_STATION:
1337 break;
1338 case NL80211_IFTYPE_ADHOC:
1339 MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR, TCR_AUTOBCNTX);
1340 MACvRegBitsOff(priv->PortOffset,
1341 MAC_REG_TFTCTL, TFTCTL_TSFCNTREN);
1342 MACvRegBitsOff(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_ADHOC);
1343 break;
1344 case NL80211_IFTYPE_AP:
1345 MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR, TCR_AUTOBCNTX);
1346 MACvRegBitsOff(priv->PortOffset,
1347 MAC_REG_TFTCTL, TFTCTL_TSFCNTREN);
1348 MACvRegBitsOff(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_AP);
1349 break;
1350 default:
1351 break;
1352 }
1353
1354 priv->op_mode = NL80211_IFTYPE_UNSPECIFIED;
1355}
1356
1357static int vnt_config(struct ieee80211_hw *hw, u32 changed)
1358{
1359 struct vnt_private *priv = hw->priv;
1360 struct ieee80211_conf *conf = &hw->conf;
1361 u8 bb_type;
1362
1363 if (changed & IEEE80211_CONF_CHANGE_PS) {
1364 if (conf->flags & IEEE80211_CONF_PS)
1365 PSvEnablePowerSaving(priv, conf->listen_interval);
1366 else
1367 PSvDisablePowerSaving(priv);
1368 }
1369
1370 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) ||
1371 (conf->flags & IEEE80211_CONF_OFFCHANNEL)) {
1372 set_channel(priv, conf->chandef.chan);
1373
1374 if (conf->chandef.chan->band == NL80211_BAND_5GHZ)
1375 bb_type = BB_TYPE_11A;
1376 else
1377 bb_type = BB_TYPE_11G;
1378
1379 if (priv->byBBType != bb_type) {
1380 priv->byBBType = bb_type;
1381
1382 CARDbSetPhyParameter(priv, priv->byBBType);
1383 }
1384 }
1385
1386 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1387 if (priv->byBBType == BB_TYPE_11B)
1388 priv->wCurrentRate = RATE_1M;
1389 else
1390 priv->wCurrentRate = RATE_54M;
1391
1392 RFbSetPower(priv, priv->wCurrentRate,
1393 conf->chandef.chan->hw_value);
1394 }
1395
1396 return 0;
1397}
1398
1399static void vnt_bss_info_changed(struct ieee80211_hw *hw,
1400 struct ieee80211_vif *vif,
1401 struct ieee80211_bss_conf *conf, u32 changed)
1402{
1403 struct vnt_private *priv = hw->priv;
1404
1405 priv->current_aid = conf->aid;
1406
1407 if (changed & BSS_CHANGED_BSSID && conf->bssid) {
1408 unsigned long flags;
1409
1410 spin_lock_irqsave(&priv->lock, flags);
1411
1412 MACvWriteBSSIDAddress(priv->PortOffset, (u8 *)conf->bssid);
1413
1414 spin_unlock_irqrestore(&priv->lock, flags);
1415 }
1416
1417 if (changed & BSS_CHANGED_BASIC_RATES) {
1418 priv->basic_rates = conf->basic_rates;
1419
1420 CARDvUpdateBasicTopRate(priv);
1421
1422 dev_dbg(&priv->pcid->dev,
1423 "basic rates %x\n", conf->basic_rates);
1424 }
1425
1426 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1427 if (conf->use_short_preamble) {
1428 MACvEnableBarkerPreambleMd(priv->PortOffset);
1429 priv->byPreambleType = true;
1430 } else {
1431 MACvDisableBarkerPreambleMd(priv->PortOffset);
1432 priv->byPreambleType = false;
1433 }
1434 }
1435
1436 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1437 if (conf->use_cts_prot)
1438 MACvEnableProtectMD(priv->PortOffset);
1439 else
1440 MACvDisableProtectMD(priv->PortOffset);
1441 }
1442
1443 if (changed & BSS_CHANGED_ERP_SLOT) {
1444 if (conf->use_short_slot)
1445 priv->bShortSlotTime = true;
1446 else
1447 priv->bShortSlotTime = false;
1448
1449 CARDbSetPhyParameter(priv, priv->byBBType);
1450 bb_set_vga_gain_offset(priv, priv->abyBBVGA[0]);
1451 }
1452
1453 if (changed & BSS_CHANGED_TXPOWER)
1454 RFbSetPower(priv, priv->wCurrentRate,
1455 conf->chandef.chan->hw_value);
1456
1457 if (changed & BSS_CHANGED_BEACON_ENABLED) {
1458 dev_dbg(&priv->pcid->dev,
1459 "Beacon enable %d\n", conf->enable_beacon);
1460
1461 if (conf->enable_beacon) {
1462 vnt_beacon_enable(priv, vif, conf);
1463
1464 MACvRegBitsOn(priv->PortOffset, MAC_REG_TCR,
1465 TCR_AUTOBCNTX);
1466 } else {
1467 MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR,
1468 TCR_AUTOBCNTX);
1469 }
1470 }
1471
1472 if (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INFO) &&
1473 priv->op_mode != NL80211_IFTYPE_AP) {
1474 if (conf->assoc && conf->beacon_rate) {
1475 CARDbUpdateTSF(priv, conf->beacon_rate->hw_value,
1476 conf->sync_tsf);
1477
1478 CARDbSetBeaconPeriod(priv, conf->beacon_int);
1479
1480 CARDvSetFirstNextTBTT(priv, conf->beacon_int);
1481 } else {
1482 VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL,
1483 TFTCTL_TSFCNTRST);
1484 VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL,
1485 TFTCTL_TSFCNTREN);
1486 }
1487 }
1488}
1489
1490static u64 vnt_prepare_multicast(struct ieee80211_hw *hw,
1491 struct netdev_hw_addr_list *mc_list)
1492{
1493 struct vnt_private *priv = hw->priv;
1494 struct netdev_hw_addr *ha;
1495 u64 mc_filter = 0;
1496 u32 bit_nr = 0;
1497
1498 netdev_hw_addr_list_for_each(ha, mc_list) {
1499 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1500
1501 mc_filter |= 1ULL << (bit_nr & 0x3f);
1502 }
1503
1504 priv->mc_list_count = mc_list->count;
1505
1506 return mc_filter;
1507}
1508
1509static void vnt_configure(struct ieee80211_hw *hw,
1510 unsigned int changed_flags,
1511 unsigned int *total_flags, u64 multicast)
1512{
1513 struct vnt_private *priv = hw->priv;
1514 u8 rx_mode = 0;
1515
1516 *total_flags &= FIF_ALLMULTI | FIF_OTHER_BSS | FIF_BCN_PRBRESP_PROMISC;
1517
1518 VNSvInPortB(priv->PortOffset + MAC_REG_RCR, &rx_mode);
1519
1520 dev_dbg(&priv->pcid->dev, "rx mode in = %x\n", rx_mode);
1521
1522 if (changed_flags & FIF_ALLMULTI) {
1523 if (*total_flags & FIF_ALLMULTI) {
1524 unsigned long flags;
1525
1526 spin_lock_irqsave(&priv->lock, flags);
1527
1528 if (priv->mc_list_count > 2) {
1529 MACvSelectPage1(priv->PortOffset);
1530
1531 VNSvOutPortD(priv->PortOffset +
1532 MAC_REG_MAR0, 0xffffffff);
1533 VNSvOutPortD(priv->PortOffset +
1534 MAC_REG_MAR0 + 4, 0xffffffff);
1535
1536 MACvSelectPage0(priv->PortOffset);
1537 } else {
1538 MACvSelectPage1(priv->PortOffset);
1539
1540 VNSvOutPortD(priv->PortOffset +
1541 MAC_REG_MAR0, (u32)multicast);
1542 VNSvOutPortD(priv->PortOffset +
1543 MAC_REG_MAR0 + 4,
1544 (u32)(multicast >> 32));
1545
1546 MACvSelectPage0(priv->PortOffset);
1547 }
1548
1549 spin_unlock_irqrestore(&priv->lock, flags);
1550
1551 rx_mode |= RCR_MULTICAST | RCR_BROADCAST;
1552 } else {
1553 rx_mode &= ~(RCR_MULTICAST | RCR_BROADCAST);
1554 }
1555 }
1556
1557 if (changed_flags & (FIF_OTHER_BSS | FIF_BCN_PRBRESP_PROMISC)) {
1558 rx_mode |= RCR_MULTICAST | RCR_BROADCAST;
1559
1560 if (*total_flags & (FIF_OTHER_BSS | FIF_BCN_PRBRESP_PROMISC))
1561 rx_mode &= ~RCR_BSSID;
1562 else
1563 rx_mode |= RCR_BSSID;
1564 }
1565
1566 VNSvOutPortB(priv->PortOffset + MAC_REG_RCR, rx_mode);
1567
1568 dev_dbg(&priv->pcid->dev, "rx mode out= %x\n", rx_mode);
1569}
1570
1571static int vnt_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
1572 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
1573 struct ieee80211_key_conf *key)
1574{
1575 struct vnt_private *priv = hw->priv;
1576
1577 switch (cmd) {
1578 case SET_KEY:
1579 if (vnt_set_keys(hw, sta, vif, key))
1580 return -EOPNOTSUPP;
1581 break;
1582 case DISABLE_KEY:
1583 if (test_bit(key->hw_key_idx, &priv->key_entry_inuse))
1584 clear_bit(key->hw_key_idx, &priv->key_entry_inuse);
1585 break;
1586 default:
1587 break;
1588 }
1589
1590 return 0;
1591}
1592
1593static int vnt_get_stats(struct ieee80211_hw *hw,
1594 struct ieee80211_low_level_stats *stats)
1595{
1596 struct vnt_private *priv = hw->priv;
1597
1598 memcpy(stats, &priv->low_stats, sizeof(*stats));
1599
1600 return 0;
1601}
1602
1603static u64 vnt_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1604{
1605 struct vnt_private *priv = hw->priv;
1606 u64 tsf;
1607
1608 CARDbGetCurrentTSF(priv, &tsf);
1609
1610 return tsf;
1611}
1612
1613static void vnt_set_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1614 u64 tsf)
1615{
1616 struct vnt_private *priv = hw->priv;
1617
1618 CARDvUpdateNextTBTT(priv, tsf, vif->bss_conf.beacon_int);
1619}
1620
1621static void vnt_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1622{
1623 struct vnt_private *priv = hw->priv;
1624
1625
1626 VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTRST);
1627}
1628
1629static const struct ieee80211_ops vnt_mac_ops = {
1630 .tx = vnt_tx_80211,
1631 .start = vnt_start,
1632 .stop = vnt_stop,
1633 .add_interface = vnt_add_interface,
1634 .remove_interface = vnt_remove_interface,
1635 .config = vnt_config,
1636 .bss_info_changed = vnt_bss_info_changed,
1637 .prepare_multicast = vnt_prepare_multicast,
1638 .configure_filter = vnt_configure,
1639 .set_key = vnt_set_key,
1640 .get_stats = vnt_get_stats,
1641 .get_tsf = vnt_get_tsf,
1642 .set_tsf = vnt_set_tsf,
1643 .reset_tsf = vnt_reset_tsf,
1644};
1645
1646static int vnt_init(struct vnt_private *priv)
1647{
1648 SET_IEEE80211_PERM_ADDR(priv->hw, priv->abyCurrentNetAddr);
1649
1650 vnt_init_bands(priv);
1651
1652 if (ieee80211_register_hw(priv->hw))
1653 return -ENODEV;
1654
1655 priv->mac_hw = true;
1656
1657 CARDbRadioPowerOff(priv);
1658
1659 return 0;
1660}
1661
1662static int
1663vt6655_probe(struct pci_dev *pcid, const struct pci_device_id *ent)
1664{
1665 struct vnt_private *priv;
1666 struct ieee80211_hw *hw;
1667 struct wiphy *wiphy;
1668 int rc;
1669
1670 dev_notice(&pcid->dev,
1671 "%s Ver. %s\n", DEVICE_FULL_DRV_NAM, DEVICE_VERSION);
1672
1673 dev_notice(&pcid->dev,
1674 "Copyright (c) 2003 VIA Networking Technologies, Inc.\n");
1675
1676 hw = ieee80211_alloc_hw(sizeof(*priv), &vnt_mac_ops);
1677 if (!hw) {
1678 dev_err(&pcid->dev, "could not register ieee80211_hw\n");
1679 return -ENOMEM;
1680 }
1681
1682 priv = hw->priv;
1683 priv->pcid = pcid;
1684
1685 spin_lock_init(&priv->lock);
1686
1687 priv->hw = hw;
1688
1689 SET_IEEE80211_DEV(priv->hw, &pcid->dev);
1690
1691 if (pci_enable_device(pcid)) {
1692 device_free_info(priv);
1693 return -ENODEV;
1694 }
1695
1696 dev_dbg(&pcid->dev,
1697 "Before get pci_info memaddr is %x\n", priv->memaddr);
1698
1699 pci_set_master(pcid);
1700
1701 priv->memaddr = pci_resource_start(pcid, 0);
1702 priv->ioaddr = pci_resource_start(pcid, 1);
1703 priv->PortOffset = ioremap(priv->memaddr & PCI_BASE_ADDRESS_MEM_MASK,
1704 256);
1705 if (!priv->PortOffset) {
1706 dev_err(&pcid->dev, ": Failed to IO remapping ..\n");
1707 device_free_info(priv);
1708 return -ENODEV;
1709 }
1710
1711 rc = pci_request_regions(pcid, DEVICE_NAME);
1712 if (rc) {
1713 dev_err(&pcid->dev, ": Failed to find PCI device\n");
1714 device_free_info(priv);
1715 return -ENODEV;
1716 }
1717
1718 if (dma_set_mask(&pcid->dev, DMA_BIT_MASK(32))) {
1719 dev_err(&pcid->dev, ": Failed to set dma 32 bit mask\n");
1720 device_free_info(priv);
1721 return -ENODEV;
1722 }
1723
1724 INIT_WORK(&priv->interrupt_work, vnt_interrupt_work);
1725
1726
1727 if (!MACbSoftwareReset(priv)) {
1728 dev_err(&pcid->dev, ": Failed to access MAC hardware..\n");
1729 device_free_info(priv);
1730 return -ENODEV;
1731 }
1732
1733 MACvInitialize(priv);
1734 MACvReadEtherAddress(priv->PortOffset, priv->abyCurrentNetAddr);
1735
1736
1737 priv->byRFType = SROMbyReadEmbedded(priv->PortOffset, EEP_OFS_RFTYPE);
1738 priv->byRFType &= RF_MASK;
1739
1740 dev_dbg(&pcid->dev, "RF Type = %x\n", priv->byRFType);
1741
1742 device_get_options(priv);
1743 device_set_options(priv);
1744
1745 wiphy = priv->hw->wiphy;
1746
1747 wiphy->frag_threshold = FRAG_THRESH_DEF;
1748 wiphy->rts_threshold = RTS_THRESH_DEF;
1749 wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1750 BIT(NL80211_IFTYPE_ADHOC) | BIT(NL80211_IFTYPE_AP);
1751
1752 ieee80211_hw_set(priv->hw, TIMING_BEACON_ONLY);
1753 ieee80211_hw_set(priv->hw, SIGNAL_DBM);
1754 ieee80211_hw_set(priv->hw, RX_INCLUDES_FCS);
1755 ieee80211_hw_set(priv->hw, REPORTS_TX_ACK_STATUS);
1756 ieee80211_hw_set(priv->hw, SUPPORTS_PS);
1757
1758 priv->hw->max_signal = 100;
1759
1760 if (vnt_init(priv)) {
1761 device_free_info(priv);
1762 return -ENODEV;
1763 }
1764
1765 device_print_info(priv);
1766 pci_set_drvdata(pcid, priv);
1767
1768 return 0;
1769}
1770
1771
1772
1773static int __maybe_unused vt6655_suspend(struct device *dev_d)
1774{
1775 struct vnt_private *priv = dev_get_drvdata(dev_d);
1776 unsigned long flags;
1777
1778 spin_lock_irqsave(&priv->lock, flags);
1779
1780 MACbShutdown(priv);
1781
1782 spin_unlock_irqrestore(&priv->lock, flags);
1783
1784 return 0;
1785}
1786
1787static int __maybe_unused vt6655_resume(struct device *dev_d)
1788{
1789 device_wakeup_disable(dev_d);
1790
1791 return 0;
1792}
1793
1794MODULE_DEVICE_TABLE(pci, vt6655_pci_id_table);
1795
1796static SIMPLE_DEV_PM_OPS(vt6655_pm_ops, vt6655_suspend, vt6655_resume);
1797
1798static struct pci_driver device_driver = {
1799 .name = DEVICE_NAME,
1800 .id_table = vt6655_pci_id_table,
1801 .probe = vt6655_probe,
1802 .remove = vt6655_remove,
1803 .driver.pm = &vt6655_pm_ops,
1804};
1805
1806module_pci_driver(device_driver);
1807
