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12#ifndef __LINUX_CDNSP_GADGET_H
13#define __LINUX_CDNSP_GADGET_H
14
15#include <linux/io-64-nonatomic-lo-hi.h>
16#include <linux/usb/gadget.h>
17#include <linux/irq.h>
18
19
20#define CDNSP_DEV_MAX_SLOTS 1
21
22#define CDNSP_EP0_SETUP_SIZE 512
23
24
25#define CDNSP_ENDPOINTS_NUM 31
26
27
28#define CDNSP_DEFAULT_BESL 0
29
30
31#define CDNSP_CMD_TIMEOUT (15 * 1000)
32
33
34#define CDNSP_MAX_HALT_USEC (16 * 1000)
35
36#define CDNSP_CTX_SIZE 2112
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53
54struct cdnsp_cap_regs {
55 __le32 hc_capbase;
56 __le32 hcs_params1;
57 __le32 hcs_params2;
58 __le32 hcs_params3;
59 __le32 hcc_params;
60 __le32 db_off;
61 __le32 run_regs_off;
62 __le32 hcc_params2;
63
64};
65
66
67
68#define HC_LENGTH(p) (((p) >> 00) & GENMASK(7, 0))
69
70#define HC_VERSION(p) (((p) >> 16) & GENMASK(15, 1))
71
72
73
74#define HCS_ENDPOINTS_MASK GENMASK(7, 0)
75#define HCS_ENDPOINTS(p) (((p) & HCS_ENDPOINTS_MASK) >> 0)
76
77
78#define HCC_PARAMS_OFFSET 0x10
79
80
81
82#define HCC_64BIT_ADDR(p) ((p) & BIT(0))
83
84#define HCC_64BYTE_CONTEXT(p) ((p) & BIT(2))
85
86#define HCC_MAX_PSA(p) ((((p) >> 12) & 0xf) + 1)
87
88#define HCC_EXT_CAPS(p) (((p) & GENMASK(31, 16)) >> 16)
89
90#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
91
92
93#define DBOFF_MASK GENMASK(31, 2)
94
95
96#define RTSOFF_MASK GENMASK(31, 5)
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115struct cdnsp_op_regs {
116 __le32 command;
117 __le32 status;
118 __le32 page_size;
119 __le32 reserved1;
120 __le32 reserved2;
121 __le32 dnctrl;
122 __le64 cmd_ring;
123
124 __le32 reserved3[4];
125 __le64 dcbaa_ptr;
126 __le32 config_reg;
127
128 __le32 reserved4[241];
129
130 __le32 port_reg_base;
131};
132
133
134#define NUM_PORT_REGS 4
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141
142struct cdnsp_port_regs {
143 __le32 portsc;
144 __le32 portpmsc;
145 __le32 portli;
146 __le32 reserved;
147};
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154
155#define CDNSP_PORT_RO (PORT_CONNECT | DEV_SPEED_MASK)
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160
161#define CDNSP_PORT_RWS (PORT_PLS_MASK | PORT_WKCONN_E | PORT_WKDISC_E)
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167
168#define CDNSP_PORT_RW1CS (PORT_PED | PORT_CSC | PORT_RC | PORT_PLC)
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171
172#define CMD_R_S BIT(0)
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176
177#define CMD_RESET BIT(1)
178
179#define CMD_INTE BIT(2)
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183
184#define CMD_DSEIE BIT(3)
185
186#define CMD_CSS BIT(8)
187#define CMD_CRS BIT(9)
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191
192#define CMD_EWE BIT(10)
193
194#define CMD_DEVEN BIT(17)
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197
198#define CDNSP_IRQS (CMD_INTE | CMD_DSEIE | CMD_EWE)
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201
202#define STS_HALT BIT(0)
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206
207#define STS_FATAL BIT(2)
208
209#define STS_EINT BIT(3)
210
211#define STS_PCD BIT(4)
212
213#define STS_SSS BIT(8)
214
215#define STS_RSS BIT(9)
216
217#define STS_SRE BIT(10)
218
219#define STS_CNR BIT(11)
220
221#define STS_HCE BIT(12)
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224
225#define CMD_RING_CS BIT(0)
226
227#define CMD_RING_ABORT BIT(2)
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233#define CMD_RING_BUSY(p) ((p) & BIT(4))
234
235#define CMD_RING_RUNNING BIT(3)
236
237#define CMD_RING_RSVD_BITS GENMASK(5, 0)
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241#define MAX_DEVS GENMASK(7, 0)
242
243#define CONFIG_U3E BIT(8)
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247#define PORT_CONNECT BIT(0)
248
249#define PORT_PED BIT(1)
250
251#define PORT_RESET BIT(4)
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256
257#define PORT_PLS_MASK GENMASK(8, 5)
258#define XDEV_U0 (0x0 << 5)
259#define XDEV_U1 (0x1 << 5)
260#define XDEV_U2 (0x2 << 5)
261#define XDEV_U3 (0x3 << 5)
262#define XDEV_DISABLED (0x4 << 5)
263#define XDEV_RXDETECT (0x5 << 5)
264#define XDEV_INACTIVE (0x6 << 5)
265#define XDEV_POLLING (0x7 << 5)
266#define XDEV_RECOVERY (0x8 << 5)
267#define XDEV_HOT_RESET (0x9 << 5)
268#define XDEV_COMP_MODE (0xa << 5)
269#define XDEV_TEST_MODE (0xb << 5)
270#define XDEV_RESUME (0xf << 5)
271
272#define PORT_POWER BIT(9)
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283#define DEV_SPEED_MASK GENMASK(13, 10)
284#define XDEV_FS (0x1 << 10)
285#define XDEV_HS (0x3 << 10)
286#define XDEV_SS (0x4 << 10)
287#define XDEV_SSP (0x5 << 10)
288#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0 << 10))
289#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
290#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
291#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
292#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
293#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
294#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
295
296#define PORT_LINK_STROBE BIT(16)
297
298#define PORT_CSC BIT(17)
299
300#define PORT_WRC BIT(19)
301
302#define PORT_RC BIT(21)
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317#define PORT_PLC BIT(22)
318
319#define PORT_CEC BIT(23)
320
321#define PORT_WKCONN_E BIT(25)
322
323#define PORT_WKDISC_E BIT(26)
324
325#define PORT_WR BIT(31)
326
327#define PORT_CHANGE_BITS (PORT_CSC | PORT_WRC | PORT_RC | PORT_PLC | PORT_CEC)
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331#define PORT_U1_TIMEOUT_MASK GENMASK(7, 0)
332#define PORT_U1_TIMEOUT(p) ((p) & PORT_U1_TIMEOUT_MASK)
333
334#define PORT_U2_TIMEOUT_MASK GENMASK(14, 8)
335#define PORT_U2_TIMEOUT(p) (((p) << 8) & PORT_U2_TIMEOUT_MASK)
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337
338#define PORT_L1S_MASK GENMASK(2, 0)
339#define PORT_L1S(p) ((p) & PORT_L1S_MASK)
340#define PORT_L1S_ACK PORT_L1S(1)
341#define PORT_L1S_NYET PORT_L1S(2)
342#define PORT_L1S_STALL PORT_L1S(3)
343#define PORT_L1S_TIMEOUT PORT_L1S(4)
344
345#define PORT_RWE BIT(3)
346
347#define PORT_BESL(p) (((p) << 4) & GENMASK(7, 4))
348
349#define PORT_HLE BIT(16)
350
351#define PORT_RRBESL(p) (((p) & GENMASK(20, 17)) >> 17)
352
353#define PORT_TEST_MODE_MASK GENMASK(31, 28)
354#define PORT_TEST_MODE(p) (((p) << 28) & PORT_TEST_MODE_MASK)
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373struct cdnsp_intr_reg {
374 __le32 irq_pending;
375 __le32 irq_control;
376 __le32 erst_size;
377 __le32 rsvd;
378 __le64 erst_base;
379 __le64 erst_dequeue;
380};
381
382
383#define IMAN_IE BIT(1)
384#define IMAN_IP BIT(0)
385
386#define IMAN_IE_SET(p) ((p) | IMAN_IE)
387#define IMAN_IE_CLEAR(p) ((p) & ~IMAN_IE)
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395#define IMOD_INTERVAL_MASK GENMASK(15, 0)
396
397#define IMOD_COUNTER_MASK GENMASK(31, 16)
398#define IMOD_DEFAULT_INTERVAL 0
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401
402#define ERST_SIZE_MASK GENMASK(31, 16)
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409#define ERST_DESI_MASK GENMASK(2, 0)
410
411#define ERST_EHB BIT(3)
412#define ERST_PTR_MASK GENMASK(3, 0)
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423struct cdnsp_run_regs {
424 __le32 microframe_index;
425 __le32 rsvd[7];
426 struct cdnsp_intr_reg ir_set[128];
427};
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439struct cdnsp_20port_cap {
440 __le32 ext_cap;
441 __le32 port_reg1;
442 __le32 port_reg2;
443 __le32 port_reg3;
444 __le32 port_reg4;
445 __le32 port_reg5;
446 __le32 port_reg6;
447};
448
449
450#define EXT_CAPS_ID(p) (((p) >> 0) & GENMASK(7, 0))
451#define EXT_CAPS_NEXT(p) (((p) >> 8) & GENMASK(7, 0))
452
453#define EXT_CAPS_PROTOCOL 2
454
455
456#define EXT_CAP_CFG_DEV_20PORT_CAP_ID 0xC1
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460
461#define PORT_REG6_L1_L0_HW_EN BIT(1)
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466#define PORT_REG6_FORCE_FS BIT(0)
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473
474struct cdnsp_3xport_cap {
475 __le32 ext_cap;
476 __le32 mode_addr;
477 __le32 reserved[52];
478 __le32 mode_2;
479};
480
481
482#define D_XEC_CFG_3XPORT_CAP 0xC0
483#define CFG_3XPORT_SSP_SUPPORT BIT(31)
484#define CFG_3XPORT_U1_PIPE_CLK_GATE_EN BIT(0)
485
486
487#define RTL_REV_CAP 0xC4
488#define RTL_REV_CAP_RX_BUFF_CMD_SIZE BITMASK(31, 24)
489#define RTL_REV_CAP_RX_BUFF_SIZE BITMASK(15, 0)
490#define RTL_REV_CAP_TX_BUFF_CMD_SIZE BITMASK(31, 24)
491#define RTL_REV_CAP_TX_BUFF_SIZE BITMASK(15, 0)
492
493#define CDNSP_VER_1 0x00000000
494#define CDNSP_VER_2 0x10000000
495
496#define CDNSP_IF_EP_EXIST(pdev, ep_num, dir) \
497 (readl(&(pdev)->rev_cap->ep_supported) & \
498 (BIT(ep_num) << ((dir) ? 0 : 16)))
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509struct cdnsp_rev_cap {
510 __le32 ext_cap;
511 __le32 rtl_revision;
512 __le32 rx_buff_size;
513 __le32 tx_buff_size;
514 __le32 ep_supported;
515 __le32 ctrl_revision;
516};
517
518
519#define D_XEC_PRE_REGS_CAP 0xC8
520#define REG_CHICKEN_BITS_2_OFFSET 0x48
521#define CHICKEN_XDMA_2_TP_CACHE_DIS BIT(28)
522
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524#define XBUF_CAP_ID 0xCB
525#define XBUF_RX_TAG_MASK_0_OFFSET 0x1C
526#define XBUF_RX_TAG_MASK_1_OFFSET 0x24
527#define XBUF_TX_CMD_OFFSET 0x2C
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537struct cdnsp_doorbell_array {
538 __le32 cmd_db;
539 __le32 ep_db;
540};
541
542#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
543#define DB_VALUE_EP0_OUT(ep, stream) ((ep) & 0xff)
544#define DB_VALUE_CMD 0x00000000
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557struct cdnsp_container_ctx {
558 unsigned int type;
559#define CDNSP_CTX_TYPE_DEVICE 0x1
560#define CDNSP_CTX_TYPE_INPUT 0x2
561 int size;
562 int ctx_size;
563 dma_addr_t dma;
564 u8 *bytes;
565};
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578struct cdnsp_slot_ctx {
579 __le32 dev_info;
580 __le32 dev_port;
581 __le32 int_target;
582 __le32 dev_state;
583
584 __le32 reserved[4];
585};
586
587
588#define SLOT_SPEED_FS (XDEV_FS << 10)
589#define SLOT_SPEED_HS (XDEV_HS << 10)
590#define SLOT_SPEED_SS (XDEV_SS << 10)
591#define SLOT_SPEED_SSP (XDEV_SSP << 10)
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595#define DEV_SPEED GENMASK(23, 20)
596#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
597
598#define LAST_CTX_MASK ((unsigned int)GENMASK(31, 27))
599#define LAST_CTX(p) ((p) << 27)
600#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
601#define SLOT_FLAG BIT(0)
602#define EP0_FLAG BIT(1)
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606#define DEV_PORT(p) (((p) & 0xff) << 16)
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609
610#define DEV_ADDR_MASK GENMASK(7, 0)
611
612#define SLOT_STATE GENMASK(31, 27)
613#define GET_SLOT_STATE(p) (((p) & SLOT_STATE) >> 27)
614
615#define SLOT_STATE_DISABLED 0
616#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
617#define SLOT_STATE_DEFAULT 1
618#define SLOT_STATE_ADDRESSED 2
619#define SLOT_STATE_CONFIGURED 3
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639struct cdnsp_ep_ctx {
640 __le32 ep_info;
641 __le32 ep_info2;
642 __le64 deq;
643 __le32 tx_info;
644
645 __le32 reserved[3];
646};
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658#define EP_STATE_MASK GENMASK(3, 0)
659#define EP_STATE_DISABLED 0
660#define EP_STATE_RUNNING 1
661#define EP_STATE_HALTED 2
662#define EP_STATE_STOPPED 3
663#define EP_STATE_ERROR 4
664#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
665
666
667#define EP_MULT(p) (((p) << 8) & GENMASK(9, 8))
668#define CTX_TO_EP_MULT(p) (((p) & GENMASK(9, 8)) >> 8)
669
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671
672#define EP_INTERVAL(p) (((p) << 16) & GENMASK(23, 16))
673#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) & GENMASK(23, 16)) >> 16))
674#define CTX_TO_EP_INTERVAL(p) (((p) & GENMASK(23, 16)) >> 16)
675#define EP_MAXPSTREAMS_MASK GENMASK(14, 10)
676#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
677#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
678
679#define EP_HAS_LSA BIT(15)
680
681
682#define ERROR_COUNT(p) (((p) & 0x3) << 1)
683#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
684#define EP_TYPE(p) ((p) << 3)
685#define ISOC_OUT_EP 1
686#define BULK_OUT_EP 2
687#define INT_OUT_EP 3
688#define CTRL_EP 4
689#define ISOC_IN_EP 5
690#define BULK_IN_EP 6
691#define INT_IN_EP 7
692
693
694#define MAX_BURST(p) (((p) << 8) & GENMASK(15, 8))
695#define CTX_TO_MAX_BURST(p) (((p) & GENMASK(15, 8)) >> 8)
696#define MAX_PACKET(p) (((p) << 16) & GENMASK(31, 16))
697#define MAX_PACKET_MASK GENMASK(31, 16)
698#define MAX_PACKET_DECODED(p) (((p) & GENMASK(31, 16)) >> 16)
699
700
701#define EP_AVG_TRB_LENGTH(p) ((p) & GENMASK(15, 0))
702#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) << 16) & GENMASK(31, 16))
703#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) & GENMASK(23, 16)) >> 16) << 24)
704#define CTX_TO_MAX_ESIT_PAYLOAD_LO(p) (((p) & GENMASK(31, 16)) >> 16)
705#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) & GENMASK(31, 24)) >> 24)
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707
708#define EP_CTX_CYCLE_MASK BIT(0)
709#define CTX_DEQ_MASK (~0xfL)
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718struct cdnsp_input_control_ctx {
719 __le32 drop_flags;
720 __le32 add_flags;
721 __le32 rsvd2[6];
722};
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731struct cdnsp_command {
732
733 struct cdnsp_container_ctx *in_ctx;
734 u32 status;
735 union cdnsp_trb *command_trb;
736};
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744struct cdnsp_stream_ctx {
745 __le64 stream_ring;
746 __le32 reserved[2];
747};
748
749
750#define SCT_FOR_CTX(p) (((p) << 1) & GENMASK(3, 1))
751
752#define SCT_SEC_TR 0
753
754#define SCT_PRI_TR 1
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772struct cdnsp_stream_info {
773 struct cdnsp_ring **stream_rings;
774 unsigned int num_streams;
775 struct cdnsp_stream_ctx *stream_ctx_array;
776 unsigned int num_stream_ctxs;
777 dma_addr_t ctx_array_dma;
778 struct radix_tree_root trb_address_map;
779 int td_count;
780 u8 first_prime_det;
781#define STREAM_DRBL_FIFO_DEPTH 2
782 u8 drbls_count;
783};
784
785#define STREAM_LOG_STREAMS 4
786#define STREAM_NUM_STREAMS BIT(STREAM_LOG_STREAMS)
787
788#if STREAM_LOG_STREAMS > 16 && STREAM_LOG_STREAMS < 1
789#error "Not suupported stream value"
790#endif
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815struct cdnsp_ep {
816 struct usb_ep endpoint;
817 struct list_head pending_list;
818 struct cdnsp_device *pdev;
819 u8 number;
820 u8 idx;
821 u32 interval;
822 char name[20];
823 u8 direction;
824 u8 buffering;
825 u8 buffering_period;
826 struct cdnsp_ep_ctx *in_ctx;
827 struct cdnsp_ep_ctx *out_ctx;
828 struct cdnsp_ring *ring;
829 struct cdnsp_stream_info stream_info;
830 unsigned int ep_state;
831#define EP_ENABLED BIT(0)
832#define EP_DIS_IN_RROGRESS BIT(1)
833#define EP_HALTED BIT(2)
834#define EP_STOPPED BIT(3)
835#define EP_WEDGE BIT(4)
836#define EP0_HALTED_STATUS BIT(5)
837#define EP_HAS_STREAMS BIT(6)
838#define EP_UNCONFIGURED BIT(7)
839
840 bool skip;
841};
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847
848struct cdnsp_device_context_array {
849 __le64 dev_context_ptrs[CDNSP_DEV_MAX_SLOTS + 1];
850 dma_addr_t dma;
851};
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859struct cdnsp_transfer_event {
860 __le64 buffer;
861 __le32 transfer_len;
862 __le32 flags;
863};
864
865
866#define TRB_EVENT_INVALIDATE 8
867
868
869
870#define EVENT_TRB_LEN(p) ((p) & GENMASK(23, 0))
871
872#define COMP_CODE_MASK (0xff << 24)
873#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
874#define COMP_INVALID 0
875#define COMP_SUCCESS 1
876#define COMP_DATA_BUFFER_ERROR 2
877#define COMP_BABBLE_DETECTED_ERROR 3
878#define COMP_TRB_ERROR 5
879#define COMP_RESOURCE_ERROR 7
880#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
881#define COMP_INVALID_STREAM_TYPE_ERROR 10
882#define COMP_SLOT_NOT_ENABLED_ERROR 11
883#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
884#define COMP_SHORT_PACKET 13
885#define COMP_RING_UNDERRUN 14
886#define COMP_RING_OVERRUN 15
887#define COMP_VF_EVENT_RING_FULL_ERROR 16
888#define COMP_PARAMETER_ERROR 17
889#define COMP_CONTEXT_STATE_ERROR 19
890#define COMP_EVENT_RING_FULL_ERROR 21
891#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
892#define COMP_MISSED_SERVICE_ERROR 23
893#define COMP_COMMAND_RING_STOPPED 24
894#define COMP_COMMAND_ABORTED 25
895#define COMP_STOPPED 26
896#define COMP_STOPPED_LENGTH_INVALID 27
897#define COMP_STOPPED_SHORT_PACKET 28
898#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
899#define COMP_ISOCH_BUFFER_OVERRUN 31
900#define COMP_EVENT_LOST_ERROR 32
901#define COMP_UNDEFINED_ERROR 33
902#define COMP_INVALID_STREAM_ID_ERROR 34
903
904
905#define TRB_TO_DEV_STREAM(p) ((p) & GENMASK(16, 0))
906#define TRB_TO_HOST_STREAM(p) ((p) & GENMASK(16, 0))
907#define STREAM_PRIME_ACK 0xFFFE
908#define STREAM_REJECTED 0xFFFF
909
910
911#define TRB_TO_EP_ID(p) (((p) & GENMASK(20, 16)) >> 16)
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919struct cdnsp_link_trb {
920 __le64 segment_ptr;
921 __le32 intr_target;
922 __le32 control;
923};
924
925
926#define LINK_TOGGLE BIT(1)
927
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930
931
932
933
934struct cdnsp_event_cmd {
935 __le64 cmd_trb;
936 __le32 status;
937 __le32 flags;
938};
939
940
941
942
943#define TRB_BSR BIT(9)
944
945
946#define TRB_DC BIT(9)
947
948
949#define TRB_FH_TO_PACKET_TYPE(p) ((p) & GENMASK(4, 0))
950#define TRB_FH_TR_PACKET 0x4
951#define TRB_FH_TO_DEVICE_ADDRESS(p) (((p) << 25) & GENMASK(31, 25))
952#define TRB_FH_TR_PACKET_DEV_NOT 0x6
953#define TRB_FH_TO_NOT_TYPE(p) (((p) << 4) & GENMASK(7, 4))
954#define TRB_FH_TR_PACKET_FUNCTION_WAKE 0x1
955#define TRB_FH_TO_INTERFACE(p) (((p) << 8) & GENMASK(15, 8))
956
957enum cdnsp_setup_dev {
958 SETUP_CONTEXT_ONLY,
959 SETUP_CONTEXT_ADDRESS,
960};
961
962
963#define TRB_TO_SLOT_ID(p) (((p) & GENMASK(31, 24)) >> 24)
964#define SLOT_ID_FOR_TRB(p) (((p) << 24) & GENMASK(31, 24))
965
966
967#define TRB_TO_EP_INDEX(p) (((p) >> 16) & 0x1f)
968
969#define EP_ID_FOR_TRB(p) ((((p) + 1) << 16) & GENMASK(20, 16))
970
971#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
972#define TRB_TO_SUSPEND_PORT(p) (((p) >> 23) & 0x1)
973#define LAST_EP_INDEX 30
974
975
976#define TRB_TO_STREAM_ID(p) ((((p) & GENMASK(31, 16)) >> 16))
977#define STREAM_ID_FOR_TRB(p) ((((p)) << 16) & GENMASK(31, 16))
978#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
979
980
981#define TRB_TC BIT(1)
982
983
984
985#define GET_PORT_ID(p) (((p) & GENMASK(31, 24)) >> 24)
986#define SET_PORT_ID(p) (((p) << 24) & GENMASK(31, 24))
987#define EVENT_DATA BIT(2)
988
989
990
991#define TRB_LEN(p) ((p) & GENMASK(16, 0))
992
993#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
994#define GET_TD_SIZE(p) (((p) & GENMASK(21, 17)) >> 17)
995
996
997
998
999#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1000
1001#define TRB_INTR_TARGET(p) (((p) << 22) & GENMASK(31, 22))
1002#define GET_INTR_TARGET(p) (((p) & GENMASK(31, 22)) >> 22)
1003
1004
1005
1006
1007#define TRB_TBC(p) (((p) & 0x3) << 7)
1008#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1009
1010
1011#define TRB_CYCLE BIT(0)
1012
1013
1014
1015
1016#define TRB_ENT BIT(1)
1017
1018#define TRB_ISP BIT(2)
1019
1020#define TRB_NO_SNOOP BIT(3)
1021
1022#define TRB_CHAIN BIT(4)
1023
1024#define TRB_IOC BIT(5)
1025
1026#define TRB_IDT BIT(6)
1027
1028#define TRB_STAT BIT(7)
1029
1030#define TRB_BEI BIT(9)
1031
1032
1033#define TRB_DIR_IN BIT(16)
1034
1035
1036#define TRB_SETUPID_BITMASK GENMASK(9, 8)
1037#define TRB_SETUPID(p) ((p) << 8)
1038#define TRB_SETUPID_TO_TYPE(p) (((p) & TRB_SETUPID_BITMASK) >> 8)
1039
1040#define TRB_SETUP_SPEEDID_USB3 0x1
1041#define TRB_SETUP_SPEEDID_USB2 0x0
1042#define TRB_SETUP_SPEEDID(p) ((p) & (1 << 7))
1043
1044#define TRB_SETUPSTAT_ACK 0x1
1045#define TRB_SETUPSTAT_STALL 0x0
1046#define TRB_SETUPSTAT(p) ((p) << 6)
1047
1048
1049#define TRB_SIA BIT(31)
1050#define TRB_FRAME_ID(p) (((p) << 20) & GENMASK(30, 20))
1051
1052struct cdnsp_generic_trb {
1053 __le32 field[4];
1054};
1055
1056union cdnsp_trb {
1057 struct cdnsp_link_trb link;
1058 struct cdnsp_transfer_event trans_event;
1059 struct cdnsp_event_cmd event_cmd;
1060 struct cdnsp_generic_trb generic;
1061};
1062
1063
1064#define TRB_TYPE_BITMASK GENMASK(15, 10)
1065#define TRB_TYPE(p) ((p) << 10)
1066#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1067
1068
1069
1070#define TRB_NORMAL 1
1071
1072#define TRB_SETUP 2
1073
1074#define TRB_DATA 3
1075
1076#define TRB_STATUS 4
1077
1078#define TRB_ISOC 5
1079
1080#define TRB_LINK 6
1081#define TRB_EVENT_DATA 7
1082
1083#define TRB_TR_NOOP 8
1084
1085
1086
1087#define TRB_ENABLE_SLOT 9
1088
1089#define TRB_DISABLE_SLOT 10
1090
1091#define TRB_ADDR_DEV 11
1092
1093#define TRB_CONFIG_EP 12
1094
1095#define TRB_EVAL_CONTEXT 13
1096
1097#define TRB_RESET_EP 14
1098
1099#define TRB_STOP_RING 15
1100
1101#define TRB_SET_DEQ 16
1102
1103#define TRB_RESET_DEV 17
1104
1105#define TRB_FORCE_EVENT 18
1106
1107#define TRB_FORCE_HEADER 22
1108
1109#define TRB_CMD_NOOP 23
1110
1111
1112
1113
1114#define TRB_TRANSFER 32
1115
1116#define TRB_COMPLETION 33
1117
1118#define TRB_PORT_STATUS 34
1119
1120#define TRB_HC_EVENT 37
1121
1122#define TRB_MFINDEX_WRAP 39
1123
1124
1125#define TRB_ENDPOINT_NRDY 48
1126
1127
1128#define TRB_HALT_ENDPOINT 54
1129
1130#define TRB_DRB_OVERFLOW 57
1131
1132#define TRB_FLUSH_ENDPOINT 58
1133
1134#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1135#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1136 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1137#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1138 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1139
1140
1141
1142
1143
1144#define TRBS_PER_SEGMENT 256
1145#define TRBS_PER_EVENT_SEGMENT 256
1146#define TRBS_PER_EV_DEQ_UPDATE 100
1147#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT * 16)
1148#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1149
1150#define TRB_MAX_BUFF_SHIFT 16
1151#define TRB_MAX_BUFF_SIZE BIT(TRB_MAX_BUFF_SHIFT)
1152
1153#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1154 ((addr) & (TRB_MAX_BUFF_SIZE - 1)))
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166struct cdnsp_segment {
1167 union cdnsp_trb *trbs;
1168 struct cdnsp_segment *next;
1169 dma_addr_t dma;
1170
1171 dma_addr_t bounce_dma;
1172 void *bounce_buf;
1173 unsigned int bounce_offs;
1174 unsigned int bounce_len;
1175};
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189struct cdnsp_td {
1190 struct list_head td_list;
1191 struct cdnsp_request *preq;
1192 struct cdnsp_segment *start_seg;
1193 union cdnsp_trb *first_trb;
1194 union cdnsp_trb *last_trb;
1195 struct cdnsp_segment *bounce_seg;
1196 bool request_length_set;
1197 bool drbl;
1198};
1199
1200
1201
1202
1203
1204
1205
1206
1207struct cdnsp_dequeue_state {
1208 struct cdnsp_segment *new_deq_seg;
1209 union cdnsp_trb *new_deq_ptr;
1210 int new_cycle_state;
1211 unsigned int stream_id;
1212};
1213
1214enum cdnsp_ring_type {
1215 TYPE_CTRL = 0,
1216 TYPE_ISOC,
1217 TYPE_BULK,
1218 TYPE_INTR,
1219 TYPE_STREAM,
1220 TYPE_COMMAND,
1221 TYPE_EVENT,
1222};
1223
1224
1225
1226
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1228
1229
1230
1231
1232
1233
1234
1235
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1246
1247
1248
1249struct cdnsp_ring {
1250 struct cdnsp_segment *first_seg;
1251 struct cdnsp_segment *last_seg;
1252 union cdnsp_trb *enqueue;
1253 struct cdnsp_segment *enq_seg;
1254 union cdnsp_trb *dequeue;
1255 struct cdnsp_segment *deq_seg;
1256 struct list_head td_list;
1257 u32 cycle_state;
1258 unsigned int stream_id;
1259 unsigned int stream_active;
1260 unsigned int stream_rejected;
1261 int num_tds;
1262 unsigned int num_segs;
1263 unsigned int num_trbs_free;
1264 unsigned int bounce_buf_len;
1265 enum cdnsp_ring_type type;
1266 bool last_td_was_short;
1267 struct radix_tree_root *trb_address_map;
1268};
1269
1270
1271
1272
1273
1274
1275struct cdnsp_erst_entry {
1276 __le64 seg_addr;
1277 __le32 seg_size;
1278
1279 __le32 rsvd;
1280};
1281
1282
1283
1284
1285
1286
1287
1288struct cdnsp_erst {
1289 struct cdnsp_erst_entry *entries;
1290 unsigned int num_entries;
1291 dma_addr_t erst_dma_addr;
1292};
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304struct cdnsp_request {
1305 struct cdnsp_td td;
1306 struct usb_request request;
1307 struct list_head list;
1308 struct cdnsp_ep *pep;
1309 u8 epnum;
1310 unsigned direction:1;
1311};
1312
1313#define ERST_NUM_SEGS 1
1314
1315
1316enum cdnsp_ep0_stage {
1317 CDNSP_SETUP_STAGE,
1318 CDNSP_DATA_STAGE,
1319 CDNSP_STATUS_STAGE,
1320};
1321
1322
1323
1324
1325
1326
1327
1328
1329struct cdnsp_port {
1330 struct cdnsp_port_regs __iomem *regs;
1331 u8 port_num;
1332 u8 exist;
1333 u8 maj_rev;
1334 u8 min_rev;
1335};
1336
1337#define CDNSP_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
1338#define CDNSP_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
1339#define CDNSP_EXT_PORT_OFF(x) ((x) & 0xff)
1340#define CDNSP_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
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1359
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1364
1365
1366
1367
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1370
1371
1372
1373
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1375
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1379
1380
1381
1382
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1384
1385
1386
1387
1388
1389
1390
1391
1392struct cdnsp_device {
1393 struct device *dev;
1394 struct usb_gadget gadget;
1395 struct usb_gadget_driver *gadget_driver;
1396 unsigned int irq;
1397 void __iomem *regs;
1398
1399
1400 struct cdnsp_cap_regs __iomem *cap_regs;
1401 struct cdnsp_op_regs __iomem *op_regs;
1402 struct cdnsp_run_regs __iomem *run_regs;
1403 struct cdnsp_doorbell_array __iomem *dba;
1404 struct cdnsp_intr_reg __iomem *ir_set;
1405 struct cdnsp_20port_cap __iomem *port20_regs;
1406 struct cdnsp_3xport_cap __iomem *port3x_regs;
1407 struct cdnsp_rev_cap __iomem *rev_cap;
1408
1409
1410 __u32 hcs_params1;
1411 __u32 hcs_params3;
1412 __u32 hcc_params;
1413
1414 spinlock_t lock;
1415 struct usb_ctrlrequest setup;
1416 struct cdnsp_request ep0_preq;
1417 enum cdnsp_ep0_stage ep0_stage;
1418 u8 three_stage_setup;
1419 u8 ep0_expect_in;
1420 u8 setup_id;
1421 u8 setup_speed;
1422 void *setup_buf;
1423 u8 device_address;
1424 int may_wakeup;
1425 u16 hci_version;
1426
1427
1428 struct cdnsp_device_context_array *dcbaa;
1429 struct cdnsp_ring *cmd_ring;
1430 struct cdnsp_command cmd;
1431 struct cdnsp_ring *event_ring;
1432 struct cdnsp_erst erst;
1433 int slot_id;
1434
1435
1436
1437
1438
1439
1440
1441 struct cdnsp_container_ctx out_ctx;
1442 struct cdnsp_container_ctx in_ctx;
1443 struct cdnsp_ep eps[CDNSP_ENDPOINTS_NUM];
1444 u8 usb2_hw_lpm_capable:1;
1445 u8 u1_allowed:1;
1446 u8 u2_allowed:1;
1447
1448
1449 struct dma_pool *device_pool;
1450 struct dma_pool *segment_pool;
1451
1452#define CDNSP_STATE_HALTED BIT(1)
1453#define CDNSP_STATE_DYING BIT(2)
1454#define CDNSP_STATE_DISCONNECT_PENDING BIT(3)
1455#define CDNSP_WAKEUP_PENDING BIT(4)
1456 unsigned int cdnsp_state;
1457 unsigned int link_state;
1458
1459 struct cdnsp_port usb2_port;
1460 struct cdnsp_port usb3_port;
1461 struct cdnsp_port *active_port;
1462 u16 test_mode;
1463};
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473static inline u64 cdnsp_read_64(__le64 __iomem *regs)
1474{
1475 return lo_hi_readq(regs);
1476}
1477
1478static inline void cdnsp_write_64(const u64 val, __le64 __iomem *regs)
1479{
1480 lo_hi_writeq(val, regs);
1481}
1482
1483
1484void cdnsp_mem_cleanup(struct cdnsp_device *pdev);
1485int cdnsp_mem_init(struct cdnsp_device *pdev);
1486int cdnsp_setup_addressable_priv_dev(struct cdnsp_device *pdev);
1487void cdnsp_copy_ep0_dequeue_into_input_ctx(struct cdnsp_device *pdev);
1488void cdnsp_endpoint_zero(struct cdnsp_device *pdev, struct cdnsp_ep *ep);
1489int cdnsp_endpoint_init(struct cdnsp_device *pdev,
1490 struct cdnsp_ep *pep,
1491 gfp_t mem_flags);
1492int cdnsp_ring_expansion(struct cdnsp_device *pdev,
1493 struct cdnsp_ring *ring,
1494 unsigned int num_trbs, gfp_t flags);
1495struct cdnsp_ring *cdnsp_dma_to_transfer_ring(struct cdnsp_ep *ep, u64 address);
1496int cdnsp_alloc_stream_info(struct cdnsp_device *pdev,
1497 struct cdnsp_ep *pep,
1498 unsigned int num_stream_ctxs,
1499 unsigned int num_streams);
1500int cdnsp_alloc_streams(struct cdnsp_device *pdev, struct cdnsp_ep *pep);
1501void cdnsp_free_endpoint_rings(struct cdnsp_device *pdev, struct cdnsp_ep *pep);
1502
1503
1504int cdnsp_find_next_ext_cap(void __iomem *base, u32 start, int id);
1505int cdnsp_halt(struct cdnsp_device *pdev);
1506void cdnsp_died(struct cdnsp_device *pdev);
1507int cdnsp_reset(struct cdnsp_device *pdev);
1508irqreturn_t cdnsp_irq_handler(int irq, void *priv);
1509int cdnsp_setup_device(struct cdnsp_device *pdev, enum cdnsp_setup_dev setup);
1510void cdnsp_set_usb2_hardware_lpm(struct cdnsp_device *usbsssp_data,
1511 struct usb_request *req, int enable);
1512irqreturn_t cdnsp_thread_irq_handler(int irq, void *data);
1513
1514
1515dma_addr_t cdnsp_trb_virt_to_dma(struct cdnsp_segment *seg,
1516 union cdnsp_trb *trb);
1517bool cdnsp_last_trb_on_seg(struct cdnsp_segment *seg, union cdnsp_trb *trb);
1518bool cdnsp_last_trb_on_ring(struct cdnsp_ring *ring,
1519 struct cdnsp_segment *seg,
1520 union cdnsp_trb *trb);
1521int cdnsp_wait_for_cmd_compl(struct cdnsp_device *pdev);
1522void cdnsp_update_erst_dequeue(struct cdnsp_device *pdev,
1523 union cdnsp_trb *event_ring_deq,
1524 u8 clear_ehb);
1525void cdnsp_initialize_ring_info(struct cdnsp_ring *ring);
1526void cdnsp_ring_cmd_db(struct cdnsp_device *pdev);
1527void cdnsp_queue_slot_control(struct cdnsp_device *pdev, u32 trb_type);
1528void cdnsp_queue_address_device(struct cdnsp_device *pdev,
1529 dma_addr_t in_ctx_ptr,
1530 enum cdnsp_setup_dev setup);
1531void cdnsp_queue_stop_endpoint(struct cdnsp_device *pdev,
1532 unsigned int ep_index);
1533int cdnsp_queue_ctrl_tx(struct cdnsp_device *pdev, struct cdnsp_request *preq);
1534int cdnsp_queue_bulk_tx(struct cdnsp_device *pdev, struct cdnsp_request *preq);
1535int cdnsp_queue_isoc_tx_prepare(struct cdnsp_device *pdev,
1536 struct cdnsp_request *preq);
1537void cdnsp_queue_configure_endpoint(struct cdnsp_device *pdev,
1538 dma_addr_t in_ctx_ptr);
1539void cdnsp_queue_reset_ep(struct cdnsp_device *pdev, unsigned int ep_index);
1540void cdnsp_queue_halt_endpoint(struct cdnsp_device *pdev,
1541 unsigned int ep_index);
1542void cdnsp_queue_flush_endpoint(struct cdnsp_device *pdev,
1543 unsigned int ep_index);
1544void cdnsp_force_header_wakeup(struct cdnsp_device *pdev, int intf_num);
1545void cdnsp_queue_reset_device(struct cdnsp_device *pdev);
1546void cdnsp_queue_new_dequeue_state(struct cdnsp_device *pdev,
1547 struct cdnsp_ep *pep,
1548 struct cdnsp_dequeue_state *deq_state);
1549void cdnsp_ring_doorbell_for_active_rings(struct cdnsp_device *pdev,
1550 struct cdnsp_ep *pep);
1551void cdnsp_inc_deq(struct cdnsp_device *pdev, struct cdnsp_ring *ring);
1552void cdnsp_set_link_state(struct cdnsp_device *pdev,
1553 __le32 __iomem *port_regs, u32 link_state);
1554u32 cdnsp_port_state_to_neutral(u32 state);
1555
1556
1557int cdnsp_enable_slot(struct cdnsp_device *pdev);
1558int cdnsp_disable_slot(struct cdnsp_device *pdev);
1559struct cdnsp_input_control_ctx
1560 *cdnsp_get_input_control_ctx(struct cdnsp_container_ctx *ctx);
1561struct cdnsp_slot_ctx *cdnsp_get_slot_ctx(struct cdnsp_container_ctx *ctx);
1562struct cdnsp_ep_ctx *cdnsp_get_ep_ctx(struct cdnsp_container_ctx *ctx,
1563 unsigned int ep_index);
1564
1565void cdnsp_suspend_gadget(struct cdnsp_device *pdev);
1566void cdnsp_resume_gadget(struct cdnsp_device *pdev);
1567void cdnsp_disconnect_gadget(struct cdnsp_device *pdev);
1568void cdnsp_gadget_giveback(struct cdnsp_ep *pep, struct cdnsp_request *preq,
1569 int status);
1570int cdnsp_ep_enqueue(struct cdnsp_ep *pep, struct cdnsp_request *preq);
1571int cdnsp_ep_dequeue(struct cdnsp_ep *pep, struct cdnsp_request *preq);
1572unsigned int cdnsp_port_speed(unsigned int port_status);
1573void cdnsp_irq_reset(struct cdnsp_device *pdev);
1574int cdnsp_halt_endpoint(struct cdnsp_device *pdev,
1575 struct cdnsp_ep *pep, int value);
1576int cdnsp_cmd_stop_ep(struct cdnsp_device *pdev, struct cdnsp_ep *pep);
1577int cdnsp_cmd_flush_ep(struct cdnsp_device *pdev, struct cdnsp_ep *pep);
1578void cdnsp_setup_analyze(struct cdnsp_device *pdev);
1579int cdnsp_status_stage(struct cdnsp_device *pdev);
1580int cdnsp_reset_device(struct cdnsp_device *pdev);
1581
1582
1583
1584
1585
1586
1587
1588
1589static inline struct cdnsp_request *next_request(struct list_head *list)
1590{
1591 return list_first_entry_or_null(list, struct cdnsp_request, list);
1592}
1593
1594#define to_cdnsp_ep(ep) (container_of(ep, struct cdnsp_ep, endpoint))
1595#define gadget_to_cdnsp(g) (container_of(g, struct cdnsp_device, gadget))
1596#define request_to_cdnsp_request(r) (container_of(r, struct cdnsp_request, \
1597 request))
1598#define to_cdnsp_request(r) (container_of(r, struct cdnsp_request, request))
1599int cdnsp_remove_request(struct cdnsp_device *pdev, struct cdnsp_request *preq,
1600 struct cdnsp_ep *pep);
1601
1602#endif
1603