LXR linux/include/linux/hpet.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef __HPET__
   3#define __HPET__ 1
   4
   5#include <uapi/linux/hpet.h>
   6
   7
   8/*
   9 * Offsets into HPET Registers
  10 */
  11
  12struct hpet {
  13        u64 hpet_cap;           /* capabilities */
  14        u64 res0;               /* reserved */
  15        u64 hpet_config;        /* configuration */
  16        u64 res1;               /* reserved */
  17        u64 hpet_isr;           /* interrupt status reg */
  18        u64 res2[25];           /* reserved */
  19        union {                 /* main counter */
  20                u64 _hpet_mc64;
  21                u32 _hpet_mc32;
  22                unsigned long _hpet_mc;
  23        } _u0;
  24        u64 res3;               /* reserved */
  25        struct hpet_timer {
  26                u64 hpet_config;        /* configuration/cap */
  27                union {         /* timer compare register */
  28                        u64 _hpet_hc64;
  29                        u32 _hpet_hc32;
  30                        unsigned long _hpet_compare;
  31                } _u1;
  32                u64 hpet_fsb[2];        /* FSB route */
  33        } hpet_timers[1];
  34};
  35
  36#define hpet_mc         _u0._hpet_mc
  37#define hpet_compare    _u1._hpet_compare
  38
  39#define HPET_MAX_TIMERS (32)
  40#define HPET_MAX_IRQ    (32)
  41
  42/*
  43 * HPET general capabilities register
  44 */
  45
  46#define HPET_COUNTER_CLK_PERIOD_MASK    (0xffffffff00000000ULL)
  47#define HPET_COUNTER_CLK_PERIOD_SHIFT   (32UL)
  48#define HPET_VENDOR_ID_MASK             (0x00000000ffff0000ULL)
  49#define HPET_VENDOR_ID_SHIFT            (16ULL)
  50#define HPET_LEG_RT_CAP_MASK            (0x8000)
  51#define HPET_COUNTER_SIZE_MASK          (0x2000)
  52#define HPET_NUM_TIM_CAP_MASK           (0x1f00)
  53#define HPET_NUM_TIM_CAP_SHIFT          (8ULL)
  54
  55/*
  56 * HPET general configuration register
  57 */
  58
  59#define HPET_LEG_RT_CNF_MASK            (2UL)
  60#define HPET_ENABLE_CNF_MASK            (1UL)
  61
  62
  63/*
  64 * Timer configuration register
  65 */
  66
  67#define Tn_INT_ROUTE_CAP_MASK           (0xffffffff00000000ULL)
  68#define Tn_INT_ROUTE_CAP_SHIFT          (32UL)
  69#define Tn_FSB_INT_DELCAP_MASK          (0x8000UL)
  70#define Tn_FSB_INT_DELCAP_SHIFT         (15)
  71#define Tn_FSB_EN_CNF_MASK              (0x4000UL)
  72#define Tn_FSB_EN_CNF_SHIFT             (14)
  73#define Tn_INT_ROUTE_CNF_MASK           (0x3e00UL)
  74#define Tn_INT_ROUTE_CNF_SHIFT          (9)
  75#define Tn_32MODE_CNF_MASK              (0x0100UL)
  76#define Tn_VAL_SET_CNF_MASK             (0x0040UL)
  77#define Tn_SIZE_CAP_MASK                (0x0020UL)
  78#define Tn_PER_INT_CAP_MASK             (0x0010UL)
  79#define Tn_TYPE_CNF_MASK                (0x0008UL)
  80#define Tn_INT_ENB_CNF_MASK             (0x0004UL)
  81#define Tn_INT_TYPE_CNF_MASK            (0x0002UL)
  82
  83/*
  84 * Timer FSB Interrupt Route Register
  85 */
  86
  87#define Tn_FSB_INT_ADDR_MASK            (0xffffffff00000000ULL)
  88#define Tn_FSB_INT_ADDR_SHIFT           (32UL)
  89#define Tn_FSB_INT_VAL_MASK             (0x00000000ffffffffULL)
  90
  91/*
  92 * exported interfaces
  93 */
  94
  95struct hpet_data {
  96        unsigned long hd_phys_address;
  97        void __iomem *hd_address;
  98        unsigned short hd_nirqs;
  99        unsigned int hd_state;  /* timer allocated */
 100        unsigned int hd_irq[HPET_MAX_TIMERS];
 101};
 102
 103static inline void hpet_reserve_timer(struct hpet_data *hd, int timer)
 104{
 105        hd->hd_state |= (1 << timer);
 106        return;
 107}
 108
 109int hpet_alloc(struct hpet_data *);
 110
 111#endif                          /* !__HPET__ */
 112