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23#ifndef LINUX_PCI_H
24#define LINUX_PCI_H
25
26
27#include <linux/mod_devicetable.h>
28
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/ioport.h>
32#include <linux/list.h>
33#include <linux/compiler.h>
34#include <linux/errno.h>
35#include <linux/kobject.h>
36#include <linux/atomic.h>
37#include <linux/device.h>
38#include <linux/interrupt.h>
39#include <linux/io.h>
40#include <linux/resource_ext.h>
41#include <uapi/linux/pci.h>
42
43#include <linux/pci_ids.h>
44
45#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
50 PCI_STATUS_PARITY)
51
52
53
54
55
56
57
58
59
60
61
62
63
64#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
65
66#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
67
68
69struct pci_slot {
70 struct pci_bus *bus;
71 struct list_head list;
72 struct hotplug_slot *hotplug;
73 unsigned char number;
74 struct kobject kobj;
75};
76
77static inline const char *pci_slot_name(const struct pci_slot *slot)
78{
79 return kobject_name(&slot->kobj);
80}
81
82
83enum pci_mmap_state {
84 pci_mmap_io,
85 pci_mmap_mem
86};
87
88
89enum {
90
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
93
94
95 PCI_ROM_RESOURCE,
96
97
98#ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101#endif
102
103
104#define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
105#define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
106#define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
107
108
109#define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
110#define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
111#define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
112#define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
113
114
115#define PCI_BRIDGE_RESOURCE_NUM 4
116
117
118 PCI_BRIDGE_RESOURCES,
119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
120 PCI_BRIDGE_RESOURCE_NUM - 1,
121
122
123 PCI_NUM_RESOURCES,
124
125
126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
127};
128
129
130
131
132
133
134
135
136
137
138
139
140enum pci_interrupt_pin {
141 PCI_INTERRUPT_UNKNOWN,
142 PCI_INTERRUPT_INTA,
143 PCI_INTERRUPT_INTB,
144 PCI_INTERRUPT_INTC,
145 PCI_INTERRUPT_INTD,
146};
147
148
149#define PCI_NUM_INTX 4
150
151
152
153
154
155typedef int __bitwise pci_power_t;
156
157#define PCI_D0 ((pci_power_t __force) 0)
158#define PCI_D1 ((pci_power_t __force) 1)
159#define PCI_D2 ((pci_power_t __force) 2)
160#define PCI_D3hot ((pci_power_t __force) 3)
161#define PCI_D3cold ((pci_power_t __force) 4)
162#define PCI_UNKNOWN ((pci_power_t __force) 5)
163#define PCI_POWER_ERROR ((pci_power_t __force) -1)
164
165
166extern const char *pci_power_names[];
167
168static inline const char *pci_power_name(pci_power_t state)
169{
170 return pci_power_names[1 + (__force int) state];
171}
172
173
174
175
176
177
178
179
180typedef unsigned int __bitwise pci_channel_state_t;
181
182enum {
183
184 pci_channel_io_normal = (__force pci_channel_state_t) 1,
185
186
187 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
188
189
190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
191};
192
193typedef unsigned int __bitwise pcie_reset_state_t;
194
195enum pcie_reset_state {
196
197 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
198
199
200 pcie_warm_reset = (__force pcie_reset_state_t) 2,
201
202
203 pcie_hot_reset = (__force pcie_reset_state_t) 3
204};
205
206typedef unsigned short __bitwise pci_dev_flags_t;
207enum pci_dev_flags {
208
209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
210
211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
212
213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
214
215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
216
217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
218
219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
220
221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
222
223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
224
225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
226
227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
228
229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
230};
231
232enum pci_irq_reroute_variant {
233 INTEL_IRQ_REROUTE_VARIANT = 1,
234 MAX_IRQ_REROUTE_VARIANTS = 3
235};
236
237typedef unsigned short __bitwise pci_bus_flags_t;
238enum pci_bus_flags {
239 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
240 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
241 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
242 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
243};
244
245
246enum pcie_link_width {
247 PCIE_LNK_WIDTH_RESRV = 0x00,
248 PCIE_LNK_X1 = 0x01,
249 PCIE_LNK_X2 = 0x02,
250 PCIE_LNK_X4 = 0x04,
251 PCIE_LNK_X8 = 0x08,
252 PCIE_LNK_X12 = 0x0c,
253 PCIE_LNK_X16 = 0x10,
254 PCIE_LNK_X32 = 0x20,
255 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
256};
257
258
259enum pci_bus_speed {
260 PCI_SPEED_33MHz = 0x00,
261 PCI_SPEED_66MHz = 0x01,
262 PCI_SPEED_66MHz_PCIX = 0x02,
263 PCI_SPEED_100MHz_PCIX = 0x03,
264 PCI_SPEED_133MHz_PCIX = 0x04,
265 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
266 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
267 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
268 PCI_SPEED_66MHz_PCIX_266 = 0x09,
269 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
270 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
271 AGP_UNKNOWN = 0x0c,
272 AGP_1X = 0x0d,
273 AGP_2X = 0x0e,
274 AGP_4X = 0x0f,
275 AGP_8X = 0x10,
276 PCI_SPEED_66MHz_PCIX_533 = 0x11,
277 PCI_SPEED_100MHz_PCIX_533 = 0x12,
278 PCI_SPEED_133MHz_PCIX_533 = 0x13,
279 PCIE_SPEED_2_5GT = 0x14,
280 PCIE_SPEED_5_0GT = 0x15,
281 PCIE_SPEED_8_0GT = 0x16,
282 PCIE_SPEED_16_0GT = 0x17,
283 PCIE_SPEED_32_0GT = 0x18,
284 PCIE_SPEED_64_0GT = 0x19,
285 PCI_SPEED_UNKNOWN = 0xff,
286};
287
288enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
289enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
290
291struct pci_cap_saved_data {
292 u16 cap_nr;
293 bool cap_extended;
294 unsigned int size;
295 u32 data[];
296};
297
298struct pci_cap_saved_state {
299 struct hlist_node next;
300 struct pci_cap_saved_data cap;
301};
302
303struct irq_affinity;
304struct pcie_link_state;
305struct pci_vpd;
306struct pci_sriov;
307struct pci_p2pdma;
308struct rcec_ea;
309
310
311struct pci_dev {
312 struct list_head bus_list;
313 struct pci_bus *bus;
314 struct pci_bus *subordinate;
315
316 void *sysdata;
317 struct proc_dir_entry *procent;
318 struct pci_slot *slot;
319
320 unsigned int devfn;
321 unsigned short vendor;
322 unsigned short device;
323 unsigned short subsystem_vendor;
324 unsigned short subsystem_device;
325 unsigned int class;
326 u8 revision;
327 u8 hdr_type;
328#ifdef CONFIG_PCIEAER
329 u16 aer_cap;
330 struct aer_stats *aer_stats;
331#endif
332#ifdef CONFIG_PCIEPORTBUS
333 struct rcec_ea *rcec_ea;
334 struct pci_dev *rcec;
335#endif
336 u8 pcie_cap;
337 u8 msi_cap;
338 u8 msix_cap;
339 u8 pcie_mpss:3;
340 u8 rom_base_reg;
341 u8 pin;
342 u16 pcie_flags_reg;
343 unsigned long *dma_alias_mask;
344
345 struct pci_driver *driver;
346 u64 dma_mask;
347
348
349
350
351
352 struct device_dma_parameters dma_parms;
353
354 pci_power_t current_state;
355
356
357 unsigned int imm_ready:1;
358 u8 pm_cap;
359 unsigned int pme_support:5;
360
361 unsigned int pme_poll:1;
362 unsigned int d1_support:1;
363 unsigned int d2_support:1;
364 unsigned int no_d1d2:1;
365 unsigned int no_d3cold:1;
366 unsigned int bridge_d3:1;
367 unsigned int d3cold_allowed:1;
368 unsigned int mmio_always_on:1;
369
370 unsigned int wakeup_prepared:1;
371 unsigned int runtime_d3cold:1;
372
373
374
375 unsigned int skip_bus_pm:1;
376 unsigned int ignore_hotplug:1;
377 unsigned int hotplug_user_indicators:1;
378
379
380 unsigned int clear_retrain_link:1;
381
382 unsigned int d3hot_delay;
383 unsigned int d3cold_delay;
384
385#ifdef CONFIG_PCIEASPM
386 struct pcie_link_state *link_state;
387 unsigned int ltr_path:1;
388
389 u16 l1ss;
390#endif
391 unsigned int eetlp_prefix_path:1;
392
393 pci_channel_state_t error_state;
394 struct device dev;
395
396 int cfg_size;
397
398
399
400
401
402 unsigned int irq;
403 struct resource resource[DEVICE_COUNT_RESOURCE];
404
405 bool match_driver;
406
407 unsigned int transparent:1;
408 unsigned int io_window:1;
409 unsigned int pref_window:1;
410 unsigned int pref_64_window:1;
411 unsigned int multifunction:1;
412
413 unsigned int is_busmaster:1;
414 unsigned int no_msi:1;
415 unsigned int no_64bit_msi:1;
416 unsigned int block_cfg_access:1;
417 unsigned int broken_parity_status:1;
418 unsigned int irq_reroute_variant:2;
419 unsigned int msi_enabled:1;
420 unsigned int msix_enabled:1;
421 unsigned int ari_enabled:1;
422 unsigned int ats_enabled:1;
423 unsigned int pasid_enabled:1;
424 unsigned int pri_enabled:1;
425 unsigned int is_managed:1;
426 unsigned int needs_freset:1;
427 unsigned int state_saved:1;
428 unsigned int is_physfn:1;
429 unsigned int is_virtfn:1;
430 unsigned int reset_fn:1;
431 unsigned int is_hotplug_bridge:1;
432 unsigned int shpc_managed:1;
433 unsigned int is_thunderbolt:1;
434
435
436
437
438
439
440
441 unsigned int untrusted:1;
442
443
444
445
446
447 unsigned int external_facing:1;
448 unsigned int broken_intx_masking:1;
449 unsigned int io_window_1k:1;
450 unsigned int irq_managed:1;
451 unsigned int non_compliant_bars:1;
452 unsigned int is_probed:1;
453 unsigned int link_active_reporting:1;
454 unsigned int no_vf_scan:1;
455 unsigned int no_command_memory:1;
456 pci_dev_flags_t dev_flags;
457 atomic_t enable_cnt;
458
459 u32 saved_config_space[16];
460 struct hlist_head saved_cap_space;
461 int rom_attr_enabled;
462 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
463 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
464
465#ifdef CONFIG_HOTPLUG_PCI_PCIE
466 unsigned int broken_cmd_compl:1;
467#endif
468#ifdef CONFIG_PCIE_PTM
469 unsigned int ptm_root:1;
470 unsigned int ptm_enabled:1;
471 u8 ptm_granularity;
472#endif
473#ifdef CONFIG_PCI_MSI
474 const struct attribute_group **msi_irq_groups;
475#endif
476 struct pci_vpd *vpd;
477#ifdef CONFIG_PCIE_DPC
478 u16 dpc_cap;
479 unsigned int dpc_rp_extensions:1;
480 u8 dpc_rp_log_size;
481#endif
482#ifdef CONFIG_PCI_ATS
483 union {
484 struct pci_sriov *sriov;
485 struct pci_dev *physfn;
486 };
487 u16 ats_cap;
488 u8 ats_stu;
489#endif
490#ifdef CONFIG_PCI_PRI
491 u16 pri_cap;
492 u32 pri_reqs_alloc;
493 unsigned int pasid_required:1;
494#endif
495#ifdef CONFIG_PCI_PASID
496 u16 pasid_cap;
497 u16 pasid_features;
498#endif
499#ifdef CONFIG_PCI_P2PDMA
500 struct pci_p2pdma __rcu *p2pdma;
501#endif
502 u16 acs_cap;
503 phys_addr_t rom;
504 size_t romlen;
505 char *driver_override;
506
507 unsigned long priv_flags;
508};
509
510static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
511{
512#ifdef CONFIG_PCI_IOV
513 if (dev->is_virtfn)
514 dev = dev->physfn;
515#endif
516 return dev;
517}
518
519struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
520
521#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
522#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
523
524static inline int pci_channel_offline(struct pci_dev *pdev)
525{
526 return (pdev->error_state != pci_channel_io_normal);
527}
528
529struct pci_host_bridge {
530 struct device dev;
531 struct pci_bus *bus;
532 struct pci_ops *ops;
533 struct pci_ops *child_ops;
534 void *sysdata;
535 int busnr;
536 struct list_head windows;
537 struct list_head dma_ranges;
538 u8 (*swizzle_irq)(struct pci_dev *, u8 *);
539 int (*map_irq)(const struct pci_dev *, u8, u8);
540 void (*release_fn)(struct pci_host_bridge *);
541 void *release_data;
542 unsigned int ignore_reset_delay:1;
543 unsigned int no_ext_tags:1;
544 unsigned int native_aer:1;
545 unsigned int native_pcie_hotplug:1;
546 unsigned int native_shpc_hotplug:1;
547 unsigned int native_pme:1;
548 unsigned int native_ltr:1;
549 unsigned int native_dpc:1;
550 unsigned int preserve_config:1;
551 unsigned int size_windows:1;
552 unsigned int msi_domain:1;
553
554
555 resource_size_t (*align_resource)(struct pci_dev *dev,
556 const struct resource *res,
557 resource_size_t start,
558 resource_size_t size,
559 resource_size_t align);
560 unsigned long private[] ____cacheline_aligned;
561};
562
563#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
564
565static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
566{
567 return (void *)bridge->private;
568}
569
570static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
571{
572 return container_of(priv, struct pci_host_bridge, private);
573}
574
575struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
576struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
577 size_t priv);
578void pci_free_host_bridge(struct pci_host_bridge *bridge);
579struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
580
581void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
582 void (*release_fn)(struct pci_host_bridge *),
583 void *release_data);
584
585int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
586
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588
589
590
591
592
593
594
595
596
597
598
599
600#define PCI_SUBTRACTIVE_DECODE 0x1
601
602struct pci_bus_resource {
603 struct list_head list;
604 struct resource *res;
605 unsigned int flags;
606};
607
608#define PCI_REGION_FLAG_MASK 0x0fU
609
610struct pci_bus {
611 struct list_head node;
612 struct pci_bus *parent;
613 struct list_head children;
614 struct list_head devices;
615 struct pci_dev *self;
616 struct list_head slots;
617
618 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
619 struct list_head resources;
620 struct resource busn_res;
621
622 struct pci_ops *ops;
623 void *sysdata;
624 struct proc_dir_entry *procdir;
625
626 unsigned char number;
627 unsigned char primary;
628 unsigned char max_bus_speed;
629 unsigned char cur_bus_speed;
630#ifdef CONFIG_PCI_DOMAINS_GENERIC
631 int domain_nr;
632#endif
633
634 char name[48];
635
636 unsigned short bridge_ctl;
637 pci_bus_flags_t bus_flags;
638 struct device *bridge;
639 struct device dev;
640 struct bin_attribute *legacy_io;
641 struct bin_attribute *legacy_mem;
642 unsigned int is_added:1;
643};
644
645#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
646
647static inline u16 pci_dev_id(struct pci_dev *dev)
648{
649 return PCI_DEVID(dev->bus->number, dev->devfn);
650}
651
652
653
654
655
656
657
658
659
660static inline bool pci_is_root_bus(struct pci_bus *pbus)
661{
662 return !(pbus->parent);
663}
664
665
666
667
668
669
670
671
672static inline bool pci_is_bridge(struct pci_dev *dev)
673{
674 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
675 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
676}
677
678#define for_each_pci_bridge(dev, bus) \
679 list_for_each_entry(dev, &bus->devices, bus_list) \
680 if (!pci_is_bridge(dev)) {} else
681
682static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
683{
684 dev = pci_physfn(dev);
685 if (pci_is_root_bus(dev->bus))
686 return NULL;
687
688 return dev->bus->self;
689}
690
691#ifdef CONFIG_PCI_MSI
692static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
693{
694 return pci_dev->msi_enabled || pci_dev->msix_enabled;
695}
696#else
697static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
698#endif
699
700
701#define PCIBIOS_SUCCESSFUL 0x00
702#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
703#define PCIBIOS_BAD_VENDOR_ID 0x83
704#define PCIBIOS_DEVICE_NOT_FOUND 0x86
705#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
706#define PCIBIOS_SET_FAILED 0x88
707#define PCIBIOS_BUFFER_TOO_SMALL 0x89
708
709
710static inline int pcibios_err_to_errno(int err)
711{
712 if (err <= PCIBIOS_SUCCESSFUL)
713 return err;
714
715 switch (err) {
716 case PCIBIOS_FUNC_NOT_SUPPORTED:
717 return -ENOENT;
718 case PCIBIOS_BAD_VENDOR_ID:
719 return -ENOTTY;
720 case PCIBIOS_DEVICE_NOT_FOUND:
721 return -ENODEV;
722 case PCIBIOS_BAD_REGISTER_NUMBER:
723 return -EFAULT;
724 case PCIBIOS_SET_FAILED:
725 return -EIO;
726 case PCIBIOS_BUFFER_TOO_SMALL:
727 return -ENOSPC;
728 }
729
730 return -ERANGE;
731}
732
733
734
735struct pci_ops {
736 int (*add_bus)(struct pci_bus *bus);
737 void (*remove_bus)(struct pci_bus *bus);
738 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
739 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
740 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
741};
742
743
744
745
746
747int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
748 int reg, int len, u32 *val);
749int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
750 int reg, int len, u32 val);
751
752#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
753typedef u64 pci_bus_addr_t;
754#else
755typedef u32 pci_bus_addr_t;
756#endif
757
758struct pci_bus_region {
759 pci_bus_addr_t start;
760 pci_bus_addr_t end;
761};
762
763struct pci_dynids {
764 spinlock_t lock;
765 struct list_head list;
766};
767
768
769
770
771
772
773
774
775
776typedef unsigned int __bitwise pci_ers_result_t;
777
778enum pci_ers_result {
779
780 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
781
782
783 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
784
785
786 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
787
788
789 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
790
791
792 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
793
794
795 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
796};
797
798
799struct pci_error_handlers {
800
801 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
802 pci_channel_state_t error);
803
804
805 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
806
807
808 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
809
810
811 void (*reset_prepare)(struct pci_dev *dev);
812 void (*reset_done)(struct pci_dev *dev);
813
814
815 void (*resume)(struct pci_dev *dev);
816};
817
818
819struct module;
820
821
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869
870struct pci_driver {
871 struct list_head node;
872 const char *name;
873 const struct pci_device_id *id_table;
874 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
875 void (*remove)(struct pci_dev *dev);
876 int (*suspend)(struct pci_dev *dev, pm_message_t state);
877 int (*resume)(struct pci_dev *dev);
878 void (*shutdown)(struct pci_dev *dev);
879 int (*sriov_configure)(struct pci_dev *dev, int num_vfs);
880 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count);
881 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
882 const struct pci_error_handlers *err_handler;
883 const struct attribute_group **groups;
884 const struct attribute_group **dev_groups;
885 struct device_driver driver;
886 struct pci_dynids dynids;
887};
888
889#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
890
891
892
893
894
895
896
897
898
899
900#define PCI_DEVICE(vend,dev) \
901 .vendor = (vend), .device = (dev), \
902 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
903
904
905
906
907
908
909
910
911
912
913
914#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
915 .vendor = (vend), .device = (dev), \
916 .subvendor = (subvend), .subdevice = (subdev)
917
918
919
920
921
922
923
924
925
926
927#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
928 .class = (dev_class), .class_mask = (dev_class_mask), \
929 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
930 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
931
932
933
934
935
936
937
938
939
940
941
942#define PCI_VDEVICE(vend, dev) \
943 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
944 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
945
946
947
948
949
950
951
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953
954
955
956#define PCI_DEVICE_DATA(vend, dev, data) \
957 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
958 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
959 .driver_data = (kernel_ulong_t)(data)
960
961enum {
962 PCI_REASSIGN_ALL_RSRC = 0x00000001,
963 PCI_REASSIGN_ALL_BUS = 0x00000002,
964 PCI_PROBE_ONLY = 0x00000004,
965 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
966 PCI_ENABLE_PROC_DOMAINS = 0x00000010,
967 PCI_COMPAT_DOMAIN_0 = 0x00000020,
968 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
969};
970
971#define PCI_IRQ_LEGACY (1 << 0)
972#define PCI_IRQ_MSI (1 << 1)
973#define PCI_IRQ_MSIX (1 << 2)
974#define PCI_IRQ_AFFINITY (1 << 3)
975
976
977#ifdef CONFIG_PCI
978
979extern unsigned int pci_flags;
980
981static inline void pci_set_flags(int flags) { pci_flags = flags; }
982static inline void pci_add_flags(int flags) { pci_flags |= flags; }
983static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
984static inline int pci_has_flag(int flag) { return pci_flags & flag; }
985
986void pcie_bus_configure_settings(struct pci_bus *bus);
987
988enum pcie_bus_config_types {
989 PCIE_BUS_TUNE_OFF,
990 PCIE_BUS_DEFAULT,
991 PCIE_BUS_SAFE,
992 PCIE_BUS_PERFORMANCE,
993 PCIE_BUS_PEER2PEER,
994};
995
996extern enum pcie_bus_config_types pcie_bus_config;
997
998extern struct bus_type pci_bus_type;
999
1000
1001
1002extern struct list_head pci_root_buses;
1003
1004int no_pci_devices(void);
1005
1006void pcibios_resource_survey_bus(struct pci_bus *bus);
1007void pcibios_bus_add_device(struct pci_dev *pdev);
1008void pcibios_add_bus(struct pci_bus *bus);
1009void pcibios_remove_bus(struct pci_bus *bus);
1010void pcibios_fixup_bus(struct pci_bus *);
1011int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1012
1013char *pcibios_setup(char *str);
1014
1015
1016resource_size_t pcibios_align_resource(void *, const struct resource *,
1017 resource_size_t,
1018 resource_size_t);
1019
1020
1021void pci_fixup_cardbus(struct pci_bus *);
1022
1023
1024
1025void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1026 struct resource *res);
1027void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1028 struct pci_bus_region *region);
1029void pcibios_scan_specific_bus(int busn);
1030struct pci_bus *pci_find_bus(int domain, int busnr);
1031void pci_bus_add_devices(const struct pci_bus *bus);
1032struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1033struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1034 struct pci_ops *ops, void *sysdata,
1035 struct list_head *resources);
1036int pci_host_probe(struct pci_host_bridge *bridge);
1037int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1038int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1039void pci_bus_release_busn_res(struct pci_bus *b);
1040struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1041 struct pci_ops *ops, void *sysdata,
1042 struct list_head *resources);
1043int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1044struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1045 int busnr);
1046struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1047 const char *name,
1048 struct hotplug_slot *hotplug);
1049void pci_destroy_slot(struct pci_slot *slot);
1050#ifdef CONFIG_SYSFS
1051void pci_dev_assign_slot(struct pci_dev *dev);
1052#else
1053static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1054#endif
1055int pci_scan_slot(struct pci_bus *bus, int devfn);
1056struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1057void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1058unsigned int pci_scan_child_bus(struct pci_bus *bus);
1059void pci_bus_add_device(struct pci_dev *dev);
1060void pci_read_bridge_bases(struct pci_bus *child);
1061struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1062 struct resource *res);
1063u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1064int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1065u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1066struct pci_dev *pci_dev_get(struct pci_dev *dev);
1067void pci_dev_put(struct pci_dev *dev);
1068void pci_remove_bus(struct pci_bus *b);
1069void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1070void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1071void pci_stop_root_bus(struct pci_bus *bus);
1072void pci_remove_root_bus(struct pci_bus *bus);
1073void pci_setup_cardbus(struct pci_bus *bus);
1074void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1075void pci_sort_breadthfirst(void);
1076#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1077#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1078
1079
1080
1081u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1082u8 pci_find_capability(struct pci_dev *dev, int cap);
1083u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1084u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1085u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1086u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1087u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1088struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1089u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1090
1091u64 pci_get_dsn(struct pci_dev *dev);
1092
1093struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1094 struct pci_dev *from);
1095struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1096 unsigned int ss_vendor, unsigned int ss_device,
1097 struct pci_dev *from);
1098struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1099struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1100 unsigned int devfn);
1101struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1102int pci_dev_present(const struct pci_device_id *ids);
1103
1104int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1105 int where, u8 *val);
1106int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1107 int where, u16 *val);
1108int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1109 int where, u32 *val);
1110int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1111 int where, u8 val);
1112int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1113 int where, u16 val);
1114int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1115 int where, u32 val);
1116
1117int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1118 int where, int size, u32 *val);
1119int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1120 int where, int size, u32 val);
1121int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1122 int where, int size, u32 *val);
1123int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1124 int where, int size, u32 val);
1125
1126struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1127
1128int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1129int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1130int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1131int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1132int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1133int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1134
1135int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1136int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1137int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1138int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1139int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1140 u16 clear, u16 set);
1141int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1142 u32 clear, u32 set);
1143
1144static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1145 u16 set)
1146{
1147 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1148}
1149
1150static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1151 u32 set)
1152{
1153 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1154}
1155
1156static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1157 u16 clear)
1158{
1159 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1160}
1161
1162static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1163 u32 clear)
1164{
1165 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1166}
1167
1168
1169int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1170int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1171int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1172int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1173int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1174int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1175
1176int __must_check pci_enable_device(struct pci_dev *dev);
1177int __must_check pci_enable_device_io(struct pci_dev *dev);
1178int __must_check pci_enable_device_mem(struct pci_dev *dev);
1179int __must_check pci_reenable_device(struct pci_dev *);
1180int __must_check pcim_enable_device(struct pci_dev *pdev);
1181void pcim_pin_device(struct pci_dev *pdev);
1182
1183static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1184{
1185
1186
1187
1188
1189 return !pdev->broken_intx_masking;
1190}
1191
1192static inline int pci_is_enabled(struct pci_dev *pdev)
1193{
1194 return (atomic_read(&pdev->enable_cnt) > 0);
1195}
1196
1197static inline int pci_is_managed(struct pci_dev *pdev)
1198{
1199 return pdev->is_managed;
1200}
1201
1202void pci_disable_device(struct pci_dev *dev);
1203
1204extern unsigned int pcibios_max_latency;
1205void pci_set_master(struct pci_dev *dev);
1206void pci_clear_master(struct pci_dev *dev);
1207
1208int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1209int pci_set_cacheline_size(struct pci_dev *dev);
1210int __must_check pci_set_mwi(struct pci_dev *dev);
1211int __must_check pcim_set_mwi(struct pci_dev *dev);
1212int pci_try_set_mwi(struct pci_dev *dev);
1213void pci_clear_mwi(struct pci_dev *dev);
1214void pci_disable_parity(struct pci_dev *dev);
1215void pci_intx(struct pci_dev *dev, int enable);
1216bool pci_check_and_mask_intx(struct pci_dev *dev);
1217bool pci_check_and_unmask_intx(struct pci_dev *dev);
1218int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1219int pci_wait_for_pending_transaction(struct pci_dev *dev);
1220int pcix_get_max_mmrbc(struct pci_dev *dev);
1221int pcix_get_mmrbc(struct pci_dev *dev);
1222int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1223int pcie_get_readrq(struct pci_dev *dev);
1224int pcie_set_readrq(struct pci_dev *dev, int rq);
1225int pcie_get_mps(struct pci_dev *dev);
1226int pcie_set_mps(struct pci_dev *dev, int mps);
1227u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1228 enum pci_bus_speed *speed,
1229 enum pcie_link_width *width);
1230void pcie_print_link_status(struct pci_dev *dev);
1231bool pcie_has_flr(struct pci_dev *dev);
1232int pcie_flr(struct pci_dev *dev);
1233int __pci_reset_function_locked(struct pci_dev *dev);
1234int pci_reset_function(struct pci_dev *dev);
1235int pci_reset_function_locked(struct pci_dev *dev);
1236int pci_try_reset_function(struct pci_dev *dev);
1237int pci_probe_reset_slot(struct pci_slot *slot);
1238int pci_probe_reset_bus(struct pci_bus *bus);
1239int pci_reset_bus(struct pci_dev *dev);
1240void pci_reset_secondary_bus(struct pci_dev *dev);
1241void pcibios_reset_secondary_bus(struct pci_dev *dev);
1242void pci_update_resource(struct pci_dev *dev, int resno);
1243int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1244int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1245void pci_release_resource(struct pci_dev *dev, int resno);
1246static inline int pci_rebar_bytes_to_size(u64 bytes)
1247{
1248 bytes = roundup_pow_of_two(bytes);
1249
1250
1251 return max(ilog2(bytes), 20) - 20;
1252}
1253
1254u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1255int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1256int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1257bool pci_device_is_present(struct pci_dev *pdev);
1258void pci_ignore_hotplug(struct pci_dev *dev);
1259struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1260int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1261
1262int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1263 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1264 const char *fmt, ...);
1265void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1266
1267
1268int pci_enable_rom(struct pci_dev *pdev);
1269void pci_disable_rom(struct pci_dev *pdev);
1270void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1271void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1272
1273
1274int pci_save_state(struct pci_dev *dev);
1275void pci_restore_state(struct pci_dev *dev);
1276struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1277int pci_load_saved_state(struct pci_dev *dev,
1278 struct pci_saved_state *state);
1279int pci_load_and_free_saved_state(struct pci_dev *dev,
1280 struct pci_saved_state **state);
1281struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1282struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1283 u16 cap);
1284int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1285int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1286 u16 cap, unsigned int size);
1287int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1288int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1289pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1290bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1291void pci_pme_active(struct pci_dev *dev, bool enable);
1292int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1293int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1294int pci_prepare_to_sleep(struct pci_dev *dev);
1295int pci_back_from_sleep(struct pci_dev *dev);
1296bool pci_dev_run_wake(struct pci_dev *dev);
1297void pci_d3cold_enable(struct pci_dev *dev);
1298void pci_d3cold_disable(struct pci_dev *dev);
1299bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1300void pci_resume_bus(struct pci_bus *bus);
1301void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1302
1303
1304void set_pcie_port_type(struct pci_dev *pdev);
1305void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1306
1307
1308unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1309unsigned int pci_rescan_bus(struct pci_bus *bus);
1310void pci_lock_rescan_remove(void);
1311void pci_unlock_rescan_remove(void);
1312
1313
1314ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1315ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1316
1317
1318resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1319void pci_bus_assign_resources(const struct pci_bus *bus);
1320void pci_bus_claim_resources(struct pci_bus *bus);
1321void pci_bus_size_bridges(struct pci_bus *bus);
1322int pci_claim_resource(struct pci_dev *, int);
1323int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1324void pci_assign_unassigned_resources(void);
1325void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1326void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1327void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1328int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1329void pdev_enable_device(struct pci_dev *);
1330int pci_enable_resources(struct pci_dev *, int mask);
1331void pci_assign_irq(struct pci_dev *dev);
1332struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1333#define HAVE_PCI_REQ_REGIONS 2
1334int __must_check pci_request_regions(struct pci_dev *, const char *);
1335int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1336void pci_release_regions(struct pci_dev *);
1337int __must_check pci_request_region(struct pci_dev *, int, const char *);
1338void pci_release_region(struct pci_dev *, int);
1339int pci_request_selected_regions(struct pci_dev *, int, const char *);
1340int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1341void pci_release_selected_regions(struct pci_dev *, int);
1342
1343
1344void pci_add_resource(struct list_head *resources, struct resource *res);
1345void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1346 resource_size_t offset);
1347void pci_free_resource_list(struct list_head *resources);
1348void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1349 unsigned int flags);
1350struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1351void pci_bus_remove_resources(struct pci_bus *bus);
1352int devm_request_pci_bus_resources(struct device *dev,
1353 struct list_head *resources);
1354
1355
1356int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1357
1358#define pci_bus_for_each_resource(bus, res, i) \
1359 for (i = 0; \
1360 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1361 i++)
1362
1363int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1364 struct resource *res, resource_size_t size,
1365 resource_size_t align, resource_size_t min,
1366 unsigned long type_mask,
1367 resource_size_t (*alignf)(void *,
1368 const struct resource *,
1369 resource_size_t,
1370 resource_size_t),
1371 void *alignf_data);
1372
1373
1374int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1375 resource_size_t size);
1376unsigned long pci_address_to_pio(phys_addr_t addr);
1377phys_addr_t pci_pio_to_address(unsigned long pio);
1378int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1379int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1380 phys_addr_t phys_addr);
1381void pci_unmap_iospace(struct resource *res);
1382void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1383 resource_size_t offset,
1384 resource_size_t size);
1385void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1386 struct resource *res);
1387
1388static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1389{
1390 struct pci_bus_region region;
1391
1392 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1393 return region.start;
1394}
1395
1396
1397int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1398 const char *mod_name);
1399
1400
1401#define pci_register_driver(driver) \
1402 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1403
1404void pci_unregister_driver(struct pci_driver *dev);
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414#define module_pci_driver(__pci_driver) \
1415 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425#define builtin_pci_driver(__pci_driver) \
1426 builtin_driver(__pci_driver, pci_register_driver)
1427
1428struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1429int pci_add_dynid(struct pci_driver *drv,
1430 unsigned int vendor, unsigned int device,
1431 unsigned int subvendor, unsigned int subdevice,
1432 unsigned int class, unsigned int class_mask,
1433 unsigned long driver_data);
1434const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1435 struct pci_dev *dev);
1436int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1437 int pass);
1438
1439void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1440 void *userdata);
1441int pci_cfg_space_size(struct pci_dev *dev);
1442unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1443void pci_setup_bridge(struct pci_bus *bus);
1444resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1445 unsigned long type);
1446
1447#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1448#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1449
1450int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1451 unsigned int command_bits, u32 flags);
1452
1453
1454
1455
1456
1457
1458
1459#define PCI_IRQ_VIRTUAL (1 << 4)
1460
1461#define PCI_IRQ_ALL_TYPES \
1462 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1463
1464
1465
1466#include <linux/dmapool.h>
1467
1468#define pci_pool dma_pool
1469#define pci_pool_create(name, pdev, size, align, allocation) \
1470 dma_pool_create(name, &pdev->dev, size, align, allocation)
1471#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1472#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1473#define pci_pool_zalloc(pool, flags, handle) \
1474 dma_pool_zalloc(pool, flags, handle)
1475#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1476
1477struct msix_entry {
1478 u32 vector;
1479 u16 entry;
1480};
1481
1482#ifdef CONFIG_PCI_MSI
1483int pci_msi_vec_count(struct pci_dev *dev);
1484void pci_disable_msi(struct pci_dev *dev);
1485int pci_msix_vec_count(struct pci_dev *dev);
1486void pci_disable_msix(struct pci_dev *dev);
1487void pci_restore_msi_state(struct pci_dev *dev);
1488int pci_msi_enabled(void);
1489int pci_enable_msi(struct pci_dev *dev);
1490int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1491 int minvec, int maxvec);
1492static inline int pci_enable_msix_exact(struct pci_dev *dev,
1493 struct msix_entry *entries, int nvec)
1494{
1495 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1496 if (rc < 0)
1497 return rc;
1498 return 0;
1499}
1500int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1501 unsigned int max_vecs, unsigned int flags,
1502 struct irq_affinity *affd);
1503
1504void pci_free_irq_vectors(struct pci_dev *dev);
1505int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1506const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1507
1508#else
1509static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1510static inline void pci_disable_msi(struct pci_dev *dev) { }
1511static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1512static inline void pci_disable_msix(struct pci_dev *dev) { }
1513static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1514static inline int pci_msi_enabled(void) { return 0; }
1515static inline int pci_enable_msi(struct pci_dev *dev)
1516{ return -ENOSYS; }
1517static inline int pci_enable_msix_range(struct pci_dev *dev,
1518 struct msix_entry *entries, int minvec, int maxvec)
1519{ return -ENOSYS; }
1520static inline int pci_enable_msix_exact(struct pci_dev *dev,
1521 struct msix_entry *entries, int nvec)
1522{ return -ENOSYS; }
1523
1524static inline int
1525pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1526 unsigned int max_vecs, unsigned int flags,
1527 struct irq_affinity *aff_desc)
1528{
1529 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1530 return 1;
1531 return -ENOSPC;
1532}
1533
1534static inline void pci_free_irq_vectors(struct pci_dev *dev)
1535{
1536}
1537
1538static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1539{
1540 if (WARN_ON_ONCE(nr > 0))
1541 return -EINVAL;
1542 return dev->irq;
1543}
1544static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1545 int vec)
1546{
1547 return cpu_possible_mask;
1548}
1549#endif
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1568 struct device_node *node,
1569 const u32 *intspec,
1570 unsigned int intsize,
1571 unsigned long *out_hwirq,
1572 unsigned int *out_type)
1573{
1574 const u32 intx = intspec[0];
1575
1576 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1577 return -EINVAL;
1578
1579 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1580 return 0;
1581}
1582
1583#ifdef CONFIG_PCIEPORTBUS
1584extern bool pcie_ports_disabled;
1585extern bool pcie_ports_native;
1586#else
1587#define pcie_ports_disabled true
1588#define pcie_ports_native false
1589#endif
1590
1591#define PCIE_LINK_STATE_L0S BIT(0)
1592#define PCIE_LINK_STATE_L1 BIT(1)
1593#define PCIE_LINK_STATE_CLKPM BIT(2)
1594#define PCIE_LINK_STATE_L1_1 BIT(3)
1595#define PCIE_LINK_STATE_L1_2 BIT(4)
1596#define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1597#define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1598
1599#ifdef CONFIG_PCIEASPM
1600int pci_disable_link_state(struct pci_dev *pdev, int state);
1601int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1602void pcie_no_aspm(void);
1603bool pcie_aspm_support_enabled(void);
1604bool pcie_aspm_enabled(struct pci_dev *pdev);
1605#else
1606static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1607{ return 0; }
1608static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1609{ return 0; }
1610static inline void pcie_no_aspm(void) { }
1611static inline bool pcie_aspm_support_enabled(void) { return false; }
1612static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1613#endif
1614
1615#ifdef CONFIG_PCIEAER
1616bool pci_aer_available(void);
1617#else
1618static inline bool pci_aer_available(void) { return false; }
1619#endif
1620
1621bool pci_ats_disabled(void);
1622
1623void pci_cfg_access_lock(struct pci_dev *dev);
1624bool pci_cfg_access_trylock(struct pci_dev *dev);
1625void pci_cfg_access_unlock(struct pci_dev *dev);
1626
1627int pci_dev_trylock(struct pci_dev *dev);
1628void pci_dev_unlock(struct pci_dev *dev);
1629
1630
1631
1632
1633
1634
1635#ifdef CONFIG_PCI_DOMAINS
1636extern int pci_domains_supported;
1637#else
1638enum { pci_domains_supported = 0 };
1639static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1640static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1641#endif
1642
1643
1644
1645
1646
1647
1648#ifdef CONFIG_PCI_DOMAINS_GENERIC
1649static inline int pci_domain_nr(struct pci_bus *bus)
1650{
1651 return bus->domain_nr;
1652}
1653#ifdef CONFIG_ACPI
1654int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1655#else
1656static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1657{ return 0; }
1658#endif
1659int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1660#endif
1661
1662
1663typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1664 unsigned int command_bits, u32 flags);
1665void pci_register_set_vga_state(arch_set_vga_state_t func);
1666
1667static inline int
1668pci_request_io_regions(struct pci_dev *pdev, const char *name)
1669{
1670 return pci_request_selected_regions(pdev,
1671 pci_select_bars(pdev, IORESOURCE_IO), name);
1672}
1673
1674static inline void
1675pci_release_io_regions(struct pci_dev *pdev)
1676{
1677 return pci_release_selected_regions(pdev,
1678 pci_select_bars(pdev, IORESOURCE_IO));
1679}
1680
1681static inline int
1682pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1683{
1684 return pci_request_selected_regions(pdev,
1685 pci_select_bars(pdev, IORESOURCE_MEM), name);
1686}
1687
1688static inline void
1689pci_release_mem_regions(struct pci_dev *pdev)
1690{
1691 return pci_release_selected_regions(pdev,
1692 pci_select_bars(pdev, IORESOURCE_MEM));
1693}
1694
1695#else
1696
1697static inline void pci_set_flags(int flags) { }
1698static inline void pci_add_flags(int flags) { }
1699static inline void pci_clear_flags(int flags) { }
1700static inline int pci_has_flag(int flag) { return 0; }
1701
1702
1703
1704
1705
1706#define _PCI_NOP(o, s, t) \
1707 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1708 int where, t val) \
1709 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1710
1711#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1712 _PCI_NOP(o, word, u16 x) \
1713 _PCI_NOP(o, dword, u32 x)
1714_PCI_NOP_ALL(read, *)
1715_PCI_NOP_ALL(write,)
1716
1717static inline struct pci_dev *pci_get_device(unsigned int vendor,
1718 unsigned int device,
1719 struct pci_dev *from)
1720{ return NULL; }
1721
1722static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1723 unsigned int device,
1724 unsigned int ss_vendor,
1725 unsigned int ss_device,
1726 struct pci_dev *from)
1727{ return NULL; }
1728
1729static inline struct pci_dev *pci_get_class(unsigned int class,
1730 struct pci_dev *from)
1731{ return NULL; }
1732
1733#define pci_dev_present(ids) (0)
1734#define no_pci_devices() (1)
1735#define pci_dev_put(dev) do { } while (0)
1736
1737static inline void pci_set_master(struct pci_dev *dev) { }
1738static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1739static inline void pci_disable_device(struct pci_dev *dev) { }
1740static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1741static inline int pci_assign_resource(struct pci_dev *dev, int i)
1742{ return -EBUSY; }
1743static inline int __pci_register_driver(struct pci_driver *drv,
1744 struct module *owner)
1745{ return 0; }
1746static inline int pci_register_driver(struct pci_driver *drv)
1747{ return 0; }
1748static inline void pci_unregister_driver(struct pci_driver *drv) { }
1749static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1750{ return 0; }
1751static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1752 int cap)
1753{ return 0; }
1754static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1755{ return 0; }
1756
1757static inline u64 pci_get_dsn(struct pci_dev *dev)
1758{ return 0; }
1759
1760
1761static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1762static inline void pci_restore_state(struct pci_dev *dev) { }
1763static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1764{ return 0; }
1765static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1766{ return 0; }
1767static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1768 pm_message_t state)
1769{ return PCI_D0; }
1770static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1771 int enable)
1772{ return 0; }
1773
1774static inline struct resource *pci_find_resource(struct pci_dev *dev,
1775 struct resource *res)
1776{ return NULL; }
1777static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1778{ return -EIO; }
1779static inline void pci_release_regions(struct pci_dev *dev) { }
1780
1781static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1782 phys_addr_t addr, resource_size_t size)
1783{ return -EINVAL; }
1784
1785static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1786
1787static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1788{ return NULL; }
1789static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1790 unsigned int devfn)
1791{ return NULL; }
1792static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1793 unsigned int bus, unsigned int devfn)
1794{ return NULL; }
1795
1796static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1797static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1798
1799#define dev_is_pci(d) (false)
1800#define dev_is_pf(d) (false)
1801static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1802{ return false; }
1803static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1804 struct device_node *node,
1805 const u32 *intspec,
1806 unsigned int intsize,
1807 unsigned long *out_hwirq,
1808 unsigned int *out_type)
1809{ return -EINVAL; }
1810
1811static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1812 struct pci_dev *dev)
1813{ return NULL; }
1814static inline bool pci_ats_disabled(void) { return true; }
1815
1816static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1817{
1818 return -EINVAL;
1819}
1820
1821static inline int
1822pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1823 unsigned int max_vecs, unsigned int flags,
1824 struct irq_affinity *aff_desc)
1825{
1826 return -ENOSPC;
1827}
1828#endif
1829
1830static inline int
1831pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1832 unsigned int max_vecs, unsigned int flags)
1833{
1834 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1835 NULL);
1836}
1837
1838
1839
1840#include <asm/pci.h>
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1855 struct vm_area_struct *vma,
1856 enum pci_mmap_state mmap_state, int write_combine);
1857int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1858 struct vm_area_struct *vma,
1859 enum pci_mmap_state mmap_state, int write_combine);
1860
1861#ifndef arch_can_pci_mmap_wc
1862#define arch_can_pci_mmap_wc() 0
1863#endif
1864
1865#ifndef arch_can_pci_mmap_io
1866#define arch_can_pci_mmap_io() 0
1867#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1868#else
1869int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1870#endif
1871
1872#ifndef pci_root_bus_fwnode
1873#define pci_root_bus_fwnode(bus) NULL
1874#endif
1875
1876
1877
1878
1879
1880#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1881#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1882#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1883#define pci_resource_len(dev,bar) \
1884 ((pci_resource_start((dev), (bar)) == 0 && \
1885 pci_resource_end((dev), (bar)) == \
1886 pci_resource_start((dev), (bar))) ? 0 : \
1887 \
1888 (pci_resource_end((dev), (bar)) - \
1889 pci_resource_start((dev), (bar)) + 1))
1890
1891
1892
1893
1894
1895
1896static inline void *pci_get_drvdata(struct pci_dev *pdev)
1897{
1898 return dev_get_drvdata(&pdev->dev);
1899}
1900
1901static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1902{
1903 dev_set_drvdata(&pdev->dev, data);
1904}
1905
1906static inline const char *pci_name(const struct pci_dev *pdev)
1907{
1908 return dev_name(&pdev->dev);
1909}
1910
1911void pci_resource_to_user(const struct pci_dev *dev, int bar,
1912 const struct resource *rsrc,
1913 resource_size_t *start, resource_size_t *end);
1914
1915
1916
1917
1918
1919
1920
1921
1922struct pci_fixup {
1923 u16 vendor;
1924 u16 device;
1925 u32 class;
1926 unsigned int class_shift;
1927#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1928 int hook_offset;
1929#else
1930 void (*hook)(struct pci_dev *dev);
1931#endif
1932};
1933
1934enum pci_fixup_pass {
1935 pci_fixup_early,
1936 pci_fixup_header,
1937 pci_fixup_final,
1938 pci_fixup_enable,
1939 pci_fixup_resume,
1940 pci_fixup_suspend,
1941 pci_fixup_resume_early,
1942 pci_fixup_suspend_late,
1943};
1944
1945#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1946#define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1947 class_shift, hook) \
1948 __ADDRESSABLE(hook) \
1949 asm(".section " #sec ", \"a\" \n" \
1950 ".balign 16 \n" \
1951 ".short " #vendor ", " #device " \n" \
1952 ".long " #class ", " #class_shift " \n" \
1953 ".long " #hook " - . \n" \
1954 ".previous \n");
1955
1956
1957
1958
1959
1960
1961#ifdef CONFIG_LTO_CLANG
1962#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1963 class_shift, hook, stub) \
1964 void __cficanonical stub(struct pci_dev *dev); \
1965 void __cficanonical stub(struct pci_dev *dev) \
1966 { \
1967 hook(dev); \
1968 } \
1969 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1970 class_shift, stub)
1971#else
1972#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1973 class_shift, hook, stub) \
1974 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1975 class_shift, hook)
1976#endif
1977
1978#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1979 class_shift, hook) \
1980 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1981 class_shift, hook, __UNIQUE_ID(hook))
1982#else
1983
1984#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1985 class_shift, hook) \
1986 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1987 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1988 = { vendor, device, class, class_shift, hook };
1989#endif
1990
1991#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1992 class_shift, hook) \
1993 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1994 hook, vendor, device, class, class_shift, hook)
1995#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1996 class_shift, hook) \
1997 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1998 hook, vendor, device, class, class_shift, hook)
1999#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2000 class_shift, hook) \
2001 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2002 hook, vendor, device, class, class_shift, hook)
2003#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2004 class_shift, hook) \
2005 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2006 hook, vendor, device, class, class_shift, hook)
2007#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2008 class_shift, hook) \
2009 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2010 resume##hook, vendor, device, class, class_shift, hook)
2011#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2012 class_shift, hook) \
2013 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2014 resume_early##hook, vendor, device, class, class_shift, hook)
2015#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2016 class_shift, hook) \
2017 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2018 suspend##hook, vendor, device, class, class_shift, hook)
2019#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2020 class_shift, hook) \
2021 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2022 suspend_late##hook, vendor, device, class, class_shift, hook)
2023
2024#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2025 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2026 hook, vendor, device, PCI_ANY_ID, 0, hook)
2027#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2028 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2029 hook, vendor, device, PCI_ANY_ID, 0, hook)
2030#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2031 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2032 hook, vendor, device, PCI_ANY_ID, 0, hook)
2033#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2034 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2035 hook, vendor, device, PCI_ANY_ID, 0, hook)
2036#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2037 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2038 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2039#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2040 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2041 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2042#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2043 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2044 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2045#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2046 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2047 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2048
2049#ifdef CONFIG_PCI_QUIRKS
2050void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2051#else
2052static inline void pci_fixup_device(enum pci_fixup_pass pass,
2053 struct pci_dev *dev) { }
2054#endif
2055
2056void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2057void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2058void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2059int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2060int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2061 const char *name);
2062void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2063
2064extern int pci_pci_problems;
2065#define PCIPCI_FAIL 1
2066#define PCIPCI_TRITON 2
2067#define PCIPCI_NATOMA 4
2068#define PCIPCI_VIAETBF 8
2069#define PCIPCI_VSFX 16
2070#define PCIPCI_ALIMAGIK 32
2071#define PCIAGP_FAIL 64
2072
2073extern unsigned long pci_cardbus_io_size;
2074extern unsigned long pci_cardbus_mem_size;
2075extern u8 pci_dfl_cache_line_size;
2076extern u8 pci_cache_line_size;
2077
2078
2079void pcibios_disable_device(struct pci_dev *dev);
2080void pcibios_set_master(struct pci_dev *dev);
2081int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2082 enum pcie_reset_state state);
2083int pcibios_add_device(struct pci_dev *dev);
2084void pcibios_release_device(struct pci_dev *dev);
2085#ifdef CONFIG_PCI
2086void pcibios_penalize_isa_irq(int irq, int active);
2087#else
2088static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2089#endif
2090int pcibios_alloc_irq(struct pci_dev *dev);
2091void pcibios_free_irq(struct pci_dev *dev);
2092resource_size_t pcibios_default_alignment(void);
2093
2094#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2095void __init pci_mmcfg_early_init(void);
2096void __init pci_mmcfg_late_init(void);
2097#else
2098static inline void pci_mmcfg_early_init(void) { }
2099static inline void pci_mmcfg_late_init(void) { }
2100#endif
2101
2102int pci_ext_cfg_avail(void);
2103
2104void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2105void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2106
2107#ifdef CONFIG_PCI_IOV
2108int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2109int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2110
2111int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2112void pci_disable_sriov(struct pci_dev *dev);
2113
2114int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2115int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2116void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2117int pci_num_vf(struct pci_dev *dev);
2118int pci_vfs_assigned(struct pci_dev *dev);
2119int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2120int pci_sriov_get_totalvfs(struct pci_dev *dev);
2121int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2122resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2123void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2124
2125
2126int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2127int pcibios_sriov_disable(struct pci_dev *pdev);
2128resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2129#else
2130static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2131{
2132 return -ENOSYS;
2133}
2134static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2135{
2136 return -ENOSYS;
2137}
2138static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2139{ return -ENODEV; }
2140
2141static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2142 struct pci_dev *virtfn, int id)
2143{
2144 return -ENODEV;
2145}
2146static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2147{
2148 return -ENOSYS;
2149}
2150static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2151 int id) { }
2152static inline void pci_disable_sriov(struct pci_dev *dev) { }
2153static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2154static inline int pci_vfs_assigned(struct pci_dev *dev)
2155{ return 0; }
2156static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2157{ return 0; }
2158static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2159{ return 0; }
2160#define pci_sriov_configure_simple NULL
2161static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2162{ return 0; }
2163static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2164#endif
2165
2166#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2167void pci_hp_create_module_link(struct pci_slot *pci_slot);
2168void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2169#endif
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182static inline int pci_pcie_cap(struct pci_dev *dev)
2183{
2184 return dev->pcie_cap;
2185}
2186
2187
2188
2189
2190
2191
2192
2193static inline bool pci_is_pcie(struct pci_dev *dev)
2194{
2195 return pci_pcie_cap(dev);
2196}
2197
2198
2199
2200
2201
2202static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2203{
2204 return dev->pcie_flags_reg;
2205}
2206
2207
2208
2209
2210
2211static inline int pci_pcie_type(const struct pci_dev *dev)
2212{
2213 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2214}
2215
2216
2217
2218
2219
2220
2221
2222
2223static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2224{
2225 while (dev) {
2226 if (pci_is_pcie(dev) &&
2227 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2228 return dev;
2229 dev = pci_upstream_bridge(dev);
2230 }
2231
2232 return NULL;
2233}
2234
2235void pci_request_acs(void);
2236bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2237bool pci_acs_path_enabled(struct pci_dev *start,
2238 struct pci_dev *end, u16 acs_flags);
2239int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2240
2241#define PCI_VPD_LRDT 0x80
2242#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2243
2244
2245#define PCI_VPD_LTIN_ID_STRING 0x02
2246#define PCI_VPD_LTIN_RO_DATA 0x10
2247#define PCI_VPD_LTIN_RW_DATA 0x11
2248
2249#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2250#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2251#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2252
2253
2254#define PCI_VPD_STIN_END 0x0f
2255
2256#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2257
2258#define PCI_VPD_SRDT_TIN_MASK 0x78
2259#define PCI_VPD_SRDT_LEN_MASK 0x07
2260#define PCI_VPD_LRDT_TIN_MASK 0x7f
2261
2262#define PCI_VPD_LRDT_TAG_SIZE 3
2263#define PCI_VPD_SRDT_TAG_SIZE 1
2264
2265#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2266
2267#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2268#define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2269#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2270#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2271#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2272
2273
2274
2275
2276
2277
2278
2279static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2280{
2281 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2282}
2283
2284
2285
2286
2287
2288
2289
2290static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2291{
2292 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2293}
2294
2295
2296
2297
2298
2299
2300
2301static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2302{
2303 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2304}
2305
2306
2307
2308
2309
2310
2311
2312static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2313{
2314 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2315}
2316
2317
2318
2319
2320
2321
2322
2323static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2324{
2325 return info_field[2];
2326}
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337int pci_vpd_find_tag(const u8 *buf, unsigned int len, u8 rdt);
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2350 unsigned int len, const char *kw);
2351
2352
2353#ifdef CONFIG_OF
2354struct device_node;
2355struct irq_domain;
2356struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2357bool pci_host_of_has_msi_map(struct device *dev);
2358
2359
2360struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2361
2362#else
2363static inline struct irq_domain *
2364pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2365static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2366#endif
2367
2368static inline struct device_node *
2369pci_device_to_OF_node(const struct pci_dev *pdev)
2370{
2371 return pdev ? pdev->dev.of_node : NULL;
2372}
2373
2374static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2375{
2376 return bus ? bus->dev.of_node : NULL;
2377}
2378
2379#ifdef CONFIG_ACPI
2380struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2381
2382void
2383pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2384bool pci_pr3_present(struct pci_dev *pdev);
2385#else
2386static inline struct irq_domain *
2387pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2388static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2389#endif
2390
2391#ifdef CONFIG_EEH
2392static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2393{
2394 return pdev->dev.archdata.edev;
2395}
2396#endif
2397
2398void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2399bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2400int pci_for_each_dma_alias(struct pci_dev *pdev,
2401 int (*fn)(struct pci_dev *pdev,
2402 u16 alias, void *data), void *data);
2403
2404
2405static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2406{
2407 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2408}
2409static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2410{
2411 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2412}
2413static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2414{
2415 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2416}
2417
2418
2419
2420
2421
2422
2423
2424static inline bool pci_ari_enabled(struct pci_bus *bus)
2425{
2426 return bus->self && bus->self->ari_enabled;
2427}
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2438{
2439 struct pci_dev *parent = pdev;
2440
2441 if (pdev->is_thunderbolt)
2442 return true;
2443
2444 while ((parent = pci_upstream_bridge(parent)))
2445 if (parent->is_thunderbolt)
2446 return true;
2447
2448 return false;
2449}
2450
2451#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2452void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2453#endif
2454
2455
2456#include <linux/pci-dma-compat.h>
2457
2458#define pci_printk(level, pdev, fmt, arg...) \
2459 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2460
2461#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2462#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2463#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2464#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2465#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2466#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2467#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2468#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2469
2470#define pci_notice_ratelimited(pdev, fmt, arg...) \
2471 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2472
2473#define pci_info_ratelimited(pdev, fmt, arg...) \
2474 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2475
2476#define pci_WARN(pdev, condition, fmt, arg...) \
2477 WARN(condition, "%s %s: " fmt, \
2478 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2479
2480#define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2481 WARN_ONCE(condition, "%s %s: " fmt, \
2482 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2483
2484#endif
2485