1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2001-2002 by David Brownell 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software Foundation, 17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20#ifndef __LINUX_USB_EHCI_DEF_H 21#define __LINUX_USB_EHCI_DEF_H 22 23#include <linux/usb/ehci-dbgp.h> 24 25/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ 26 27/* Section 2.2 Host Controller Capability Registers */ 28struct ehci_caps { 29 /* these fields are specified as 8 and 16 bit registers, 30 * but some hosts can't perform 8 or 16 bit PCI accesses. 31 * some hosts treat caplength and hciversion as parts of a 32-bit 32 * register, others treat them as two separate registers, this 33 * affects the memory map for big endian controllers. 34 */ 35 u32 hc_capbase; 36#define HC_LENGTH(ehci, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \ 37 (ehci_big_endian_capbase(ehci) ? 24 : 0))) 38#define HC_VERSION(ehci, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \ 39 (ehci_big_endian_capbase(ehci) ? 0 : 16))) 40 u32 hcs_params; /* HCSPARAMS - offset 0x4 */ 41#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ 42#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ 43#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ 44#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ 45#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ 46#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 47#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ 48 49 u32 hcc_params; /* HCCPARAMS - offset 0x8 */ 50/* EHCI 1.1 addendum */ 51#define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19)) 52#define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18)) 53#define HCC_LPM(p) ((p)&(1 << 17)) 54#define HCC_HW_PREFETCH(p) ((p)&(1 << 16)) 55 56#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ 57#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ 58#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ 59#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ 60#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ 61#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ 62 u8 portroute[8]; /* nibbles for routing - offset 0xC */ 63}; 64 65 66/* Section 2.3 Host Controller Operational Registers */ 67struct ehci_regs { 68 69 /* USBCMD: offset 0x00 */ 70 u32 command; 71 72/* EHCI 1.1 addendum */ 73#define CMD_HIRD (0xf<<24) /* host initiated resume duration */ 74#define CMD_PPCEE (1<<15) /* per port change event enable */ 75#define CMD_FSP (1<<14) /* fully synchronized prefetch */ 76#define CMD_ASPE (1<<13) /* async schedule prefetch enable */ 77#define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */ 78/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ 79#define CMD_PARK (1<<11) /* enable "park" on async qh */ 80#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ 81#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ 82#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ 83#define CMD_ASE (1<<5) /* async schedule enable */ 84#define CMD_PSE (1<<4) /* periodic schedule enable */ 85/* 3:2 is periodic frame list size */ 86#define CMD_RESET (1<<1) /* reset HC not bus */ 87#define CMD_RUN (1<<0) /* start/stop HC */ 88 89 /* USBSTS: offset 0x04 */ 90 u32 status; 91#define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */ 92#define STS_ASS (1<<15) /* Async Schedule Status */ 93#define STS_PSS (1<<14) /* Periodic Schedule Status */ 94#define STS_RECL (1<<13) /* Reclamation */ 95#define STS_HALT (1<<12) /* Not running (any reason) */ 96/* some bits reserved */ 97 /* these STS_* flags are also intr_enable bits (USBINTR) */ 98#define STS_IAA (1<<5) /* Interrupted on async advance */ 99#define STS_FATAL (1<<4) /* such as some PCI access errors */ 100#define STS_FLR (1<<3) /* frame list rolled over */ 101#define STS_PCD (1<<2) /* port change detect */ 102#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ 103#define STS_INT (1<<0) /* "normal" completion (short, ...) */ 104 105 /* USBINTR: offset 0x08 */ 106 u32 intr_enable; 107 108 /* FRINDEX: offset 0x0C */ 109 u32 frame_index; /* current microframe number */ 110 /* CTRLDSSEGMENT: offset 0x10 */ 111 u32 segment; /* address bits 63:32 if needed */ 112 /* PERIODICLISTBASE: offset 0x14 */ 113 u32 frame_list; /* points to periodic list */ 114 /* ASYNCLISTADDR: offset 0x18 */ 115 u32 async_next; /* address of next async queue head */ 116 117 u32 reserved1[2]; 118 119 /* TXFILLTUNING: offset 0x24 */ 120 u32 txfill_tuning; /* TX FIFO Tuning register */ 121#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */ 122 123 u32 reserved2[6]; 124 125 /* CONFIGFLAG: offset 0x40 */ 126 u32 configured_flag; 127#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ 128 129 /* PORTSC: offset 0x44 */ 130 u32 port_status[0]; /* up to N_PORTS */ 131/* EHCI 1.1 addendum */ 132#define PORTSC_SUSPEND_STS_ACK 0 133#define PORTSC_SUSPEND_STS_NYET 1 134#define PORTSC_SUSPEND_STS_STALL 2 135#define PORTSC_SUSPEND_STS_ERR 3 136 137#define PORT_DEV_ADDR (0x7f<<25) /* device address */ 138#define PORT_SSTS (0x3<<23) /* suspend status */ 139/* 31:23 reserved */ 140#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ 141#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ 142#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ 143/* 19:16 for port testing */ 144#define PORT_TEST(x) (((x)&0xf)<<16) /* Port Test Control */ 145#define PORT_TEST_PKT PORT_TEST(0x4) /* Port Test Control - packet test */ 146#define PORT_TEST_FORCE PORT_TEST(0x5) /* Port Test Control - force enable */ 147#define PORT_LED_OFF (0<<14) 148#define PORT_LED_AMBER (1<<14) 149#define PORT_LED_GREEN (2<<14) 150#define PORT_LED_MASK (3<<14) 151#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ 152#define PORT_POWER (1<<12) /* true: has power (see PPC) */ 153#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */ 154#define PORT_LS_MASK (3<<10) /* Link status (SE0, K or J */ 155/* 9 reserved */ 156#define PORT_LPM (1<<9) /* LPM transaction */ 157#define PORT_RESET (1<<8) /* reset port */ 158#define PORT_SUSPEND (1<<7) /* suspend port */ 159#define PORT_RESUME (1<<6) /* resume it */ 160#define PORT_OCC (1<<5) /* over current change */ 161#define PORT_OC (1<<4) /* over current active */ 162#define PORT_PEC (1<<3) /* port enable change */ 163#define PORT_PE (1<<2) /* port enable */ 164#define PORT_CSC (1<<1) /* connect status change */ 165#define PORT_CONNECT (1<<0) /* device connected */ 166#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) 167 168 u32 reserved3[9]; 169 170 /* USBMODE: offset 0x68 */ 171 u32 usbmode; /* USB Device mode */ 172#define USBMODE_SDIS (1<<3) /* Stream disable */ 173#define USBMODE_BE (1<<2) /* BE/LE endianness select */ 174#define USBMODE_CM_HC (3<<0) /* host controller mode */ 175#define USBMODE_CM_IDLE (0<<0) /* idle state */ 176 177 u32 reserved4[6]; 178 179/* Moorestown has some non-standard registers, partially due to the fact that 180 * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to 181 * PORTSCx 182 */ 183 /* HOSTPC: offset 0x84 */ 184 u32 hostpc[0]; /* HOSTPC extension */ 185#define HOSTPC_PHCD (1<<22) /* Phy clock disable */ 186#define HOSTPC_PSPD (3<<25) /* Port speed detection */ 187 188 u32 reserved5[17]; 189 190 /* USBMODE_EX: offset 0xc8 */ 191 u32 usbmode_ex; /* USB Device mode extension */ 192#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */ 193#define USBMODE_EX_HC (3<<0) /* host controller mode */ 194}; 195 196#endif /* __LINUX_USB_EHCI_DEF_H */ 197