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11#ifndef __UCC_SLOW_H__
12#define __UCC_SLOW_H__
13
14#include <linux/kernel.h>
15
16#include <soc/fsl/qe/immap_qe.h>
17#include <soc/fsl/qe/qe.h>
18
19#include <soc/fsl/qe/ucc.h>
20
21
22#define T_R 0x80000000
23#define T_PAD 0x40000000
24#define T_W 0x20000000
25#define T_I 0x10000000
26#define T_L 0x08000000
27
28#define T_A 0x04000000
29
30#define T_TC 0x04000000
31#define T_CM 0x02000000
32#define T_DEF 0x02000000
33#define T_P 0x01000000
34
35#define T_HB 0x01000000
36#define T_NS 0x00800000
37#define T_LC 0x00800000
38#define T_RL 0x00400000
39#define T_UN 0x00020000
40#define T_CT 0x00010000
41#define T_CSL 0x00010000
42#define T_RC 0x003c0000
43
44
45#define R_E 0x80000000
46#define R_W 0x20000000
47#define R_I 0x10000000
48#define R_L 0x08000000
49#define R_C 0x08000000
50
51#define R_F 0x04000000
52#define R_A 0x04000000
53
54#define R_CM 0x02000000
55#define R_ID 0x01000000
56#define R_M 0x01000000
57
58#define R_AM 0x00800000
59#define R_DE 0x00800000
60#define R_LG 0x00200000
61#define R_BR 0x00200000
62#define R_NO 0x00100000
63#define R_FR 0x00100000
64
65#define R_PR 0x00080000
66#define R_AB 0x00080000
67#define R_SH 0x00080000
68#define R_CR 0x00040000
69#define R_OV 0x00020000
70#define R_CD 0x00010000
71#define R_CL 0x00010000
72
73
74
75#define UCC_SLOW_RX_ALIGN 4
76#define UCC_SLOW_MRBLR_ALIGNMENT 4
77#define UCC_SLOW_PRAM_SIZE 0x100
78#define ALIGNMENT_OF_UCC_SLOW_PRAM 64
79
80
81enum ucc_slow_channel_protocol_mode {
82 UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002,
83 UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004,
84 UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008,
85};
86
87
88enum ucc_slow_transparent_tcrc {
89
90 UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000,
91
92 UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000,
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94 UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000,
95};
96
97
98enum ucc_slow_tx_oversampling_rate {
99
100 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000,
101
102 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000,
103
104 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000,
105
106 UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000,
107};
108
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110
111enum ucc_slow_rx_oversampling_rate {
112
113 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000,
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115 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000,
116
117 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000,
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119 UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000,
120};
121
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123
124enum ucc_slow_tx_encoding_method {
125 UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
126 UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
127};
128
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131enum ucc_slow_rx_decoding_method {
132 UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
133 UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
134};
135
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137
138enum ucc_slow_diag_mode {
139 UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
140 UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
141 UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
142 UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
143};
144
145struct ucc_slow_info {
146 int ucc_num;
147 int protocol;
148 enum qe_clock rx_clock;
149 enum qe_clock tx_clock;
150 phys_addr_t regs;
151 int irq;
152 u16 uccm_mask;
153 int data_mem_part;
154 int init_tx;
155 int init_rx;
156 u32 tx_bd_ring_len;
157 u32 rx_bd_ring_len;
158 int rx_interrupts;
159 int brkpt_support;
160 int grant_support;
161 int tsa;
162 int cdp;
163 int cds;
164 int ctsp;
165 int ctss;
166 int rinv;
167 int tinv;
168 int rtsm;
169 int rfw;
170 int tci;
171 int tend;
172 int tfl;
173 int txsy;
174 u16 max_rx_buf_length;
175 enum ucc_slow_transparent_tcrc tcrc;
176 enum ucc_slow_channel_protocol_mode mode;
177 enum ucc_slow_diag_mode diag;
178 enum ucc_slow_tx_oversampling_rate tdcr;
179 enum ucc_slow_rx_oversampling_rate rdcr;
180 enum ucc_slow_tx_encoding_method tenc;
181 enum ucc_slow_rx_decoding_method renc;
182};
183
184struct ucc_slow_private {
185 struct ucc_slow_info *us_info;
186 struct ucc_slow __iomem *us_regs;
187 struct ucc_slow_pram __iomem *us_pram;
188 s32 us_pram_offset;
189 int enabled_tx;
190 int enabled_rx;
191 int stopped_tx;
192
193 int stopped_rx;
194 struct list_head confQ;
195 u32 first_tx_bd_mask;
196
197 s32 tx_base_offset;
198 s32 rx_base_offset;
199 struct qe_bd __iomem *confBd;
200 struct qe_bd __iomem *tx_bd;
201 struct qe_bd __iomem *rx_bd;
202 void *p_rx_frame;
203 __be16 __iomem *p_ucce;
204 __be16 __iomem *p_uccm;
205 u16 saved_uccm;
206#ifdef STATISTICS
207 u32 tx_frames;
208 u32 rx_frames;
209
210 u32 rx_discarded;
211
212
213#endif
214};
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222int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret);
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229void ucc_slow_free(struct ucc_slow_private * uccs);
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238void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
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247void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
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254void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
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261void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
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268void ucc_slow_restart_tx(struct ucc_slow_private *uccs);
269
270u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
271
272#endif
273