LXR linux/include/soc/mscc/ocelot.h

   1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
   2/* Copyright (c) 2017 Microsemi Corporation
   3 */
   4
   5#ifndef _SOC_MSCC_OCELOT_H
   6#define _SOC_MSCC_OCELOT_H
   7
   8#include <linux/ptp_clock_kernel.h>
   9#include <linux/net_tstamp.h>
  10#include <linux/if_vlan.h>
  11#include <linux/regmap.h>
  12#include <net/dsa.h>
  13
  14/* Port Group IDs (PGID) are masks of destination ports.
  15 *
  16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
  17 * frame, and forwards the frame to the ports that are present in the logical
  18 * AND of all 3 PGIDs.
  19 *
  20 * These PGID lookups are:
  21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
  22 *   which the switch selects a destination PGID:
  23 *     - The {DMAC, VID} is present in the MAC table. In that case, the
  24 *       destination PGID is given by the DEST_IDX field of the MAC table entry
  25 *       that matched.
  26 *     - The {DMAC, VID} is not present in the MAC table (it is unknown). The
  27 *       frame is disseminated as being either unicast, multicast or broadcast,
  28 *       and according to that, the destination PGID is chosen as being the
  29 *       value contained by ANA_FLOODING_FLD_UNICAST,
  30 *       ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
  31 *   The destination PGID can be an unicast set: the first PGIDs, 0 to
  32 *   ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
  33 *   ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
  34 *   a physical port and has a single bit set in the destination ports mask:
  35 *   that corresponding to the port number itself. In contrast, a multicast
  36 *   PGID will have potentially more than one single bit set in the destination
  37 *   ports mask.
  38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
  39 *   dissects each frame and generates a 4-bit Link Aggregation Code which is
  40 *   used for this second PGID table lookup. The goal of link aggregation is to
  41 *   hash multiple flows within the same LAG on to different destination ports.
  42 *   The first lookup will result in a PGID with all the LAG members present in
  43 *   the destination ports mask, and the second lookup, by Link Aggregation
  44 *   Code, will ensure that each flow gets forwarded only to a single port out
  45 *   of that mask (there are no duplicates).
  46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
  47 *   is indexed with the ingress port (plus 80). These PGIDs answer the
  48 *   question "is port i allowed to forward traffic to port j?" If yes, then
  49 *   BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
  50 *   to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
  51 */
  52
  53/* Reserve some destination PGIDs at the end of the range:
  54 * PGID_BLACKHOLE: used for not forwarding the frames
  55 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
  56 *           of the switch port net devices, towards the CPU port module.
  57 * PGID_UC: the flooding destinations for unknown unicast traffic.
  58 * PGID_MC: the flooding destinations for non-IP multicast traffic.
  59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
  60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
  61 * PGID_BC: the flooding destinations for broadcast traffic.
  62 */
  63#define PGID_BLACKHOLE                  57
  64#define PGID_CPU                        58
  65#define PGID_UC                         59
  66#define PGID_MC                         60
  67#define PGID_MCIPV4                     61
  68#define PGID_MCIPV6                     62
  69#define PGID_BC                         63
  70
  71#define for_each_unicast_dest_pgid(ocelot, pgid)                \
  72        for ((pgid) = 0;                                        \
  73             (pgid) < (ocelot)->num_phys_ports;                 \
  74             (pgid)++)
  75
  76#define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid)  \
  77        for ((pgid) = (ocelot)->num_phys_ports + 1;             \
  78             (pgid) < PGID_BLACKHOLE;                           \
  79             (pgid)++)
  80
  81#define for_each_aggr_pgid(ocelot, pgid)                        \
  82        for ((pgid) = PGID_AGGR;                                \
  83             (pgid) < PGID_SRC;                                 \
  84             (pgid)++)
  85
  86/* Aggregation PGIDs, one per Link Aggregation Code */
  87#define PGID_AGGR                       64
  88
  89/* Source PGIDs, one per physical port */
  90#define PGID_SRC                        80
  91
  92#define IFH_TAG_TYPE_C                  0
  93#define IFH_TAG_TYPE_S                  1
  94
  95#define IFH_REW_OP_NOOP                 0x0
  96#define IFH_REW_OP_DSCP                 0x1
  97#define IFH_REW_OP_ONE_STEP_PTP         0x2
  98#define IFH_REW_OP_TWO_STEP_PTP         0x3
  99#define IFH_REW_OP_ORIGIN_PTP           0x5
 100
 101#define OCELOT_NUM_TC                   8
 102
 103#define OCELOT_SPEED_2500               0
 104#define OCELOT_SPEED_1000               1
 105#define OCELOT_SPEED_100                2
 106#define OCELOT_SPEED_10                 3
 107
 108#define OCELOT_PTP_PINS_NUM             4
 109
 110#define TARGET_OFFSET                   24
 111#define REG_MASK                        GENMASK(TARGET_OFFSET - 1, 0)
 112#define REG(reg, offset)                [reg & REG_MASK] = offset
 113
 114#define REG_RESERVED_ADDR               0xffffffff
 115#define REG_RESERVED(reg)               REG(reg, REG_RESERVED_ADDR)
 116
 117#define OCELOT_MRP_CPUQ                 7
 118
 119enum ocelot_target {
 120        ANA = 1,
 121        QS,
 122        QSYS,
 123        REW,
 124        SYS,
 125        S0,
 126        S1,
 127        S2,
 128        HSIO,
 129        PTP,
 130        GCB,
 131        DEV_GMII,
 132        TARGET_MAX,
 133};
 134
 135enum ocelot_reg {
 136        ANA_ADVLEARN = ANA << TARGET_OFFSET,
 137        ANA_VLANMASK,
 138        ANA_PORT_B_DOMAIN,
 139        ANA_ANAGEFIL,
 140        ANA_ANEVENTS,
 141        ANA_STORMLIMIT_BURST,
 142        ANA_STORMLIMIT_CFG,
 143        ANA_ISOLATED_PORTS,
 144        ANA_COMMUNITY_PORTS,
 145        ANA_AUTOAGE,
 146        ANA_MACTOPTIONS,
 147        ANA_LEARNDISC,
 148        ANA_AGENCTRL,
 149        ANA_MIRRORPORTS,
 150        ANA_EMIRRORPORTS,
 151        ANA_FLOODING,
 152        ANA_FLOODING_IPMC,
 153        ANA_SFLOW_CFG,
 154        ANA_PORT_MODE,
 155        ANA_CUT_THRU_CFG,
 156        ANA_PGID_PGID,
 157        ANA_TABLES_ANMOVED,
 158        ANA_TABLES_MACHDATA,
 159        ANA_TABLES_MACLDATA,
 160        ANA_TABLES_STREAMDATA,
 161        ANA_TABLES_MACACCESS,
 162        ANA_TABLES_MACTINDX,
 163        ANA_TABLES_VLANACCESS,
 164        ANA_TABLES_VLANTIDX,
 165        ANA_TABLES_ISDXACCESS,
 166        ANA_TABLES_ISDXTIDX,
 167        ANA_TABLES_ENTRYLIM,
 168        ANA_TABLES_PTP_ID_HIGH,
 169        ANA_TABLES_PTP_ID_LOW,
 170        ANA_TABLES_STREAMACCESS,
 171        ANA_TABLES_STREAMTIDX,
 172        ANA_TABLES_SEQ_HISTORY,
 173        ANA_TABLES_SEQ_MASK,
 174        ANA_TABLES_SFID_MASK,
 175        ANA_TABLES_SFIDACCESS,
 176        ANA_TABLES_SFIDTIDX,
 177        ANA_MSTI_STATE,
 178        ANA_OAM_UPM_LM_CNT,
 179        ANA_SG_ACCESS_CTRL,
 180        ANA_SG_CONFIG_REG_1,
 181        ANA_SG_CONFIG_REG_2,
 182        ANA_SG_CONFIG_REG_3,
 183        ANA_SG_CONFIG_REG_4,
 184        ANA_SG_CONFIG_REG_5,
 185        ANA_SG_GCL_GS_CONFIG,
 186        ANA_SG_GCL_TI_CONFIG,
 187        ANA_SG_STATUS_REG_1,
 188        ANA_SG_STATUS_REG_2,
 189        ANA_SG_STATUS_REG_3,
 190        ANA_PORT_VLAN_CFG,
 191        ANA_PORT_DROP_CFG,
 192        ANA_PORT_QOS_CFG,
 193        ANA_PORT_VCAP_CFG,
 194        ANA_PORT_VCAP_S1_KEY_CFG,
 195        ANA_PORT_VCAP_S2_CFG,
 196        ANA_PORT_PCP_DEI_MAP,
 197        ANA_PORT_CPU_FWD_CFG,
 198        ANA_PORT_CPU_FWD_BPDU_CFG,
 199        ANA_PORT_CPU_FWD_GARP_CFG,
 200        ANA_PORT_CPU_FWD_CCM_CFG,
 201        ANA_PORT_PORT_CFG,
 202        ANA_PORT_POL_CFG,
 203        ANA_PORT_PTP_CFG,
 204        ANA_PORT_PTP_DLY1_CFG,
 205        ANA_PORT_PTP_DLY2_CFG,
 206        ANA_PORT_SFID_CFG,
 207        ANA_PFC_PFC_CFG,
 208        ANA_PFC_PFC_TIMER,
 209        ANA_IPT_OAM_MEP_CFG,
 210        ANA_IPT_IPT,
 211        ANA_PPT_PPT,
 212        ANA_FID_MAP_FID_MAP,
 213        ANA_AGGR_CFG,
 214        ANA_CPUQ_CFG,
 215        ANA_CPUQ_CFG2,
 216        ANA_CPUQ_8021_CFG,
 217        ANA_DSCP_CFG,
 218        ANA_DSCP_REWR_CFG,
 219        ANA_VCAP_RNG_TYPE_CFG,
 220        ANA_VCAP_RNG_VAL_CFG,
 221        ANA_VRAP_CFG,
 222        ANA_VRAP_HDR_DATA,
 223        ANA_VRAP_HDR_MASK,
 224        ANA_DISCARD_CFG,
 225        ANA_FID_CFG,
 226        ANA_POL_PIR_CFG,
 227        ANA_POL_CIR_CFG,
 228        ANA_POL_MODE_CFG,
 229        ANA_POL_PIR_STATE,
 230        ANA_POL_CIR_STATE,
 231        ANA_POL_STATE,
 232        ANA_POL_FLOWC,
 233        ANA_POL_HYST,
 234        ANA_POL_MISC_CFG,
 235        QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
 236        QS_XTR_RD,
 237        QS_XTR_FRM_PRUNING,
 238        QS_XTR_FLUSH,
 239        QS_XTR_DATA_PRESENT,
 240        QS_XTR_CFG,
 241        QS_INJ_GRP_CFG,
 242        QS_INJ_WR,
 243        QS_INJ_CTRL,
 244        QS_INJ_STATUS,
 245        QS_INJ_ERR,
 246        QS_INH_DBG,
 247        QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
 248        QSYS_SWITCH_PORT_MODE,
 249        QSYS_STAT_CNT_CFG,
 250        QSYS_EEE_CFG,
 251        QSYS_EEE_THRES,
 252        QSYS_IGR_NO_SHARING,
 253        QSYS_EGR_NO_SHARING,
 254        QSYS_SW_STATUS,
 255        QSYS_EXT_CPU_CFG,
 256        QSYS_PAD_CFG,
 257        QSYS_CPU_GROUP_MAP,
 258        QSYS_QMAP,
 259        QSYS_ISDX_SGRP,
 260        QSYS_TIMED_FRAME_ENTRY,
 261        QSYS_TFRM_MISC,
 262        QSYS_TFRM_PORT_DLY,
 263        QSYS_TFRM_TIMER_CFG_1,
 264        QSYS_TFRM_TIMER_CFG_2,
 265        QSYS_TFRM_TIMER_CFG_3,
 266        QSYS_TFRM_TIMER_CFG_4,
 267        QSYS_TFRM_TIMER_CFG_5,
 268        QSYS_TFRM_TIMER_CFG_6,
 269        QSYS_TFRM_TIMER_CFG_7,
 270        QSYS_TFRM_TIMER_CFG_8,
 271        QSYS_RED_PROFILE,
 272        QSYS_RES_QOS_MODE,
 273        QSYS_RES_CFG,
 274        QSYS_RES_STAT,
 275        QSYS_EGR_DROP_MODE,
 276        QSYS_EQ_CTRL,
 277        QSYS_EVENTS_CORE,
 278        QSYS_QMAXSDU_CFG_0,
 279        QSYS_QMAXSDU_CFG_1,
 280        QSYS_QMAXSDU_CFG_2,
 281        QSYS_QMAXSDU_CFG_3,
 282        QSYS_QMAXSDU_CFG_4,
 283        QSYS_QMAXSDU_CFG_5,
 284        QSYS_QMAXSDU_CFG_6,
 285        QSYS_QMAXSDU_CFG_7,
 286        QSYS_PREEMPTION_CFG,
 287        QSYS_CIR_CFG,
 288        QSYS_EIR_CFG,
 289        QSYS_SE_CFG,
 290        QSYS_SE_DWRR_CFG,
 291        QSYS_SE_CONNECT,
 292        QSYS_SE_DLB_SENSE,
 293        QSYS_CIR_STATE,
 294        QSYS_EIR_STATE,
 295        QSYS_SE_STATE,
 296        QSYS_HSCH_MISC_CFG,
 297        QSYS_TAG_CONFIG,
 298        QSYS_TAS_PARAM_CFG_CTRL,
 299        QSYS_PORT_MAX_SDU,
 300        QSYS_PARAM_CFG_REG_1,
 301        QSYS_PARAM_CFG_REG_2,
 302        QSYS_PARAM_CFG_REG_3,
 303        QSYS_PARAM_CFG_REG_4,
 304        QSYS_PARAM_CFG_REG_5,
 305        QSYS_GCL_CFG_REG_1,
 306        QSYS_GCL_CFG_REG_2,
 307        QSYS_PARAM_STATUS_REG_1,
 308        QSYS_PARAM_STATUS_REG_2,
 309        QSYS_PARAM_STATUS_REG_3,
 310        QSYS_PARAM_STATUS_REG_4,
 311        QSYS_PARAM_STATUS_REG_5,
 312        QSYS_PARAM_STATUS_REG_6,
 313        QSYS_PARAM_STATUS_REG_7,
 314        QSYS_PARAM_STATUS_REG_8,
 315        QSYS_PARAM_STATUS_REG_9,
 316        QSYS_GCL_STATUS_REG_1,
 317        QSYS_GCL_STATUS_REG_2,
 318        REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
 319        REW_TAG_CFG,
 320        REW_PORT_CFG,
 321        REW_DSCP_CFG,
 322        REW_PCP_DEI_QOS_MAP_CFG,
 323        REW_PTP_CFG,
 324        REW_PTP_DLY1_CFG,
 325        REW_RED_TAG_CFG,
 326        REW_DSCP_REMAP_DP1_CFG,
 327        REW_DSCP_REMAP_CFG,
 328        REW_STAT_CFG,
 329        REW_REW_STICKY,
 330        REW_PPT,
 331        SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
 332        SYS_COUNT_RX_UNICAST,
 333        SYS_COUNT_RX_MULTICAST,
 334        SYS_COUNT_RX_BROADCAST,
 335        SYS_COUNT_RX_SHORTS,
 336        SYS_COUNT_RX_FRAGMENTS,
 337        SYS_COUNT_RX_JABBERS,
 338        SYS_COUNT_RX_CRC_ALIGN_ERRS,
 339        SYS_COUNT_RX_SYM_ERRS,
 340        SYS_COUNT_RX_64,
 341        SYS_COUNT_RX_65_127,
 342        SYS_COUNT_RX_128_255,
 343        SYS_COUNT_RX_256_1023,
 344        SYS_COUNT_RX_1024_1526,
 345        SYS_COUNT_RX_1527_MAX,
 346        SYS_COUNT_RX_PAUSE,
 347        SYS_COUNT_RX_CONTROL,
 348        SYS_COUNT_RX_LONGS,
 349        SYS_COUNT_RX_CLASSIFIED_DROPS,
 350        SYS_COUNT_TX_OCTETS,
 351        SYS_COUNT_TX_UNICAST,
 352        SYS_COUNT_TX_MULTICAST,
 353        SYS_COUNT_TX_BROADCAST,
 354        SYS_COUNT_TX_COLLISION,
 355        SYS_COUNT_TX_DROPS,
 356        SYS_COUNT_TX_PAUSE,
 357        SYS_COUNT_TX_64,
 358        SYS_COUNT_TX_65_127,
 359        SYS_COUNT_TX_128_511,
 360        SYS_COUNT_TX_512_1023,
 361        SYS_COUNT_TX_1024_1526,
 362        SYS_COUNT_TX_1527_MAX,
 363        SYS_COUNT_TX_AGING,
 364        SYS_RESET_CFG,
 365        SYS_SR_ETYPE_CFG,
 366        SYS_VLAN_ETYPE_CFG,
 367        SYS_PORT_MODE,
 368        SYS_FRONT_PORT_MODE,
 369        SYS_FRM_AGING,
 370        SYS_STAT_CFG,
 371        SYS_SW_STATUS,
 372        SYS_MISC_CFG,
 373        SYS_REW_MAC_HIGH_CFG,
 374        SYS_REW_MAC_LOW_CFG,
 375        SYS_TIMESTAMP_OFFSET,
 376        SYS_CMID,
 377        SYS_PAUSE_CFG,
 378        SYS_PAUSE_TOT_CFG,
 379        SYS_ATOP,
 380        SYS_ATOP_TOT_CFG,
 381        SYS_MAC_FC_CFG,
 382        SYS_MMGT,
 383        SYS_MMGT_FAST,
 384        SYS_EVENTS_DIF,
 385        SYS_EVENTS_CORE,
 386        SYS_CNT,
 387        SYS_PTP_STATUS,
 388        SYS_PTP_TXSTAMP,
 389        SYS_PTP_NXT,
 390        SYS_PTP_CFG,
 391        SYS_RAM_INIT,
 392        SYS_CM_ADDR,
 393        SYS_CM_DATA_WR,
 394        SYS_CM_DATA_RD,
 395        SYS_CM_OP,
 396        SYS_CM_DATA,
 397        PTP_PIN_CFG = PTP << TARGET_OFFSET,
 398        PTP_PIN_TOD_SEC_MSB,
 399        PTP_PIN_TOD_SEC_LSB,
 400        PTP_PIN_TOD_NSEC,
 401        PTP_PIN_WF_HIGH_PERIOD,
 402        PTP_PIN_WF_LOW_PERIOD,
 403        PTP_CFG_MISC,
 404        PTP_CLK_CFG_ADJ_CFG,
 405        PTP_CLK_CFG_ADJ_FREQ,
 406        GCB_SOFT_RST = GCB << TARGET_OFFSET,
 407        GCB_MIIM_MII_STATUS,
 408        GCB_MIIM_MII_CMD,
 409        GCB_MIIM_MII_DATA,
 410        DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
 411        DEV_PORT_MISC,
 412        DEV_EVENTS,
 413        DEV_EEE_CFG,
 414        DEV_RX_PATH_DELAY,
 415        DEV_TX_PATH_DELAY,
 416        DEV_PTP_PREDICT_CFG,
 417        DEV_MAC_ENA_CFG,
 418        DEV_MAC_MODE_CFG,
 419        DEV_MAC_MAXLEN_CFG,
 420        DEV_MAC_TAGS_CFG,
 421        DEV_MAC_ADV_CHK_CFG,
 422        DEV_MAC_IFG_CFG,
 423        DEV_MAC_HDX_CFG,
 424        DEV_MAC_DBG_CFG,
 425        DEV_MAC_FC_MAC_LOW_CFG,
 426        DEV_MAC_FC_MAC_HIGH_CFG,
 427        DEV_MAC_STICKY,
 428        PCS1G_CFG,
 429        PCS1G_MODE_CFG,
 430        PCS1G_SD_CFG,
 431        PCS1G_ANEG_CFG,
 432        PCS1G_ANEG_NP_CFG,
 433        PCS1G_LB_CFG,
 434        PCS1G_DBG_CFG,
 435        PCS1G_CDET_CFG,
 436        PCS1G_ANEG_STATUS,
 437        PCS1G_ANEG_NP_STATUS,
 438        PCS1G_LINK_STATUS,
 439        PCS1G_LINK_DOWN_CNT,
 440        PCS1G_STICKY,
 441        PCS1G_DEBUG_STATUS,
 442        PCS1G_LPI_CFG,
 443        PCS1G_LPI_WAKE_ERROR_CNT,
 444        PCS1G_LPI_STATUS,
 445        PCS1G_TSTPAT_MODE_CFG,
 446        PCS1G_TSTPAT_STATUS,
 447        DEV_PCS_FX100_CFG,
 448        DEV_PCS_FX100_STATUS,
 449};
 450
 451enum ocelot_regfield {
 452        ANA_ADVLEARN_VLAN_CHK,
 453        ANA_ADVLEARN_LEARN_MIRROR,
 454        ANA_ANEVENTS_FLOOD_DISCARD,
 455        ANA_ANEVENTS_MSTI_DROP,
 456        ANA_ANEVENTS_ACLKILL,
 457        ANA_ANEVENTS_ACLUSED,
 458        ANA_ANEVENTS_AUTOAGE,
 459        ANA_ANEVENTS_VS2TTL1,
 460        ANA_ANEVENTS_STORM_DROP,
 461        ANA_ANEVENTS_LEARN_DROP,
 462        ANA_ANEVENTS_AGED_ENTRY,
 463        ANA_ANEVENTS_CPU_LEARN_FAILED,
 464        ANA_ANEVENTS_AUTO_LEARN_FAILED,
 465        ANA_ANEVENTS_LEARN_REMOVE,
 466        ANA_ANEVENTS_AUTO_LEARNED,
 467        ANA_ANEVENTS_AUTO_MOVED,
 468        ANA_ANEVENTS_DROPPED,
 469        ANA_ANEVENTS_CLASSIFIED_DROP,
 470        ANA_ANEVENTS_CLASSIFIED_COPY,
 471        ANA_ANEVENTS_VLAN_DISCARD,
 472        ANA_ANEVENTS_FWD_DISCARD,
 473        ANA_ANEVENTS_MULTICAST_FLOOD,
 474        ANA_ANEVENTS_UNICAST_FLOOD,
 475        ANA_ANEVENTS_DEST_KNOWN,
 476        ANA_ANEVENTS_BUCKET3_MATCH,
 477        ANA_ANEVENTS_BUCKET2_MATCH,
 478        ANA_ANEVENTS_BUCKET1_MATCH,
 479        ANA_ANEVENTS_BUCKET0_MATCH,
 480        ANA_ANEVENTS_CPU_OPERATION,
 481        ANA_ANEVENTS_DMAC_LOOKUP,
 482        ANA_ANEVENTS_SMAC_LOOKUP,
 483        ANA_ANEVENTS_SEQ_GEN_ERR_0,
 484        ANA_ANEVENTS_SEQ_GEN_ERR_1,
 485        ANA_TABLES_MACACCESS_B_DOM,
 486        ANA_TABLES_MACTINDX_BUCKET,
 487        ANA_TABLES_MACTINDX_M_INDEX,
 488        QSYS_SWITCH_PORT_MODE_PORT_ENA,
 489        QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG,
 490        QSYS_SWITCH_PORT_MODE_YEL_RSRVD,
 491        QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE,
 492        QSYS_SWITCH_PORT_MODE_TX_PFC_ENA,
 493        QSYS_SWITCH_PORT_MODE_TX_PFC_MODE,
 494        QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
 495        QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
 496        QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
 497        QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
 498        QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
 499        SYS_PORT_MODE_DATA_WO_TS,
 500        SYS_PORT_MODE_INCL_INJ_HDR,
 501        SYS_PORT_MODE_INCL_XTR_HDR,
 502        SYS_PORT_MODE_INCL_HDR_ERR,
 503        SYS_RESET_CFG_CORE_ENA,
 504        SYS_RESET_CFG_MEM_ENA,
 505        SYS_RESET_CFG_MEM_INIT,
 506        GCB_SOFT_RST_SWC_RST,
 507        GCB_MIIM_MII_STATUS_PENDING,
 508        GCB_MIIM_MII_STATUS_BUSY,
 509        SYS_PAUSE_CFG_PAUSE_START,
 510        SYS_PAUSE_CFG_PAUSE_STOP,
 511        SYS_PAUSE_CFG_PAUSE_ENA,
 512        REGFIELD_MAX
 513};
 514
 515enum {
 516        /* VCAP_CORE_CFG */
 517        VCAP_CORE_UPDATE_CTRL,
 518        VCAP_CORE_MV_CFG,
 519        /* VCAP_CORE_CACHE */
 520        VCAP_CACHE_ENTRY_DAT,
 521        VCAP_CACHE_MASK_DAT,
 522        VCAP_CACHE_ACTION_DAT,
 523        VCAP_CACHE_CNT_DAT,
 524        VCAP_CACHE_TG_DAT,
 525        /* VCAP_CONST */
 526        VCAP_CONST_VCAP_VER,
 527        VCAP_CONST_ENTRY_WIDTH,
 528        VCAP_CONST_ENTRY_CNT,
 529        VCAP_CONST_ENTRY_SWCNT,
 530        VCAP_CONST_ENTRY_TG_WIDTH,
 531        VCAP_CONST_ACTION_DEF_CNT,
 532        VCAP_CONST_ACTION_WIDTH,
 533        VCAP_CONST_CNT_WIDTH,
 534        VCAP_CONST_CORE_CNT,
 535        VCAP_CONST_IF_CNT,
 536};
 537
 538enum ocelot_ptp_pins {
 539        PTP_PIN_0,
 540        PTP_PIN_1,
 541        PTP_PIN_2,
 542        PTP_PIN_3,
 543        TOD_ACC_PIN
 544};
 545
 546struct ocelot_stat_layout {
 547        u32 offset;
 548        char name[ETH_GSTRING_LEN];
 549};
 550
 551enum ocelot_tag_prefix {
 552        OCELOT_TAG_PREFIX_DISABLED      = 0,
 553        OCELOT_TAG_PREFIX_NONE,
 554        OCELOT_TAG_PREFIX_SHORT,
 555        OCELOT_TAG_PREFIX_LONG,
 556};
 557
 558struct ocelot;
 559
 560struct ocelot_ops {
 561        struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
 562        int (*netdev_to_port)(struct net_device *dev);
 563        int (*reset)(struct ocelot *ocelot);
 564        u16 (*wm_enc)(u16 value);
 565        u16 (*wm_dec)(u16 value);
 566        void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse);
 567};
 568
 569struct ocelot_vcap_block {
 570        struct list_head rules;
 571        int count;
 572        int pol_lpr;
 573};
 574
 575struct ocelot_vlan {
 576        bool valid;
 577        u16 vid;
 578};
 579
 580enum ocelot_sb {
 581        OCELOT_SB_BUF,
 582        OCELOT_SB_REF,
 583        OCELOT_SB_NUM,
 584};
 585
 586enum ocelot_sb_pool {
 587        OCELOT_SB_POOL_ING,
 588        OCELOT_SB_POOL_EGR,
 589        OCELOT_SB_POOL_NUM,
 590};
 591
 592struct ocelot_port {
 593        struct ocelot                   *ocelot;
 594
 595        struct regmap                   *target;
 596
 597        bool                            vlan_aware;
 598        /* VLAN that untagged frames are classified to, on ingress */
 599        struct ocelot_vlan              pvid_vlan;
 600        /* The VLAN ID that will be transmitted as untagged, on egress */
 601        struct ocelot_vlan              native_vlan;
 602
 603        u8                              ptp_cmd;
 604        struct sk_buff_head             tx_skbs;
 605        u8                              ts_id;
 606        spinlock_t                      ts_id_lock;
 607
 608        phy_interface_t                 phy_mode;
 609
 610        u8                              *xmit_template;
 611        bool                            is_dsa_8021q_cpu;
 612        bool                            learn_ena;
 613
 614        struct net_device               *bond;
 615        bool                            lag_tx_active;
 616
 617        u16                             mrp_ring_id;
 618
 619        struct net_device               *bridge;
 620        u8                              stp_state;
 621};
 622
 623struct ocelot {
 624        struct device                   *dev;
 625        struct devlink                  *devlink;
 626        struct devlink_port             *devlink_ports;
 627
 628        const struct ocelot_ops         *ops;
 629        struct regmap                   *targets[TARGET_MAX];
 630        struct regmap_field             *regfields[REGFIELD_MAX];
 631        const u32 *const                *map;
 632        const struct ocelot_stat_layout *stats_layout;
 633        unsigned int                    num_stats;
 634
 635        u32                             pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM];
 636        int                             packet_buffer_size;
 637        int                             num_frame_refs;
 638        int                             num_mact_rows;
 639
 640        struct ocelot_port              **ports;
 641
 642        u8                              base_mac[ETH_ALEN];
 643
 644        /* Keep track of the vlan port masks */
 645        u32                             vlan_mask[VLAN_N_VID];
 646
 647        /* Switches like VSC9959 have flooding per traffic class */
 648        int                             num_flooding_pgids;
 649
 650        /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
 651         * the CPU is located after the physical ports (at the
 652         * num_phys_ports index).
 653         */
 654        u8                              num_phys_ports;
 655
 656        int                             npi;
 657
 658        enum ocelot_tag_prefix          npi_inj_prefix;
 659        enum ocelot_tag_prefix          npi_xtr_prefix;
 660
 661        struct list_head                multicast;
 662        struct list_head                pgids;
 663
 664        struct list_head                dummy_rules;
 665        struct ocelot_vcap_block        block[3];
 666        struct vcap_props               *vcap;
 667
 668        /* Workqueue to check statistics for overflow with its lock */
 669        struct mutex                    stats_lock;
 670        u64                             *stats;
 671        struct delayed_work             stats_work;
 672        struct workqueue_struct         *stats_queue;
 673
 674        struct workqueue_struct         *owq;
 675
 676        u8                              ptp:1;
 677        struct ptp_clock                *ptp_clock;
 678        struct ptp_clock_info           ptp_info;
 679        struct hwtstamp_config          hwtstamp_config;
 680        /* Protects the PTP interface state */
 681        struct mutex                    ptp_lock;
 682        /* Protects the PTP clock */
 683        spinlock_t                      ptp_clock_lock;
 684        struct ptp_pin_desc             ptp_pins[OCELOT_PTP_PINS_NUM];
 685};
 686
 687struct ocelot_policer {
 688        u32 rate; /* kilobit per second */
 689        u32 burst; /* bytes */
 690};
 691
 692struct ocelot_skb_cb {
 693        struct sk_buff *clone;
 694        u8 ptp_cmd;
 695        u8 ts_id;
 696};
 697
 698#define OCELOT_SKB_CB(skb) \
 699        ((struct ocelot_skb_cb *)((skb)->cb))
 700
 701#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 702#define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
 703#define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
 704#define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
 705
 706#define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 707#define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
 708#define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
 709#define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
 710
 711#define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 712#define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
 713#define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
 714#define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
 715
 716#define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
 717#define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
 718#define ocelot_fields_write(ocelot, id, reg, val) regmap_fields_write((ocelot)->regfields[(reg)], (id), (val))
 719#define ocelot_fields_read(ocelot, id, reg, val) regmap_fields_read((ocelot)->regfields[(reg)], (id), (val))
 720
 721#define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \
 722        __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 723#define ocelot_target_read_gix(ocelot, target, reg, gi) \
 724        __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi))
 725#define ocelot_target_read_rix(ocelot, target, reg, ri) \
 726        __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri))
 727#define ocelot_target_read(ocelot, target, reg) \
 728        __ocelot_target_read_ix(ocelot, target, reg, 0)
 729
 730#define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \
 731        __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
 732#define ocelot_target_write_gix(ocelot, target, val, reg, gi) \
 733        __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi))
 734#define ocelot_target_write_rix(ocelot, target, val, reg, ri) \
 735        __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri))
 736#define ocelot_target_write(ocelot, target, val, reg) \
 737        __ocelot_target_write_ix(ocelot, target, val, reg, 0)
 738
 739/* I/O */
 740u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
 741void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
 742void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg);
 743u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
 744void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
 745void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
 746                     u32 offset);
 747u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
 748                            u32 reg, u32 offset);
 749void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
 750                              u32 val, u32 reg, u32 offset);
 751
 752#if IS_ENABLED(CONFIG_MSCC_OCELOT_SWITCH_LIB)
 753
 754/* Packet I/O */
 755bool ocelot_can_inject(struct ocelot *ocelot, int grp);
 756void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
 757                              u32 rew_op, struct sk_buff *skb);
 758int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb);
 759void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp);
 760
 761u32 ocelot_ptp_rew_op(struct sk_buff *skb);
 762#else
 763
 764static inline bool ocelot_can_inject(struct ocelot *ocelot, int grp)
 765{
 766        return false;
 767}
 768
 769static inline void ocelot_port_inject_frame(struct ocelot *ocelot, int port,
 770                                            int grp, u32 rew_op,
 771                                            struct sk_buff *skb)
 772{
 773}
 774
 775static inline int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp,
 776                                        struct sk_buff **skb)
 777{
 778        return -EIO;
 779}
 780
 781static inline void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
 782{
 783}
 784
 785static inline u32 ocelot_ptp_rew_op(struct sk_buff *skb)
 786{
 787        return 0;
 788}
 789#endif
 790
 791/* Hardware initialization */
 792int ocelot_regfields_init(struct ocelot *ocelot,
 793                          const struct reg_field *const regfields);
 794struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
 795int ocelot_init(struct ocelot *ocelot);
 796void ocelot_deinit(struct ocelot *ocelot);
 797void ocelot_init_port(struct ocelot *ocelot, int port);
 798void ocelot_deinit_port(struct ocelot *ocelot, int port);
 799
 800/* DSA callbacks */
 801void ocelot_port_enable(struct ocelot *ocelot, int port,
 802                        struct phy_device *phy);
 803void ocelot_port_disable(struct ocelot *ocelot, int port);
 804void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
 805void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
 806int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
 807int ocelot_get_ts_info(struct ocelot *ocelot, int port,
 808                       struct ethtool_ts_info *info);
 809void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
 810int ocelot_port_flush(struct ocelot *ocelot, int port);
 811void ocelot_adjust_link(struct ocelot *ocelot, int port,
 812                        struct phy_device *phydev);
 813int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled);
 814void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
 815void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot);
 816int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
 817                                 struct switchdev_brport_flags val);
 818void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
 819                              struct switchdev_brport_flags val);
 820void ocelot_port_bridge_join(struct ocelot *ocelot, int port,
 821                             struct net_device *bridge);
 822void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
 823                              struct net_device *bridge);
 824int ocelot_fdb_dump(struct ocelot *ocelot, int port,
 825                    dsa_fdb_dump_cb_t *cb, void *data);
 826int ocelot_fdb_add(struct ocelot *ocelot, int port,
 827                   const unsigned char *addr, u16 vid);
 828int ocelot_fdb_del(struct ocelot *ocelot, int port,
 829                   const unsigned char *addr, u16 vid);
 830int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
 831                        bool untagged);
 832int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
 833                    bool untagged);
 834int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
 835int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
 836int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
 837int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port,
 838                                 struct sk_buff *skb,
 839                                 struct sk_buff **clone);
 840void ocelot_get_txtstamp(struct ocelot *ocelot);
 841void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
 842int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
 843int ocelot_port_policer_add(struct ocelot *ocelot, int port,
 844                            struct ocelot_policer *pol);
 845int ocelot_port_policer_del(struct ocelot *ocelot, int port);
 846int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
 847                              struct flow_cls_offload *f, bool ingress);
 848int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
 849                              struct flow_cls_offload *f, bool ingress);
 850int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
 851                            struct flow_cls_offload *f, bool ingress);
 852int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
 853                        const struct switchdev_obj_port_mdb *mdb);
 854int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
 855                        const struct switchdev_obj_port_mdb *mdb);
 856int ocelot_port_lag_join(struct ocelot *ocelot, int port,
 857                         struct net_device *bond,
 858                         struct netdev_lag_upper_info *info);
 859void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
 860                           struct net_device *bond);
 861void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active);
 862
 863int ocelot_devlink_sb_register(struct ocelot *ocelot);
 864void ocelot_devlink_sb_unregister(struct ocelot *ocelot);
 865int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index,
 866                       u16 pool_index,
 867                       struct devlink_sb_pool_info *pool_info);
 868int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index,
 869                       u16 pool_index, u32 size,
 870                       enum devlink_sb_threshold_type threshold_type,
 871                       struct netlink_ext_ack *extack);
 872int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port,
 873                            unsigned int sb_index, u16 pool_index,
 874                            u32 *p_threshold);
 875int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port,
 876                            unsigned int sb_index, u16 pool_index,
 877                            u32 threshold, struct netlink_ext_ack *extack);
 878int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port,
 879                               unsigned int sb_index, u16 tc_index,
 880                               enum devlink_sb_pool_type pool_type,
 881                               u16 *p_pool_index, u32 *p_threshold);
 882int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port,
 883                               unsigned int sb_index, u16 tc_index,
 884                               enum devlink_sb_pool_type pool_type,
 885                               u16 pool_index, u32 threshold,
 886                               struct netlink_ext_ack *extack);
 887int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index);
 888int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index);
 889int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port,
 890                                unsigned int sb_index, u16 pool_index,
 891                                u32 *p_cur, u32 *p_max);
 892int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port,
 893                                   unsigned int sb_index, u16 tc_index,
 894                                   enum devlink_sb_pool_type pool_type,
 895                                   u32 *p_cur, u32 *p_max);
 896
 897#if IS_ENABLED(CONFIG_BRIDGE_MRP)
 898int ocelot_mrp_add(struct ocelot *ocelot, int port,
 899                   const struct switchdev_obj_mrp *mrp);
 900int ocelot_mrp_del(struct ocelot *ocelot, int port,
 901                   const struct switchdev_obj_mrp *mrp);
 902int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
 903                             const struct switchdev_obj_ring_role_mrp *mrp);
 904int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
 905                             const struct switchdev_obj_ring_role_mrp *mrp);
 906#else
 907static inline int ocelot_mrp_add(struct ocelot *ocelot, int port,
 908                                 const struct switchdev_obj_mrp *mrp)
 909{
 910        return -EOPNOTSUPP;
 911}
 912
 913static inline int ocelot_mrp_del(struct ocelot *ocelot, int port,
 914                                 const struct switchdev_obj_mrp *mrp)
 915{
 916        return -EOPNOTSUPP;
 917}
 918
 919static inline int
 920ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
 921                         const struct switchdev_obj_ring_role_mrp *mrp)
 922{
 923        return -EOPNOTSUPP;
 924}
 925
 926static inline int
 927ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
 928                         const struct switchdev_obj_ring_role_mrp *mrp)
 929{
 930        return -EOPNOTSUPP;
 931}
 932#endif
 933
 934#endif
 935