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10#ifndef __SOUND_VX_COMMON_H
11#define __SOUND_VX_COMMON_H
12
13#include <sound/pcm.h>
14#include <sound/hwdep.h>
15#include <linux/interrupt.h>
16
17struct firmware;
18struct device;
19
20#define VX_DRIVER_VERSION 0x010000
21
22
23
24#define SIZE_MAX_CMD 0x10
25#define SIZE_MAX_STATUS 0x10
26
27struct vx_rmh {
28 u16 LgCmd;
29 u16 LgStat;
30 u32 Cmd[SIZE_MAX_CMD];
31 u32 Stat[SIZE_MAX_STATUS];
32 u16 DspStat;
33};
34
35typedef u64 pcx_time_t;
36
37#define VX_MAX_PIPES 16
38#define VX_MAX_PERIODS 32
39#define VX_MAX_CODECS 2
40
41struct vx_ibl_info {
42 int size;
43 int max_size;
44 int min_size;
45 int granularity;
46};
47
48struct vx_pipe {
49 int number;
50 unsigned int is_capture: 1;
51 unsigned int data_mode: 1;
52 unsigned int running: 1;
53 unsigned int prepared: 1;
54 int channels;
55 unsigned int differed_type;
56 pcx_time_t pcx_time;
57 struct snd_pcm_substream *substream;
58
59 int hbuf_size;
60 int buffer_bytes;
61 int period_bytes;
62 int hw_ptr;
63 int position;
64 int transferred;
65 int align;
66 u64 cur_count;
67
68 unsigned int references;
69 struct vx_pipe *monitoring_pipe;
70};
71
72struct vx_core;
73
74struct snd_vx_ops {
75
76 unsigned char (*in8)(struct vx_core *chip, int reg);
77 unsigned int (*in32)(struct vx_core *chip, int reg);
78 void (*out8)(struct vx_core *chip, int reg, unsigned char val);
79 void (*out32)(struct vx_core *chip, int reg, unsigned int val);
80
81 int (*test_and_ack)(struct vx_core *chip);
82 void (*validate_irq)(struct vx_core *chip, int enable);
83
84 void (*write_codec)(struct vx_core *chip, int codec, unsigned int data);
85 void (*akm_write)(struct vx_core *chip, int reg, unsigned int data);
86 void (*reset_codec)(struct vx_core *chip);
87 void (*change_audio_source)(struct vx_core *chip, int src);
88 void (*set_clock_source)(struct vx_core *chp, int src);
89
90 int (*load_dsp)(struct vx_core *chip, int idx, const struct firmware *fw);
91 void (*reset_dsp)(struct vx_core *chip);
92 void (*reset_board)(struct vx_core *chip, int cold_reset);
93 int (*add_controls)(struct vx_core *chip);
94
95 void (*dma_write)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
96 struct vx_pipe *pipe, int count);
97 void (*dma_read)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
98 struct vx_pipe *pipe, int count);
99};
100
101struct snd_vx_hardware {
102 const char *name;
103 int type;
104
105
106 unsigned int num_codecs;
107 unsigned int num_ins;
108 unsigned int num_outs;
109 unsigned int output_level_max;
110 const unsigned int *output_level_db_scale;
111};
112
113
114#define SND_VX_HWDEP_ID "VX Loader"
115
116
117enum {
118
119 VX_TYPE_BOARD,
120 VX_TYPE_V2,
121 VX_TYPE_MIC,
122
123 VX_TYPE_VXPOCKET,
124 VX_TYPE_VXP440,
125 VX_TYPE_NUMS
126};
127
128
129enum {
130 VX_STAT_XILINX_LOADED = (1 << 0),
131 VX_STAT_DEVICE_INIT = (1 << 1),
132 VX_STAT_CHIP_INIT = (1 << 2),
133 VX_STAT_IN_SUSPEND = (1 << 10),
134 VX_STAT_IS_STALE = (1 << 15)
135};
136
137
138#define VX_ANALOG_OUT_LEVEL_MAX 0xe3
139
140struct vx_core {
141
142 struct snd_card *card;
143 struct snd_pcm *pcm[VX_MAX_CODECS];
144 int type;
145
146 int irq;
147
148
149
150 const struct snd_vx_hardware *hw;
151 const struct snd_vx_ops *ops;
152
153 struct mutex lock;
154
155 unsigned int chip_status;
156 unsigned int pcm_running;
157
158 struct device *dev;
159 struct snd_hwdep *hwdep;
160
161 struct vx_rmh irq_rmh;
162
163 unsigned int audio_info;
164 unsigned int audio_ins;
165 unsigned int audio_outs;
166 struct vx_pipe **playback_pipes;
167 struct vx_pipe **capture_pipes;
168
169
170 unsigned int audio_source;
171 unsigned int audio_source_target;
172 unsigned int clock_mode;
173 unsigned int clock_source;
174 unsigned int freq;
175 unsigned int freq_detected;
176 unsigned int uer_detected;
177 unsigned int uer_bits;
178 struct vx_ibl_info ibl;
179
180
181 int output_level[VX_MAX_CODECS][2];
182 int audio_gain[2][4];
183 unsigned char audio_active[4];
184 int audio_monitor[4];
185 unsigned char audio_monitor_active[4];
186
187 struct mutex mixer_mutex;
188
189 const struct firmware *firmware[4];
190};
191
192
193
194
195
196struct vx_core *snd_vx_create(struct snd_card *card,
197 const struct snd_vx_hardware *hw,
198 const struct snd_vx_ops *ops, int extra_size);
199int snd_vx_setup_firmware(struct vx_core *chip);
200int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *dsp);
201int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *dsp);
202int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp);
203
204void snd_vx_free_firmware(struct vx_core *chip);
205
206
207
208
209irqreturn_t snd_vx_irq_handler(int irq, void *dev);
210irqreturn_t snd_vx_threaded_irq_handler(int irq, void *dev);
211
212
213
214
215static inline int vx_test_and_ack(struct vx_core *chip)
216{
217 return chip->ops->test_and_ack(chip);
218}
219
220static inline void vx_validate_irq(struct vx_core *chip, int enable)
221{
222 chip->ops->validate_irq(chip, enable);
223}
224
225static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg)
226{
227 return chip->ops->in8(chip, reg);
228}
229
230static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg)
231{
232 return chip->ops->in32(chip, reg);
233}
234
235static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val)
236{
237 chip->ops->out8(chip, reg, val);
238}
239
240static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val)
241{
242 chip->ops->out32(chip, reg, val);
243}
244
245#define vx_inb(chip,reg) snd_vx_inb(chip, VX_##reg)
246#define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val)
247#define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg)
248#define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val)
249
250static inline void vx_reset_dsp(struct vx_core *chip)
251{
252 chip->ops->reset_dsp(chip);
253}
254
255int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh);
256int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh);
257int vx_send_rih(struct vx_core *chip, int cmd);
258int vx_send_rih_nolock(struct vx_core *chip, int cmd);
259
260void vx_reset_codec(struct vx_core *chip, int cold_reset);
261
262
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264
265
266
267int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time);
268#define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time)
269#define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200)
270#define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL)
271
272
273
274
275
276static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
277 struct vx_pipe *pipe, int count)
278{
279 chip->ops->dma_write(chip, runtime, pipe, count);
280}
281
282static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
283 struct vx_pipe *pipe, int count)
284{
285 chip->ops->dma_read(chip, runtime, pipe, count);
286}
287
288
289
290
291
292
293#define VX_ERR_MASK 0x1000000
294#define vx_get_error(err) (-(err) & ~VX_ERR_MASK)
295
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297
298
299
300int snd_vx_pcm_new(struct vx_core *chip);
301void vx_pcm_update_intr(struct vx_core *chip, unsigned int events);
302
303
304
305
306int snd_vx_mixer_new(struct vx_core *chip);
307void vx_toggle_dac_mute(struct vx_core *chip, int mute);
308int vx_sync_audio_source(struct vx_core *chip);
309int vx_set_monitor_level(struct vx_core *chip, int audio, int level, int active);
310
311
312
313
314void vx_set_iec958_status(struct vx_core *chip, unsigned int bits);
315int vx_set_clock(struct vx_core *chip, unsigned int freq);
316void vx_set_internal_clock(struct vx_core *chip, unsigned int freq);
317int vx_change_frequency(struct vx_core *chip);
318
319
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321
322
323int snd_vx_suspend(struct vx_core *card);
324int snd_vx_resume(struct vx_core *card);
325
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328
329
330#define vx_has_new_dsp(chip) ((chip)->type != VX_TYPE_BOARD)
331#define vx_is_pcmcia(chip) ((chip)->type >= VX_TYPE_VXPOCKET)
332
333
334enum {
335 VX_AUDIO_SRC_DIGITAL,
336 VX_AUDIO_SRC_LINE,
337 VX_AUDIO_SRC_MIC
338};
339
340
341enum {
342 INTERNAL_QUARTZ,
343 UER_SYNC
344};
345
346
347enum {
348 VX_CLOCK_MODE_AUTO,
349 VX_CLOCK_MODE_INTERNAL,
350 VX_CLOCK_MODE_EXTERNAL
351};
352
353
354enum {
355 VX_UER_MODE_CONSUMER,
356 VX_UER_MODE_PROFESSIONAL,
357 VX_UER_MODE_NOT_PRESENT,
358};
359
360
361enum {
362 VX_ICR,
363 VX_CVR,
364 VX_ISR,
365 VX_IVR,
366 VX_RXH,
367 VX_TXH = VX_RXH,
368 VX_RXM,
369 VX_TXM = VX_RXM,
370 VX_RXL,
371 VX_TXL = VX_RXL,
372 VX_DMA,
373 VX_CDSP,
374 VX_RFREQ,
375 VX_RUER_V2,
376 VX_GAIN,
377 VX_DATA = VX_GAIN,
378 VX_MEMIRQ,
379 VX_ACQ,
380 VX_BIT0,
381 VX_BIT1,
382 VX_MIC0,
383 VX_MIC1,
384 VX_MIC2,
385 VX_MIC3,
386 VX_PLX0,
387 VX_PLX1,
388 VX_PLX2,
389
390 VX_LOFREQ,
391 VX_HIFREQ,
392 VX_CSUER,
393 VX_RUER,
394
395 VX_REG_MAX,
396
397
398 VX_RESET_DMA = VX_ISR,
399 VX_CFG = VX_RFREQ,
400 VX_STATUS = VX_MEMIRQ,
401 VX_SELMIC = VX_MIC0,
402 VX_COMPOT = VX_MIC1,
403 VX_SCOMPR = VX_MIC2,
404 VX_GLIMIT = VX_MIC3,
405 VX_INTCSR = VX_PLX0,
406 VX_CNTRL = VX_PLX1,
407 VX_GPIOC = VX_PLX2,
408
409
410 VX_MICRO = VX_MEMIRQ,
411 VX_CODEC2 = VX_MEMIRQ,
412 VX_DIALOG = VX_ACQ,
413
414};
415
416
417enum {
418 RMH_SSIZE_FIXED = 0,
419 RMH_SSIZE_ARG = 1,
420 RMH_SSIZE_MASK = 2,
421};
422
423
424
425#define ICR_HF1 0x10
426#define ICR_HF0 0x08
427#define ICR_TREQ 0x02
428#define ICR_RREQ 0x01
429
430
431#define CVR_HC 0x80
432
433
434#define ISR_HF3 0x10
435#define ISR_HF2 0x08
436#define ISR_CHK 0x10
437#define ISR_ERR 0x08
438#define ISR_TX_READY 0x04
439#define ISR_TX_EMPTY 0x02
440#define ISR_RX_FULL 0x01
441
442
443#define VX_DATA_CODEC_MASK 0x80
444#define VX_DATA_XICOR_MASK 0x80
445
446
447#define VX_SUER_FREQ_MASK 0x0c
448#define VX_SUER_FREQ_32KHz_MASK 0x0c
449#define VX_SUER_FREQ_44KHz_MASK 0x00
450#define VX_SUER_FREQ_48KHz_MASK 0x04
451#define VX_SUER_DATA_PRESENT_MASK 0x02
452#define VX_SUER_CLOCK_PRESENT_MASK 0x01
453
454#define VX_CUER_HH_BITC_SEL_MASK 0x08
455#define VX_CUER_MH_BITC_SEL_MASK 0x04
456#define VX_CUER_ML_BITC_SEL_MASK 0x02
457#define VX_CUER_LL_BITC_SEL_MASK 0x01
458
459#define XX_UER_CBITS_OFFSET_MASK 0x1f
460
461
462
463#define VX_AUDIO_INFO_REAL_TIME (1<<0)
464#define VX_AUDIO_INFO_OFFLINE (1<<1)
465#define VX_AUDIO_INFO_MPEG1 (1<<5)
466#define VX_AUDIO_INFO_MPEG2 (1<<6)
467#define VX_AUDIO_INFO_LINEAR_8 (1<<7)
468#define VX_AUDIO_INFO_LINEAR_16 (1<<8)
469#define VX_AUDIO_INFO_LINEAR_24 (1<<9)
470
471
472#define VXP_IRQ_OFFSET 0x40
473
474#define IRQ_MESS_WRITE_END 0x30
475#define IRQ_MESS_WRITE_NEXT 0x32
476#define IRQ_MESS_READ_NEXT 0x34
477#define IRQ_MESS_READ_END 0x36
478#define IRQ_MESSAGE 0x38
479#define IRQ_RESET_CHK 0x3A
480#define IRQ_CONNECT_STREAM_NEXT 0x26
481#define IRQ_CONNECT_STREAM_END 0x28
482#define IRQ_PAUSE_START_CONNECT 0x2A
483#define IRQ_END_CONNECTION 0x2C
484
485
486#define ASYNC_EVENTS_PENDING 0x008000
487#define HBUFFER_EVENTS_PENDING 0x004000
488#define NOTIF_EVENTS_PENDING 0x002000
489#define TIME_CODE_EVENT_PENDING 0x001000
490#define FREQUENCY_CHANGE_EVENT_PENDING 0x000800
491#define END_OF_BUFFER_EVENTS_PENDING 0x000400
492#define FATAL_DSP_ERROR 0xff0000
493
494
495#define HEADER_FMT_BASE 0xFED00000
496#define HEADER_FMT_MONO 0x000000C0
497#define HEADER_FMT_INTEL 0x00008000
498#define HEADER_FMT_16BITS 0x00002000
499#define HEADER_FMT_24BITS 0x00004000
500#define HEADER_FMT_UPTO11 0x00000200
501#define HEADER_FMT_UPTO32 0x00000100
502
503
504#define XX_CODEC_SELECTOR 0x20
505
506#define XX_CODEC_ADC_CONTROL_REGISTER 0x01
507#define XX_CODEC_DAC_CONTROL_REGISTER 0x02
508#define XX_CODEC_LEVEL_LEFT_REGISTER 0x03
509#define XX_CODEC_LEVEL_RIGHT_REGISTER 0x04
510#define XX_CODEC_PORT_MODE_REGISTER 0x05
511#define XX_CODEC_STATUS_REPORT_REGISTER 0x06
512#define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07
513
514
515
516
517#define CVAL_M110DB 0x000
518#define CVAL_M99DB 0x02C
519#define CVAL_M21DB 0x163
520#define CVAL_M18DB 0x16F
521#define CVAL_M10DB 0x18F
522#define CVAL_0DB 0x1B7
523#define CVAL_18DB 0x1FF
524#define CVAL_MAX 0x1FF
525
526#define AUDIO_IO_HAS_MUTE_LEVEL 0x400000
527#define AUDIO_IO_HAS_MUTE_MONITORING_1 0x200000
528#define AUDIO_IO_HAS_MUTE_MONITORING_2 0x100000
529#define VALID_AUDIO_IO_DIGITAL_LEVEL 0x01
530#define VALID_AUDIO_IO_MONITORING_LEVEL 0x02
531#define VALID_AUDIO_IO_MUTE_LEVEL 0x04
532#define VALID_AUDIO_IO_MUTE_MONITORING_1 0x08
533#define VALID_AUDIO_IO_MUTE_MONITORING_2 0x10
534
535
536#endif
537