1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * cs42l52.h -- CS42L52 ALSA SoC audio driver 4 * 5 * Copyright 2012 CirrusLogic, Inc. 6 * 7 * Author: Georgi Vlaev <joe@nucleusys.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 */ 10 11#ifndef __CS42L52_H__ 12#define __CS42L52_H__ 13 14#define CS42L52_NAME "CS42L52" 15#define CS42L52_DEFAULT_CLK 12000000 16#define CS42L52_MIN_CLK 11000000 17#define CS42L52_MAX_CLK 27000000 18#define CS42L52_DEFAULT_FORMAT SNDRV_PCM_FMTBIT_S16_LE 19#define CS42L52_DEFAULT_MAX_CHANS 2 20#define CS42L52_SYSCLK 1 21 22#define CS42L52_CHIP_SWICTH (1 << 17) 23#define CS42L52_ALL_IN_ONE (1 << 16) 24#define CS42L52_CHIP_ONE 0x00 25#define CS42L52_CHIP_TWO 0x01 26#define CS42L52_CHIP_THR 0x02 27#define CS42L52_CHIP_MASK 0x0f 28 29#define CS42L52_FIX_BITS_CTL 0x00 30#define CS42L52_CHIP 0x01 31#define CS42L52_CHIP_ID 0xE0 32#define CS42L52_CHIP_ID_MASK 0xF8 33#define CS42L52_CHIP_REV_A0 0x00 34#define CS42L52_CHIP_REV_A1 0x01 35#define CS42L52_CHIP_REV_B0 0x02 36#define CS42L52_CHIP_REV_MASK 0x07 37 38#define CS42L52_PWRCTL1 0x02 39#define CS42L52_PWRCTL1_PDN_ALL 0x9F 40#define CS42L52_PWRCTL1_PDN_CHRG 0x80 41#define CS42L52_PWRCTL1_PDN_PGAB 0x10 42#define CS42L52_PWRCTL1_PDN_PGAA 0x08 43#define CS42L52_PWRCTL1_PDN_ADCB 0x04 44#define CS42L52_PWRCTL1_PDN_ADCA 0x02 45#define CS42L52_PWRCTL1_PDN_CODEC 0x01 46 47#define CS42L52_PWRCTL2 0x03 48#define CS42L52_PWRCTL2_OVRDB (1 << 4) 49#define CS42L52_PWRCTL2_OVRDA (1 << 3) 50#define CS42L52_PWRCTL2_PDN_MICB (1 << 2) 51#define CS42L52_PWRCTL2_PDN_MICB_SHIFT 2 52#define CS42L52_PWRCTL2_PDN_MICA (1 << 1) 53#define CS42L52_PWRCTL2_PDN_MICA_SHIFT 1 54#define CS42L52_PWRCTL2_PDN_MICBIAS (1 << 0) 55#define CS42L52_PWRCTL2_PDN_MICBIAS_SHIFT 0 56 57#define CS42L52_PWRCTL3 0x04 58#define CS42L52_PWRCTL3_HPB_PDN_SHIFT 6 59#define CS42L52_PWRCTL3_HPB_ON_LOW 0x00 60#define CS42L52_PWRCTL3_HPB_ON_HIGH 0x01 61#define CS42L52_PWRCTL3_HPB_ALWAYS_ON 0x02 62#define CS42L52_PWRCTL3_HPB_ALWAYS_OFF 0x03 63#define CS42L52_PWRCTL3_HPA_PDN_SHIFT 4 64#define CS42L52_PWRCTL3_HPA_ON_LOW 0x00 65#define CS42L52_PWRCTL3_HPA_ON_HIGH 0x01 66#define CS42L52_PWRCTL3_HPA_ALWAYS_ON 0x02 67#define CS42L52_PWRCTL3_HPA_ALWAYS_OFF 0x03 68#define CS42L52_PWRCTL3_SPKB_PDN_SHIFT 2 69#define CS42L52_PWRCTL3_SPKB_ON_LOW 0x00 70#define CS42L52_PWRCTL3_SPKB_ON_HIGH 0x01 71#define CS42L52_PWRCTL3_SPKB_ALWAYS_ON 0x02 72#define CS42L52_PWRCTL3_PDN_SPKB (1 << 2) 73#define CS42L52_PWRCTL3_PDN_SPKA (1 << 0) 74#define CS42L52_PWRCTL3_SPKA_PDN_SHIFT 0 75#define CS42L52_PWRCTL3_SPKA_ON_LOW 0x00 76#define CS42L52_PWRCTL3_SPKA_ON_HIGH 0x01 77#define CS42L52_PWRCTL3_SPKA_ALWAYS_ON 0x02 78 79#define CS42L52_DEFAULT_OUTPUT_STATE 0x05 80#define CS42L52_PWRCTL3_CONF_MASK 0x03 81 82#define CS42L52_CLK_CTL 0x05 83#define CLK_AUTODECT_ENABLE (1 << 7) 84#define CLK_SPEED_SHIFT 5 85#define CLK_DS_MODE 0x00 86#define CLK_SS_MODE 0x01 87#define CLK_HS_MODE 0x02 88#define CLK_QS_MODE 0x03 89#define CLK_32K_SR_SHIFT 4 90#define CLK_32K 0x01 91#define CLK_NO_32K 0x00 92#define CLK_27M_MCLK_SHIFT 3 93#define CLK_27M_MCLK 0x01 94#define CLK_NO_27M 0x00 95#define CLK_RATIO_SHIFT 1 96#define CLK_R_128 0x00 97#define CLK_R_125 0x01 98#define CLK_R_132 0x02 99#define CLK_R_136 0x03 100 101#define CS42L52_IFACE_CTL1 0x06 102#define CS42L52_IFACE_CTL1_MASTER (1 << 7) 103#define CS42L52_IFACE_CTL1_SLAVE (0 << 7) 104#define CS42L52_IFACE_CTL1_INV_SCLK (1 << 6) 105#define CS42L52_IFACE_CTL1_ADC_FMT_I2S (1 << 5) 106#define CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J (0 << 5) 107#define CS42L52_IFACE_CTL1_DSP_MODE_EN (1 << 4) 108#define CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J (0 << 2) 109#define CS42L52_IFACE_CTL1_DAC_FMT_I2S (1 << 2) 110#define CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J (2 << 2) 111#define CS42L52_IFACE_CTL1_WL_32BIT (0x00) 112#define CS42L52_IFACE_CTL1_WL_24BIT (0x01) 113#define CS42L52_IFACE_CTL1_WL_20BIT (0x02) 114#define CS42L52_IFACE_CTL1_WL_16BIT (0x03) 115#define CS42L52_IFACE_CTL1_WL_MASK 0xFFFF 116 117#define CS42L52_IFACE_CTL2 0x07 118#define CS42L52_IFACE_CTL2_SC_MC_EQ (1 << 6) 119#define CS42L52_IFACE_CTL2_LOOPBACK (1 << 5) 120#define CS42L52_IFACE_CTL2_S_MODE_OUTPUT_EN (0 << 4) 121#define CS42L52_IFACE_CTL2_S_MODE_OUTPUT_HIZ (1 << 4) 122#define CS42L52_IFACE_CTL2_HP_SW_INV (1 << 3) 123#define CS42L52_IFACE_CTL2_BIAS_LVL 0x07 124 125#define CS42L52_ADC_PGA_A 0x08 126#define CS42L52_ADC_PGA_B 0x09 127#define CS42L52_ADC_SEL_SHIFT 5 128#define CS42L52_ADC_SEL_AIN1 0x00 129#define CS42L52_ADC_SEL_AIN2 0x01 130#define CS42L52_ADC_SEL_AIN3 0x02 131#define CS42L52_ADC_SEL_AIN4 0x03 132#define CS42L52_ADC_SEL_PGA 0x04 133 134#define CS42L52_ANALOG_HPF_CTL 0x0A 135#define CS42L52_HPF_CTL_ANLGSFTB (1 << 3) 136#define CS42L52_HPF_CTL_ANLGSFTA (1 << 0) 137 138#define CS42L52_ADC_HPF_FREQ 0x0B 139#define CS42L52_ADC_MISC_CTL 0x0C 140#define CS42L52_ADC_MISC_CTL_SOURCE_DSP (1 << 6) 141 142#define CS42L52_PB_CTL1 0x0D 143#define CS42L52_PB_CTL1_HP_GAIN_SHIFT 5 144#define CS42L52_PB_CTL1_HP_GAIN_03959 0x00 145#define CS42L52_PB_CTL1_HP_GAIN_04571 0x01 146#define CS42L52_PB_CTL1_HP_GAIN_05111 0x02 147#define CS42L52_PB_CTL1_HP_GAIN_06047 0x03 148#define CS42L52_PB_CTL1_HP_GAIN_07099 0x04 149#define CS42L52_PB_CTL1_HP_GAIN_08399 0x05 150#define CS42L52_PB_CTL1_HP_GAIN_10000 0x06 151#define CS42L52_PB_CTL1_HP_GAIN_11430 0x07 152#define CS42L52_PB_CTL1_INV_PCMB (1 << 3) 153#define CS42L52_PB_CTL1_INV_PCMA (1 << 2) 154#define CS42L52_PB_CTL1_MSTB_MUTE (1 << 1) 155#define CS42L52_PB_CTL1_MSTA_MUTE (1 << 0) 156#define CS42L52_PB_CTL1_MUTE_MASK 0x03 157#define CS42L52_PB_CTL1_MUTE 3 158#define CS42L52_PB_CTL1_UNMUTE 0 159 160#define CS42L52_MISC_CTL 0x0E 161#define CS42L52_MISC_CTL_DEEMPH (1 << 2) 162#define CS42L52_MISC_CTL_DIGSFT (1 << 1) 163#define CS42L52_MISC_CTL_DIGZC (1 << 0) 164 165#define CS42L52_PB_CTL2 0x0F 166#define CS42L52_PB_CTL2_HPB_MUTE (1 << 7) 167#define CS42L52_PB_CTL2_HPA_MUTE (1 << 6) 168#define CS42L52_PB_CTL2_SPKB_MUTE (1 << 5) 169#define CS42L52_PB_CTL2_SPKA_MUTE (1 << 4) 170#define CS42L52_PB_CTL2_SPK_SWAP (1 << 2) 171#define CS42L52_PB_CTL2_SPK_MONO (1 << 1) 172#define CS42L52_PB_CTL2_SPK_MUTE50 (1 << 0) 173 174#define CS42L52_MICA_CTL 0x10 175#define CS42L52_MICB_CTL 0x11 176#define CS42L52_MIC_CTL_MIC_SEL_MASK 0xBF 177#define CS42L52_MIC_CTL_MIC_SEL_SHIFT 6 178#define CS42L52_MIC_CTL_TYPE_MASK 0x20 179#define CS42L52_MIC_CTL_TYPE_SHIFT 5 180 181 182#define CS42L52_PGAA_CTL 0x12 183#define CS42L52_PGAB_CTL 0x13 184#define CS42L52_PGAX_CTL_VOL_12DB 24 185#define CS42L52_PGAX_CTL_VOL_6DB 12 /*step size 0.5db*/ 186 187#define CS42L52_PASSTHRUA_VOL 0x14 188#define CS42L52_PASSTHRUB_VOL 0x15 189 190#define CS42L52_ADCA_VOL 0x16 191#define CS42L52_ADCB_VOL 0x17 192#define CS42L52_ADCX_VOL_24DB 24 /*step size 1db*/ 193#define CS42L52_ADCX_VOL_12DB 12 194#define CS42L52_ADCX_VOL_6DB 6 195 196#define CS42L52_ADCA_MIXER_VOL 0x18 197#define CS42L52_ADCB_MIXER_VOL 0x19 198#define CS42L52_ADC_MIXER_VOL_12DB 0x18 199 200#define CS42L52_PCMA_MIXER_VOL 0x1A 201#define CS42L52_PCMB_MIXER_VOL 0x1B 202 203#define CS42L52_BEEP_FREQ 0x1C 204#define CS42L52_BEEP_VOL 0x1D 205#define CS42L52_BEEP_TONE_CTL 0x1E 206#define CS42L52_BEEP_RATE_SHIFT 4 207#define CS42L52_BEEP_RATE_MASK 0x0F 208 209#define CS42L52_TONE_CTL 0x1F 210#define CS42L52_BEEP_EN_MASK 0x3F 211 212#define CS42L52_MASTERA_VOL 0x20 213#define CS42L52_MASTERB_VOL 0x21 214 215#define CS42L52_HPA_VOL 0x22 216#define CS42L52_HPB_VOL 0x23 217#define CS42L52_DEFAULT_HP_VOL 0xF0 218 219#define CS42L52_SPKA_VOL 0x24 220#define CS42L52_SPKB_VOL 0x25 221#define CS42L52_DEFAULT_SPK_VOL 0xF0 222 223#define CS42L52_ADC_PCM_MIXER 0x26 224 225#define CS42L52_LIMITER_CTL1 0x27 226#define CS42L52_LIMITER_CTL2 0x28 227#define CS42L52_LIMITER_AT_RATE 0x29 228 229#define CS42L52_ALC_CTL 0x2A 230#define CS42L52_ALC_CTL_ALCB_ENABLE_SHIFT 7 231#define CS42L52_ALC_CTL_ALCA_ENABLE_SHIFT 6 232#define CS42L52_ALC_CTL_FASTEST_ATTACK 0 233 234#define CS42L52_ALC_RATE 0x2B 235#define CS42L52_ALC_SLOWEST_RELEASE 0x3F 236 237#define CS42L52_ALC_THRESHOLD 0x2C 238#define CS42L52_ALC_MAX_RATE_SHIFT 5 239#define CS42L52_ALC_MIN_RATE_SHIFT 2 240#define CS42L52_ALC_RATE_0DB 0 241#define CS42L52_ALC_RATE_3DB 1 242#define CS42L52_ALC_RATE_6DB 2 243 244#define CS42L52_NOISE_GATE_CTL 0x2D 245#define CS42L52_NG_ENABLE_SHIFT 6 246#define CS42L52_NG_THRESHOLD_SHIFT 2 247#define CS42L52_NG_MIN_70DB 2 248#define CS42L52_NG_DELAY_SHIFT 0 249#define CS42L52_NG_DELAY_100MS 1 250 251#define CS42L52_CLK_STATUS 0x2E 252#define CS42L52_BATT_COMPEN 0x2F 253 254#define CS42L52_BATT_LEVEL 0x30 255#define CS42L52_SPK_STATUS 0x31 256#define CS42L52_SPK_STATUS_PIN_SHIFT 3 257#define CS42L52_SPK_STATUS_PIN_HIGH 1 258 259#define CS42L52_TEM_CTL 0x32 260#define CS42L52_TEM_CTL_SET 0x80 261#define CS42L52_THE_FOLDBACK 0x33 262#define CS42L52_CHARGE_PUMP 0x34 263#define CS42L52_CHARGE_PUMP_MASK 0xF0 264#define CS42L52_CHARGE_PUMP_SHIFT 4 265#define CS42L52_FIX_BITS1 0x3E 266#define CS42L52_FIX_BITS2 0x47 267 268#define CS42L52_MAX_REGISTER 0x47 269 270#endif 271